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2024-03-12meson: Allow intel-clc=disabled to be usedintel-clc-disabledJordan Justen1-1/+0
2024-03-12intel/shaders: Don't run intel-clc if intel-clc=disabledJordan Justen1-6/+10
2024-03-12anv, iris: Don't build code paths for internal shaders if intel-clc=disabledJordan Justen2-2/+9
2024-03-12anv, iris: Look at INTEL_CLC_DISABLED on various code pathsJordan Justen5-0/+22
2024-03-12meson: Define INTEL_CLC_DISABLED if intel-clc=disable is usedJordan Justen1-0/+4
2024-03-12meson: Add intel-clc=disabled (but, it currently generates an error)Jordan Justen2-1/+4
2024-03-12meson: Split build_intel_clc out from with_intel_clcJordan Justen2-5/+12
2024-03-12glsl_types: derive htAlyssa Rosenzweig1-27/+6
2024-03-12v3d: derive htAlyssa Rosenzweig1-14/+2
2024-03-12radeonsi: derive htAlyssa Rosenzweig1-12/+2
2024-03-12nvk: derive htAlyssa Rosenzweig1-13/+3
2024-03-12asahi: derive htAlyssa Rosenzweig1-12/+2
2024-03-12panfrost: derive htAlyssa Rosenzweig3-67/+10
2024-03-12util/hash_table: add DERIVE macroAlyssa Rosenzweig1-0/+20
2024-03-12nir/print: do not print empty lists on intrinsicsAlyssa Rosenzweig1-5/+11
2024-03-12util: add _mesa_hash_table_u64_num_entriesAlyssa Rosenzweig1-0/+7
2024-03-12nir/opt_shrink_vectors: shrink some intrinsics from startAlyssa Rosenzweig19-43/+69
2024-03-12nir/opt_shrink_vectors: hoist alu helpersAlyssa Rosenzweig1-25/+25
2024-03-12intel/dev: Nuke display_verJosé Roberto de Souza2-11/+0
2024-03-12intel/dev: Nuke 'ver == 10' checkJosé Roberto de Souza1-5/+0
2024-03-12radv: stop using 5/8 component SSBO storesRhys Perry1-37/+45
2024-03-12radv: don't advertise DGC with LLVMRhys Perry1-2/+2
2024-03-12etnaviv: isa: Support multiple encodings for texldbChristian Gmeiner1-1/+1
2024-03-12etnaviv: isa: Fix #instruction-tex-src0-src1-src2 bitsetChristian Gmeiner2-5/+5
2024-03-12etnaviv: isa: Support multiple encodings for texldlChristian Gmeiner1-1/+44
2024-03-12etnaviv: isa: Support unary texkill instructionChristian Gmeiner1-0/+6
2024-03-12etnaviv: isa: Support unary branch instructionChristian Gmeiner1-0/+10
2024-03-12etnaviv: isa: Combine branch and branch_ifChristian Gmeiner1-11/+12
2024-03-12etnaviv: isa: Correct #instruction-alu-no-dst-has-src0-src1 expr nameChristian Gmeiner1-2/+2
2024-03-12etnaviv: isa: Correct #instruction-alu-no-dst-maybe-src1-src2 nameChristian Gmeiner1-2/+2
2024-03-12etnaviv: isa: Correct #instruction-cf-src1-src2 bitset nameChristian Gmeiner1-3/+3
2024-03-12etnaviv: isa: Correct SRC0_AMODEChristian Gmeiner1-17/+15
2024-03-12etnaviv: isa: Move {TEX_SWIZ}Christian Gmeiner2-10/+10
2024-03-12etnaviv: isa: Add movar opcodeChristian Gmeiner1-1/+5
2024-03-12etnaviv: isa: Add internal register groupChristian Gmeiner1-0/+1
2024-03-12etnaviv: isa: Rename reg_group u2 to uChristian Gmeiner1-1/+1
2024-03-12etnaviv: isa: Reorder instructionsChristian Gmeiner1-24/+24
2024-03-12etnaviv: isa: Add div opcodeChristian Gmeiner2-0/+43
2024-03-12etnaviv: isa: Remove note about GC3000Christian Gmeiner1-1/+0
2024-03-12etnaviv: isa: Add texldd opcodeChristian Gmeiner2-1/+6
2024-03-12etnaviv: isa: Add texldl opcodeChristian Gmeiner2-1/+6
2024-03-12etnaviv: isa: Add texldb opcodeChristian Gmeiner2-0/+5
2024-03-12etnaviv: isa: Add bit_rev opcodeChristian Gmeiner2-0/+6
2024-03-12etnaviv: isa: Add movai opcodeChristian Gmeiner2-0/+6
2024-03-12etnaviv: isa: Name cond enum value 22Christian Gmeiner2-2/+2
2024-03-12etnaviv: isa: Add branch_any opcodeChristian Gmeiner2-1/+5
2024-03-12etnaviv: isa: Correct dp2 opcodeChristian Gmeiner2-5/+6
2024-03-12etnaviv: isa: Add bit_extract opcodeChristian Gmeiner2-0/+6
2024-03-12etnaviv: isa: Add norm_dp2, norm_dp3 and norm_dp4 opcodesChristian Gmeiner2-1/+18
2024-03-12etnaviv: isa: Add frc opcodeChristian Gmeiner2-1/+5
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-15 01:56:27 +0000