diff options
| author | Ian Romanick <ian.d.romanick@intel.com> | 2022-08-22 14:28:47 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2024-03-20 15:46:44 -0700 |
| commit | 0aed86a3872d7b7de1028b20f7f218ae097cabe8 (patch) | |
| tree | 0c1a9eb7131df626aac230b81b2d118ac035b536 | |
| parent | 522d9c5d9dc1630aa8fbae7fcea949e5e6e65413 (diff) | |
intel/brw/xe2: Correctly disassemble RT write subtypesxe2-compiler-2-subset
The encoding changed when SIMD32 was added.
Part of Wa_14011334914.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
| -rw-r--r-- | src/intel/compiler/brw_disasm.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index ccf6780eade..09aa0191b31 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -326,6 +326,16 @@ static const char *const m_rt_write_subtype[] = { [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */ }; +static const char *const m_rt_write_subtype_xe2[] = { + [0b000] = "SIMD16", + [0b001] = "SIMD32", + [0b010] = "SIMD16/DualSrc", + [0b011] = "invalid", + [0b100] = "invalid", + [0b101] = "invalid", + [0b111] = "invalid", +}; + static const char *const dp_dc0_msg_type_gfx7[16] = { [GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read", [GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] = @@ -2183,7 +2193,8 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; if (is_rt_write) { - err |= control(file, "RT message type", m_rt_write_subtype, + err |= control(file, "RT message type", + devinfo->ver >= 20 ? m_rt_write_subtype_xe2 : m_rt_write_subtype, brw_inst_rt_message_type(devinfo, inst), &space); if (brw_inst_rt_slot_group(devinfo, inst)) string(file, " Hi"); |