diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2020-01-16 13:16:24 -0800 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2020-01-28 13:52:27 -0800 |
| commit | a99acf79fe629a68668a0a2ceb043b94919626e3 (patch) | |
| tree | e599041d9bac52ab8068804f2ce7f0631249721c | |
| parent | d5a80afc986f167a60c3cd38fb3c07b6f9b47916 (diff) | |
anv: Emit CS Stall before Instruction Cache flush for gen12 WAwa-1409226450
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.
Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 6fabe9134a3..209135ffe79 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1908,6 +1908,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) bits |= ANV_PIPE_TILE_CACHE_FLUSH_BIT; } + /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which + * invalidates the instruction cache + */ + if (GEN_GEN == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)) + bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT; + if ((GEN_GEN >= 8 && GEN_GEN <= 9) && (bits & ANV_PIPE_CS_STALL_BIT) && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) { |