diff options
| author | Christian Gmeiner <cgmeiner@igalia.com> | 2024-02-29 13:48:19 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2024-03-12 17:02:44 +0000 |
| commit | 0701f3ef9b60bad6e7c73bf1825747d0a38c9c06 (patch) | |
| tree | 2427353fdc9e841c673a9f1175cf5298003cbf82 | |
| parent | 8c86bd0209be133c0b2ad64919905a4510d06406 (diff) | |
etnaviv: isa: Add texldl opcode
Encoded instruction is taken from blob running:
- dEQP-GLES3.functional.shaders.texture_functions.texturegrad.isampler2d_vertex
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27871>
| -rw-r--r-- | src/etnaviv/isa/etnaviv.xml | 6 | ||||
| -rw-r--r-- | src/etnaviv/isa/tests/disasm.cpp | 1 |
2 files changed, 6 insertions, 1 deletions
diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml index ba619c30b17..46f909ce0a2 100644 --- a/src/etnaviv/isa/etnaviv.xml +++ b/src/etnaviv/isa/etnaviv.xml @@ -986,10 +986,14 @@ SPDX-License-Identifier: MIT <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> </bitset> +<bitset name="texldl" extends="#instruction-tex-src0"> + <pattern low="0" high="5">011011</pattern> <!-- OPC --> + <pattern pos="80">0</pattern> <!-- OPCODE_BIT6 --> +</bitset> + <!-- 0x7800000f 0x9011007c 0x00200804 0x0100100c --> <!-- texldd --> -<!-- texldl --> <!-- texldpcf --> <!-- rep --> <!-- endrep --> diff --git a/src/etnaviv/isa/tests/disasm.cpp b/src/etnaviv/isa/tests/disasm.cpp index 99fd5e25c88..00539de48e4 100644 --- a/src/etnaviv/isa/tests/disasm.cpp +++ b/src/etnaviv/isa/tests/disasm.cpp @@ -113,6 +113,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest, disasm_state{ {0x00000057, 0x00002800, 0x00000040, 0x00000002}, "texkill.gt.pack void, t2.xxxx, u0.xxxx, void\n" }, disasm_state{ {0x07811018, 0x15001f20, 0x00000000, 0x00000000}, "texld.xyzw t1, tex0, t1.xyyy, void, void\n" }, disasm_state{ {0x07811019, 0x39002f20, 0x00000000, 0x00000000}, "texldb.xyzw t1, tex0, t2.xyzw, void, void\n" }, + disasm_state{ {0x4781101b, 0x39003f20, 0x00000000, 0x00000000}, "texldl.xyzw t1, tex8, t3.xyzw, void, void\n" }, disasm_state{ {0x00801021, 0x00000004, 0x00000000, 0x00000008}, "sqrt t0.x___, void, void, t0.xxxx\n" }, disasm_state{ {0x03001022, 0x00000005, 0x00000000, 0x00154008}, "sin.rtz t0.zy, void, void, t0.yyyy\n" }, disasm_state{ {0x01801023, 0x00000005, 0x00000000, 0x00000008}, "cos.rtz t0.xy__, void, void, t0.xxxx\n" }, |