diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-06-30 19:08:17 +0000 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-07-01 22:06:27 +0000 |
| commit | b613a82c474fd44760fcb6cf51cc21a1cadd5cce (patch) | |
| tree | 42d6f0a72fcd03bb1edc87bc6168d6a8b58cfae5 | |
| parent | 459622213ac228bdeed32fc7af3d49f16b1ad153 (diff) | |
i965/gen8: Enable hiz for all depth levelsnon-miptree-hiz-v1
After modifying the hiz buffer allocation and qpitch calculation, hiz
appears to work in all cases on gen8.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index e959b8cd83..314882117d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -1355,7 +1355,7 @@ intel_miptree_level_enable_hiz(struct brw_context *brw, { assert(mt->hiz_buf); - if (brw->gen >= 8 || brw->is_haswell) { + if (brw->is_haswell) { uint32_t width = minify(mt->physical_width0, level); uint32_t height = minify(mt->physical_height0, level); |