workaround level_x not 8 aligned issue for LODs >= 2gen6-z16-hiz-workaround

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>

1 files changed, 14 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index f300197399..5265f220ba 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1333,11 +1333,10 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw,
                                uint32_t level,
                                uint32_t layer)
 {
+   const struct intel_mipmap_level *l = &mt->level[level];
    assert(mt->hiz_mt);
 
    if (brw->is_haswell) {
-      const struct intel_mipmap_level *l = &mt->level[level];
-
       /* Disable HiZ for LOD > 0 unless the width is 8 aligned
        * and the height is 4 aligned. This allows our HiZ support
        * to fulfill Haswell restrictions for HiZ ops. For LOD == 0,
@@ -1349,6 +1348,19 @@ intel_miptree_slice_enable_hiz(struct brw_context *brw,
       }
    }
 
+   if (brw->gen == 6) {
+      /* Disable HiZ for LOD > 2 unless the level_x is 8 aligned.
+       *
+       * There is no related spec reference, but this was found
+       * to be an issue with Sandy Bridge when converting the
+       * depth surface state to point to the top of the depth
+       * buffer to support layered rendering.
+       */
+      if (level >= 2 && (l->level_x & 7) != 0) {
+         return false;
+      }
+   }
+
    mt->level[level].slice[layer].has_hiz = true;
    return true;
 }