diff options
author | Jordan Justen <jordan.l.justen@intel.com> | 2014-05-28 10:44:13 -0700 |
---|---|---|
committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-07-31 23:53:41 -0700 |
commit | cc1dab8d0a0a2ff82a428c0b8ec7f9382a92d4a6 (patch) | |
tree | da7414a75dbe64f5571f585cc8a5dab68cdfc381 | |
parent | 366c1be7eedb6c4b5946214463914435f68f87e1 (diff) |
i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hizgen6-layered-v3
For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for
separate stencil/hiz. This is needed because gen6 hiz and separate
stencil only support a single miplevel. When accessing the other LODs,
we will program a tile aligned offset for the bo.
PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
"The separate stencil buffer does not support mip mapping, thus the
storage for LODs other than LOD 0 is not needed."
We still allocate storage for the other stencil mip-levels within a
single texture, but each mip-level will use non-mip-array spacing.
PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
"[DevSNB]: The hierarchical depth buffer does not support the LOD
field, it is assumed by hardware to be zero. A separate
hierarachical depth buffer is required for each LOD used, and the
corresponding buffer’s state delivered to hardware each time a new
depth buffer state with modified LOD is delivered."
We allocate storage for the other hiz mip-levels within a single
texture, but each mip-level will use non-mip-array spacing.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 924792b5be..3808662b8d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -359,6 +359,7 @@ intel_miptree_create_layout(struct brw_context *brw, _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && (brw->must_use_separate_stencil || (brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) { + const bool force_all_slices_at_each_lod = brw->gen == 6; mt->stencil_mt = intel_miptree_create(brw, mt->target, MESA_FORMAT_S_UINT8, @@ -370,7 +371,7 @@ intel_miptree_create_layout(struct brw_context *brw, true, num_samples, INTEL_MIPTREE_TILING_ANY, - false); + force_all_slices_at_each_lod); if (!mt->stencil_mt) { intel_miptree_release(&mt); return NULL; @@ -1387,6 +1388,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, struct intel_mipmap_tree *mt) { assert(mt->hiz_mt == NULL); + const bool force_all_slices_at_each_lod = brw->gen == 6; mt->hiz_mt = intel_miptree_create(brw, mt->target, mt->format, @@ -1398,7 +1400,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw, true, mt->num_samples, INTEL_MIPTREE_TILING_ANY, - false); + force_all_slices_at_each_lod); if (!mt->hiz_mt) return false; |