wip: no piglit regressions, 1 fixgen6-layered-2

10 files changed, 115 insertions, 29 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 17a008c979..4f588e903c 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -739,12 +739,21 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
       /* Emit hiz buffer. */
       if (hiz) {
          struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt;
+         uint32_t offset = 0;
+
+         if (hiz_mt->array_spacing_lod0) {
+            offset = intel_region_get_aligned_offset(hiz_mt->region,
+                                                     hiz_mt->level[lod].level_x,
+                                                     hiz_mt->level[lod].level_y,
+                                                     false);
+         }
+
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 	 OUT_BATCH(hiz_mt->region->pitch - 1);
 	 OUT_RELOC(hiz_mt->region->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		   0);
+		   offset);
 	 ADVANCE_BATCH();
       } else {
 	 BEGIN_BATCH(3);
@@ -757,6 +766,24 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
       /* Emit stencil buffer. */
       if (separate_stencil) {
 	 struct intel_region *region = stencil_mt->region;
+         uint32_t offset = 0;
+
+         if (stencil_mt->array_spacing_lod0) {
+            if (stencil_mt->format == MESA_FORMAT_S_UINT8) {
+               /* Note: we can't compute the stencil offset using
+                * intel_region_get_aligned_offset(), because stencil_region claims
+                * that the region is untiled even though it's W tiled.
+                */
+               offset =
+                  stencil_mt->level[lod].level_y * stencil_mt->region->pitch +
+                  stencil_mt->level[lod].level_x * 64;
+            } else {
+               offset = intel_region_get_aligned_offset(stencil_mt->region,
+                                                        stencil_mt->level[lod].level_x,
+                                                        stencil_mt->level[lod].level_y,
+                                                        false);
+            }
+         }
 
 	 BEGIN_BATCH(3);
 	 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
@@ -768,7 +795,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
 	 OUT_BATCH(2 * region->pitch - 1);
 	 OUT_RELOC(region->bo,
 		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-		   0);
+		   offset);
 	 ADVANCE_BATCH();
       } else {
 	 BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 61a2eba2f5..fd6115771d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -204,14 +204,18 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
       if (mt->compressed)
 	 img_height /= mt->align_h;
 
+      if (mt->array_spacing_lod0) {
+         /* Compact arrays with separated miplevels */
+	 img_height *= depth;
+      }
+
       /* Because the images are packed better, the final offset
        * might not be the maximal one:
        */
       mt->total_height = MAX2(mt->total_height, y + img_height);
 
-      /* Layout_below: step right after second mipmap.
-       */
-      if (level == mt->first_level + 1) {
+      if (/*!mt->array_spacing_lod0 && */level == mt->first_level + 1) {
+         /* Layout_below: step right after second mipmap. */
 	 x += ALIGN(width, mt->align_w);
       } else {
 	 y += img_height;
@@ -239,6 +243,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
 				 struct intel_mipmap_tree *mt)
 {
    int h0, h1;
+   unsigned height = mt->physical_height0;
 
    h0 = ALIGN(mt->physical_height0, mt->align_h);
    h1 = ALIGN(minify(mt->physical_height0, 1), mt->align_h);
@@ -252,11 +257,24 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
    brw_miptree_layout_2d(mt);
 
    for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
+      unsigned img_height;
+      img_height = ALIGN(height, mt->align_h);
+      if (mt->compressed)
+         img_height /= mt->align_h;
+
       for (int q = 0; q < mt->physical_depth0; q++) {
-	 intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
+         if (mt->array_spacing_lod0) {
+            intel_miptree_set_image_offset(mt, level, q, 0, q * img_height);
+         } else {
+            intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
+         }
       }
+      //if (mt->array_spacing_lod0)
+      //   physical_qpitch = minify(physical_qpitch, 1);
+      height = minify(height, 1);
    }
-   mt->total_height = physical_qpitch * mt->physical_depth0;
+   if (!mt->array_spacing_lod0)
+      mt->total_height = physical_qpitch * mt->physical_depth0;
 
    align_cube(mt);
 }
@@ -302,9 +320,18 @@ void
 brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt)
 {
    bool multisampled = mt->num_samples > 1;
-   mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
-   mt->align_h =
-      intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
+
+   if (brw->gen == 6 && mt->array_spacing_lod0 /*&&
+       mt->format == MESA_FORMAT_S_UINT8*/) {
+      /* Align to size of W tile, 64x64. */
+      //mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
+      mt->align_w = 64;
+      mt->align_h = 64;
+   } else {
+      mt->align_w = intel_horizontal_texture_alignment_unit(brw, mt->format);
+      mt->align_h =
+         intel_vertical_texture_alignment_unit(brw, mt->format, multisampled);
+   }
 
    switch (mt->target) {
    case GL_TEXTURE_CUBE_MAP:
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 020610dfa7..90bd04b405 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -871,14 +871,23 @@ gen6_blorp_emit_depth_stencil_config(struct brw_context *brw,
 
    /* 3DSTATE_HIER_DEPTH_BUFFER */
    {
+      struct intel_mipmap_tree *hiz_mt = params->depth.mt->hiz_mt;
       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
+      uint32_t offset = 0;
+
+      if (hiz_mt->array_spacing_lod0) {
+         offset = intel_region_get_aligned_offset(hiz_mt->region,
+                                                  hiz_mt->level[lod].level_x,
+                                                  hiz_mt->level[lod].level_y,
+                                                  false);
+      }
 
       BEGIN_BATCH(3);
       OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
       OUT_BATCH(hiz_region->pitch - 1);
       OUT_RELOC(hiz_region->bo,
                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-                0);
+                offset);
       ADVANCE_BATCH();
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index d3650d26d2..4f350eb2a7 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -866,7 +866,8 @@ intel_renderbuffer_move_to_temp(struct brw_context *brw,
                                  width, height, depth,
                                  true,
                                  irb->mt->num_samples,
-                                 INTEL_MIPTREE_TILING_ANY);
+                                 INTEL_MIPTREE_TILING_ANY,
+                                 false);
 
    if (brw_is_hiz_depth_format(brw, new_mt->format)) {
       intel_miptree_alloc_hiz(brw, new_mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c9f5bb3c3d..f56d6c0c44 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -232,7 +232,8 @@ intel_miptree_create_layout(struct brw_context *brw,
                             GLuint height0,
                             GLuint depth0,
                             bool for_bo,
-                            GLuint num_samples)
+                            GLuint num_samples,
+                            bool force_array_spacing)
 {
    struct intel_mipmap_tree *mt = calloc(sizeof(*mt), 1);
    if (!mt)
@@ -351,6 +352,7 @@ intel_miptree_create_layout(struct brw_context *brw,
        _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL &&
        (brw->must_use_separate_stencil ||
 	(brw->has_separate_stencil && brw_is_hiz_depth_format(brw, format)))) {
+      bool separate_lods = brw->gen == 6;
       mt->stencil_mt = intel_miptree_create(brw,
                                             mt->target,
                                             MESA_FORMAT_S_UINT8,
@@ -361,7 +363,8 @@ intel_miptree_create_layout(struct brw_context *brw,
                                             mt->logical_depth0,
                                             true,
                                             num_samples,
-                                            INTEL_MIPTREE_TILING_ANY);
+                                            INTEL_MIPTREE_TILING_ANY,
+                                            separate_lods);
       if (!mt->stencil_mt) {
 	 intel_miptree_release(&mt);
 	 return NULL;
@@ -381,6 +384,9 @@ intel_miptree_create_layout(struct brw_context *brw,
       }
    }
 
+   if (force_array_spacing)
+      mt->array_spacing_lod0 = true;
+
    brw_miptree_layout(brw, mt);
 
    return mt;
@@ -494,7 +500,8 @@ intel_miptree_create(struct brw_context *brw,
 		     GLuint depth0,
 		     bool expect_accelerated_upload,
                      GLuint num_samples,
-                     enum intel_miptree_tiling_mode requested_tiling)
+                     enum intel_miptree_tiling_mode requested_tiling,
+                     bool force_array_spacing)
 {
    struct intel_mipmap_tree *mt;
    mesa_format tex_format = format;
@@ -541,7 +548,8 @@ intel_miptree_create(struct brw_context *brw,
    mt = intel_miptree_create_layout(brw, target, format,
 				      first_level, last_level, width0,
 				      height0, depth0,
-				      false, num_samples);
+                                    false, num_samples,
+                                    force_array_spacing);
    /*
     * pitch == 0 || height == 0  indicates the null texture
     */
@@ -645,7 +653,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
    mt = intel_miptree_create_layout(brw, GL_TEXTURE_2D, format,
                                     0, 0,
                                     width, height, 1,
-                                    true, 0 /* num_samples */);
+                                    true, 0, false);
    if (!mt) {
       free(region);
       return mt;
@@ -816,7 +824,7 @@ intel_miptree_create_for_renderbuffer(struct brw_context *brw,
 
    mt = intel_miptree_create(brw, GL_TEXTURE_2D, format, 0, 0,
 			     width, height, depth, true, num_samples,
-                             INTEL_MIPTREE_TILING_ANY);
+                             INTEL_MIPTREE_TILING_ANY, false);
    if (!mt)
       goto fail;
 
@@ -1248,7 +1256,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
                                      mt->logical_depth0,
                                      true,
                                      0 /* num_samples */,
-                                     INTEL_MIPTREE_TILING_Y);
+                                     INTEL_MIPTREE_TILING_Y,
+                                     false);
 
    /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
     *
@@ -1305,7 +1314,8 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
                                      mt->logical_depth0,
                                      true,
                                      0 /* num_samples */,
-                                     INTEL_MIPTREE_TILING_Y);
+                                     INTEL_MIPTREE_TILING_Y,
+                                     false);
 
    return mt->mcs_mt;
 }
@@ -1349,6 +1359,10 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
 			struct intel_mipmap_tree *mt)
 {
    assert(mt->hiz_mt == NULL);
+   bool separate_lods = brw->gen == 6;
+   enum intel_miptree_tiling_mode tiling =
+      separate_lods ? INTEL_MIPTREE_TILING_Y : INTEL_MIPTREE_TILING_ANY;
+   //tiling = INTEL_MIPTREE_TILING_ANY;
    mt->hiz_mt = intel_miptree_create(brw,
                                      mt->target,
                                      mt->format,
@@ -1359,7 +1373,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
                                      mt->logical_depth0,
                                      true,
                                      mt->num_samples,
-                                     INTEL_MIPTREE_TILING_ANY);
+                                     tiling,
+                                     separate_lods);
 
    if (!mt->hiz_mt)
       return false;
@@ -1785,7 +1800,8 @@ intel_miptree_map_blit(struct brw_context *brw,
                                   0, 0,
                                   map->w, map->h, 1,
                                   false, 0,
-                                  INTEL_MIPTREE_TILING_NONE);
+                                  INTEL_MIPTREE_TILING_NONE,
+                                  false);
    if (!map->mt) {
       fprintf(stderr, "Failed to allocate blit temporary\n");
       goto fail;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 0c0a3d316a..ec4f33eb13 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -505,7 +505,8 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
                                                GLuint depth0,
 					       bool expect_accelerated_upload,
                                                GLuint num_samples,
-                                               enum intel_miptree_tiling_mode);
+                                               enum intel_miptree_tiling_mode,
+                                               bool force_array_spacing);
 
 struct intel_mipmap_tree *
 intel_miptree_create_layout(struct brw_context *brw,
@@ -517,7 +518,8 @@ intel_miptree_create_layout(struct brw_context *brw,
                             GLuint height0,
                             GLuint depth0,
                             bool for_bo,
-                            GLuint num_samples);
+                            GLuint num_samples,
+                            bool force_array_spacing);
 
 struct intel_mipmap_tree *
 intel_miptree_create_for_bo(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/intel_tex.c b/src/mesa/drivers/dri/i965/intel_tex.c
index 0e08aab563..b416dc303d 100644
--- a/src/mesa/drivers/dri/i965/intel_tex.c
+++ b/src/mesa/drivers/dri/i965/intel_tex.c
@@ -145,7 +145,8 @@ intel_alloc_texture_storage(struct gl_context *ctx,
                                               width, height, depth,
                                               false, /* expect_accelerated */
                                               num_samples,
-                                              INTEL_MIPTREE_TILING_ANY);
+                                              INTEL_MIPTREE_TILING_ANY,
+                                              false);
 
    }
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index ee02e68978..c6f3e04e69 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -78,7 +78,8 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
 			       depth,
 			       expect_accelerated_upload,
                                intelImage->base.Base.NumSamples,
-                               INTEL_MIPTREE_TILING_ANY);
+                               INTEL_MIPTREE_TILING_ANY,
+                               false);
 }
 
 /* XXX: Do this for TexSubImage also:
@@ -233,7 +234,7 @@ intel_set_texture_image_region(struct gl_context *ctx,
    intel_image->mt = intel_miptree_create_layout(brw, target, image->TexFormat,
                                                  0, 0,
                                                  width, height, 1,
-                                                 true, 0 /* num_samples */);
+                                                 true, 0, false);
    if (intel_image->mt == NULL)
        return;
    intel_region_reference(&intel_image->mt->region, region);
diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
index 6942039fdc..c226440855 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c
@@ -129,7 +129,8 @@ intel_blit_texsubimage(struct gl_context * ctx,
       intel_miptree_create(brw, GL_TEXTURE_2D, texImage->TexFormat,
                            0, 0,
                            width, height, 1,
-                           false, 0, INTEL_MIPTREE_TILING_NONE);
+                           false, 0, INTEL_MIPTREE_TILING_NONE,
+                           false);
    if (!temp_mt)
       goto err;
 
diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index d8497a681e..eff970dc51 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -137,7 +137,8 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint unit)
                                           depth,
 					  true,
                                           0 /* num_samples */,
-                                          INTEL_MIPTREE_TILING_ANY);
+                                          INTEL_MIPTREE_TILING_ANY,
+                                          false);
       if (!intelObj->mt)
          return false;
    }