diff options
| author | Jordan Justen <jordan.l.justen@intel.com> | 2015-04-23 20:58:14 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2015-04-29 13:00:42 -0700 |
| commit | c528e865535e4a89b90ab80753c03844812de0eb (patch) | |
| tree | 05c3240f5e80c2838d19f722e3f7295016dd086a | |
| parent | 1cbfd50e612ff6049f57c295cedbfa517b29bb1d (diff) | |
i965: Don't spill payload header registerscs-29
When a register destination is a partial write or has force writemask
all set, then it is likely a payload header.
These registers should be spilled and filled with writemask all, but
instead we just exclude them from being spilled.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 999a9f1f58..12a1706df3 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -787,7 +787,9 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) if (inst->dst.file == GRF) { spill_costs[inst->dst.reg] += inst->regs_written * loop_scale; - if (!inst->dst.is_contiguous()) { + if (!inst->dst.is_contiguous() || + inst->is_partial_write() || + inst->force_writemask_all) { no_spill[inst->dst.reg] = true; } } |