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2012-09-06radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI.HEADmasterMichel Dänzer1-3/+8
Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06radeon: Memory footprint of SI mipmap base level is padded to powers of two.Michel Dänzer1-3/+10
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-05radeon: Fix layout of linear aligned mipmaps on SI.Michel Dänzer1-1/+123
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-24radeon: align r600 msaa buffers to a multiple of macrotile size * num samplesMarek Olšák1-1/+1
I am not sure whether this is needed, but better be safe than sorry.
2012-08-24radeon: fix allocation of MSAA surfaces on r600-r700Marek Olšák1-1/+1
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-14radeon: add prime import/export supportDave Airlie3-2/+52
this adds radeon version of the prime import/export support. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-08-09radeon: tweak TILE_SPLIT for MSAA surfacesMarek Olšák1-6/+31
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: force 2D tiling for MSAA surfacesMarek Olšák1-2/+22
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-09radeon: optimize allocation for depth w/o stencil and stencil w/o depth on EGMarek Olšák1-15/+8
If we don't need stencil, don't allocate it. If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth. v2: actually do it correctly Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-09radeon: simplify ZS buffer checking on r600Marek Olšák1-8/+1
Setting those flags has no effect anywhere else. Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-06radeon: add some new SI pci idsAlex Deucher1-0/+3
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-06radeon: add some missing evergreen pci idsAlex Deucher1-0/+3
Noticed by: Harald van Dijk <fdo@gigawatt.nl> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=53124 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-17radeon/surface: free version after using it.Dave Airlie1-0/+2
fixes leak in valgrind. Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-12radeon: force 1D array mode for z/stencil surfaceJerome Glisse1-0/+37
On r6xx or evergreen z/stencil surface don't support linear or linear aligned surface, force 1D tiled mode for those. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: enabled 2D tiling for evergreen only on fixed kernelJerome Glisse1-1/+1
Due to a kernel bug, enabled 2D tiling for evergreen only on newer fixed kernel. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-11radeon: always properly initialize stencil_offset fieldJerome Glisse1-3/+3
Reported-by: Vadim Girlin <vadimgirlin@gmail.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-06-07radeon: fall back to 1D tiling only with broken kernelsAlex Deucher1-7/+21
Certain cards report the the wrong bank setup which causes surface init to fail in the ddx and leads to no accel. If we hit an invalid tiling parameter, just set a default value and disable 2D tiling. Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=43448 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-06-05radeon: add new pci idsAlex Deucher1-5/+28
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-05-16radeon: Add Southern Islands PCI IDs.Michel Dänzer2-0/+44
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-05-10radeon: Add new R600 PCI ids for surface managerAnisse Astier1-0/+10
This is the same list of PCI ids added by Alex Deucher in xf86-video-ati commit aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3. This is needed since the addition of the surface allocator helper in commit c51f7f0e460dcadb9f1a56ecf1615810877c33c8 ; it needs to differentiate pre and post-R600 GPUs. Therefore we should maintain another PCI id list. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=48138 Signed-off-by: Anisse Astier <anisse@astier.eu> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-03-20radeon: add TN surface supportAlex Deucher2-0/+9
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-13radeon: fix pitch alignment for scanout bufferJerome Glisse1-1/+13
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-08radeon_cs_setup_bo: Fix accounting if caller specified write and read domains.Michel Dänzer1-6/+9
Only account for the write domain in that case. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=43893 . Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-02-06radeon: add r600_pci_ids.h to header fileJerome Glisse1-1/+2
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-03radeon: fix surface API for good before anyone start relying on itJerome Glisse2-20/+11
The mipmap level computation was wrong, we need to know the block width, height, depth of compressed texture to properly compute this. Change API to provide block width, height, depth instead of nblk_x, nblk_y, nblk_z. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-02radeon: surface fix macro -> micro tile fallbackJerome Glisse1-58/+67
We need to force 1D tiling only on old kernel the fallback was broken along the way. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-02-01radeon: add surface allocator helper v10Jerome Glisse4-0/+1382
The surface allocator is able to build complete miptree when allocating surface for r600/r700/evergreen/northern islands GPU family. It also compute bo size and alignment for render buffer, depth buffer and scanout buffer. v2 fix r6xx/r7xx 2D tiling width align computation v3 add tile split support and fix 1d texture alignment v4 rework to more properly support compressed format, split surface pixel size and surface element size in separate fields v5 support texture array (still issue on r6xx) v6 split surface value computation and mipmap tree building, rework eg and newer computation v7 add a check for tile split and 2d tiled v8 initialize mode value before testing it in all case, reenable 2D macro tile mode on r6xx for cubemap and array. Fix cubemap to force array size to the number of face. v9 fix handling of stencil buffer on evergreen v10 on evergreen depth buffer need to have enough room for a stencil buffer just after depth one Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-12-02radeon: silence valgrind warnings by zeroing memoryMarek Olšák2-2/+2
2010-06-10Fix radeon distcheck.Eric Anholt1-1/+2
2010-04-26radeon: use the const qualifier in radeon_cs_write_tableMarek Olšák1-1/+1
Signed-off-by: Marek Olšák <maraeo@gmail.com>
2010-04-08drm/radeon: add new cs command stream dumping facilitiesJerome Glisse4-5/+667
Dump command stream + associated bo into a binary file which follow a similar design as json file. It allows to intercept a command stream and replay it in a standalone program (see radeondb tools).
2010-03-29drm/radeon: tab/whitespace cleanupJerome Glisse1-5/+5
2010-03-17Install headers to $(includedir)/libdrmJulien Cristau2-2/+2
Avoids conflicts with kernel headers. Signed-off-by: Julien Cristau <jcristau@debian.org> Reviewed-by: Rémi Cardona <remi@gentoo.org> Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-17libdrm_radeon: Optimize cs_gem_reloc to do less looping.Pauli Nieminen6-32/+110
bo->referenced_in_cs is checked if bo is already in cs. Adding and removing reference in bo is done with atomic operations to allow parallel access to a bo from multiple contexts. cs->id generation code quarentees there is not duplicated ids which limits number of cs->ids to 32. If there is more cs objects rest will get id 0. V2: - Fix configure to check for atomics operations if libdrm_radeon is only selected. - Make atomic operations private to libdrm. This optimization decreases cs_write_reloc share of torcs profiling from 4.3% to 2.6%. Tested-by: Michel Dänzer <michel@daenzer.net> Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
2010-02-18radeon: add square-tiling flagMarek Olšák1-0/+1
2010-02-04libdrm/radeon: Fix section size mismatch to reset the section.Pauli Nieminen1-1/+4
If there is section size mismatch reusing the section object makes section start fail. Reseting the object before doing error checking prevents the possible flood of errors.
2010-02-02radeon: enable by default now that kms is out of stagingDave Airlie1-1/+1
2010-01-14radeon: get device id from the kernel, use it in cs_printJerome Glisse1-6/+27
This allow external tools to know for which asics a cs is destinated to.
2010-01-14radeon: simpler cs print functionJerome Glisse1-93/+4
We don't intend libdrm-radeon to become clever enough to decode cs for all GPU we support. Better to let an external tool do the job. This will print raw cs in an easy to parse way.
2010-01-14radeon: indentation + trailing space cleanupJerome Glisse1-20/+18
2010-01-14radeon: indentation & trailing space cleanupJerome Glisse8-165/+189
2010-01-14radeon: indentation + trailing space cleanupJerome Glisse1-11/+11
2009-12-21radeon: fix BO null check, should be in higher level fnDave Airlie2-3/+3
2009-12-21radeon: straighten out the API insanity.Dave Airlie12-647/+511
as Michel pointed out we are exposing too much info for these object for this to be maintainable going forward. This patch set minimises the exposed parts of the radeon_bo and radeon_cs objects to the piece necessary for ddx/mesa to operate at a decent speed. The major problem is mesa contains a legacy BO/CS managers which we still need to expose functionality to, and we really cannot change the API until we can drop the non-KMS codepaths. Signed-off-by: Dave Airlie <airlied@redhat.com>
2009-12-07radeon: Use drmIoctl so we restart ioctl on EINTR or EAGAINJerome Glisse1-4/+3
This is needed as change in kernel will lead to ioctl returning EINTR if they are interrupted. Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2009-11-20Merge remote branch 'origin/master' into libdrmKristian Høgsberg1-0/+14
2009-11-17Move libdrm/ up one levelKristian Høgsberg11-0/+1849
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