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authorLionel Landwerlin <lionel.g.landwerlin@intel.com>2023-05-09 11:34:05 +0300
committerLionel Landwerlin <lionel.g.landwerlin@intel.com>2023-05-11 15:24:03 +0300
commit73814050959ee5127328865e64c2faa5401daba2 (patch)
tree08cbe6a9e13808e7c82d3c15bd9ff937f41cf0a1
parent5a7520d2529204c5b9eaeaf17675a7fe1d7c1852 (diff)
anv: fixup workaround 16011411144
We're missing it for the memcpy with streamout Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 5cc4075f95 ("anv, iris: Add Wa_16011411144 for DG2") Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22930>
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c4
-rw-r--r--src/intel/vulkan/genX_gpu_memcpy.c17
2 files changed, 19 insertions, 2 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 24996940eff..8a2dae5815c 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3344,7 +3344,7 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer)
* 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_*
* state is not combined with other state changes.
*/
- if (intel_device_info_is_dg2(cmd_buffer->device->info)) {
+ if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
"before SO_BUFFER change WA");
@@ -3378,7 +3378,7 @@ genX(cmd_buffer_flush_gfx_state)(struct anv_cmd_buffer *cmd_buffer)
}
}
- if (intel_device_info_is_dg2(cmd_buffer->device->info)) {
+ if (intel_needs_workaround(cmd_buffer->device->info, 16011411144)) {
/* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_CS_STALL_BIT,
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c
index 19b97c284de..b903ac92c17 100644
--- a/src/intel/vulkan/genX_gpu_memcpy.c
+++ b/src/intel/vulkan/genX_gpu_memcpy.c
@@ -167,6 +167,17 @@ emit_so_memcpy(struct anv_batch *batch, struct anv_device *device,
});
+ /* Wa_16011411144:
+ *
+ * SW must insert a PIPE_CONTROL cmd before and after the
+ * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_*
+ * state is not combined with other state changes.
+ */
+ if (intel_needs_workaround(device->info, 16011411144)) {
+ anv_batch_emit(batch, GENX(PIPE_CONTROL), pc)
+ pc.CommandStreamerStallEnable = true;
+ }
+
anv_batch_emit(batch, GENX(3DSTATE_SO_BUFFER), sob) {
#if GFX_VER < 12
sob.SOBufferIndex = 0;
@@ -189,6 +200,12 @@ emit_so_memcpy(struct anv_batch *batch, struct anv_device *device,
sob.StreamOffset = 0;
}
+ if (intel_needs_workaround(device->info, 16011411144)) {
+ /* Wa_16011411144: also CS_STALL after touching SO_BUFFER change */
+ anv_batch_emit(batch, GENX(PIPE_CONTROL), pc)
+ pc.CommandStreamerStallEnable = true;
+ }
+
dw = anv_batch_emitn(batch, 5, GENX(3DSTATE_SO_DECL_LIST),
.StreamtoBufferSelects0 = (1 << 0),
.NumEntries0 = 1);