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authorChris Wilson <chris@chris-wilson.co.uk>2020-12-10 16:04:28 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2020-12-13 12:01:31 +0000
commit84786ef748a4ccb0165620075b1e502d0db0399b (patch)
tree91873fd385e5d7da950ce1bb52734dd55bb160d8
parent0d5c94d302fca711737ef3d17584b3e661066b93 (diff)
i915: Add gem_cancel
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
-rw-r--r--tests/Makefile.sources3
-rw-r--r--tests/i915/gem_cancel.c176
-rw-r--r--tests/meson.build1
3 files changed, 180 insertions, 0 deletions
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index b4a47262..8b23237a 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -461,6 +461,9 @@ gem_unref_active_buffers_SOURCES = i915/gem_unref_active_buffers.c
TESTS_progs += gem_userptr_blits
gem_userptr_blits_SOURCES = i915/gem_userptr_blits.c
+TESTS_progs += gem_cancel
+gem_cancel_SOURCES = i915/gem_cancel.c
+
TESTS_progs += gem_wait
gem_wait_SOURCES = i915/gem_wait.c
diff --git a/tests/i915/gem_cancel.c b/tests/i915/gem_cancel.c
new file mode 100644
index 00000000..de4a4698
--- /dev/null
+++ b/tests/i915/gem_cancel.c
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include <unistd.h>
+
+#include "drmtest.h"
+#include "i915/gem.h"
+#include "i915/gem_engine_topology.h"
+#include "igt_core.h"
+#include "igt_dummyload.h"
+#include "ioctl_wrappers.h"
+#include "sw_sync.h"
+
+#define DRM_I915_GEM_CANCEL 0x3c
+#define DRM_IOCTL_I915_GEM_CANCEL DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CANCEL, struct drm_i915_gem_cancel)
+struct drm_i915_gem_cancel {
+ __u32 handle;
+ __u32 flags;
+#define CANCEL_SYNCOBJ (1 << 0)
+};
+
+static int __gem_cancel(int i915, uint32_t handle, uint32_t flags)
+{
+ struct drm_i915_gem_cancel arg = {
+ .handle = handle,
+ .flags = flags,
+ };
+ int err;
+
+ err = 0;
+ if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_CANCEL, &arg)) {
+ err = -errno;
+ igt_assume(err);
+ }
+
+ errno = 0;
+ return err;
+}
+
+static void gem_cancel(int i915, uint32_t handle, uint32_t flags)
+{
+ igt_assert_eq(__gem_cancel(i915, handle, flags), 0);
+}
+
+static bool has_cancel(int i915)
+{
+ return __gem_cancel(i915, -1, 0) == -ENOENT;
+}
+
+static void test_active(int i915, unsigned int engine)
+{
+ igt_spin_t *spin;
+
+ spin = igt_spin_new(i915,
+ .engine = engine,
+ .flags = IGT_SPIN_POLL_RUN | IGT_SPIN_FENCE_OUT);
+ igt_spin_busywait_until_started(spin);
+
+ gem_cancel(i915, spin->out_fence, 0);
+ igt_assert_eq(sync_fence_wait(spin->out_fence, 50), 0);
+ igt_assert_eq(sync_fence_status(spin->out_fence), -EINTR);
+
+ igt_spin_free(i915, spin);
+}
+
+static void test_signaled(int i915, unsigned int engine)
+{
+ igt_spin_t *spin;
+
+ spin = igt_spin_new(i915,
+ .engine = engine,
+ .flags = IGT_SPIN_POLL_RUN | IGT_SPIN_FENCE_OUT);
+ igt_spin_busywait_until_started(spin);
+ igt_spin_end(spin);
+ igt_assert_eq(sync_fence_wait(spin->out_fence, 50), 0);
+
+ gem_cancel(i915, spin->out_fence, 0);
+ igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+
+ igt_spin_free(i915, spin);
+}
+
+static void test_unready(int i915, unsigned int engine)
+{
+ igt_spin_t *spin[2];
+
+ spin[0] = igt_spin_new(i915,
+ .engine = engine,
+ .flags = IGT_SPIN_POLL_RUN);
+ igt_spin_busywait_until_started(spin[0]);
+
+ spin[1] = igt_spin_new(i915,
+ .engine = engine,
+ .flags = IGT_SPIN_FENCE_OUT);
+
+ gem_cancel(i915, spin[1]->out_fence, 0);
+ igt_spin_end(spin[0]);
+
+ igt_assert_eq(sync_fence_wait(spin[1]->out_fence, 50), 0);
+ igt_assert_eq(sync_fence_status(spin[1]->out_fence), -EINTR);
+
+ igt_spin_free(i915, spin[1]);
+ igt_spin_free(i915, spin[0]);
+}
+
+static void test_parallel(int i915)
+{
+ struct intel_execution_engine2 *e;
+ igt_spin_t *spin;
+ int first = -1;
+ int last = -1;
+
+ __for_each_physical_engine(i915, e) {
+ spin = igt_spin_new(i915,
+ .engine = e->flags,
+ .fence = last,
+ .flags = (IGT_SPIN_POLL_RUN |
+ IGT_SPIN_FENCE_OUT |
+ IGT_SPIN_FENCE_SUBMIT));
+ igt_spin_busywait_until_started(spin);
+
+ last = spin->out_fence;
+ if (first == -1)
+ first = last;
+ }
+ igt_require(first != -1);
+
+ gem_cancel(i915, first, 0);
+ igt_assert_eq(sync_fence_wait(last, 50), 0);
+ igt_assert_eq(sync_fence_status(last), -EINTR);
+
+ gem_quiescent_gpu(i915);
+}
+
+igt_main
+{
+ struct intel_execution_engine2 *e;
+ int i915;
+
+ igt_fixture {
+ i915 = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(i915);
+
+ igt_require(has_cancel(i915));
+ }
+
+ igt_subtest_with_dynamic("active") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ test_active(i915, e->flags);
+ }
+ }
+
+ igt_subtest_with_dynamic("signaled") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ test_signaled(i915, e->flags);
+ }
+ }
+
+ igt_subtest_with_dynamic("unready") {
+ __for_each_physical_engine(i915, e) {
+ igt_dynamic_f("%s", e->name)
+ test_unready(i915, e->flags);
+ }
+ }
+
+ igt_subtest("parallel")
+ test_parallel(i915);
+
+ igt_fixture {
+ close(i915);
+ }
+}
diff --git a/tests/meson.build b/tests/meson.build
index 86dbae95..b77627e8 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -121,6 +121,7 @@ i915_progs = [
'gem_blits',
'gem_busy',
'gem_caching',
+ 'gem_cancel',
'gem_close',
'gem_close_race',
'gem_concurrent_blit',