diff options
author | Mikita Lipski <mikita.lipski@amd.com> | 2017-12-18 16:45:12 -0500 |
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committer | Harry Wentland <harry.wentland@amd.com> | 2018-02-15 09:23:17 -0500 |
commit | 334a6e1472324c19f34b563cd217909933175c8c (patch) | |
tree | deb4724d1ac384ab8ad9bb92a2da9b219cfa66f2 | |
parent | e68545c970c6be5397476e862fe1c2c662f347d8 (diff) |
drm/amd/display: AMD VSDB PARSERmdvsync
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 70 |
1 files changed, 66 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb1872782fb5..807cf2e13a9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2353,6 +2353,70 @@ static void set_master_stream(struct dc_stream_state *stream_set[], } } +bool dm_helpers_parse_amd_vsdb(struct edid *edid) +{ + uint8_t *edid_ext = NULL; + unsigned int start, finish, i, j; + uint8_t *disp_block; + unsigned int disp_block_len; + uint8_t ieeeID; + uint8_t masked_counter = 0; + + if (edid == NULL || edid->extensions == 0) + return false; + + for (i = 0; i < edid->extensions; ++i) { + edid_ext = (uint8_t *)edid + (EDID_LENGTH * (i + 1)); + if (edid_ext[0] == CEA_EXT) + break; + } + + start = 4; + finish = (unsigned int)edid_ext[2]; + + if (finish == 0) + finish = 127; + + if (finish < 4 || finish > 127) + return false; + + if (i == edid->extensions) + return false; + + j = start; + + if (!edid_ext[j]) + return false; + + masked_counter = edid_ext[j] & 0x1f; + + if (masked_counter == 0) + return false; + + for (j = start; (j < finish) && (j + masked_counter) < finish; j += (masked_counter + 1)) { + masked_counter = edid_ext[j] & 0x1f; + + if (&edid_ext[j] == NULL) + return false; + + disp_block = &(edid_ext[j]); + disp_block_len = ((unsigned int)masked_counter); + + if (disp_block_len < 5) + continue; + + ieeeID = disp_block[1] | disp_block[2] | disp_block[3]; + + if (ieeeID == 26) { + if (((disp_block[5] & 8) == 8) && ((disp_block[14] & 1) == 1)) + return true; + } + + } + + return false; +} + static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) { int i = 0; @@ -2362,10 +2426,8 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) for (i = 0; i < context->stream_count ; i++) { if (!context->streams[i]) continue; - /* TODO: add a function to read AMD VSDB bits and will set - * crtc_sync_master.multi_sync_enabled flag - * For now its set to false - */ + context->streams[i]->triggered_crtc_reset.enabled = + dm_helpers_parse_amd_vsdb((struct edid *) context->streams[i]->sink->dc_edid.raw_edid); set_multisync_trigger_params(context->streams[i]); } set_master_stream(context->streams, context->stream_count); |