i965: Use device_info instead of the context for computing vue maps

Reviewed-by: Matt Turner <mattst88@gmail.com>

4 files changed, 12 insertions, 7 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 3707fd0386..57249321c0 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -507,7 +507,8 @@ static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map,
    return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
 }
 
-void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
+void brw_compute_vue_map(const struct brw_device_info *devinfo,
+                         struct brw_vue_map *vue_map,
                          GLbitfield64 slots_valid);
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5f83470ea9..2725270864 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1793,7 +1793,7 @@ fs_visitor::calculate_urb_setup()
           * (geometry or vertex shader).
           */
          struct brw_vue_map prev_stage_vue_map;
-         brw_compute_vue_map(brw, &prev_stage_vue_map,
+         brw_compute_vue_map(devinfo, &prev_stage_vue_map,
                              key->input_slots_valid);
          int first_slot = 2 * BRW_SF_URB_ENTRY_READ_OFFSET;
          assert(prev_stage_vue_map.num_slots <= first_slot + 32);
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index bea90d8d60..74be9c4a7c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -126,7 +126,8 @@ brw_compile_gs_prog(struct brw_context *brw,
       outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1);
    }
 
-   brw_compute_vue_map(brw, &c.prog_data.base.vue_map, outputs_written);
+   brw_compute_vue_map(brw->intelScreen->devinfo,
+                       &c.prog_data.base.vue_map, outputs_written);
 
    /* Compute the output vertex size.
     *
@@ -248,7 +249,8 @@ brw_compile_gs_prog(struct brw_context *brw,
    c.prog_data.output_topology =
       get_hw_prim_for_gl_prim(gp->program.OutputType);
 
-   brw_compute_vue_map(brw, &c.input_vue_map, c.key.input_varyings);
+   brw_compute_vue_map(brw->intelScreen->devinfo,
+                       &c.input_vue_map, c.key.input_varyings);
 
    /* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
     * need to program a URB read length of ceiling(num_slots / 2).
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index dabff43a6e..2ff1a67477 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -54,7 +54,8 @@ static inline void assign_vue_slot(struct brw_vue_map *vue_map,
  * Compute the VUE map for vertex shader program.
  */
 void
-brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
+brw_compute_vue_map(const struct brw_device_info *devinfo,
+                    struct brw_vue_map *vue_map,
                     GLbitfield64 slots_valid)
 {
    vue_map->slots_valid = slots_valid;
@@ -82,7 +83,7 @@ brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
    /* VUE header: format depends on chip generation and whether clipping is
     * enabled.
     */
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       /* There are 8 dwords in VUE header pre-Ironlake:
        * dword 0-3 is indices, point width, clip flags.
        * dword 4-7 is ndc position
@@ -279,7 +280,8 @@ brw_compile_vs_prog(struct brw_context *brw,
       outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1);
    }
 
-   brw_compute_vue_map(brw, &prog_data.base.vue_map, outputs_written);
+   brw_compute_vue_map(brw->intelScreen->devinfo,
+                       &prog_data.base.vue_map, outputs_written);
 
    if (0) {
       _mesa_fprint_program_opt(stderr, &c.vp->program.Base, PROG_PRINT_DEBUG,