i965: Add a devinfo field to backend_visitor and use it for gen checks

Reviewed-by: Matt Turner <mattst88@gmail.com>

19 files changed, 225 insertions, 221 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index cf1c385f09..5f83470ea9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -313,7 +313,7 @@ fs_inst *
 fs_visitor::IF(const fs_reg &src0, const fs_reg &src1,
                enum brw_conditional_mod condition)
 {
-   assert(brw->gen == 6);
+   assert(devinfo->gen == 6);
    fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF, dispatch_width,
                                         reg_null_d, src0, src1);
    inst->conditional_mod = condition;
@@ -405,7 +405,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
                               varying_offset, fs_reg(const_offset & ~3)));
 
    int scale = 1;
-   if (brw->gen == 4 && dst.width == 8) {
+   if (devinfo->gen == 4 && dst.width == 8) {
       /* Pre-gen5, we can either use a SIMD8 message that requires (header,
        * u, v, r) as parameters, or we can just use the SIMD16 message
        * consisting of (header, u).  We choose the second, at the cost of a
@@ -415,7 +415,7 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
    }
 
    enum opcode op;
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
       op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
    else
       op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
@@ -428,10 +428,10 @@ fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
    inst->regs_written = regs_written;
    instructions.push_tail(inst);
 
-   if (brw->gen < 7) {
+   if (devinfo->gen < 7) {
       inst->base_mrf = 13;
       inst->header_present = true;
-      if (brw->gen == 4)
+      if (devinfo->gen == 4)
          inst->mlen = 3;
       else
          inst->mlen = 1 + dispatch_width / 8;
@@ -517,9 +517,9 @@ fs_inst::is_send_from_grf() const
 }
 
 bool
-fs_inst::can_do_source_mods(struct brw_context *brw)
+fs_inst::can_do_source_mods(const struct brw_device_info *devinfo)
 {
-   if (brw->gen == 6 && is_math())
+   if (devinfo->gen == 6 && is_math())
       return false;
 
    if (is_send_from_grf())
@@ -689,7 +689,7 @@ fs_visitor::type_size(const struct glsl_type *type)
 fs_reg
 fs_visitor::get_timestamp(fs_inst **out_mov)
 {
-   assert(brw->gen >= 7);
+   assert(devinfo->gen >= 7);
 
    fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE,
                                           BRW_ARF_TIMESTAMP,
@@ -1261,7 +1261,7 @@ fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer,
    wpos = offset(wpos, 1);
 
    /* gl_FragCoord.z */
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       emit(MOV(wpos, fs_reg(brw_vec8_grf(payload.source_depth_reg, 0))));
    } else {
       emit(FS_OPCODE_LINTERP, wpos,
@@ -1282,7 +1282,7 @@ fs_visitor::emit_linterp(const fs_reg &attr, const fs_reg &interp,
                          bool is_centroid, bool is_sample)
 {
    brw_wm_barycentric_interp_mode barycoord_mode;
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       if (is_centroid) {
          if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
             barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
@@ -1372,7 +1372,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
 	    /* Smooth/noperspective interpolation case. */
 	    for (unsigned int k = 0; k < type->vector_elements; k++) {
                struct brw_reg interp = interp_reg(location, k);
-               if (brw->needs_unlit_centroid_workaround && mod_centroid) {
+               if (devinfo->needs_unlit_centroid_workaround && mod_centroid) {
                   /* Get the pixel/sample mask into f0 so that we know
                    * which pixels are lit.  Then, for each channel that is
                    * unlit, replace the centroid data with non-centroid
@@ -1385,7 +1385,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                       false, false);
                   inst->predicate = BRW_PREDICATE_NORMAL;
                   inst->predicate_inverse = true;
-                  if (brw->has_pln)
+                  if (devinfo->has_pln)
                      inst->no_dd_clear = true;
 
                   inst = emit_linterp(attr, fs_reg(interp), interpolation_mode,
@@ -1393,7 +1393,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                       mod_sample || key->persample_shading);
                   inst->predicate = BRW_PREDICATE_NORMAL;
                   inst->predicate_inverse = false;
-                  if (brw->has_pln)
+                  if (devinfo->has_pln)
                      inst->no_dd_check = true;
 
                } else {
@@ -1401,7 +1401,7 @@ fs_visitor::emit_general_interpolation(fs_reg attr, const char *name,
                                mod_centroid && !key->persample_shading,
                                mod_sample || key->persample_shading);
                }
-               if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
+               if (devinfo->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
                   emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
                }
 	       attr = offset(attr, 1);
@@ -1418,7 +1418,7 @@ fs_visitor::emit_frontfacing_interpolation()
 {
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::bool_type));
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
        * a boolean result from this (~0/true or 0/false).
        *
@@ -1480,7 +1480,7 @@ fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
 fs_reg *
 fs_visitor::emit_samplepos_setup()
 {
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    this->current_annotation = "compute sample position";
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::vec2_type));
@@ -1531,7 +1531,7 @@ fs_visitor::emit_sampleid_setup()
 {
    assert(stage == MESA_SHADER_FRAGMENT);
    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    this->current_annotation = "compute sample id";
    fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::int_type));
@@ -1607,14 +1607,14 @@ fs_visitor::fix_math_operand(fs_reg src)
     * The hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (brw->gen == 6 && src.file != UNIFORM && src.file != IMM &&
+   if (devinfo->gen == 6 && src.file != UNIFORM && src.file != IMM &&
        !src.abs && !src.negate)
       return src;
 
    /* Gen7 relaxes most of the above restrictions, but still can't use IMM
     * operands to math
     */
-   if (brw->gen >= 7 && src.file != IMM)
+   if (devinfo->gen >= 7 && src.file != IMM)
       return src;
 
    fs_reg expanded = vgrf(glsl_type::float_type);
@@ -1647,12 +1647,12 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
     * Gen 6 hardware ignores source modifiers (negate and abs) on math
     * instructions, so we also move to a temp to set those up.
     */
-   if (brw->gen == 6 || brw->gen == 7)
+   if (devinfo->gen == 6 || devinfo->gen == 7)
       src = fix_math_operand(src);
 
    fs_inst *inst = emit(opcode, dst, src);
 
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       inst->base_mrf = 2;
       inst->mlen = dispatch_width / 8;
    }
@@ -1666,9 +1666,9 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
    int base_mrf = 2;
    fs_inst *inst;
 
-   if (brw->gen >= 8) {
+   if (devinfo->gen >= 8) {
       inst = emit(opcode, dst, src0, src1);
-   } else if (brw->gen >= 6) {
+   } else if (devinfo->gen >= 6) {
       src0 = fix_math_operand(src0);
       src1 = fix_math_operand(src1);
 
@@ -1768,7 +1768,7 @@ fs_visitor::calculate_urb_setup()
 
    int urb_next = 0;
    /* Figure out where each of the incoming setup attributes lands. */
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       if (_mesa_bitcount_64(prog->InputsRead &
                             BRW_FS_VARYING_INPUT_MASK) <= 16) {
          /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
@@ -2548,7 +2548,7 @@ fs_visitor::opt_sampler_eot()
 {
    brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
 
-   if (brw->gen < 9 && !brw->is_cherryview)
+   if (devinfo->gen < 9 && !devinfo->is_cherryview)
       return false;
 
    /* FINISHME: It should be possible to implement this optimization when there
@@ -2732,7 +2732,7 @@ fs_visitor::compute_to_mrf()
    int next_ip = 0;
 
    /* No MRFs on Gen >= 7. */
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
       return false;
 
    calculate_live_intervals();
@@ -2797,7 +2797,7 @@ fs_visitor::compute_to_mrf()
 	    if (scan_inst->mlen)
 	       break;
 
-	    if (brw->gen == 6) {
+	    if (devinfo->gen == 6) {
 	       /* gen6 math instructions must have the destination be
 		* GRF, so no compute-to-MRF for them.
 		*/
@@ -3164,7 +3164,7 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins
 void
 fs_visitor::insert_gen4_send_dependency_workarounds()
 {
-   if (brw->gen != 4 || brw->is_g4x)
+   if (devinfo->gen != 4 || devinfo->is_g4x)
       return;
 
    bool progress = false;
@@ -3208,7 +3208,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
       if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
          continue;
 
-      if (brw->gen >= 7) {
+      if (devinfo->gen >= 7) {
          /* The offset arg before was a vec4-aligned byte offset.  We need to
           * turn it into a dword offset.
           */
@@ -3221,7 +3221,7 @@ fs_visitor::lower_uniform_pull_constant_loads()
          /* We have to use a message header on Skylake to get SIMD4x2 mode.
           * Reserve space for the register.
           */
-         if (brw->gen >= 9) {
+         if (devinfo->gen >= 9) {
             payload.reg_offset++;
             alloc.sizes[payload.reg] = 2;
          }
@@ -3306,7 +3306,7 @@ fs_visitor::lower_load_payload()
                /* Do nothing but otherwise increment as normal */
             } else if (dst.file == MRF &&
                        dst.width == 8 &&
-                       brw->has_compr4 &&
+                       devinfo->has_compr4 &&
                        i + 4 < inst->sources &&
                        inst->src[i + 4].equals(horiz_offset(inst->src[i], 8))) {
                fs_reg compr4_dst = dst;
@@ -3427,7 +3427,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
    if (inst->conditional_mod) {
       fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
       if (!inst->predicate &&
-          (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+          (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
                               inst->opcode != BRW_OPCODE_IF &&
                               inst->opcode != BRW_OPCODE_WHILE))) {
          fprintf(file, ".f0.%d", inst->flag_subreg);
@@ -3646,7 +3646,7 @@ fs_visitor::setup_payload_gen6()
       (stage == MESA_SHADER_FRAGMENT) ?
       ((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0;
 
-   assert(brw->gen >= 6);
+   assert(devinfo->gen >= 6);
 
    /* R0-1: masks, pixel X/Y coordinates. */
    payload.num_regs = 2;
@@ -3701,7 +3701,7 @@ fs_visitor::setup_payload_gen6()
 
    /* R32: MSAA input coverage mask */
    if (prog->SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) {
-      assert(brw->gen >= 7);
+      assert(devinfo->gen >= 7);
       payload.sample_mask_in_reg = payload.num_regs;
       payload.num_regs++;
       if (dispatch_width == 16) {
@@ -3978,7 +3978,7 @@ fs_visitor::run_fs()
 
    assign_binding_table_offsets();
 
-   if (brw->gen >= 6)
+   if (devinfo->gen >= 6)
       setup_payload_gen6();
    else
       setup_payload_gen4();
@@ -3993,7 +3993,7 @@ fs_visitor::run_fs()
 
       calculate_urb_setup();
       if (prog->InputsRead > 0) {
-         if (brw->gen < 6)
+         if (devinfo->gen < 6)
             emit_interpolation_setup_gen4();
          else
             emit_interpolation_setup_gen6();
diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
index ebde8df2ff..a51b726d4a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp
@@ -42,9 +42,9 @@
  * replaced with a GRF source.
  */
 static bool
-could_coissue(const struct brw_context *brw, const fs_inst *inst)
+could_coissue(const struct brw_device_info *devinfo, const fs_inst *inst)
 {
-   if (brw->gen != 7)
+   if (devinfo->gen != 7)
       return false;
 
    switch (inst->opcode) {
@@ -207,7 +207,7 @@ fs_visitor::opt_combine_constants()
    foreach_block_and_inst(block, fs_inst, inst, cfg) {
       ip++;
 
-      if (!could_coissue(brw, inst) && !must_promote_imm(inst))
+      if (!could_coissue(devinfo, inst) && !must_promote_imm(inst))
          continue;
 
       for (int i = 0; i < inst->sources; i++) {
@@ -224,7 +224,7 @@ fs_visitor::opt_combine_constants()
                imm->inst = NULL;
             imm->block = intersection;
             imm->uses->push_tail(link(const_ctx, &inst->src[i]));
-            imm->uses_by_coissue += could_coissue(brw, inst);
+            imm->uses_by_coissue += could_coissue(devinfo, inst);
             imm->must_promote = imm->must_promote || must_promote_imm(inst);
             imm->last_use_ip = ip;
          } else {
@@ -234,7 +234,7 @@ fs_visitor::opt_combine_constants()
             imm->uses = new(const_ctx) exec_list();
             imm->uses->push_tail(link(const_ctx, &inst->src[i]));
             imm->val = val;
-            imm->uses_by_coissue = could_coissue(brw, inst);
+            imm->uses_by_coissue = could_coissue(devinfo, inst);
             imm->must_promote = must_promote_imm(inst);
             imm->first_use_ip = ip;
             imm->last_use_ip = ip;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index 6a8e7bf5b5..6b6565fec2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
@@ -325,7 +325,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
 
    if ((has_source_modifiers || entry->src.file == UNIFORM ||
         !entry->src.is_contiguous()) &&
-       !inst->can_do_source_mods(brw))
+       !inst->can_do_source_mods(devinfo))
       return false;
 
    if (has_source_modifiers &&
@@ -361,7 +361,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
        !can_change_source_types(inst))
       return false;
 
-   if (brw->gen >= 8 && (entry->src.negate || entry->src.abs) &&
+   if (devinfo->gen >= 8 && (entry->src.negate || entry->src.abs) &&
        is_logic_op(inst->opcode)) {
       return false;
    }
@@ -479,14 +479,14 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
       val.type = inst->src[i].type;
 
       if (inst->src[i].abs) {
-         if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+         if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
              !brw_abs_immediate(val.type, &val.fixed_hw_reg)) {
             continue;
          }
       }
 
       if (inst->src[i].negate) {
-         if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+         if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
              !brw_negate_immediate(val.type, &val.fixed_hw_reg)) {
             continue;
          }
@@ -502,7 +502,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
       case SHADER_OPCODE_POW:
       case SHADER_OPCODE_INT_QUOTIENT:
       case SHADER_OPCODE_INT_REMAINDER:
-         if (brw->gen < 8)
+         if (devinfo->gen < 8)
             break;
          /* fallthrough */
       case BRW_OPCODE_BFI1:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 21d677a45a..6518ff60c3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -251,7 +251,7 @@ fs_visitor::emit_fragment_program_code()
             cmp->predicate = BRW_PREDICATE_NORMAL;
             cmp->flag_subreg = 1;
 
-            if (brw->gen >= 6)
+            if (devinfo->gen >= 6)
                emit_discard_jump();
          }
          break;
@@ -319,7 +319,7 @@ fs_visitor::emit_fragment_program_code()
       case OPCODE_MAD:
          for (int i = 0; i < 4; i++) {
             if (fpi->DstReg.WriteMask & (1 << i)) {
-               if (brw->gen >= 6) {
+               if (devinfo->gen >= 6) {
                   emit(MAD(offset(dst, i), offset(src[2], i),
                            offset(src[1], i), offset(src[0], i)));
                } else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index f2f78be5e8..0dcbc3b467 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -324,7 +324,7 @@ emit_system_values_block(nir_block *block, void *void_visitor)
 
       case nir_intrinsic_load_sample_mask_in:
          assert(v->stage == MESA_SHADER_FRAGMENT);
-         assert(v->brw->gen >= 7);
+         assert(v->devinfo->gen >= 7);
          reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
          if (reg->file == BAD_FILE)
             *reg = fs_reg(retype(brw_vec8_grf(v->payload.sample_mask_in_reg, 0),
@@ -408,7 +408,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
 
    emit(BRW_OPCODE_ENDIF);
 
-   if (!try_replace_with_sel() && brw->gen < 6) {
+   if (!try_replace_with_sel() && devinfo->gen < 6) {
       no16("Can't support (non-uniform) control flow on SIMD16\n");
    }
 }
@@ -416,7 +416,7 @@ fs_visitor::nir_emit_if(nir_if *if_stmt)
 void
 fs_visitor::nir_emit_loop(nir_loop *loop)
 {
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       no16("Can't support (non-uniform) control flow on SIMD16\n");
    }
 
@@ -517,7 +517,7 @@ fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
 
    fs_reg tmp = vgrf(glsl_type::int_type);
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
       fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
 
@@ -785,7 +785,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
       break;
 
    case nir_op_imul: {
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          emit(MUL(result, op[0], op[1]));
          break;
       } else {
@@ -793,14 +793,14 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
          nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
 
          if (value0 && value0->u[0] < (1 << 16)) {
-            if (brw->gen < 7) {
+            if (devinfo->gen < 7) {
                emit(MUL(result, op[0], op[1]));
             } else {
                emit(MUL(result, op[1], op[0]));
             }
             break;
          } else if (value1 && value1->u[0] < (1 << 16)) {
-            if (brw->gen < 7) {
+            if (devinfo->gen < 7) {
                emit(MUL(result, op[1], op[0]));
             } else {
                emit(MUL(result, op[0], op[1]));
@@ -809,7 +809,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
          }
       }
 
-      if (brw->gen >= 7)
+      if (devinfo->gen >= 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
@@ -822,7 +822,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
 
    case nir_op_imul_high:
    case nir_op_umul_high: {
-      if (brw->gen >= 7)
+      if (devinfo->gen >= 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
@@ -838,7 +838,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
       break;
 
    case nir_op_uadd_carry: {
-      if (brw->gen >= 7)
+      if (devinfo->gen >= 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -850,7 +850,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
    }
 
    case nir_op_usub_borrow: {
-      if (brw->gen >= 7)
+      if (devinfo->gen >= 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -888,27 +888,27 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
       break;
 
    case nir_op_inot:
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          resolve_source_modifiers(&op[0]);
       }
       emit(NOT(result, op[0]));
       break;
    case nir_op_ixor:
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          resolve_source_modifiers(&op[0]);
          resolve_source_modifiers(&op[1]);
       }
       emit(XOR(result, op[0], op[1]));
       break;
    case nir_op_ior:
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          resolve_source_modifiers(&op[0]);
          resolve_source_modifiers(&op[1]);
       }
       emit(OR(result, op[0], op[1]));
       break;
    case nir_op_iand:
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          resolve_source_modifiers(&op[0]);
          resolve_source_modifiers(&op[1]);
       }
@@ -1013,7 +1013,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
    case nir_op_fmin:
    case nir_op_imin:
    case nir_op_umin:
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          inst = emit(BRW_OPCODE_SEL, result, op[0], op[1]);
          inst->conditional_mod = BRW_CONDITIONAL_L;
       } else {
@@ -1027,7 +1027,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
    case nir_op_fmax:
    case nir_op_imax:
    case nir_op_umax:
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          inst = emit(BRW_OPCODE_SEL, result, op[0], op[1]);
          inst->conditional_mod = BRW_CONDITIONAL_GE;
       } else {
@@ -1148,7 +1148,7 @@ fs_visitor::nir_emit_alu(nir_alu_instr *instr)
    /* If we need to do a boolean resolve, replace the result with -(x & 1)
     * to sign extend the low bit to 0/~0
     */
-   if (brw->gen <= 5 &&
+   if (devinfo->gen <= 5 &&
        (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
       fs_reg masked = vgrf(glsl_type::int_type);
       emit(AND(masked, result, fs_reg(1)));
@@ -1257,7 +1257,7 @@ fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
       cmp->predicate = BRW_PREDICATE_NORMAL;
       cmp->flag_subreg = 1;
 
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          emit_discard_jump();
       }
       break;
@@ -1676,7 +1676,7 @@ fs_visitor::nir_emit_texture(nir_tex_instr *instr)
       case nir_tex_src_sampler_offset: {
          /* Figure out the highest possible sampler index and mark it as used */
          uint32_t max_used = sampler + instr->sampler_array_size - 1;
-         if (instr->op == nir_texop_tg4 && brw->gen < 8) {
+         if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
             max_used += stage_prog_data->binding_table.gather_texture_start;
          } else {
             max_used += stage_prog_data->binding_table.texture_start;
@@ -1696,7 +1696,7 @@ fs_visitor::nir_emit_texture(nir_tex_instr *instr)
    }
 
    if (instr->op == nir_texop_txf_ms) {
-      if (brw->gen >= 7 &&
+      if (devinfo->gen >= 7 &&
           key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
          mcs = emit_mcs_fetch(coordinate, instr->coord_components, sampler_reg);
       } else {
diff --git a/src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp b/src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp
index 047c2c0b1c..cf3da7b188 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp
@@ -84,7 +84,7 @@ fs_visitor::opt_peephole_predicated_break()
       /* For Sandybridge with IF with embedded comparison we need to emit an
        * instruction to set the flag register.
        */
-      if (brw->gen == 6 && if_inst->conditional_mod) {
+      if (devinfo->gen == 6 && if_inst->conditional_mod) {
          fs_inst *cmp_inst = CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
                                  if_inst->conditional_mod);
          if_inst->insert_before(if_block, cmp_inst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 47f5a42b18..92d29a4d53 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -390,7 +390,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
           * in the arguments.  Pre-gen6, the deltas are computed in normal
           * VGRFs.
           */
-         if (brw->gen >= 6) {
+         if (devinfo->gen >= 6) {
             int delta_x_arg = 0;
             if (inst->src[delta_x_arg].file == HW_REG &&
                 inst->src[delta_x_arg].fixed_hw_reg.file ==
@@ -443,7 +443,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
        * The alternative would be to have per-physical-register classes, which
        * would just be silly.
        */
-      if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) {
+      if (devinfo->gen <= 5 && dispatch_width == 16) {
          /* We have to divide by 2 here because we only have even numbered
           * registers.  Some of the payload registers will be odd, but
           * that's ok because their physical register numbers have already
@@ -541,7 +541,7 @@ fs_visitor::assign_regs(bool allow_spilling)
    int first_payload_node = node_count;
    node_count += payload_node_count;
    int first_mrf_hack_node = node_count;
-   if (brw->gen >= 7)
+   if (devinfo->gen >= 7)
       node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
    struct ra_graph *g =
       ra_alloc_interference_graph(screen->wm_reg_sets[rsi].regs, node_count);
@@ -579,7 +579,7 @@ fs_visitor::assign_regs(bool allow_spilling)
    }
 
    setup_payload_interference(g, payload_node_count, first_payload_node);
-   if (brw->gen >= 7) {
+   if (devinfo->gen >= 7) {
       setup_mrf_hack_interference(g, first_mrf_hack_node);
 
       foreach_block_and_inst(block, fs_inst, inst, cfg) {
@@ -694,7 +694,7 @@ fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst,
 
    for (int i = 0; i < count / reg_size; i++) {
       /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
-      bool gen7_read = brw->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
+      bool gen7_read = devinfo->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
 
       fs_inst *unspill_inst =
          new(mem_ctx) fs_inst(gen7_read ?
diff --git a/src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp b/src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp
index 740ba67bb9..52aa5590c2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp
@@ -158,7 +158,7 @@ fs_visitor::opt_peephole_sel()
 
       enum brw_predicate predicate;
       bool predicate_inverse;
-      if (brw->gen == 6 && if_inst->conditional_mod) {
+      if (devinfo->gen == 6 && if_inst->conditional_mod) {
          /* For Sandybridge with IF with embedded comparison */
          predicate = BRW_PREDICATE_NORMAL;
          predicate_inverse = false;
@@ -213,7 +213,7 @@ fs_visitor::opt_peephole_sel()
          continue;
 
       /* Emit a CMP if our IF used the embedded comparison */
-      if (brw->gen == 6 && if_inst->conditional_mod) {
+      if (devinfo->gen == 6 && if_inst->conditional_mod) {
          fs_inst *cmp_inst = CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
                                  if_inst->conditional_mod);
          if_inst->insert_before(block, cmp_inst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 4d1afb1407..11f38c2600 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -197,7 +197,7 @@ fs_visitor::visit(ir_variable *ir)
 	 reg = emit_sampleid_setup();
          break;
       case SYSTEM_VALUE_SAMPLE_MASK_IN:
-         assert(brw->gen >= 7);
+         assert(devinfo->gen >= 7);
          reg = new(mem_ctx)
             fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
                           BRW_REGISTER_TYPE_D));
@@ -292,7 +292,7 @@ fs_inst *
 fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
                      const fs_reg &a)
 {
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       /* We can't use the LRP instruction.  Emit x*(1-a) + y*a. */
       fs_reg y_times_a           = vgrf(glsl_type::float_type);
       fs_reg one_minus_a         = vgrf(glsl_type::float_type);
@@ -323,7 +323,7 @@ fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &d
 
    fs_inst *inst;
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
       inst->conditional_mod = conditionalmod;
    } else {
@@ -420,7 +420,7 @@ bool
 fs_visitor::try_emit_mad(ir_expression *ir)
 {
    /* 3-src instructions were introduced in gen6. */
-   if (brw->gen < 6)
+   if (devinfo->gen < 6)
       return false;
 
    /* MAD can only handle floating-point data. */
@@ -699,7 +699,7 @@ fs_visitor::visit(ir_expression *ir)
    /* Deal with the real oddball stuff first */
    switch (ir->operation) {
    case ir_binop_add:
-      if (brw->gen <= 5 && try_emit_line(ir))
+      if (devinfo->gen <= 5 && try_emit_line(ir))
          return;
       if (try_emit_mad(ir))
          return;
@@ -719,7 +719,7 @@ fs_visitor::visit(ir_expression *ir)
       return;
 
    case ir_unop_b2f:
-      if (brw->gen <= 5 && try_emit_b2f_of_comparison(ir))
+      if (devinfo->gen <= 5 && try_emit_b2f_of_comparison(ir))
          return;
       break;
 
@@ -860,24 +860,24 @@ fs_visitor::visit(ir_expression *ir)
       unreachable("not reached: should be handled by ir_sub_to_add_neg");
 
    case ir_binop_mul:
-      if (brw->gen < 8 && ir->type->is_integer()) {
+      if (devinfo->gen < 8 && ir->type->is_integer()) {
 	 /* For integer multiplication, the MUL uses the low 16 bits
 	  * of one of the operands (src0 on gen6, src1 on gen7).  The
 	  * MACH accumulates in the contribution of the upper 16 bits
 	  * of that operand.
           */
          if (ir->operands[0]->is_uint16_constant()) {
-            if (brw->gen < 7)
+            if (devinfo->gen < 7)
                emit(MUL(this->result, op[0], op[1]));
             else
                emit(MUL(this->result, op[1], op[0]));
          } else if (ir->operands[1]->is_uint16_constant()) {
-            if (brw->gen < 7)
+            if (devinfo->gen < 7)
                emit(MUL(this->result, op[1], op[0]));
             else
                emit(MUL(this->result, op[0], op[1]));
          } else {
-            if (brw->gen >= 7)
+            if (devinfo->gen >= 7)
                no16("SIMD16 explicit accumulator operands unsupported\n");
 
             struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -892,7 +892,7 @@ fs_visitor::visit(ir_expression *ir)
       }
       break;
    case ir_binop_imul_high: {
-      if (brw->gen == 7)
+      if (devinfo->gen == 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -911,7 +911,7 @@ fs_visitor::visit(ir_expression *ir)
        *
        * FINISHME: Don't use source modifiers on src1.
        */
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
                 mul->src[1].type == BRW_REGISTER_TYPE_UD);
          if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
@@ -929,7 +929,7 @@ fs_visitor::visit(ir_expression *ir)
       emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
       break;
    case ir_binop_carry: {
-      if (brw->gen == 7)
+      if (devinfo->gen == 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -940,7 +940,7 @@ fs_visitor::visit(ir_expression *ir)
       break;
    }
    case ir_binop_borrow: {
-      if (brw->gen == 7)
+      if (devinfo->gen == 7)
          no16("SIMD16 explicit accumulator operands unsupported\n");
 
       struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
@@ -964,7 +964,7 @@ fs_visitor::visit(ir_expression *ir)
    case ir_binop_all_equal:
    case ir_binop_nequal:
    case ir_binop_any_nequal:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
          resolve_bool_comparison(ir->operands[1], &op[1]);
       }
@@ -1038,7 +1038,7 @@ fs_visitor::visit(ir_expression *ir)
       emit(AND(this->result, op[0], fs_reg(1)));
       break;
    case ir_unop_b2f:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
       }
       op[0].type = BRW_REGISTER_TYPE_D;
@@ -1786,9 +1786,9 @@ fs_visitor::emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 }
 
 static bool
-is_high_sampler(struct brw_context *brw, fs_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, fs_reg sampler)
 {
-   if (brw->gen < 8 && !brw->is_haswell)
+   if (devinfo->gen < 8 && !devinfo->is_haswell)
       return false;
 
    return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
@@ -1812,7 +1812,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
    int length = 0;
 
    if (op == ir_tg4 || offset_value.file != BAD_FILE ||
-       is_high_sampler(brw, sampler)) {
+       is_high_sampler(devinfo, sampler)) {
       /* For general texture offsets (no txf workaround), we need a header to
        * put them in.  Note that for SIMD16 we're making space for two actual
        * hardware registers here, so the emit will have to fix up for this.
@@ -1904,7 +1904,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
       coordinate = offset(coordinate, 1);
       length++;
 
-      if (brw->gen >= 9) {
+      if (devinfo->gen >= 9) {
          if (coord_components >= 2) {
             emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
             coordinate = offset(coordinate, 1);
@@ -1915,7 +1915,7 @@ fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
       emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod));
       length++;
 
-      for (int i = brw->gen >= 9 ? 2 : 1; i < coord_components; i++) {
+      for (int i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++) {
 	 emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
 	 coordinate = offset(coordinate, 1);
 	 length++;
@@ -2038,9 +2038,9 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int coord_components,
     * tracking to get the scaling factor.
     */
    if (is_rect &&
-       (brw->gen < 6 ||
-        (brw->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
-                           key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
+       (devinfo->gen < 6 ||
+        (devinfo->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
+                               key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
       struct gl_program_parameter_list *params = prog->Parameters;
       int tokens[STATE_LENGTH] = {
 	 STATE_INTERNAL,
@@ -2083,7 +2083,7 @@ fs_visitor::rescale_texcoord(fs_reg coordinate, int coord_components,
     * texture coordinates.  We use the program parameter state
     * tracking to get the scaling factor.
     */
-   if (brw->gen < 6 && is_rect) {
+   if (devinfo->gen < 6 && is_rect) {
       fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
       fs_reg src = coordinate;
       coordinate = dst;
@@ -2217,12 +2217,12 @@ fs_visitor::emit_texture(ir_texture_opcode op,
     */
    fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
 
-   if (brw->gen >= 7) {
+   if (devinfo->gen >= 7) {
       inst = emit_texture_gen7(op, dst, coordinate, coord_components,
                                shadow_c, lod, lod2, grad_components,
                                sample_index, mcs, sampler_reg,
                                offset_value);
-   } else if (brw->gen >= 5) {
+   } else if (devinfo->gen >= 5) {
       inst = emit_texture_gen5(op, dst, coordinate, coord_components,
                                shadow_c, lod, lod2, grad_components,
                                sample_index, sampler,
@@ -2246,7 +2246,7 @@ fs_visitor::emit_texture(ir_texture_opcode op,
       inst->offset |=
          gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
 
-      if (brw->gen == 6)
+      if (devinfo->gen == 6)
          emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], dst);
    }
 
@@ -2291,7 +2291,7 @@ fs_visitor::visit(ir_texture *ir)
          ->array->type->array_size();
 
       uint32_t max_used = sampler + array_size - 1;
-      if (ir->op == ir_tg4 && brw->gen < 8) {
+      if (ir->op == ir_tg4 && devinfo->gen < 8) {
          max_used += stage_prog_data->binding_table.gather_texture_start;
       } else {
          max_used += stage_prog_data->binding_table.texture_start;
@@ -2390,7 +2390,7 @@ fs_visitor::visit(ir_texture *ir)
       ir->lod_info.sample_index->accept(this);
       sample_index = this->result;
 
-      if (brw->gen >= 7 &&
+      if (devinfo->gen >= 7 &&
           key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
          mcs = emit_mcs_fetch(coordinate, ir->coordinate->type->vector_elements,
                               sampler_reg);
@@ -2578,7 +2578,7 @@ fs_visitor::visit(ir_discard *ir)
    cmp->predicate = BRW_PREDICATE_NORMAL;
    cmp->flag_subreg = 1;
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       emit_discard_jump();
    }
 }
@@ -2691,7 +2691,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
       break;
 
    case ir_binop_logic_xor:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          fs_reg temp = vgrf(expr->type);
          emit(XOR(temp, op[0], op[1]));
          inst = emit(AND(reg_null_d, temp, fs_reg(1)));
@@ -2702,7 +2702,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
       break;
 
    case ir_binop_logic_or:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          fs_reg temp = vgrf(expr->type);
          emit(OR(temp, op[0], op[1]));
          inst = emit(AND(reg_null_d, temp, fs_reg(1)));
@@ -2713,7 +2713,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
       break;
 
    case ir_binop_logic_and:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          fs_reg temp = vgrf(expr->type);
          emit(AND(temp, op[0], op[1]));
          inst = emit(AND(reg_null_d, temp, fs_reg(1)));
@@ -2724,7 +2724,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
       break;
 
    case ir_unop_f2b:
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
       } else {
          inst = emit(MOV(reg_null_f, op[0]));
@@ -2733,7 +2733,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
       break;
 
    case ir_unop_i2b:
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
       } else {
          inst = emit(MOV(reg_null_d, op[0]));
@@ -2749,7 +2749,7 @@ fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
    case ir_binop_all_equal:
    case ir_binop_nequal:
    case ir_binop_any_nequal:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(expr->operands[0], &op[0]);
          resolve_bool_comparison(expr->operands[1], &op[1]);
       }
@@ -2839,7 +2839,7 @@ fs_visitor::emit_if_gen6(ir_if *ir)
       case ir_binop_all_equal:
       case ir_binop_nequal:
       case ir_binop_any_nequal:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             resolve_bool_comparison(expr->operands[0], &op[0]);
             resolve_bool_comparison(expr->operands[1], &op[1]);
          }
@@ -2909,7 +2909,7 @@ fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
       dst.type = BRW_REGISTER_TYPE_D;
       fs_reg tmp = vgrf(glsl_type::int_type);
 
-      if (brw->gen >= 6) {
+      if (devinfo->gen >= 6) {
          /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
          fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
 
@@ -3062,7 +3062,7 @@ fs_visitor::visit(ir_if *ir)
     */
    this->base_ir = ir->condition;
 
-   if (brw->gen == 6) {
+   if (devinfo->gen == 6) {
       emit_if_gen6(ir);
    } else {
       emit_bool_to_cond_code(ir->condition);
@@ -3086,7 +3086,7 @@ fs_visitor::visit(ir_if *ir)
 
    emit(BRW_OPCODE_ENDIF);
 
-   if (!try_replace_with_sel() && brw->gen < 6) {
+   if (!try_replace_with_sel() && devinfo->gen < 6) {
       no16("Can't support (non-uniform) control flow on SIMD16\n");
    }
 }
@@ -3094,7 +3094,7 @@ fs_visitor::visit(ir_if *ir)
 void
 fs_visitor::visit(ir_loop *ir)
 {
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       no16("Can't support (non-uniform) control flow on SIMD16\n");
    }
 
@@ -3375,7 +3375,7 @@ fs_visitor::emit_dummy_fs()
    fs_inst *write;
    write = emit(FS_OPCODE_FB_WRITE);
    write->eot = true;
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       write->base_mrf = 2;
       write->mlen = 4 * reg_width;
    } else {
@@ -3388,7 +3388,7 @@ fs_visitor::emit_dummy_fs()
     * varying to avoid GPU hangs, so set that.
     */
    brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
-   wm_prog_data->num_varying_inputs = brw->gen < 6 ? 1 : 0;
+   wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
    memset(wm_prog_data->urb_setup, -1,
           sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
 
@@ -3446,7 +3446,7 @@ fs_visitor::emit_interpolation_setup_gen4()
    const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
    const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
 
-   if (brw->has_pln && dispatch_width == 16) {
+   if (devinfo->has_pln && dispatch_width == 16) {
       emit(ADD(half(offset(delta_xy, 0), 0), half(this->pixel_x, 0), xstart));
       emit(ADD(half(offset(delta_xy, 0), 1), half(this->pixel_y, 0), ystart));
       emit(ADD(half(offset(delta_xy, 1), 0), half(this->pixel_x, 1), xstart))
@@ -3562,7 +3562,7 @@ fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
       colors_enabled = (1 << components) - 1;
    }
 
-   if (dispatch_width == 8 || (brw->gen >= 6 && !do_dual_src)) {
+   if (dispatch_width == 8 || (devinfo->gen >= 6 && !do_dual_src)) {
       /* SIMD8 write looks like:
        * m + 0: r0
        * m + 1: r1
@@ -3593,7 +3593,7 @@ fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
          len++;
       }
       return len;
-   } else if (brw->gen >= 6 && do_dual_src) {
+   } else if (devinfo->gen >= 6 && do_dual_src) {
       /* SIMD16 dual source blending for gen6+.
        *
        * From the SNB PRM, volume 4, part 1, page 193:
@@ -3727,8 +3727,8 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
     *      dispatched. This field is only required for the end-of-
     *      thread message and on all dual-source messages."
     */
-   if (brw->gen >= 6 &&
-       (brw->is_haswell || brw->gen >= 8 || !prog_data->uses_kill) &&
+   if (devinfo->gen >= 6 &&
+       (devinfo->is_haswell || devinfo->gen >= 8 || !prog_data->uses_kill) &&
        color1.file == BAD_FILE &&
        key->nr_color_regions == 1) {
       header_present = false;
@@ -3785,7 +3785,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
    }
 
    if (source_depth_to_render_target) {
-      if (brw->gen == 6) {
+      if (devinfo->gen == 6) {
 	 /* For outputting oDepth on gen6, SIMD8 writes have to be
 	  * used.  This would require SIMD8 moves of each half to
 	  * message regs, kind of like pre-gen5 SIMD16 FB writes.
@@ -3816,7 +3816,7 @@ fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
 
    fs_inst *load;
    fs_inst *write;
-   if (brw->gen >= 7) {
+   if (devinfo->gen >= 7) {
       /* Send from the GRF */
       fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
       load = emit(LOAD_PAYLOAD(payload, sources, length));
@@ -3892,7 +3892,7 @@ fs_visitor::emit_fb_writes()
                                                     "FB write target %d",
                                                     target);
          fs_reg src0_alpha;
-         if (brw->gen >= 6 && key->replicate_alpha && target != 0)
+         if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
             src0_alpha = offset(outputs[0], 3);
 
          inst = emit_single_fb_write(this->outputs[target], reg_undef,
@@ -4163,7 +4163,7 @@ fs_visitor::resolve_ud_negate(fs_reg *reg)
 void
 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
 {
-   assert(brw->gen <= 5);
+   assert(devinfo->gen <= 5);
 
    if (rvalue->type != glsl_type::bool_type)
       return;
@@ -4244,7 +4244,7 @@ fs_visitor::init()
    this->source_depth_to_render_target = false;
    this->runtime_check_aads_emit = false;
    this->first_non_payload_grf = 0;
-   this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+   this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 
    this->current_annotation = NULL;
    this->base_ir = NULL;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h
index 30c19f41a3..1e54bb2330 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h
@@ -224,7 +224,7 @@ public:
    bool is_send_from_grf() const;
    bool is_partial_write() const;
    int regs_read(int arg) const;
-   bool can_do_source_mods(struct brw_context *brw);
+   bool can_do_source_mods(const struct brw_device_info *devinfo);
    bool has_side_effects() const;
 
    bool reads_flag() const;
diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index d3bd64dbb7..955a62d5f9 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -168,7 +168,7 @@ public:
    unsigned regs_read(unsigned arg) const;
    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
    void reswizzle(int dst_writemask, int swizzle);
-   bool can_do_source_mods(struct brw_context *brw);
+   bool can_do_source_mods(const struct brw_device_info *devinfo);
 
    bool reads_flag()
    {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 91ffb532d0..d90eac120c 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -721,6 +721,7 @@ backend_visitor::backend_visitor(struct brw_context *brw,
                                  struct brw_stage_prog_data *stage_prog_data,
                                  gl_shader_stage stage)
    : brw(brw),
+     devinfo(brw->intelScreen->devinfo),
      ctx(&brw->ctx),
      shader(shader_prog ?
         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
@@ -1183,7 +1184,7 @@ backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table
    }
 
    if (prog->UsesGather) {
-      if (brw->gen >= 8) {
+      if (devinfo->gen >= 8) {
          stage_prog_data->binding_table.gather_texture_start =
             stage_prog_data->binding_table.texture_start;
       } else {
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index e6246ed7fc..b80e7405db 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -169,6 +169,7 @@ protected:
 public:
 
    struct brw_context * const brw;
+   const struct brw_device_info * const devinfo;
    struct gl_context * const ctx;
    struct brw_shader * const shader;
    struct gl_shader_program * const shader_prog;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index c4c77b2876..9398adce27 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -239,9 +239,9 @@ vec4_instruction::regs_read(unsigned arg) const
 }
 
 bool
-vec4_instruction::can_do_source_mods(struct brw_context *brw)
+vec4_instruction::can_do_source_mods(const struct brw_device_info *devinfo)
 {
-   if (brw->gen == 6 && is_math())
+   if (devinfo->gen == 6 && is_math())
       return false;
 
    if (is_send_from_grf())
@@ -783,7 +783,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
     * multiply, DepCtrl must not be used."
     * May apply to future SoCs as well.
     */
-   if (brw->is_cherryview) {
+   if (devinfo->is_cherryview) {
       if (inst->opcode == BRW_OPCODE_MUL &&
          IS_DWORD(inst->src[0]) &&
          IS_DWORD(inst->src[1]))
@@ -791,7 +791,7 @@ vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
    }
 #undef IS_DWORD
 
-   if (brw->gen >= 8) {
+   if (devinfo->gen >= 8) {
       if (inst->opcode == BRW_OPCODE_F32TO16)
          return true;
    }
@@ -1012,7 +1012,7 @@ vec4_visitor::opt_register_coalesce()
                if (scan_inst->mlen)
                   break;
 
-               if (brw->gen == 6) {
+               if (devinfo->gen == 6) {
                   /* gen6 math instructions must have the destination be
                    * GRF, so no compute-to-MRF for them.
                    */
@@ -1209,9 +1209,9 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
    if (inst->conditional_mod) {
       fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
       if (!inst->predicate &&
-          (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
-                            inst->opcode != BRW_OPCODE_IF &&
-                            inst->opcode != BRW_OPCODE_WHILE))) {
+          (devinfo->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+                                inst->opcode != BRW_OPCODE_IF &&
+                                inst->opcode != BRW_OPCODE_WHILE))) {
          fprintf(file, ".f0.%d", inst->flag_subreg);
       }
    }
@@ -1488,7 +1488,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg)
    unsigned vue_entries =
       MAX2(nr_attributes, prog_data->vue_map.num_slots);
 
-   if (brw->gen == 6)
+   if (devinfo->gen == 6)
       prog_data->urb_entry_size = ALIGN(vue_entries, 8) / 8;
    else
       prog_data->urb_entry_size = ALIGN(vue_entries, 4) / 4;
@@ -1504,7 +1504,7 @@ vec4_visitor::setup_uniforms(int reg)
    /* The pre-gen6 VS requires that some push constants get loaded no
     * matter what, or the GPU would hang.
     */
-   if (brw->gen < 6 && this->uniforms == 0) {
+   if (devinfo->gen < 6 && this->uniforms == 0) {
       assert(this->uniforms < this->uniform_array_size);
       this->uniform_vector_size[this->uniforms] = 1;
 
@@ -1557,7 +1557,7 @@ vec4_visitor::assign_binding_table_offsets()
 src_reg
 vec4_visitor::get_timestamp()
 {
-   assert(brw->gen >= 7);
+   assert(devinfo->gen >= 7);
 
    src_reg ts = src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
                                 BRW_ARF_TIMESTAMP,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index e897be299b..0fbf0ab50a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -104,7 +104,8 @@ is_logic_op(enum opcode opcode)
 }
 
 static bool
-try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
+try_constant_propagate(const struct brw_device_info *devinfo,
+                       vec4_instruction *inst,
                        int arg, struct copy_entry *entry)
 {
    /* For constant propagation, we only handle the same constant
@@ -132,14 +133,14 @@ try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
    }
 
    if (inst->src[arg].abs) {
-      if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+      if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
           !brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
          return false;
       }
    }
 
    if (inst->src[arg].negate) {
-      if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
+      if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
           !brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
          return false;
       }
@@ -157,7 +158,7 @@ try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
    case SHADER_OPCODE_POW:
    case SHADER_OPCODE_INT_QUOTIENT:
    case SHADER_OPCODE_INT_REMAINDER:
-      if (brw->gen < 8)
+      if (devinfo->gen < 8)
          break;
       /* fallthrough */
    case BRW_OPCODE_DP2:
@@ -246,7 +247,8 @@ try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
 }
 
 static bool
-try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
+try_copy_propagate(const struct brw_device_info *devinfo,
+                   vec4_instruction *inst,
                    int arg, struct copy_entry *entry)
 {
    /* For constant propagation, we only handle the same constant
@@ -283,7 +285,7 @@ try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
        value.file != ATTR)
       return false;
 
-   if (brw->gen >= 8 && (value.negate || value.abs) &&
+   if (devinfo->gen >= 8 && (value.negate || value.abs) &&
        is_logic_op(inst->opcode)) {
       return false;
    }
@@ -301,7 +303,7 @@ try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
     * instructions.
     */
    if ((has_source_modifiers || value.file == UNIFORM ||
-        value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
+        value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo))
       return false;
 
    if (has_source_modifiers && value.type != inst->src[arg].type)
@@ -433,10 +435,10 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 	 if (c != 4)
 	    continue;
 
-         if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
+         if (do_constant_prop && try_constant_propagate(devinfo, inst, i, &entry))
             progress = true;
 
-	 if (try_copy_propagate(brw, inst, i, &entry))
+	 if (try_copy_propagate(devinfo, inst, i, &entry))
 	    progress = true;
       }
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
index 70d2af5e91..8fc7a365bf 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
@@ -37,7 +37,7 @@
 using namespace brw;
 
 static bool
-can_do_writemask(const struct brw_context *brw,
+can_do_writemask(const struct brw_device_info *devinfo,
                  const vec4_instruction *inst)
 {
    switch (inst->opcode) {
@@ -50,7 +50,7 @@ can_do_writemask(const struct brw_context *brw,
       /* The MATH instruction on Gen6 only executes in align1 mode, which does
        * not support writemasking.
        */
-      if (brw->gen == 6 && inst->is_math())
+      if (devinfo->gen == 6 && inst->is_math())
          return false;
 
       if (inst->is_tex())
@@ -90,7 +90,7 @@ vec4_visitor::dead_code_eliminate()
             /* If the instruction can't do writemasking, then it's all or
              * nothing.
              */
-            if (!can_do_writemask(brw, inst)) {
+            if (!can_do_writemask(devinfo, inst)) {
                bool result = result_live[0] | result_live[1] |
                              result_live[2] | result_live[3];
                result_live[0] = result;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 18a44be737..363e30e34e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -281,7 +281,7 @@ vec4_gs_visitor::emit_urb_write_opcode(bool complete)
    /* We need to increment Global Offset by 1 to make room for Broadwell's
     * extra "Vertex Count" payload at the beginning of the URB entry.
     */
-   if (brw->gen >= 8)
+   if (devinfo->gen >= 8)
       inst->offset++;
 
    inst->urb_write_flags = BRW_URB_WRITE_PER_SLOT_OFFSET;
@@ -424,7 +424,7 @@ vec4_gs_visitor::emit_control_data_bits()
        * URB entry.  Since this is an OWord message, Global Offset is counted
        * in 128-bit units, so we must set it to 2.
        */
-      if (brw->gen >= 8)
+      if (devinfo->gen >= 8)
          inst->offset = 2;
       inst->base_mrf = base_mrf;
       inst->mlen = 2;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c9a496e6c7..ec6913b788 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -146,7 +146,7 @@ vec4_visitor::emit(enum opcode opcode)
    vec4_visitor::op(const dst_reg &dst, const src_reg &src0,		\
                     const src_reg &src1, const src_reg &src2)		\
    {									\
-      assert(brw->gen >= 6);						\
+      assert(devinfo->gen >= 6);						\
       return new(mem_ctx) vec4_instruction(BRW_OPCODE_##op, dst,	\
 					   src0, src1, src2);		\
    }
@@ -201,7 +201,7 @@ vec4_instruction *
 vec4_visitor::IF(src_reg src0, src_reg src1,
                  enum brw_conditional_mod condition)
 {
-   assert(brw->gen == 6);
+   assert(devinfo->gen == 6);
 
    vec4_instruction *inst;
 
@@ -315,7 +315,7 @@ vec4_visitor::fix_3src_operand(src_reg src)
 src_reg
 vec4_visitor::fix_math_operand(src_reg src)
 {
-   if (brw->gen < 6 || brw->gen >= 8 || src.file == BAD_FILE)
+   if (devinfo->gen < 6 || devinfo->gen >= 8 || src.file == BAD_FILE)
       return src;
 
    /* The gen6 math instruction ignores the source modifiers --
@@ -329,7 +329,7 @@ vec4_visitor::fix_math_operand(src_reg src)
     * can't use.
     */
 
-   if (brw->gen == 7 && src.file != IMM)
+   if (devinfo->gen == 7 && src.file != IMM)
       return src;
 
    dst_reg expanded = dst_reg(this, glsl_type::vec4_type);
@@ -346,12 +346,12 @@ vec4_visitor::emit_math(enum opcode opcode,
    vec4_instruction *math =
       emit(opcode, dst, fix_math_operand(src0), fix_math_operand(src1));
 
-   if (brw->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
+   if (devinfo->gen == 6 && dst.writemask != WRITEMASK_XYZW) {
       /* MATH on Gen6 must be align1, so we can't do writemasks. */
       math->dst = dst_reg(this, glsl_type::vec4_type);
       math->dst.type = dst.type;
       emit(MOV(dst, src_reg(math->dst)));
-   } else if (brw->gen < 6) {
+   } else if (devinfo->gen < 6) {
       math->base_mrf = 1;
       math->mlen = src1.file == BAD_FILE ? 1 : 2;
    }
@@ -360,7 +360,7 @@ vec4_visitor::emit_math(enum opcode opcode,
 void
 vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
 {
-   if (brw->gen < 7) {
+   if (devinfo->gen < 7) {
       unreachable("ir_unop_pack_half_2x16 should be lowered");
    }
 
@@ -437,7 +437,7 @@ vec4_visitor::emit_pack_half_2x16(dst_reg dst, src_reg src0)
 void
 vec4_visitor::emit_unpack_half_2x16(dst_reg dst, src_reg src0)
 {
-   if (brw->gen < 7) {
+   if (devinfo->gen < 7) {
       unreachable("ir_unop_unpack_half_2x16 should be lowered");
    }
 
@@ -802,7 +802,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_binop_logic_xor:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             src_reg temp = src_reg(this, ir->type);
             emit(XOR(dst_reg(temp), op[0], op[1]));
             inst = emit(AND(dst_null_d(), temp, src_reg(1)));
@@ -813,7 +813,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_binop_logic_or:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             src_reg temp = src_reg(this, ir->type);
             emit(OR(dst_reg(temp), op[0], op[1]));
             inst = emit(AND(dst_null_d(), temp, src_reg(1)));
@@ -824,7 +824,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_binop_logic_and:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             src_reg temp = src_reg(this, ir->type);
             emit(AND(dst_reg(temp), op[0], op[1]));
             inst = emit(AND(dst_null_d(), temp, src_reg(1)));
@@ -835,7 +835,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_unop_f2b:
-	 if (brw->gen >= 6) {
+	 if (devinfo->gen >= 6) {
 	    emit(CMP(dst_null_d(), op[0], src_reg(0.0f), BRW_CONDITIONAL_NZ));
 	 } else {
 	    inst = emit(MOV(dst_null_f(), op[0]));
@@ -844,7 +844,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_unop_i2b:
-	 if (brw->gen >= 6) {
+	 if (devinfo->gen >= 6) {
 	    emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
 	 } else {
 	    inst = emit(MOV(dst_null_d(), op[0]));
@@ -853,7 +853,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_binop_all_equal:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             resolve_bool_comparison(expr->operands[0], &op[0]);
             resolve_bool_comparison(expr->operands[1], &op[1]);
          }
@@ -862,7 +862,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_binop_any_nequal:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             resolve_bool_comparison(expr->operands[0], &op[0]);
             resolve_bool_comparison(expr->operands[1], &op[1]);
          }
@@ -871,7 +871,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
 	 break;
 
       case ir_unop_any:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             resolve_bool_comparison(expr->operands[0], &op[0]);
          }
 	 inst = emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
@@ -884,7 +884,7 @@ vec4_visitor::emit_bool_to_cond_code(ir_rvalue *ir,
       case ir_binop_lequal:
       case ir_binop_equal:
       case ir_binop_nequal:
-         if (brw->gen <= 5) {
+         if (devinfo->gen <= 5) {
             resolve_bool_comparison(expr->operands[0], &op[0]);
             resolve_bool_comparison(expr->operands[1], &op[1]);
          }
@@ -1147,7 +1147,7 @@ bool
 vec4_visitor::try_emit_mad(ir_expression *ir)
 {
    /* 3-src instructions were introduced in gen6. */
-   if (brw->gen < 6)
+   if (devinfo->gen < 6)
       return false;
 
    /* MAD can only handle floating-point data. */
@@ -1209,7 +1209,7 @@ vec4_visitor::try_emit_b2f_of_compare(ir_expression *ir)
     * false.  Early hardware only sets the least significant bit, and
     * leaves the other bits undefined.  So we can't use it.
     */
-   if (brw->gen < 6)
+   if (devinfo->gen < 6)
       return false;
 
    ir_expression *const cmp = ir->operands[0]->as_expression();
@@ -1257,7 +1257,7 @@ vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 {
    vec4_instruction *inst;
 
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
       inst->conditional_mod = conditionalmod;
    } else {
@@ -1272,7 +1272,7 @@ void
 vec4_visitor::emit_lrp(const dst_reg &dst,
                        const src_reg &x, const src_reg &y, const src_reg &a)
 {
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* Note that the instruction's argument order is reversed from GLSL
        * and the IR.
        */
@@ -1313,7 +1313,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
 
    vec4_instruction *pull;
 
-   if (brw->gen >= 9) {
+   if (devinfo->gen >= 9) {
       /* Gen9+ needs a message header in order to use SIMD4x2 mode */
       src_reg header(this, glsl_type::uvec4_type, 2);
 
@@ -1341,7 +1341,7 @@ vec4_visitor::emit_pull_constant_load_reg(dst_reg dst,
                                            header);
       pull->mlen = 2;
       pull->header_present = true;
-   } else if (brw->gen >= 7) {
+   } else if (devinfo->gen >= 7) {
       dst_reg grf_offset = dst_reg(this, glsl_type::int_type);
 
       grf_offset.type = offset_reg.type;
@@ -1549,7 +1549,7 @@ vec4_visitor::visit(ir_expression *ir)
       unreachable("not reached: should be handled by ir_sub_to_add_neg");
 
    case ir_binop_mul:
-      if (brw->gen < 8 && ir->type->is_integer()) {
+      if (devinfo->gen < 8 && ir->type->is_integer()) {
 	 /* For integer multiplication, the MUL uses the low 16 bits of one of
 	  * the operands (src0 through SNB, src1 on IVB and later).  The MACH
 	  * accumulates in the contribution of the upper 16 bits of that
@@ -1557,12 +1557,12 @@ vec4_visitor::visit(ir_expression *ir)
 	  * 16 bits, though, we can just emit a single MUL.
           */
          if (ir->operands[0]->is_uint16_constant()) {
-            if (brw->gen < 7)
+            if (devinfo->gen < 7)
                emit(MUL(result_dst, op[0], op[1]));
             else
                emit(MUL(result_dst, op[1], op[0]));
          } else if (ir->operands[1]->is_uint16_constant()) {
-            if (brw->gen < 7)
+            if (devinfo->gen < 7)
                emit(MUL(result_dst, op[1], op[0]));
             else
                emit(MUL(result_dst, op[0], op[1]));
@@ -1615,7 +1615,7 @@ vec4_visitor::visit(ir_expression *ir)
    case ir_binop_gequal:
    case ir_binop_equal:
    case ir_binop_nequal: {
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
          resolve_bool_comparison(ir->operands[1], &op[1]);
       }
@@ -1625,7 +1625,7 @@ vec4_visitor::visit(ir_expression *ir)
    }
 
    case ir_binop_all_equal:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
          resolve_bool_comparison(ir->operands[1], &op[1]);
       }
@@ -1642,7 +1642,7 @@ vec4_visitor::visit(ir_expression *ir)
       }
       break;
    case ir_binop_any_nequal:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
          resolve_bool_comparison(ir->operands[1], &op[1]);
       }
@@ -1661,7 +1661,7 @@ vec4_visitor::visit(ir_expression *ir)
       break;
 
    case ir_unop_any:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
       }
       emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
@@ -1724,7 +1724,7 @@ vec4_visitor::visit(ir_expression *ir)
       emit(AND(result_dst, op[0], src_reg(1)));
       break;
    case ir_unop_b2f:
-      if (brw->gen <= 5) {
+      if (devinfo->gen <= 5) {
          resolve_bool_comparison(ir->operands[0], &op[0]);
       }
       op[0].type = BRW_REGISTER_TYPE_D;
@@ -1836,7 +1836,7 @@ vec4_visitor::visit(ir_expression *ir)
       }
 
       if (const_offset_ir) {
-         if (brw->gen >= 8) {
+         if (devinfo->gen >= 8) {
             /* Store the offset in a GRF so we can send-from-GRF. */
             offset = src_reg(this, glsl_type::int_type);
             emit(MOV(dst_reg(offset), src_reg(const_offset / 16)));
@@ -2467,9 +2467,9 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler
 }
 
 static bool
-is_high_sampler(struct brw_context *brw, src_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, src_reg sampler)
 {
-   if (brw->gen < 8 && !brw->is_haswell)
+   if (devinfo->gen < 8 && !devinfo->is_haswell)
       return false;
 
    return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
@@ -2495,7 +2495,7 @@ vec4_visitor::visit(ir_texture *ir)
          ->array->type->array_size();
 
       uint32_t max_used = sampler + array_size - 1;
-      if (ir->op == ir_tg4 && brw->gen < 8) {
+      if (ir->op == ir_tg4 && devinfo->gen < 8) {
          max_used += prog_data->base.binding_table.gather_texture_start;
       } else {
          max_used += prog_data->base.binding_table.texture_start;
@@ -2582,7 +2582,7 @@ vec4_visitor::visit(ir_texture *ir)
       sample_index = this->result;
       sample_index_type = ir->lod_info.sample_index->type;
 
-      if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
+      if (devinfo->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
          mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
       else
          mcs = src_reg(0u);
@@ -2642,9 +2642,9 @@ vec4_visitor::visit(ir_texture *ir)
     * - Sampler indices too large to fit in a 4-bit value.
     */
    inst->header_present =
-      brw->gen < 5 || brw->gen >= 9 ||
+      devinfo->gen < 5 || devinfo->gen >= 9 ||
       inst->offset != 0 || ir->op == ir_tg4 ||
-      is_high_sampler(brw, sampler_reg);
+      is_high_sampler(devinfo, sampler_reg);
    inst->base_mrf = 2;
    inst->mlen = inst->header_present + 1; /* always at least one */
    inst->dst.writemask = WRITEMASK_XYZW;
@@ -2656,7 +2656,7 @@ vec4_visitor::visit(ir_texture *ir)
    int param_base = inst->base_mrf + inst->header_present;
 
    if (ir->op == ir_txs || ir->op == ir_query_levels) {
-      int writemask = brw->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
+      int writemask = devinfo->gen == 4 ? WRITEMASK_W : WRITEMASK_X;
       emit(MOV(dst_reg(MRF, param_base, lod_type, writemask), lod));
    } else {
       /* Load the coordinate */
@@ -2682,7 +2682,7 @@ vec4_visitor::visit(ir_texture *ir)
       /* Load the LOD info */
       if (ir->op == ir_tex || ir->op == ir_txl) {
 	 int mrf, writemask;
-	 if (brw->gen >= 5) {
+	 if (devinfo->gen >= 5) {
 	    mrf = param_base + 1;
 	    if (ir->shadow_comparitor) {
 	       writemask = WRITEMASK_Y;
@@ -2691,7 +2691,7 @@ vec4_visitor::visit(ir_texture *ir)
 	       writemask = WRITEMASK_X;
 	       inst->mlen++;
 	    }
-	 } else /* brw->gen == 4 */ {
+	 } else /* devinfo->gen == 4 */ {
 	    mrf = param_base;
 	    writemask = WRITEMASK_W;
 	 }
@@ -2701,7 +2701,7 @@ vec4_visitor::visit(ir_texture *ir)
       } else if (ir->op == ir_txf_ms) {
          emit(MOV(dst_reg(MRF, param_base + 1, sample_index_type, WRITEMASK_X),
                   sample_index));
-         if (brw->gen >= 7) {
+         if (devinfo->gen >= 7) {
             /* MCS data is in the first channel of `mcs`, but we need to get it into
              * the .y channel of the second vec4 of params, so replicate .x across
              * the whole vec4 and then mask off everything except .y
@@ -2714,7 +2714,7 @@ vec4_visitor::visit(ir_texture *ir)
       } else if (ir->op == ir_txd) {
 	 const glsl_type *type = lod_type;
 
-	 if (brw->gen >= 5) {
+	 if (devinfo->gen >= 5) {
 	    dPdx.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
 	    dPdy.swizzle = BRW_SWIZZLE4(SWIZZLE_X,SWIZZLE_X,SWIZZLE_Y,SWIZZLE_Y);
 	    emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XZ), dPdx));
@@ -2734,7 +2734,7 @@ vec4_visitor::visit(ir_texture *ir)
                            shadow_comparitor));
                }
 	    }
-	 } else /* brw->gen == 4 */ {
+	 } else /* devinfo->gen == 4 */ {
 	    emit(MOV(dst_reg(MRF, param_base + 1, type, WRITEMASK_XYZ), dPdx));
 	    emit(MOV(dst_reg(MRF, param_base + 2, type, WRITEMASK_XYZ), dPdy));
 	    inst->mlen += 2;
@@ -2766,7 +2766,7 @@ vec4_visitor::visit(ir_texture *ir)
       }
    }
 
-   if (brw->gen == 6 && ir->op == ir_tg4) {
+   if (devinfo->gen == 6 && ir->op == ir_tg4) {
       emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], inst->dst);
    }
 
@@ -2901,7 +2901,7 @@ vec4_visitor::visit(ir_if *ir)
     */
    this->base_ir = ir->condition;
 
-   if (brw->gen == 6) {
+   if (devinfo->gen == 6) {
       emit_if_gen6(ir);
    } else {
       enum brw_predicate predicate;
@@ -3009,9 +3009,9 @@ vec4_visitor::emit_ndc_computation()
 void
 vec4_visitor::emit_psiz_and_flags(dst_reg reg)
 {
-   if (brw->gen < 6 &&
+   if (devinfo->gen < 6 &&
        ((prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ) ||
-        key->userclip_active || brw->has_negative_rhw_bug)) {
+        key->userclip_active || devinfo->has_negative_rhw_bug)) {
       dst_reg header1 = dst_reg(this, glsl_type::uvec4_type);
       dst_reg header1_w = header1;
       header1_w.writemask = WRITEMASK_W;
@@ -3050,7 +3050,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
        * Later, clipping will detect ucp[6] and ensure the primitive is
        * clipped against all fixed planes.
        */
-      if (brw->has_negative_rhw_bug) {
+      if (devinfo->has_negative_rhw_bug) {
          src_reg ndc_w = src_reg(output_reg[BRW_VARYING_SLOT_NDC]);
          ndc_w.swizzle = BRW_SWIZZLE_WWWW;
          emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
@@ -3062,7 +3062,7 @@ vec4_visitor::emit_psiz_and_flags(dst_reg reg)
       }
 
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
-   } else if (brw->gen < 6) {
+   } else if (devinfo->gen < 6) {
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), 0u));
    } else {
       emit(MOV(retype(reg, BRW_REGISTER_TYPE_D), src_reg(0)));
@@ -3182,9 +3182,9 @@ vec4_visitor::emit_urb_slot(dst_reg reg, int varying)
 }
 
 static int
-align_interleaved_urb_mlen(struct brw_context *brw, int mlen)
+align_interleaved_urb_mlen(const struct brw_device_info *devinfo, int mlen)
 {
-   if (brw->gen >= 6) {
+   if (devinfo->gen >= 6) {
       /* URB data written (does not include the message header reg) must
        * be a multiple of 256 bits, or 2 VS registers.  See vol5c.5,
        * section 5.4.3.2.2: URB_INTERLEAVED.
@@ -3232,7 +3232,7 @@ vec4_visitor::emit_vertex()
     */
    emit_urb_write_header(mrf++);
 
-   if (brw->gen < 6) {
+   if (devinfo->gen < 6) {
       emit_ndc_computation();
    }
 
@@ -3276,7 +3276,7 @@ vec4_visitor::emit_vertex()
       current_annotation = "URB write";
       vec4_instruction *inst = emit_urb_write_opcode(complete);
       inst->base_mrf = base_mrf;
-      inst->mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf);
+      inst->mlen = align_interleaved_urb_mlen(devinfo, mrf - base_mrf);
       inst->offset += offset;
    } while(!complete);
 }
@@ -3294,7 +3294,7 @@ vec4_visitor::get_scratch_offset(bblock_t *block, vec4_instruction *inst,
    /* Pre-gen6, the message header uses byte offsets instead of vec4
     * (16-byte) offset units.
     */
-   if (brw->gen < 6)
+   if (devinfo->gen < 6)
       message_header_scale *= 16;
 
    if (reladdr) {
@@ -3324,18 +3324,18 @@ vec4_visitor::get_pull_constant_offset(bblock_t * block, vec4_instruction *inst,
       /* Pre-gen6, the message header uses byte offsets instead of vec4
        * (16-byte) offset units.
        */
-      if (brw->gen < 6) {
+      if (devinfo->gen < 6) {
          emit_before(block, inst, MUL(dst_reg(index), index, src_reg(16)));
       }
 
       return index;
-   } else if (brw->gen >= 8) {
+   } else if (devinfo->gen >= 8) {
       /* Store the offset in a GRF so we can send-from-GRF. */
       src_reg offset = src_reg(this, glsl_type::int_type);
       emit_before(block, inst, MOV(dst_reg(offset), src_reg(reg_offset)));
       return offset;
    } else {
-      int message_header_scale = brw->gen < 6 ? 16 : 1;
+      int message_header_scale = devinfo->gen < 6 ? 16 : 1;
       return src_reg(reg_offset * message_header_scale);
    }
 }
@@ -3629,7 +3629,7 @@ vec4_visitor::resolve_ud_negate(src_reg *reg)
 void
 vec4_visitor::resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg)
 {
-   assert(brw->gen <= 5);
+   assert(devinfo->gen <= 5);
 
    if (!rvalue->type->is_boolean())
       return;
@@ -3681,7 +3681,7 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
    this->virtual_grf_end = NULL;
    this->live_intervals = NULL;
 
-   this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+   this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
 
    this->uniforms = 0;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
index 8756bef79a..92d108598a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_vp.cpp
@@ -96,7 +96,7 @@ vec4_vs_visitor::emit_program_code()
          break;
 
       case OPCODE_ARL:
-         if (brw->gen >= 6) {
+         if (devinfo->gen >= 6) {
             dst.writemask = WRITEMASK_X;
             dst_reg dst_f = dst;
             dst_f.type = BRW_REGISTER_TYPE_F;
@@ -532,7 +532,7 @@ vec4_vs_visitor::get_vp_src_reg(const prog_src_register &src)
          dst_reladdr.writemask = WRITEMASK_X;
          emit(ADD(dst_reladdr, this->vp_addr_reg, src_reg(src.Index)));
 
-         if (brw->gen < 6)
+         if (devinfo->gen < 6)
             emit(MUL(dst_reladdr, reladdr, src_reg(16)));
 
       #if 0