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2015-12-21Backend: Fix a memory leak for structurizer.HEADmasterJunyan He1-5/+4
2015-12-21add support for build option -cl-fast-relaxed-mathGuo Yejun5-12/+34
2015-12-14fix debug instruction welform assert.Luo Xionghu1-1/+7
2015-12-14fix workgroup_broadcast instruction debug mode assert.Luo Xionghu1-1/+1
2015-12-14Backend: Implement the non-constant extractelement scalarizePan Xiuli1-7/+39
2015-12-14Backend: Add reduce add to gen_context.Junyan He1-2/+22
2015-12-14Backend: Implement reduce min and max in gen_contextJunyan He1-5/+279
2015-12-14Backend: Add state register into schedule consideration.Junyan He1-4/+12
2015-12-14Backend: Add WORKGROUP_OP instruction selection.Junyan He6-0/+41
2015-12-14Add forward message function for gen encoder.Junyan He2-0/+14
2015-12-14Backend: Establishing the thread/TID-EUID map.Junyan He2-8/+151
2015-12-14libocl: Refine the workgroup functions, add signed info.Junyan He1-57/+57
2015-12-14Backend: Add threadid as a curbe register.Junyan He4-3/+7
2015-12-14Backend: Add tidMapSLM and wgBroadcastSLM to each function.Junyan He3-9/+20
2015-12-14Backend: Add sr0 reg helper function.Junyan He2-7/+11
2015-12-14add Broxton supportGuo Yejun8-4/+171
2015-12-10fix LLVM 3.5 fail.Luo Xionghu1-0/+14
2015-12-10Backend: refine mix with hardware lrp functionPan Xiuli13-1/+37
2015-12-10backend: enable option -dump-spir-binary to generate SPIR binary from beignet.Luo Xionghu1-5/+22
2015-12-10libocl: Add three work-item built-in functionPan Xiuli2-0/+33
2015-12-09GBE: implement pre-register-allocation instruction scheduling.Zhigang Gong1-21/+116
2015-12-09change the sampler type value to keep same with spir spec.Luo Xionghu1-17/+16
2015-12-09gbe/libocl: define the gentype half_xxx math function instead of using MACRO.Luo Xionghu3-29/+70
2015-12-09gbe: add vec_type_hint's type into functionAttributes.Luo Xionghu3-7/+104
2015-12-09gbe/libocl: change xxx_fence function to OVERLOADABLE.Luo Xionghu2-6/+6
2015-12-09gbe: use kernel_arg_base_type to recognize image arguments.Luo Xionghu2-7/+21
2015-12-09gbe/libocl: define the vloada_xxx function instead of using MACRO.Luo Xionghu2-8/+26
2015-12-02GBE/DebugInfo: Print line and column NO. with ASMBai Yannan1-0/+7
2015-12-02GBE/DebugInfo: Pass debug info : SEL IR => GenInsnBai Yannan4-1/+23
2015-12-02GBE/DebugInfo: Pass debug info : GEN IR => SEL IRBai Yannan2-0/+14
2015-12-02GBE/DebugInfo: Pass debug info :llvm IR => GEN IRBai Yannan4-1/+25
2015-12-02GBE/DebugInfo: Enable new featureBai Yannan2-0/+7
2015-11-25Handle the WorkGroup_Broadcast logic in insn_selection.Junyan He1-0/+87
2015-11-25Add WorkGroup functions to Gen IR logic in llvm_gen_backend.Junyan He2-1/+96
2015-11-25Add the WorkGroupInstruction as a new type of instruction.Junyan He3-0/+190
2015-11-25libocl: Add the module for work_group functions.Junyan He4-1/+246
2015-11-25Backend: Refine printfs into ir unitPan Xiuli8-29/+25
2015-11-25GBE: decrease the loop unrolling threshold to 640.Zhigang Gong1-1/+1
2015-11-25GBE: remove useless assertions code.Zhigang Gong1-9/+5
2015-11-25GBE: don't assert even if we fail to compile kernel at the backend stage.Zhigang Gong5-17/+31
2015-11-25GBE: extent register allocator size/offset to 32bit.Zhigang Gong2-29/+29
2015-11-25Backend: Add gen9 barrier prediction settingPan Xiuli1-0/+1
2015-11-24Backend: add debugwait functionPan Xiuli13-5/+91
2015-11-24Backend: enable to choose notification registerPan Xiuli3-5/+5
2015-11-20GBE: CreateCall2 is removed in llvm 3.7.Ruiling Song1-4/+7
2015-11-19Fix sizing error for bitfieldGiuseppe Bilotta1-1/+1
2015-11-17Backend: Append the reg interval for registers need for profiling.Junyan He1-0/+47
2015-11-17Backend: Implement StoreProfilingInstruction in GenContext.Junyan He1-0/+167
2015-11-17Backend: Implement emitCalcTimestampInstruction in GenContext.Junyan He1-2/+109
2015-11-17Backend: Add ADD_ and SUB_ timestamps help functions.Junyan He4-7/+67
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