Backend: Add WORKGROUP_OP instruction selection.

Signed-off-by: Junyan He <junyan.he@linux.intel.com>
Reviewed-by: Yang Rong <rong.r.yang@intel.com>

6 files changed, 41 insertions, 0 deletions

diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 6d0e8a53..1bb36d5f 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -2851,6 +2851,9 @@ namespace gbe
     } p->pop();
   }
 
+  void GenContext::emitWorkGroupOpInstruction(const SelectionInstruction &insn) {
+  }
+
   void GenContext::setA0Content(uint16_t new_a0[16], uint16_t max_offset, int sz) {
     if (sz == 0)
       sz = 8;
diff --git a/backend/src/backend/gen_context.hpp b/backend/src/backend/gen_context.hpp
index da9bbbed..22ec0eac 100644
--- a/backend/src/backend/gen_context.hpp
+++ b/backend/src/backend/gen_context.hpp
@@ -179,6 +179,7 @@ namespace gbe
     virtual void emitF64DIVInstruction(const SelectionInstruction &insn);
     void emitCalcTimestampInstruction(const SelectionInstruction &insn);
     void emitStoreProfilingInstruction(const SelectionInstruction &insn);
+    void emitWorkGroupOpInstruction(const SelectionInstruction &insn);
     void scratchWrite(const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode);
     void scratchRead(const GenRegister dst, const GenRegister header, uint32_t offset, uint32_t reg_num, uint32_t reg_type, uint32_t channel_mode);
     unsigned beforeMessage(const SelectionInstruction &insn, GenRegister bti, GenRegister flagTemp, GenRegister btiTmp, unsigned desc);
diff --git a/backend/src/backend/gen_insn_gen7_schedule_info.hxx b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
index 739cc044..8ef422fa 100644
--- a/backend/src/backend/gen_insn_gen7_schedule_info.hxx
+++ b/backend/src/backend/gen_insn_gen7_schedule_info.hxx
@@ -47,3 +47,4 @@ DECL_GEN7_SCHEDULE(I64SATSUB,       20,        40,      20)
 DECL_GEN7_SCHEDULE(F64DIV,          20,        40,      20)
 DECL_GEN7_SCHEDULE(CalcTimestamp,   80,        1,        1)
 DECL_GEN7_SCHEDULE(StoreProfiling,  80,        1,        1)
+DECL_GEN7_SCHEDULE(WorkGroupOp, 	80, 		1,		 1)
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index b5e6994a..630f5bcc 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -684,6 +684,9 @@ namespace gbe
     void I64REM(Reg dst, Reg src0, Reg src1, GenRegister *tmp, int tmp_int);
     /*! double division */
     void F64DIV(Reg dst, Reg src0, Reg src1, GenRegister* tmp, int tmpNum);
+    /*! Work Group Operations */
+    void WORKGROUP_OP(uint32_t wg_op, Reg dst, GenRegister src, GenRegister nextThreadID,
+                     GenRegister threadID, GenRegister threadn, GenRegister tmp);
     /* common functions for both binary instruction and sel_cmp and compare instruction.
        It will handle the IMM or normal register assignment, and will try to avoid LOADI
        as much as possible. */
@@ -1902,6 +1905,20 @@ namespace gbe
     }
   }
 
+  void Selection::Opaque::WORKGROUP_OP(uint32_t wg_op, Reg dst, GenRegister src, GenRegister nextThreadID,
+                      GenRegister threadID, GenRegister threadn, GenRegister tmp) {
+    SelectionInstruction *insn = this->appendInsn(SEL_OP_WORKGROUP_OP, 3, 4);
+    insn->extra.workgroupOp = wg_op;
+    insn->dst(0) = dst;
+    insn->dst(1) = nextThreadID;
+    insn->dst(2) = tmp;
+
+    insn->src(0) = src;
+    insn->src(1) = nextThreadID;
+    insn->src(2) = threadID;
+    insn->src(3) = threadn;
+  }
+
   // Boiler plate to initialize the selection library at c++ pre-main
   static SelectionLibrary *selLib = NULL;
   static void destroySelectionLibrary(void) { GBE_DELETE(selLib); }
@@ -6186,9 +6203,26 @@ extern bool OCL_DEBUGINFO; // first defined by calling BVAR in program.cpp
 
         /* Third, get the next thread ID which we will Forward MSG to. */
         GenRegister nextThreadID = getNextThreadID(sel, slmAddr);
+        GenRegister threadID = sel.selReg(ocl::threadid, ir::TYPE_U32);
+        GenRegister threadNum = sel.selReg(ocl::threadn, ir::TYPE_U32);
+        GenRegister tmp = GenRegister::retype(sel.selReg(sel.reg(FAMILY_DWORD)), GEN_TYPE_UD);
+
+        const Type type = insn.getType();
+        const GenRegister dst = sel.selReg(insn.getDst(0), type);
+        const uint32_t srcNum = insn.getSrcNum();
+        GBE_ASSERT(srcNum == 3);
+        GBE_ASSERT(insn.getSrc(0) == ir::ocl::threadn);
+        GBE_ASSERT(insn.getSrc(1) == ir::ocl::threadid);
+        GenRegister src = sel.selReg(insn.getSrc(2), type);
+        sel.push(); {
+          sel.curr.flag = 0;
+          sel.curr.subFlag = 1;
+          sel.WORKGROUP_OP(workGroupOp, dst, src, nextThreadID, threadID, threadNum, tmp);
+        } sel.pop();
       } else {
         GBE_ASSERT(0);
       }
+
       return true;
     }
     DECL_CTOR(WorkGroupInstruction, 1, 1);
diff --git a/backend/src/backend/gen_insn_selection.hpp b/backend/src/backend/gen_insn_selection.hpp
index 83d64bec..3889ef20 100644
--- a/backend/src/backend/gen_insn_selection.hpp
+++ b/backend/src/backend/gen_insn_selection.hpp
@@ -149,6 +149,7 @@ namespace gbe
         uint32_t profilingType:16;
         uint32_t profilingBTI:16;
       };
+      uint32_t workgroupOp;
     } extra;
     /*! Gen opcode */
     uint8_t opcode;
diff --git a/backend/src/backend/gen_insn_selection.hxx b/backend/src/backend/gen_insn_selection.hxx
index 5611a4f8..597e0420 100644
--- a/backend/src/backend/gen_insn_selection.hxx
+++ b/backend/src/backend/gen_insn_selection.hxx
@@ -93,3 +93,4 @@ DECL_SELECTION_IR(WHILE, UnaryInstruction)
 DECL_SELECTION_IR(F64DIV, F64DIVInstruction)
 DECL_SELECTION_IR(CALC_TIMESTAMP, CalcTimestampInstruction)
 DECL_SELECTION_IR(STORE_PROFILING, StoreProfilingInstruction)
+DECL_SELECTION_IR(WORKGROUP_OP, WorkGroupOpInstruction)