draft.spillsimd16

Signed-off-by: Zhigang Gong <zhigang.gong@intel.com>

3 files changed, 55 insertions, 12 deletions

diff --git a/backend/src/backend/context.cpp b/backend/src/backend/context.cpp
index 46d8f928..dea90afd 100644
--- a/backend/src/backend/context.cpp
+++ b/backend/src/backend/context.cpp
@@ -337,6 +337,15 @@ namespace gbe
     // r0 (GEN_REG_SIZE) is always set by the HW and used at the end by EOT
     this->registerAllocator = GBE_NEW(RegisterAllocator, GEN_REG_SIZE, OCL_REG_FILE_SIZE - GEN_REG_SIZE);
     this->scratchAllocator = GBE_NEW(ScratchAllocator, 12*KB);
+#if 1
+    if (/*name == "Intersect"*/ /*name == "Sampler"*/ name == "AdvancePaths") {
+      this->simdWidth = 16;
+      return;
+    } else {
+      this->simdWidth = 8;
+      return;
+    }
+#endif
     if (fn.getSimdWidth() == 0 || OCL_SIMD_WIDTH != 15)
       this->simdWidth = nextHighestPowerOf2(OCL_SIMD_WIDTH);
     else
diff --git a/backend/src/backend/gen_insn_selection.cpp b/backend/src/backend/gen_insn_selection.cpp
index 47d9704f..0aa378d1 100644
--- a/backend/src/backend/gen_insn_selection.cpp
+++ b/backend/src/backend/gen_insn_selection.cpp
@@ -2200,9 +2200,16 @@ namespace gbe
       const uint32_t simdWidth = sel.curr.execWidth;
       const Type type = insn.getType();
       if (type == TYPE_U32 || type == TYPE_S32) {
-        GenRegister dst  = sel.selReg(insn.getDst(0), type);
-        GenRegister src0 = sel.selReg(insn.getSrc(0), type);
-        GenRegister src1 = sel.selReg(insn.getSrc(1), type);
+        GenRegister tmpDst  = sel.selReg(insn.getDst(0), type);
+        GenRegister tmpSrc0 = sel.selReg(insn.getSrc(0), type);
+        GenRegister tmpSrc1 = sel.selReg(insn.getSrc(1), type);
+
+        GenRegister dst = sel.selReg(sel.reg(FAMILY_DWORD), type);
+        GenRegister src0 = sel.selReg(sel.reg(FAMILY_DWORD), type);
+        GenRegister src1 = sel.selReg(sel.reg(FAMILY_DWORD), type);
+        //sel.MOV(dst, tmpDst);
+        sel.MOV(src0, tmpSrc0);
+        sel.MOV(src1, tmpSrc1);
 
         sel.push();
 
@@ -2243,6 +2250,7 @@ namespace gbe
         }
 
         sel.pop();
+        sel.MOV(tmpDst, dst);
 
         // All children are marked as root
         markAllChildren(dag);
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 8f0db823..38a0d58c 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -675,6 +675,7 @@ namespace gbe
     for(uint32_t i = 0; i < regNum; i++) {
       const GenRegInterval * cur = starting[i];
       const GenRegInterval * exp = ending[toExpire];
+#if 1
       if(exp->maxID < cur->minID) {
         auto it = spilledRegs.find(exp->reg);
         GBE_ASSERT(it != spilledRegs.end());
@@ -683,6 +684,7 @@ namespace gbe
         }
         toExpire++;
       }
+#endif
       auto it = spilledRegs.find(cur->reg);
       GBE_ASSERT(it != spilledRegs.end());
       if(cur->minID == cur->maxID) {
@@ -728,7 +730,7 @@ namespace gbe
        uint32_t regSize;
        ir::RegisterFamily family;
        getRegAttrib(reg, regSize, &family);
-
+       printf("insert new reg %%%d grf %d regSize %d family %d dword %d \n", reg.value(), grfOffset/32, regSize, family, ir::FAMILY_DWORD);
        if (reg.value() >= ctx.getFunction().getRegisterFile().regNum()) {
          printf("reg.value %d regNum %d \n", reg.value(), ctx.getFunction().getRegisterFile().regNum());
          return;
@@ -737,9 +739,12 @@ namespace gbe
        if ((regSize == ctx.getSimdWidth()/8 * GEN_REG_SIZE && family == ir::FAMILY_DWORD)
           /*|| (regSize == 2 * ctx.getSimdWidth()/8 * GEN_REG_SIZE && family == ir::FAMILY_QWORD)*/) {
          GBE_ASSERT(offsetReg.find(grfOffset) == offsetReg.end());
+         printf("insert grfOffset %d reg %d\n", grfOffset, reg);
          offsetReg.insert(std::make_pair(grfOffset, reg));
          spillCandidate.insert(intervals[reg]);
+         printf("reg %d maxid %d minid %d \n", intervals[reg].reg.value(), intervals[reg].maxID, intervals[reg].minID);
        }
+       printf("done\n");
      }
   }
 
@@ -770,17 +775,27 @@ namespace gbe
     return true;
   }
 
+  // Check whethere a vector which is allocated can be spilled out
   INLINE bool GenRegAllocator::Opaque::vectorCanSpill(SelectionVector *vector) {
     for(uint32_t id = 0; id < vector->regNum; id++)
-      if (spillCandidate.find(intervals[(ir::Register)(vector->reg[id]).value.reg])
-          == spillCandidate.end())
+      if (spillCandidate.find(intervals[(ir::Register)(vector->reg[id].value.reg)])
+          == spillCandidate.end()) {
+        printf("can't spill %d \n", vector->reg[id].value.reg);
+        ir::Register reg = (ir::Register)(vector->reg[id].value.reg);
+        printf("reg %d maxid %d minid %d \n", intervals[reg].reg.value(), intervals[reg].maxID, intervals[reg].minID);
         return false;
+      }
     return true;
   }
-
+#if 0
+  // Check whether a register which is not allocated can be spilled out.
+  INLINE bool GenRegAllocator::Opaque::vectorCanSpill(ir::Register reg) {
+  }
+#endif
   INLINE bool GenRegAllocator::Opaque::spillAtInterval(GenRegInterval interval,
                                                        int size,
                                                        uint32_t alignment) {
+    printf("spill At interval %d size %d \n", interval.reg.value(), size);
     if (reservedReg == 0)
       return false;
     auto it = spillCandidate.begin();
@@ -788,14 +803,17 @@ namespace gbe
     // endpoint is after all the spillCandidate register's endpoint we return false. The
     // caller will spill current register.
     if (it == spillCandidate.end()
-        || (it->getMaxID() <= interval.maxID
+        /*|| (it->getMaxID() <= interval.maxID
             && alignment == ctx.getSimdWidth()/8 * GEN_REG_SIZE
-            && interval.reg.value() < ctx.getFunction().getRegisterFile().regNum()))
+            && interval.reg.value() < ctx.getFunction().getRegisterFile().regNum())*/) {
+      printf("it spill end %d \n", it == spillCandidate.end());
       return false;
+    }
 
     ir::Register reg = it->getReg();
     set<ir::Register> spillSet;
     int32_t savedSize = size;
+    printf("try spill reg %d \n", reg.value());
     while(size > 0) {
       auto vectorIt = vectorMap.find(reg);
       bool isVector = vectorIt != vectorMap.end();
@@ -817,8 +835,10 @@ namespace gbe
         spillSet.insert(reg);
         size -= family == ir::FAMILY_QWORD ? 2 * GEN_REG_SIZE * ctx.getSimdWidth()/8
                                            : GEN_REG_SIZE * ctx.getSimdWidth()/8;
-      } else
+      } else {
         needRestart = true; // is a vector which could not be spilled.
+        printf("could not spill this vector. \n");
+      }
 
       if (size <= 0)
         break;
@@ -829,16 +849,22 @@ namespace gbe
         auto nextRegIt = offsetReg.find(nextOffset);
         if (nextRegIt != offsetReg.end())
           reg = nextRegIt->second;
-        else
+        else {
+          printf("can't find this offset \n");
           needRestart = true;
+        }
       }
 
       if (needRestart) {
         // next register is not in spill candidate.
         // let's move to next candidate and start over.
+        if (spillSet.size() > 0)
+          break;
         it++;
-        if (it == spillCandidate.end())
+        if (it == spillCandidate.end()) {
+          printf("hhhh\n");
           return false;
+        }
         reg = it->getReg();
         size = savedSize;
         spillSet.clear();