Merge from branches/ARM, all parts of the ARM-Linux port except for

the changes to do with reading and using ELF and DWARF3 info.
This breaks all targets except amd64-linux and x86-linux.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10982 a5019735-40e9-0310-863c-91ae7b9d1cf9

3 files changed, 62 insertions, 2 deletions

diff --git a/cachegrind/Makefile.am b/cachegrind/Makefile.am
index 94df249e..fc1c4007 100644
--- a/cachegrind/Makefile.am
+++ b/cachegrind/Makefile.am
@@ -40,7 +40,8 @@ CACHEGRIND_SOURCES_COMMON = \
 	cg_main.c \
 	cg-x86-amd64.c \
 	cg-ppc32.c \
-	cg-ppc64.c
+	cg-ppc64.c \
+	cg-arm.c
 
 cachegrind_@VGCONF_ARCH_PRI@_@VGCONF_OS@_SOURCES      = \
 	$(CACHEGRIND_SOURCES_COMMON)
diff --git a/cachegrind/cg-arm.c b/cachegrind/cg-arm.c
new file mode 100644
index 00000000..78250c8c
--- /dev/null
+++ b/cachegrind/cg-arm.c
@@ -0,0 +1,59 @@
+
+/*--------------------------------------------------------------------*/
+/*--- ARM-specific definitions.                           cg-arm.c ---*/
+/*--------------------------------------------------------------------*/
+
+/*
+   This file is part of Cachegrind, a Valgrind tool for cache
+   profiling programs.
+
+   Copyright (C) 2005-2009 Johan Bjork
+      jbjoerk@gmail.com
+
+   This program is free software; you can redistribute it and/or
+   modify it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307, USA.
+
+   The GNU General Public License is contained in the file COPYING.
+*/
+
+#if defined(VGA_arm)
+
+#include "pub_tool_basics.h"
+#include "pub_tool_libcbase.h"
+#include "pub_tool_libcassert.h"
+#include "pub_tool_libcprint.h"
+
+#include "cg_arch.h"
+
+void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+                           Bool all_caches_clo_defined)
+{
+   // Set caches to default (for Cortex-A8 ?)
+   *I1c = (cache_t) {  16384, 4, 64 };
+   *D1c = (cache_t) {  16384, 4, 64 };
+   *L2c = (cache_t) { 262144, 8, 64 };
+
+   if (!all_caches_clo_defined) {
+      VG_(message)(Vg_DebugMsg, 
+                   "Warning: Cannot auto-detect cache config on ARM, using one "
+                   "or more defaults ");
+   }
+}
+
+#endif // #if defined(VGA_arm)
+
+/*--------------------------------------------------------------------*/
+/*--- end                                                 cg-arm.c ---*/
+/*--------------------------------------------------------------------*/
diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c
index e19a3d35..350b5bc7 100644
--- a/cachegrind/cg_branchpred.c
+++ b/cachegrind/cg_branchpred.c
@@ -44,7 +44,7 @@
 
 /* How many bits at the bottom of an instruction address are
    guaranteed to be zero? */
-#if defined(VGA_ppc32) || defined(VGA_ppc64)
+#if defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_arm)
 #  define N_IADDR_LO_ZERO_BITS 2
 #elif defined(VGA_x86) || defined(VGA_amd64)
 #  define N_IADDR_LO_ZERO_BITS 0