path: root/src/r600_ctx.c

/*
 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Jerome Glisse
 */
#include <stdlib.h>
#include <jansson.h>
#include "radeon_priv.h"
#include "r600d.h"

struct cs_packet3 {
	unsigned		op;
	char			name[64];
	int (*parse)(struct radeon_ctx *ctx);
};

int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc)
{
	unsigned id, count, type, op;

	id = ctx->next_id;
	type = PKT_TYPE_G(ctx->pm4[id]);
	count = PKT_COUNT_G(ctx->pm4[id]);
	op = PKT3_IT_OPCODE_G(ctx->pm4[id]);
	if (type != 3 || op != PKT3_NOP) {
		fprintf(stderr, "%s next packet is not packet 3 NOP\n", __func__);
		return -EINVAL;
	}
	*reloc = ctx->pm4[id + 1];
	ctx->next_id += count + 2;
	return 0;
}

static int r600_bof_ctx_new_draw(struct radeon_ctx *ctx)
{
	struct radeon_draw *draw;
	unsigned i, j;
	int r;

	draw = ctx->cdraw;
	if (draw->state[R600_DB] == NULL) {
		draw->state[R600_DB] = radeon_state(ctx->radeon, R600_DB_TYPE, R600_DB);
		if (draw->state[R600_DB] == NULL)
			return -ENOMEM;
	}
	draw->state[R600_CB0]->nbo = 3;
	draw->state[R600_DB]->nbo = 1;
	draw->state[R600_VS_SHADER]->nbo = 2;
	draw->state[R600_PS_SHADER]->nbo = 1;
	if (draw->state[R600_DB]->bo[0] == NULL) {
		draw->state[R600_DB]->bo[0] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
		draw->state[R600_DB]->states[R600_DB__DB_DEPTH_SIZE] =
			draw->state[R600_CB0]->states[R600_CB0__CB_COLOR0_SIZE];
		draw->state[R600_DB]->states[R600_DB__DB_DEPTH_VIEW] =
			draw->state[R600_CB0]->states[R600_CB0__CB_COLOR0_VIEW];
		draw->state[R600_DB]->placement[0] = draw->state[R600_CB0]->placement[0];
		draw->state[R600_DB]->placement[1] = draw->state[R600_CB0]->placement[1];
	}
	if (draw->state[R600_CB0]->bo[1] == NULL) {
		draw->state[R600_CB0]->bo[1] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
		draw->state[R600_CB0]->placement[2] = draw->state[R600_CB0]->placement[0];
		draw->state[R600_CB0]->placement[3] = draw->state[R600_CB0]->placement[1];
	}
	if (draw->state[R600_CB0]->bo[2] == NULL) {
		draw->state[R600_CB0]->bo[2] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
		draw->state[R600_CB0]->placement[4] = draw->state[R600_CB0]->placement[0];
		draw->state[R600_CB0]->placement[5] = draw->state[R600_CB0]->placement[1];
	}
	if (draw->state[R600_VS_SHADER]->bo[1] == NULL) {
		draw->state[R600_VS_SHADER]->bo[1] = radeon_object_incref(draw->state[R600_VS_SHADER]->bo[0]);
		draw->state[R600_VS_SHADER]->placement[2] = draw->state[R600_VS_SHADER]->placement[0];
		draw->state[R600_VS_SHADER]->placement[3] = draw->state[R600_VS_SHADER]->placement[1];
	}
	for (i = 0; i < draw->nstate; i++) {
		if (draw->state[i]) {
			for (j = 0; j < draw->state[i]->nbo; j++) {
				if (draw->state[i]->bo[j] == NULL) {
					fprintf(stderr, "%s missing bo %d for state %s\n",
							__func__, j, ctx->radeon->type[i].name);
					return -EINVAL;
				}
			}
		}
	}
	draw = radeon_draw_duplicate(ctx->cdraw);
	if (draw == NULL) {
		return -ENOMEM;
	}
	draw->state[R600_DRAW] = radeon_state_decref(draw->state[R600_DRAW]);
	r = radeon_ctx_set_draw_new(ctx, draw);
	if (r) {
		radeon_draw_decref(draw);
		return r;
	}
	return 0;
}

static int cs_set_config_reg(struct radeon_ctx *ctx)
{
	unsigned i, count, base;
	int r;

	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
	base = (ctx->pm4[ctx->id + 1] + 0x2000) << 2;
	for (i = 0; i < count; i++, base += 4) {
		r = radeon_ctx_draw_set_reg(ctx, base, ctx->pm4[ctx->id + 2 + i]);
		if (r && r != -EINVAL)
			return r;
	}
	return 0;
}

static int cs_set_context_reg(struct radeon_ctx *ctx)
{
	unsigned i, count, base;
	int r;

	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
	base = (ctx->pm4[ctx->id + 1] + 0xA000) << 2;
	for (i = 0; i < count; i++, base += 4) {
		r = radeon_ctx_draw_set_reg(ctx, base, ctx->pm4[ctx->id + 2 + i]);
		if (r && r != -EINVAL)
			return r;
	}
	return 0;
}

static int cs_draw_auto(struct radeon_ctx *ctx)
{
	int r;

	r = radeon_ctx_draw_set_reg(ctx, R_008970_VGT_NUM_INDICES, ctx->pm4[ctx->id + 1]);
	if (r)
		return r;
	r = radeon_ctx_draw_set_reg(ctx, R_0287F0_VGT_DRAW_INITIATOR, ctx->pm4[ctx->id + 2]);
	if (r)
		return r;
	return r600_bof_ctx_new_draw(ctx);
}

static int cs_draw_index(struct radeon_ctx *ctx)
{
	int r;

	r = radeon_ctx_draw_set_reg(ctx, R_0287E4_VGT_DMA_BASE_HI, ctx->pm4[ctx->id + 2]);
	if (r)
		return r;
	r = radeon_ctx_draw_set_reg(ctx, R_0287E8_VGT_DMA_BASE, ctx->pm4[ctx->id + 1]);
	if (r)
		return r;
	r = radeon_ctx_draw_set_reg(ctx, R_008970_VGT_NUM_INDICES, ctx->pm4[ctx->id + 3]);
	if (r)
		return r;
	r = radeon_ctx_draw_set_reg(ctx, R_0287F0_VGT_DRAW_INITIATOR, ctx->pm4[ctx->id + 4]);
	if (r)
		return r;
	ctx->cdraw->state[R600_DRAW]->nbo = 1;
	return r600_bof_ctx_new_draw(ctx);
}

static int cs_set_alu_const(struct radeon_ctx *ctx)
{
	unsigned i, count, offset;
	int r;

	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
	offset = (ctx->pm4[ctx->id + 1] << 2) + R_030000_SQ_ALU_CONSTANT0_0;
	for (i = 0; i < count; i++, offset += 4) {
		r = radeon_ctx_draw_set_reg(ctx, offset, ctx->pm4[ctx->id + 2 + i]);
		if (r)
			return r;
	}
	return 0;
}

static int cs_set_sampler(struct radeon_ctx *ctx)
{
	unsigned i, count, offset;
	int r;

	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
	offset = (ctx->pm4[ctx->id + 1] << 2) + R_03C000_SQ_TEX_SAMPLER_WORD0_0;
	for (i = 0; i < count; i++, offset += 4) {
		r = radeon_ctx_draw_set_reg(ctx, offset, ctx->pm4[ctx->id + 2 + i]);
		if (r)
			return r;
	}
	return 0;
}

static int cs_set_resource(struct radeon_ctx *ctx)
{
	unsigned i, count, offset, typeid, stateid, id, reloc;
	struct radeon_state *state;
	struct radeon_object *bo;
	int r;

	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
	offset = (ctx->pm4[ctx->id + 1] << 2) + R_038000_SQ_TEX_RESOURCE_WORD0_0;
	for (i = 0; i < count; i++, offset += 4) {
		r = radeon_ctx_draw_set_reg(ctx, offset, ctx->pm4[ctx->id + 2 + i]);
		if (r)
			return r;
		radeon_reg_id(ctx->radeon, offset, &typeid, &stateid, &id);
		state = ctx->cdraw->state[stateid];
		if (id == 6) {
			switch (G_038018_TYPE(ctx->pm4[ctx->id + 2 + i])) {
			case 2:
				r = radeon_ctx_next_reloc(ctx, &reloc);
				if (r)
					return r;
				bo = radeon_ctx_get_bo(ctx, reloc);
				if (bo == NULL)
					return -ENOMEM;
				radeon_object_decref(state->bo[0]);
				ctx->cdraw->state[stateid]->bo[0] = bo;
				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[0]);
				r = radeon_ctx_next_reloc(ctx, &reloc);
				if (r)
					return r;
				bo = radeon_ctx_get_bo(ctx, reloc);
				if (bo == NULL)
					return -ENOMEM;
				radeon_object_decref(state->bo[1]);
				ctx->cdraw->state[stateid]->bo[1] = bo;
				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[2]);
				state->nbo = 2;
				break;
			case 3:
				r = radeon_ctx_next_reloc(ctx, &reloc);
				if (r)
					return r;
				bo = radeon_ctx_get_bo(ctx, reloc);
				if (bo == NULL)
					return -ENOMEM;
				radeon_object_decref(state->bo[0]);
				ctx->cdraw->state[stateid]->bo[0] = bo;
				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[0]);
				state->nbo = 1;
				break;
			default:
				ctx->cdraw->state[stateid] = radeon_state_decref(state);
				break;
			}
		}
	}
	return 0;
}

static int cs_index_type(struct radeon_ctx *ctx)
{
	return radeon_ctx_draw_set_reg(ctx, R_028A7C_VGT_DMA_INDEX_TYPE, ctx->pm4[ctx->id + 1]);
}

static int cs_num_instances(struct radeon_ctx *ctx)
{
	return radeon_ctx_draw_set_reg(ctx, R_028A88_VGT_DMA_NUM_INSTANCES, ctx->pm4[ctx->id + 1]);
}

static int cs_nop(struct radeon_ctx *ctx)
{
	return 0;
}

struct cs_packet3 r600_packet3[] = {
	{0x10, "NOP", &cs_nop},
	{0x17, "INDIRECT_BUFFER_END", NULL},
	{0x20, "SET_PREDICATION", NULL},
	{0x21, "REG_RMW", NULL},
	{0x22, "COND_EXEC", NULL},
	{0x23, "PRED_EXEC", NULL},
	{0x24, "START_3D_CMDBUF", &cs_nop},
	{0x27, "DRAW_INDEX_2", NULL},
	{0x28, "CONTEXT_CONTROL", &cs_nop},
	{0x29, "DRAW_INDEX_IMMD_BE", NULL},
	{0x2A, "INDEX_TYPE", &cs_index_type},
	{0x2B, "DRAW_INDEX", &cs_draw_index},
	{0x2D, "DRAW_INDEX_AUTO", &cs_draw_auto},
	{0x2E, "DRAW_INDEX_IMMD", NULL},
	{0x2F, "NUM_INSTANCES", &cs_num_instances},
	{0x32, "INDIRECT_BUFFER", NULL},
	{0x34, "STRMOUT_BUFFER_UPDATE", NULL},
	{0x38, "INDIRECT_BUFFER_MP", NULL},
	{0x39, "MEM_SEMAPHORE", NULL},
	{0x3A, "MPEG_INDEX", NULL},
	{0x3C, "WAIT_REG_MEM", NULL},
	{0x3D, "MEM_WRITE", NULL},
	{0x40, "CP_INTERRUPT", NULL},
	{0x43, "SURFACE_SYNC", &cs_nop},
	{0x44, "ME_INITIALIZE", NULL},
	{0x45, "COND_WRITE", NULL},
	{0x46, "EVENT_WRITE", &cs_nop},
	{0x47, "EVENT_WRITE_EOP", NULL},
	{0x57, "ONE_REG_WRITE", NULL},
	{0x68, "SET_CONFIG_REG", &cs_set_config_reg},
	{0x69, "SET_CONTEXT_REG", &cs_set_context_reg},
	{0x6A, "SET_ALU_CONST", &cs_set_alu_const},
	{0x6B, "SET_BOOL_CONST", NULL},
	{0x6C, "SET_LOOP_CONST", NULL},
	{0x6D, "SET_RESOURCE", &cs_set_resource},
	{0x6E, "SET_SAMPLER", &cs_set_sampler},
	{0x6F, "SET_CTL_CONST", &cs_nop},
	{0x73, "SURFACE_BASE_UPDATE", &cs_nop},
};

static int cs_packet3_ctx(struct radeon_ctx *ctx, unsigned op)
{
	unsigned i;

	for (i = 0; i < (sizeof(r600_packet3)/sizeof(r600_packet3[0])); i++) {
		if (r600_packet3[i].op == op) {
			if (r600_packet3[i].parse)
				return r600_packet3[i].parse(ctx);
		}
	}
	fprintf(stderr, "%s Unknown packet 3 0x%02X at %d\n",
			__func__, op, ctx->id);
	return 0;
}

int r600_ctx_draw(struct radeon_ctx *ctx)
{
	unsigned type, count, index, i, op;
	int r;

	ctx->id = 0;
	do {
		type = PKT_TYPE_G(ctx->pm4[ctx->id]);
		count = PKT_COUNT_G(ctx->pm4[ctx->id]);
		ctx->next_id = ctx->id + count + 2;
		switch (type) {
		case 2:
			count = 0;
			break;
		case 0:
			index = PKT0_BASE_INDEX_G(ctx->pm4[ctx->id]) << 2;
			for (i = 0; i <= count; i++, index += 4) {
				r = radeon_ctx_draw_set_reg(ctx, index, ctx->pm4[ctx->id + i + 1]);
				if (r)
					return r;
			}
			break;
		case 3:
			op = PKT3_IT_OPCODE_G(ctx->pm4[ctx->id]);
			r = cs_packet3_ctx(ctx, op);
			if (r) {
				fprintf(stderr, "%s error parsing 0x%02X packet3\n", __func__, op);
				return r;
			}
			break;
		default:
			fprintf(stderr, "(%s:%d) Unknown packet type %d at %d\n",
					__func__, __LINE__, type, ctx->id);
			return -EINVAL;
		}
		ctx->id = ctx->next_id;
	} while (ctx->id < ctx->cpm4);
	if (ctx->cdraw->state[R600_DRAW] == NULL) {
		ctx->ndraw--;
		ctx->draw[ctx->ndraw] = radeon_draw_decref(ctx->draw[ctx->ndraw]);
		ctx->cdraw = ctx->draw[ctx->ndraw - 1];
	}
	return 0;
}

unsigned r600_format_bpe(unsigned format)
{
	switch (format) {
	case V_0280A0_COLOR_8:
	case V_0280A0_COLOR_4_4:
	case V_0280A0_COLOR_3_3_2:
		return 1;
	case V_0280A0_COLOR_16:
	case V_0280A0_COLOR_16_FLOAT:
	case V_0280A0_COLOR_8_8:
	case V_0280A0_COLOR_5_6_5:
	case V_0280A0_COLOR_6_5_5:
	case V_0280A0_COLOR_1_5_5_5:
	case V_0280A0_COLOR_4_4_4_4:
	case V_0280A0_COLOR_5_5_5_1:
		return 2;
	case V_0280A0_COLOR_32:
	case V_0280A0_COLOR_32_FLOAT:
	case V_0280A0_COLOR_16_16:
	case V_0280A0_COLOR_16_16_FLOAT:
	case V_0280A0_COLOR_8_24:
	case V_0280A0_COLOR_8_24_FLOAT:
	case V_0280A0_COLOR_24_8:
	case V_0280A0_COLOR_24_8_FLOAT:
	case V_0280A0_COLOR_10_11_11:
	case V_0280A0_COLOR_10_11_11_FLOAT:
	case V_0280A0_COLOR_11_11_10:
	case V_0280A0_COLOR_11_11_10_FLOAT:
	case V_0280A0_COLOR_2_10_10_10:
	case V_0280A0_COLOR_8_8_8_8:
	case V_0280A0_COLOR_10_10_10_2:
	case V_0280A0_COLOR_X24_8_32_FLOAT:
		return 4;
	case V_0280A0_COLOR_32_32:
	case V_0280A0_COLOR_32_32_FLOAT:
	case V_0280A0_COLOR_16_16_16_16:
	case V_0280A0_COLOR_16_16_16_16_FLOAT:
		return 8;
	case V_0280A0_COLOR_32_32_32_32:
	case V_0280A0_COLOR_32_32_32_32_FLOAT:
		return 16;
	default:
		return 0;
	}
}

int r600_ctx_get_dst_surface(struct radeon_ctx *ctx, struct radeon_surface *dst)
{
	struct radeon_draw *draw = ctx->draw[0];
	struct radeon_state *state;
	unsigned tmp;

	if (draw == NULL)
		return -EINVAL;
	state = draw->state[R600_CB0];
	if (state == NULL || state->states == NULL)
		return -EINVAL;
	tmp = state->states[R600_CB0__CB_COLOR0_SIZE];
	dst->pitch = (G_028060_PITCH_TILE_MAX(tmp) + 1) * 8;
	dst->width = dst->pitch;
	dst->height = (G_028060_SLICE_TILE_MAX(tmp) + 1) * 64;
	dst->height = dst->height / dst->pitch;
	tmp = state->states[R600_CB0__CB_COLOR0_INFO];
	dst->bpe = r600_format_bpe(G_0280A0_FORMAT(tmp));
	dst->bo = state->bo[0]->bo;
	if ((dst->height * dst->pitch * dst->bpe) >= state->bo[0]->size) {
		dst->height = state->bo[0]->size / (dst->pitch * dst->bpe);
	}
	return 0;
}