diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2010-04-16 16:47:49 +0200 |
|---|---|---|
| committer | Jerome Glisse <jglisse@redhat.com> | 2010-04-16 16:47:49 +0200 |
| commit | f8832974cf62e0394bc6ec30d091fc1150073a56 (patch) | |
| tree | e2fdb228182ca840b200b790f0bd9e3ec5bc02f6 | |
| parent | 5b7ea48a52382deb083be8b251174ad74a8ab6e5 (diff) | |
radeondb: split block & register io access
Register of a block can be in different io space thus
split ioaccess from block.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
| -rw-r--r-- | json/rs600.json | 3850 | ||||
| -rw-r--r-- | src/radeon_reg.c | 2 | ||||
| -rw-r--r-- | src/radeon_reg.h | 4 | ||||
| -rw-r--r-- | src/rs600_reg.c | 140 | ||||
| -rw-r--r-- | tools/rdb.c | 14 | ||||
| -rw-r--r-- | tools/rdb_json.c | 8 |
6 files changed, 2047 insertions, 1971 deletions
diff --git a/json/rs600.json b/json/rs600.json index 90087eb..9bb7f90 100644 --- a/json/rs600.json +++ b/json/rs600.json @@ -1,3684 +1,3752 @@ { "block": [ { - "name": "MMIO", - "0x00007D08": { - "name": "DC_HOT_PLUG_DETECT1_INT_CONTROL", - "size": 32, - "field": [ - { - "bl": 0, - "name": "DC_HOT_PLUG_DETECT1_INT_ACK", - "value": [], - "description": "", - "access": "RW", - "bf": 0 - }, - { - "bl": 8, - "name": "DC_HOT_PLUG_DETECT1_INT_POLARITY", - "value": [], - "description": "", - "access": "RW", - "bf": 8 - }, - { - "bl": 16, - "name": "DC_HOT_PLUG_DETECT1_INT_EN", - "value": [], - "description": "", - "access": "RW", - "bf": 16 - } - ] - }, "0x00000040": { - "name": "GEN_INT_CNTL", - "size": 32, "field": [ { + "access": "RW", + "bf": 18, "bl": 18, - "name": "SCRATCH_INT_MASK", - "value": [], "description": "", - "access": "RW", - "bf": 18 + "name": "SCRATCH_INT_MASK", + "value": [] }, { + "access": "RW", + "bf": 19, "bl": 19, - "name": "GUI_IDLE_MASK", - "value": [], "description": "", - "access": "RW", - "bf": 19 + "name": "GUI_IDLE_MASK", + "value": [] }, { + "access": "RW", + "bf": 13, "bl": 13, - "name": "DMA_VIPH1_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 13 + "name": "DMA_VIPH1_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "DMA_VIPH2_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "DMA_VIPH2_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 15, "bl": 15, - "name": "DMA_VIPH3_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 15 + "name": "DMA_VIPH3_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 17, "bl": 17, - "name": "I2C_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 17 + "name": "I2C_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 19, "bl": 19, - "name": "GUI_IDLE", - "value": [], "description": "", - "access": "RW", - "bf": 19 + "name": "GUI_IDLE", + "value": [] }, { + "access": "RW", + "bf": 24, "bl": 24, - "name": "VIPH_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 24 + "name": "VIPH_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 25, "bl": 25, - "name": "SW_INT_EN", - "value": [], "description": "", - "access": "RW", - "bf": 25 + "name": "SW_INT_EN", + "value": [] }, { + "access": "RW", + "bf": 27, "bl": 27, - "name": "GEYSERVILLE", - "value": [], "description": "", - "access": "RW", - "bf": 27 + "name": "GEYSERVILLE", + "value": [] }, { + "access": "RW", + "bf": 28, "bl": 28, - "name": "HDCP_AUTHORIZED_INT", - "value": [], "description": "", - "access": "RW", - "bf": 28 + "name": "HDCP_AUTHORIZED_INT", + "value": [] }, { + "access": "RW", + "bf": 29, "bl": 29, - "name": "DVI_I2C_INT", - "value": [], "description": "", - "access": "RW", - "bf": 29 + "name": "DVI_I2C_INT", + "value": [] }, { + "access": "RW", + "bf": 30, "bl": 30, - "name": "GUIDMA", - "value": [], "description": "", - "access": "RW", - "bf": 30 + "name": "GUIDMA", + "value": [] }, { - "bl": 31, - "name": "VIDDMA", - "value": [], - "description": "", "access": "RW", - "bf": 31 - } - ] - }, - "0x00007D10": { - "name": "DC_HOT_PLUG_DETECT2_CONTROL", - "size": 32, - "field": [ - { - "bl": 0, - "name": "DC_HOT_PLUG_DETECT2_EN", - "value": [], + "bf": 31, + "bl": 31, "description": "", - "access": "RW", - "bf": 0 + "name": "VIDDMA", + "value": [] } - ] + ], + "ioname": "MMIO", + "name": "GEN_INT_CNTL", + "size": 32 }, - "0x000060A4": { - "name": "D1CRTC_STATUS_FRAME_COUNT", - "size": 32, + "0x00000044": { "field": [ { - "bl": 23, - "name": "D1CRTC_FRAME_COUNT", - "value": [], - "description": "", "access": "RW", - "bf": 0 - } - ] - }, - "0x00000E40": { - "name": "RBBM_STATUS", - "size": 32, - "field": [ - { - "bl": 6, - "name": "CMDFIFO_AVAIL", - "value": [], + "bf": 0, + "bl": 0, "description": "", - "access": "RW", - "bf": 0 + "name": "DISPLAY_INT_STAT", + "value": [] }, { - "bl": 8, - "name": "HIRQ_ON_RBB", - "value": [], - "description": "", "access": "RW", - "bf": 8 - }, - { - "bl": 9, - "name": "CPRQ_ON_RBB", - "value": [], + "bf": 1, + "bl": 1, "description": "", - "access": "RW", - "bf": 9 + "name": "VGA_INT_STAT", + "value": [] }, { - "bl": 10, - "name": "CFRQ_ON_RBB", - "value": [], - "description": "", "access": "RW", - "bf": 10 - }, - { - "bl": 11, - "name": "HIRQ_IN_RTBUF", - "value": [], + "bf": 8, + "bl": 8, "description": "", - "access": "RW", - "bf": 11 + "name": "CAP0_INT_ACTIVE", + "value": [] }, { + "access": "RW", + "bf": 12, "bl": 12, - "name": "CPRQ_IN_RTBUF", - "value": [], "description": "", - "access": "RW", - "bf": 12 + "name": "DMA_VIPH0_INT", + "value": [] }, { + "access": "RW", + "bf": 13, "bl": 13, - "name": "CFRQ_IN_RTBUF", - "value": [], "description": "", - "access": "RW", - "bf": 13 + "name": "DMA_VIPH1_INT", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "CF_PIPE_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "DMA_VIPH2_INT", + "value": [] }, { + "access": "RW", + "bf": 15, "bl": 15, - "name": "ENG_EV_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 15 + "name": "DMA_VIPH3_INT", + "value": [] }, { + "access": "RW", + "bf": 16, "bl": 16, - "name": "CP_CMDSTRM_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 16 + "name": "MC_PROBE_FAULT_STAT", + "value": [] }, { + "access": "RW", + "bf": 17, "bl": 17, - "name": "E2_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 17 + "name": "I2C_INT", + "value": [] }, { + "access": "RW", + "bf": 18, "bl": 18, - "name": "RB2D_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 18 + "name": "SCRATCH_INT_STAT", + "value": [] }, { + "access": "RW", + "bf": 19, "bl": 19, - "name": "RB3D_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 19 + "name": "GUI_IDLE_STAT", + "value": [] }, { + "access": "RW", + "bf": 20, "bl": 20, - "name": "VAP_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 20 + "name": "ATI_OVERDRIVE_INT_STAT", + "value": [] }, { + "access": "RW", + "bf": 21, "bl": 21, - "name": "RE_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 21 + "name": "MC_PROTECTION_FAULT_STAT", + "value": [] }, { + "access": "RW", + "bf": 22, "bl": 22, - "name": "TAM_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 22 + "name": "RBBM_READ_INT_STAT", + "value": [] }, { + "access": "RW", + "bf": 23, "bl": 23, - "name": "TDM_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 23 + "name": "CB_CONTEXT_SWITCH_STAT", + "value": [] }, { + "access": "RW", + "bf": 24, "bl": 24, - "name": "PB_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 24 + "name": "VIPH_INT", + "value": [] }, { + "access": "RW", + "bf": 25, "bl": 25, - "name": "TIM_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 25 + "name": "SW_INT", + "value": [] }, { + "access": "RW", + "bf": 26, "bl": 26, - "name": "GA_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 26 + "name": "SW_INT_SET", + "value": [] }, { + "access": "RW", + "bf": 27, "bl": 27, - "name": "CBA2D_BUSY", - "value": [], "description": "", + "name": "IDCT_INT_STAT", + "value": [] + }, + { "access": "RW", - "bf": 27 + "bf": 30, + "bl": 30, + "description": "", + "name": "GUIDMA_STAT", + "value": [] }, { + "access": "RW", + "bf": 31, "bl": 31, - "name": "GUI_ACTIVE", - "value": [], "description": "", + "name": "VIDDMA_STAT", + "value": [] + } + ], + "ioname": "MMIO", + "name": "GEN_INT_STATUS", + "size": 32 + }, + "0x0000004C": { + "field": [ + { + "access": "RW", + "bf": 14, + "bl": 14, + "description": "", + "name": "BUS_MASTER_DIS", + "value": [] + }, + { "access": "RW", - "bf": 31 + "bf": 20, + "bl": 20, + "description": "", + "name": "BUS_MSI_REARM", + "value": [] } - ] + ], + "ioname": "MMIO", + "name": "BUS_CNTL", + "size": 32 }, "0x00000070": { - "name": "MC_IND_INDEX", - "size": 32, "field": [ { + "access": "RW", + "bf": 0, "bl": 15, - "name": "MC_IND_ADDR", - "value": [], "description": "", - "access": "RW", - "bf": 0 + "name": "MC_IND_ADDR", + "value": [] }, { + "access": "RW", + "bf": 16, "bl": 16, - "name": "MC_IND_SEQ_RBS_0", - "value": [], "description": "", - "access": "RW", - "bf": 16 + "name": "MC_IND_SEQ_RBS_0", + "value": [] }, { + "access": "RW", + "bf": 17, "bl": 17, - "name": "MC_IND_SEQ_RBS_1", - "value": [], "description": "", - "access": "RW", - "bf": 17 + "name": "MC_IND_SEQ_RBS_1", + "value": [] }, { + "access": "RW", + "bf": 18, "bl": 18, - "name": "MC_IND_SEQ_RBS_2", - "value": [], "description": "", - "access": "RW", - "bf": 18 + "name": "MC_IND_SEQ_RBS_2", + "value": [] }, { + "access": "RW", + "bf": 19, "bl": 19, - "name": "MC_IND_SEQ_RBS_3", - "value": [], "description": "", - "access": "RW", - "bf": 19 + "name": "MC_IND_SEQ_RBS_3", + "value": [] }, { + "access": "RW", + "bf": 20, "bl": 20, - "name": "MC_IND_AIC_RBS", - "value": [], "description": "", - "access": "RW", - "bf": 20 + "name": "MC_IND_AIC_RBS", + "value": [] }, { + "access": "RW", + "bf": 21, "bl": 21, - "name": "MC_IND_CITF_ARB0", - "value": [], "description": "", - "access": "RW", - "bf": 21 + "name": "MC_IND_CITF_ARB0", + "value": [] }, { + "access": "RW", + "bf": 22, "bl": 22, - "name": "MC_IND_CITF_ARB1", - "value": [], "description": "", - "access": "RW", - "bf": 22 + "name": "MC_IND_CITF_ARB1", + "value": [] }, { + "access": "RW", + "bf": 23, "bl": 23, - "name": "MC_IND_WR_EN", - "value": [], "description": "", - "access": "RW", - "bf": 23 + "name": "MC_IND_WR_EN", + "value": [] }, { + "access": "RW", + "bf": 24, "bl": 24, - "name": "MC_IND_RD_INV", - "value": [], "description": "", + "name": "MC_IND_RD_INV", + "value": [] + } + ], + "ioname": "MMIO", + "name": "MC_IND_INDEX", + "size": 32 + }, + "0x00000074": { + "field": [ + { "access": "RW", - "bf": 24 + "bf": 0, + "bl": 31, + "description": "", + "name": "MC_IND_DATA", + "value": [] } - ] + ], + "ioname": "MMIO", + "name": "MC_IND_DATA", + "size": 32 }, "0x000007C0": { - "name": "CP_STAT", - "size": 32, "field": [ { + "access": "RW", + "bf": 0, "bl": 0, - "name": "MRU_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 0 + "name": "MRU_BUSY", + "value": [] }, { + "access": "RW", + "bf": 1, "bl": 1, - "name": "MWU_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 1 + "name": "MWU_BUSY", + "value": [] }, { + "access": "RW", + "bf": 2, "bl": 2, - "name": "RSIU_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 2 + "name": "RSIU_BUSY", + "value": [] }, { + "access": "RW", + "bf": 3, "bl": 3, - "name": "RCIU_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 3 + "name": "RCIU_BUSY", + "value": [] }, { + "access": "RW", + "bf": 9, "bl": 9, - "name": "CSF_PRIMARY_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 9 + "name": "CSF_PRIMARY_BUSY", + "value": [] }, { + "access": "RW", + "bf": 10, "bl": 10, - "name": "CSF_INDIRECT_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 10 + "name": "CSF_INDIRECT_BUSY", + "value": [] }, { + "access": "RW", + "bf": 11, "bl": 11, - "name": "CSQ_PRIMARY_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 11 + "name": "CSQ_PRIMARY_BUSY", + "value": [] }, { + "access": "RW", + "bf": 12, "bl": 12, - "name": "CSQ_INDIRECT_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 12 + "name": "CSQ_INDIRECT_BUSY", + "value": [] }, { + "access": "RW", + "bf": 13, "bl": 13, - "name": "CSI_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 13 + "name": "CSI_BUSY", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "CSF_INDIRECT2_BUSY", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "CSF_INDIRECT2_BUSY", + "value": [] }, { - "bl": 15, - "name": "CSQ_INDIRECT2_BUSY", - "value": [], - "description": "", "access": "RW", - "bf": 15 - }, - { - "bl": 28, - "name": "GUIDMA_BUSY", - "value": [], + "bf": 15, + "bl": 15, "description": "", - "access": "RW", - "bf": 28 + "name": "CSQ_INDIRECT2_BUSY", + "value": [] }, { - "bl": 29, - "name": "VIDDMA_BUSY", - "value": [], - "description": "", "access": "RW", - "bf": 29 - }, - { - "bl": 30, - "name": "CMDSTRM_BUSY", - "value": [], + "bf": 28, + "bl": 28, "description": "", - "access": "RW", - "bf": 30 + "name": "GUIDMA_BUSY", + "value": [] }, { - "bl": 31, - "name": "CP_BUSY", - "value": [], - "description": "", "access": "RW", - "bf": 31 - } - ] - }, - "0x0000004C": { - "name": "BUS_CNTL", - "size": 32, - "field": [ - { - "bl": 14, - "name": "BUS_MASTER_DIS", - "value": [], + "bf": 29, + "bl": 29, "description": "", - "access": "RW", - "bf": 14 + "name": "VIDDMA_BUSY", + "value": [] }, { - "bl": 20, - "name": "BUS_MSI_REARM", - "value": [], - "description": "", "access": "RW", - "bf": 20 - } - ] - }, - "0x00006548": { - "name": "D1MODE_PRIORITY_A_CNT", - "size": 32, - "field": [ - { - "bl": 14, - "name": "D1MODE_PRIORITY_MARK_A", - "value": [], - "description": "", - "access": "RW", - "bf": 0 - }, - { - "bl": 16, - "name": "D1MODE_PRIORITY_A_OFF", - "value": [], + "bf": 30, + "bl": 30, "description": "", - "access": "RW", - "bf": 16 + "name": "CMDSTRM_BUSY", + "value": [] }, { - "bl": 20, - "name": "D1MODE_PRIORITY_A_ALWAYS_ON", - "value": [], - "description": "", "access": "RW", - "bf": 20 - }, - { - "bl": 24, - "name": "D1MODE_PRIORITY_A_FORCE_MASK", - "value": [], + "bf": 31, + "bl": 31, "description": "", - "access": "RW", - "bf": 24 + "name": "CP_BUSY", + "value": [] } - ] + ], + "ioname": "MMIO", + "name": "CP_STAT", + "size": 32 }, - "0x00007A38": { - "name": "DACB_AUTODETECT_INT_CONTROL", - "size": 32, + "0x00000E40": { "field": [ { - "bl": 0, - "name": "DACB_AUTODETECT_ACK", - "value": [], - "description": "", - "access": "RW", - "bf": 0 - }, - { - "bl": 16, - "name": "DACB_AUTODETECT_INT_ENABLE", - "value": [], - "description": "", "access": "RW", - "bf": 16 - } - ] - }, - "0x00006540": { - "name": "DxMODE_INT_MASK", - "size": 32, - "field": [ - { - "bl": 0, - "name": "D1MODE_VBLANK_INT_MASK", - "value": [], + "bf": 0, + "bl": 6, "description": "", - "access": "RW", - "bf": 0 + "name": "CMDFIFO_AVAIL", + "value": [] }, { - "bl": 4, - "name": "D1MODE_VLINE_INT_MASK", - "value": [], - "description": "", "access": "RW", - "bf": 4 - }, - { + "bf": 8, "bl": 8, - "name": "D2MODE_VBLANK_INT_MASK", - "value": [], "description": "", - "access": "RW", - "bf": 8 + "name": "HIRQ_ON_RBB", + "value": [] }, { - "bl": 12, - "name": "D2MODE_VLINE_INT_MASK", - "value": [], - "description": "", "access": "RW", - "bf": 12 - }, - { - "bl": 30, - "name": "D1MODE_VBLANK_CP_SEL", - "value": [], + "bf": 9, + "bl": 9, "description": "", - "access": "RW", - "bf": 30 + "name": "CPRQ_ON_RBB", + "value": [] }, { - "bl": 31, - "name": "D2MODE_VBLANK_CP_SEL", - "value": [], - "description": "", "access": "RW", - "bf": 31 - } - ] - }, - "0x00000044": { - "name": "GEN_INT_STATUS", - "size": 32, - "field": [ - { - "bl": 0, - "name": "DISPLAY_INT_STAT", - "value": [], + "bf": 10, + "bl": 10, "description": "", - "access": "RW", - "bf": 0 + "name": "CFRQ_ON_RBB", + "value": [] }, { - "bl": 1, - "name": "VGA_INT_STAT", - "value": [], - "description": "", "access": "RW", - "bf": 1 - }, - { - "bl": 8, - "name": "CAP0_INT_ACTIVE", - "value": [], + "bf": 11, + "bl": 11, "description": "", - "access": "RW", - "bf": 8 + "name": "HIRQ_IN_RTBUF", + "value": [] }, { + "access": "RW", + "bf": 12, "bl": 12, - "name": "DMA_VIPH0_INT", - "value": [], "description": "", - "access": "RW", - "bf": 12 + "name": "CPRQ_IN_RTBUF", + "value": [] }, { + "access": "RW", + "bf": 13, "bl": 13, - "name": "DMA_VIPH1_INT", - "value": [], "description": "", - "access": "RW", - "bf": 13 + "name": "CFRQ_IN_RTBUF", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "DMA_VIPH2_INT", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "CF_PIPE_BUSY", + "value": [] }, { + "access": "RW", + "bf": 15, "bl": 15, - "name": "DMA_VIPH3_INT", - "value": [], "description": "", - "access": "RW", - "bf": 15 + "name": "ENG_EV_BUSY", + "value": [] }, { + "access": "RW", + "bf": 16, "bl": 16, - "name": "MC_PROBE_FAULT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 16 + "name": "CP_CMDSTRM_BUSY", + "value": [] }, { + "access": "RW", + "bf": 17, "bl": 17, - "name": "I2C_INT", - "value": [], "description": "", - "access": "RW", - "bf": 17 + "name": "E2_BUSY", + "value": [] }, { + "access": "RW", + "bf": 18, "bl": 18, - "name": "SCRATCH_INT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 18 + "name": "RB2D_BUSY", + "value": [] }, { + "access": "RW", + "bf": 19, "bl": 19, - "name": "GUI_IDLE_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 19 + "name": "RB3D_BUSY", + "value": [] }, { + "access": "RW", + "bf": 20, "bl": 20, - "name": "ATI_OVERDRIVE_INT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 20 + "name": "VAP_BUSY", + "value": [] }, { + "access": "RW", + "bf": 21, "bl": 21, - "name": "MC_PROTECTION_FAULT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 21 + "name": "RE_BUSY", + "value": [] }, { + "access": "RW", + "bf": 22, "bl": 22, - "name": "RBBM_READ_INT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 22 + "name": "TAM_BUSY", + "value": [] }, { + "access": "RW", + "bf": 23, "bl": 23, - "name": "CB_CONTEXT_SWITCH_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 23 + "name": "TDM_BUSY", + "value": [] }, { + "access": "RW", + "bf": 24, "bl": 24, - "name": "VIPH_INT", - "value": [], "description": "", - "access": "RW", - "bf": 24 + "name": "PB_BUSY", + "value": [] }, { + "access": "RW", + "bf": 25, "bl": 25, - "name": "SW_INT", - "value": [], "description": "", - "access": "RW", - "bf": 25 + "name": "TIM_BUSY", + "value": [] }, { + "access": "RW", + "bf": 26, "bl": 26, - "name": "SW_INT_SET", - "value": [], "description": "", - "access": "RW", - "bf": 26 + "name": "GA_BUSY", + "value": [] }, { + "access": "RW", + "bf": 27, "bl": 27, - "name": "IDCT_INT_STAT", - "value": [], "description": "", - "access": "RW", - "bf": 27 + "name": "CBA2D_BUSY", + "value": [] }, { - "bl": 30, - "name": "GUIDMA_STAT", - "value": [], - "description": "", "access": "RW", - "bf": 30 - }, - { + "bf": 31, "bl": 31, - "name": "VIDDMA_STAT", - "value": [], "description": "", + "name": "GUI_ACTIVE", + "value": [] + } + ], + "ioname": "MMIO", + "name": "RBBM_STATUS", + "size": 32 + }, + "0x000060A4": { + "field": [ + { "access": "RW", - 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"bf": 11 + "name": "EFFECTIVE_L1_CACHE_SIZE", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "ENABLE_FRAGMENT_PROCESSING", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "ENABLE_FRAGMENT_PROCESSING", + "value": [] }, { + "access": "RW", + "bf": 15, "bl": 17, - "name": "EFFECTIVE_L1_QUEUE_SIZE", - "value": [], "description": "", - "access": "RW", - "bf": 15 + "name": "EFFECTIVE_L1_QUEUE_SIZE", + "value": [] }, { + "access": "RW", + "bf": 20, "bl": 20, - "name": "INVALIDATE_L1_TLB", - "value": [], "description": "", - "access": "RW", - "bf": 20 + "name": "INVALIDATE_L1_TLB", + "value": [] } - ] + ], + "ioname": "MC", + "name": "MC_PT0_CLIENT17_CNTL", + "size": 32 }, "0x0000017E": { - "name": "MC_PT0_CLIENT18_CNTL", - "size": 32, "field": [ { + "access": "RW", + "bf": 0, "bl": 0, - "name": "ENABLE_TRANSLATION_MODE_OVERRIDE", - "value": [], "description": "", - "access": "RW", - "bf": 0 + "name": "ENABLE_TRANSLATION_MODE_OVERRIDE", + "value": [] }, { + "access": "RW", + "bf": 1, "bl": 1, - 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"value": 1, - "description": "" + "value": 1 } - ], - "description": "", - "access": "RW", - "bf": 10 + ] }, { + "access": "RW", + "bf": 11, "bl": 13, - "name": "EFFECTIVE_L1_CACHE_SIZE", - "value": [], "description": "", - "access": "RW", - "bf": 11 + "name": "EFFECTIVE_L1_CACHE_SIZE", + "value": [] }, { + "access": "RW", + "bf": 14, "bl": 14, - "name": "ENABLE_FRAGMENT_PROCESSING", - "value": [], "description": "", - "access": "RW", - "bf": 14 + "name": "ENABLE_FRAGMENT_PROCESSING", + "value": [] }, { + "access": "RW", + "bf": 15, "bl": 17, - "name": "EFFECTIVE_L1_QUEUE_SIZE", - "value": [], "description": "", - "access": "RW", - "bf": 15 + "name": "EFFECTIVE_L1_QUEUE_SIZE", + "value": [] }, { + "access": "RW", + "bf": 20, "bl": 20, - "name": "INVALIDATE_L1_TLB", - "value": [], "description": "", - "access": "RW", - "bf": 20 + "name": "INVALIDATE_L1_TLB", + "value": [] } - ] - } + ], + "ioname": "MC", + "name": "MC_PT0_CLIENT18_CNTL", + "size": 32 + }, + "name": "MC" } ] -} +}
\ No newline at end of file diff --git a/src/radeon_reg.c b/src/radeon_reg.c index 1a24466..77631c3 100644 --- a/src/radeon_reg.c +++ b/src/radeon_reg.c @@ -108,7 +108,7 @@ void radeon_register_dump(const char *bname) if ((bname && reg[i].block_id == bid) || bname == NULL) { bid = reg[i].block_id; printf("%s 0x%08X 0x%08X %s\n", block[bid].name, reg[i].offset, - block[bid].rreg(radeon, reg[i].offset), reg[i].name); + reg[i].rreg(radeon, reg[i].offset), reg[i].name); } } radeon_decref(radeon); diff --git a/src/radeon_reg.h b/src/radeon_reg.h index bc35398..0fd367f 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -37,14 +37,14 @@ typedef void (*radeon_wreg_t)(struct radeon *radeon, u32 offset, u32 value); struct reg_block { unsigned id; char name[128]; - radeon_rreg_t rreg; - radeon_wreg_t wreg; }; struct reg { unsigned offset; unsigned block_id; char name[128]; + radeon_rreg_t rreg; + radeon_wreg_t wreg; }; /* RS600 */ diff --git a/src/rs600_reg.c b/src/rs600_reg.c index 7d79876..35e1393 100644 --- a/src/rs600_reg.c +++ b/src/rs600_reg.c @@ -2,81 +2,81 @@ #include "radeon_reg.h" struct reg_block rs600_block[] = { - {0, "MMIO", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {1, "MC", rs600_MC_rreg, rs600_MC_wreg}, + {0, "DISP"}, + {1, "MC"}, }; unsigned rs600_nblock = 2; struct reg rs600_reg[] = { - {0x00000040, 0, "GEN_INT_CNTL"}, - {0x00007D08, 0, "DC_HOT_PLUG_DETECT1_INT_CONTROL"}, - {0x00000E40, 0, "RBBM_STATUS"}, - {0x00000070, 0, "MC_IND_INDEX"}, - {0x000060A4, 0, "D1CRTC_STATUS_FRAME_COUNT"}, - {0x0000004C, 0, "BUS_CNTL"}, - {0x00007A38, 0, "DACB_AUTODETECT_INT_CONTROL"}, - {0x00006548, 0, "D1MODE_PRIORITY_A_CNT"}, - {0x000007C0, 0, "CP_STAT"}, - {0x00007D10, 0, "DC_HOT_PLUG_DETECT2_CONTROL"}, - {0x00007828, 0, "DACA_AUTODETECT_CONTROL"}, - {0x00000044, 0, "GEN_INT_STATUS"}, - {0x00006540, 0, "DxMODE_INT_MASK"}, - {0x00006534, 0, "D1MODE_VBLANK_STATUS"}, - {0x00000074, 0, "MC_IND_DATA"}, - {0x000068A4, 0, "D2CRTC_STATUS_FRAME_COUNT"}, - {0x00006D34, 0, "D2MODE_VBLANK_STATUS"}, - {0x00007D00, 0, "DC_HOT_PLUG_DETECT1_CONTROL"}, - {0x00007EDC, 0, "DISP_INTERRUPT_STATUS"}, - {0x00007838, 0, "DACA_AUTODETECT_INT_CONTROL"}, - {0x00007A28, 0, "DACB_AUTODETECT_CONTROL"}, - {0x00007D04, 0, "DC_HOT_PLUG_DETECT1_INT_STATUS"}, - {0x00007D14, 0, "DC_HOT_PLUG_DETECT2_INT_STATUS"}, - {0x00007D18, 0, "DC_HOT_PLUG_DETECT2_INT_CONTROL"}, - {0x00006D4C, 0, "D2MODE_PRIORITY_B_CNT"}, - {0x0000654C, 0, "D1MODE_PRIORITY_B_CNT"}, - {0x00006D48, 0, "D2MODE_PRIORITY_A_CNT"}, - {0x0000017E, 1, "MC_PT0_CLIENT18_CNTL"}, - {0x00000134, 1, "HDP_FB_LOCATION"}, - {0x00000009, 1, "MC_CNTL1"}, - {0x00000005, 1, "MC_AGP_LOCATION"}, - {0x0000013C, 1, "MC_PT0_CONTEXT0_FLAT_START_ADDR"}, - {0x00000103, 1, "MC_PT0_CONTEXT1_CNTL"}, - {0x00000175, 1, "MC_PT0_CLIENT9_CNTL"}, - {0x00000000, 1, "MC_STATUS"}, - {0x00000179, 1, "MC_PT0_CLIENT13_CNTL"}, - {0x00000004, 1, "MC_FB_LOCATION"}, - {0x00000006, 1, "AGP_BASE"}, - {0x00000007, 1, "AGP_BASE_2"}, - {0x00000100, 1, "MC_PT0_CNTL"}, - {0x00000102, 1, "MC_PT0_CONTEXT0_CNTL"}, - {0x00000104, 1, "MC_PT0_CONTEXT2_CNTL"}, - {0x0000016C, 1, "MC_PT0_CLIENT0_CNTL"}, - {0x00000105, 1, "MC_PT0_CONTEXT3_CNTL"}, - {0x0000011C, 1, "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR"}, - {0x0000016D, 1, "MC_PT0_CLIENT1_CNTL"}, - {0x00000106, 1, "MC_PT0_CONTEXT4_CNTL"}, - {0x0000016E, 1, "MC_PT0_CLIENT2_CNTL"}, - {0x00000107, 1, "MC_PT0_CONTEXT5_CNTL"}, - {0x0000016F, 1, "MC_PT0_CLIENT3_CNTL"}, - {0x00000108, 1, "MC_PT0_CONTEXT6_CNTL"}, - {0x00000109, 1, "MC_PT0_CONTEXT7_CNTL"}, - {0x00000112, 1, "MC_PT0_SYSTEM_APERTURE_LOW_ADDR"}, - {0x0000017B, 1, "MC_PT0_CLIENT15_CNTL"}, - {0x00000114, 1, "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR"}, - {0x0000012C, 1, "MC_PT0_CONTEXT0_FLAT_BASE_ADDR"}, - {0x0000014C, 1, "MC_PT0_CONTEXT0_FLAT_END_ADDR"}, - {0x00000170, 1, "MC_PT0_CLIENT4_CNTL"}, - {0x00000171, 1, "MC_PT0_CLIENT5_CNTL"}, - {0x00000172, 1, "MC_PT0_CLIENT6_CNTL"}, - {0x00000173, 1, "MC_PT0_CLIENT7_CNTL"}, - {0x00000174, 1, "MC_PT0_CLIENT8_CNTL"}, - {0x00000176, 1, "MC_PT0_CLIENT10_CNTL"}, - {0x00000177, 1, "MC_PT0_CLIENT11_CNTL"}, - {0x00000178, 1, "MC_PT0_CLIENT12_CNTL"}, - {0x0000017A, 1, "MC_PT0_CLIENT14_CNTL"}, - {0x0000017C, 1, "MC_PT0_CLIENT16_CNTL"}, - {0x0000017D, 1, "MC_PT0_CLIENT17_CNTL"}, + {0x00007D08, 0, "DC_HOT_PLUG_DETECT1_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000040, 0, "GEN_INT_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D48, 0, "D2MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x0000654C, 0, "D1MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000060A4, 0, "D1CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000E40, 0, "RBBM_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000070, 0, "MC_IND_INDEX", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007A38, 0, "DACB_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006548, 0, "D1MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000007C0, 0, "CP_STAT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x0000004C, 0, "BUS_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006540, 0, "DxMODE_INT_MASK", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000044, 0, "GEN_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006534, 0, "D1MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000068A4, 0, "D2CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000074, 0, "MC_IND_DATA", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007828, 0, "DACA_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D00, 0, "DC_HOT_PLUG_DETECT1_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D34, 0, "D2MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D4C, 0, "D2MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007838, 0, "DACA_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D04, 0, "DC_HOT_PLUG_DETECT1_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007A28, 0, "DACB_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D10, 0, "DC_HOT_PLUG_DETECT2_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D14, 0, "DC_HOT_PLUG_DETECT2_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D18, 0, "DC_HOT_PLUG_DETECT2_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007EDC, 0, "DISP_INTERRUPT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000005, 1, "MC_AGP_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000013C, 1, "MC_PT0_CONTEXT0_FLAT_START_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000103, 1, "MC_PT0_CONTEXT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000175, 1, "MC_PT0_CLIENT9_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000000, 1, "MC_STATUS", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016E, 1, "MC_PT0_CLIENT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000107, 1, "MC_PT0_CONTEXT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000179, 1, "MC_PT0_CLIENT13_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000004, 1, "MC_FB_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000006, 1, "AGP_BASE", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000007, 1, "AGP_BASE_2", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000009, 1, "MC_CNTL1", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000100, 1, "MC_PT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000102, 1, "MC_PT0_CONTEXT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000104, 1, "MC_PT0_CONTEXT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016C, 1, "MC_PT0_CLIENT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000105, 1, "MC_PT0_CONTEXT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000011C, 1, "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016D, 1, "MC_PT0_CLIENT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000106, 1, "MC_PT0_CONTEXT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016F, 1, "MC_PT0_CLIENT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000108, 1, "MC_PT0_CONTEXT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000109, 1, "MC_PT0_CONTEXT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000112, 1, "MC_PT0_SYSTEM_APERTURE_LOW_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017B, 1, "MC_PT0_CLIENT15_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000114, 1, "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000012C, 1, "MC_PT0_CONTEXT0_FLAT_BASE_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000134, 1, "HDP_FB_LOCATION", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x0000014C, 1, "MC_PT0_CONTEXT0_FLAT_END_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000170, 1, "MC_PT0_CLIENT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000171, 1, "MC_PT0_CLIENT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000172, 1, "MC_PT0_CLIENT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000173, 1, "MC_PT0_CLIENT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000174, 1, "MC_PT0_CLIENT8_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000176, 1, "MC_PT0_CLIENT10_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000177, 1, "MC_PT0_CLIENT11_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000178, 1, "MC_PT0_CLIENT12_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017A, 1, "MC_PT0_CLIENT14_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017C, 1, "MC_PT0_CLIENT16_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017D, 1, "MC_PT0_CLIENT17_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017E, 1, "MC_PT0_CLIENT18_CNTL", rs600_MC_rreg, rs600_MC_wreg}, }; unsigned rs600_nreg = 68; diff --git a/tools/rdb.c b/tools/rdb.c index 99849ea..090f4dc 100644 --- a/tools/rdb.c +++ b/tools/rdb.c @@ -58,7 +58,7 @@ int main(int argc, char *argv[]) }; struct param param; struct rdb_json *rdb; - json_t *block, *reg, *tmp, *name; + json_t *block, *reg, *tmp, *name, *tmp2; unsigned i; int option_id; void *iter; @@ -120,10 +120,7 @@ int main(int argc, char *argv[]) for (i = 0; i < json_array_size(rdb->block); i++) { block = json_array_get(rdb->block, i); tmp = json_object_get(block, "name"); - printf("\t{%d, \"%s\", %s_%s_rreg, %s_%s_wreg},\n", i, - json_string_value(tmp), param.header_name, - json_string_value(tmp), param.header_name, - json_string_value(tmp)); + printf("\t{%d, \"%s\"},\n", i, json_string_value(tmp)); } printf("};\n\n"); printf("unsigned %s_nblock = %d;\n\n", param.header_name, json_array_size(rdb->block)); @@ -139,8 +136,11 @@ int main(int argc, char *argv[]) if (json_is_object(reg)) { offset = strtoul(json_object_iter_key(iter), NULL, 16); tmp = json_object_get(reg, "name"); - printf("\t{0x%08X, %4d, \"%s\"},\n", - offset, i, json_string_value(tmp)); + tmp2 = json_object_get(reg, "ioname"); + printf("\t{0x%08X, %4d, \"%s\", %s_%s_rreg, %s_%s_wreg},\n", + offset, i, json_string_value(tmp), + param.header_name, json_string_value(tmp2), + param.header_name, json_string_value(tmp2)); c++; } iter = json_object_iter_next(block, iter); diff --git a/tools/rdb_json.c b/tools/rdb_json.c index 40c9d36..f896379 100644 --- a/tools/rdb_json.c +++ b/tools/rdb_json.c @@ -87,6 +87,14 @@ struct rdb_json *rdb_json_load(const char *file) free(rdb); return NULL; } + json_dump_file(rdb->root, file, JSON_INDENT(2) | JSON_SORT_KEYS); + json_decref(rdb->root); + rdb->root = json_load_file(file, &error); + if (rdb->root == NULL) { + fprintf(stderr, "%s failed to load %s (%d:%s)\n", __func__, file, error.line, error.text); + free(rdb); + return NULL; + } rdb->block = json_object_get(rdb->root, "block"); return rdb; } |