diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2010-04-30 21:09:15 +0200 |
|---|---|---|
| committer | Jerome Glisse <jglisse@redhat.com> | 2010-04-30 21:09:15 +0200 |
| commit | c1e091b2923a34b3c8bd32e15184dd28a9085547 (patch) | |
| tree | 2ba2f87fd813a9642708c571793d5481c954a8a0 | |
| parent | 35c56944dfe5ca34677e39fdc0ebdab15c00b442 (diff) | |
radeondb: add r100 register dump support
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
| -rw-r--r-- | json/r100.json | 5177 | ||||
| -rw-r--r-- | json/rs600.json | 440 | ||||
| -rw-r--r-- | src/Makefile.am | 5 | ||||
| -rw-r--r-- | src/r100_reg.c | 81 | ||||
| -rw-r--r-- | src/radeon_pci.c | 9 | ||||
| -rw-r--r-- | src/radeon_priv.h | 1 | ||||
| -rw-r--r-- | src/radeon_reg.c | 88 | ||||
| -rw-r--r-- | src/radeon_reg.h | 10 | ||||
| -rw-r--r-- | src/rs600_reg.c | 140 | ||||
| -rw-r--r-- | tools/rdb.c | 39 | ||||
| -rw-r--r-- | tools/rdb_json.c | 1 | ||||
| -rw-r--r-- | tools/rdb_json.h | 5 |
12 files changed, 5751 insertions, 245 deletions
diff --git a/json/r100.json b/json/r100.json new file mode 100644 index 0000000..7021dc4 --- /dev/null +++ b/json/r100.json @@ -0,0 +1,5177 @@ +{ + "block": [ + { + "0x00000001": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "OSC_EN", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "XTL_LOW_GAIN", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "DONT_USE_XTALIN", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 5, + "description": "", + "name": "SLOW_CLOCK_SOURCE", + "value": [] + }, + { + "access": "RW", + "bf": 11, + "bl": 11, + "description": "", + "name": "CG_CLK_TO_OUTPIN", + "value": [] + }, + { + "access": "RW", + "bf": 12, + "bl": 12, + "description": "", + "name": "CG_COUNT_UP_TO_OUTPIN", + "value": [] + }, + { + "access": "RW", + "bf": 13, + "bl": 13, + "description": "", + "name": "ACCESS_REGS_IN_SUSPEND", + "value": [] + }, + { + "access": "RW", + "bf": 14, + "bl": 14, + "description": "", + "name": "CG_SPARE", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "SCLK_DYN_START_CNTL", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "CP_CLK_RUNNING", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 18, + "description": "", + "name": "CG_SPARE_RD", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 31, + "description": "", + "name": "PWRSEQ_DELAY", + "value": [] + } + ], + "name": "CLK_PIN_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000002": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "PPLL_RESET", + "value": [] + }, + { + "access": "RW", + "bf": 1, + "bl": 1, + "description": "", + "name": "PPLL_SLEEP", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "PPLL_TST_EN", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "PPLL_REFCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 5, + "description": "", + "name": "PPLL_FBCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 6, + "bl": 6, + "description": "", + "name": "PPLL_TCPOFF", + "value": [] + }, + { + "access": "RW", + "bf": 7, + "bl": 7, + "description": "", + "name": "PPLL_TVCOMAX", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 10, + "description": "", + "name": "PPLL_PCP", + "value": [] + }, + { + "access": "RW", + "bf": 11, + "bl": 13, + "description": "", + "name": "PPLL_PVG", + "value": [] + }, + { + "access": "RW", + "bf": 14, + "bl": 15, + "description": "", + "name": "PPLL_PDC", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_EN", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "PPLL_VGA_ATOMIC_UPDATE_EN", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_SYNC", + "value": [] + } + ], + "name": "PPLL_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000003": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 9, + "description": "", + "name": "PPLL_REF_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_W", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_R", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 17, + "description": "", + "name": "PPLL_REF_DIV_SRC", + "value": [] + } + ], + "name": "PPLL_REF_DIV", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000007": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 10, + "description": "", + "name": "PPLL_FB3_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_W", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "PPLL_ATOMIC_UPDATE_R", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 18, + "description": "", + "name": "PPLL_POST3_DIV", + "value": [] + } + ], + "name": "PPLL_DIV_3", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000008": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 1, + "description": "", + "name": "VCLK_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "VCLK_INVERT", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 9, + "description": "", + "name": "ECP_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "ECP_FORCE_ON", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "SUBCLK_FORCE_ON", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 17, + "description": "", + "name": "BYTE_CLK_POST_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 20, + "description": "", + "name": "BYTE_CLK_OUT_EN", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 26, + "description": "", + "name": "BYTE_CLK_SKEW", + "value": [] + } + ], + "name": "VCLK_ECP_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000000A": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 7, + "description": "", + "name": "M_SPLL_REF_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 15, + "description": "", + "name": "MPLL_FB_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 23, + "description": "", + "name": "SPLL_FB_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 24, + "description": "", + "name": "MPLL_REF_SRC_SEL", + "value": [] + } + ], + "name": "M_SPLL_REF_FB_DIV", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000000C": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "SPLL_SLEEP", + "value": [] + }, + { + "access": "RW", + "bf": 1, + "bl": 1, + "description": "", + "name": "SPLL_RESET", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "SPLL_TST_EN", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "SPLL_REFCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 5, + "description": "", + "name": "SPLL_FBCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 6, + "bl": 6, + "description": "", + "name": "SPLL_TCPOFF", + "value": [] + }, + { + "access": "RW", + "bf": 7, + "bl": 7, + "description": "", + "name": "SPLL_TVCOMAX", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 10, + "description": "", + "name": "SPLL_PCP", + "value": [] + }, + { + "access": "RW", + "bf": 11, + "bl": 13, + "description": "", + "name": "SPLL_PVG", + "value": [] + }, + { + "access": "RW", + "bf": 14, + "bl": 15, + "description": "", + "name": "SPLL_PDC", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 18, + "description": "", + "name": "SPLL_X1_CLK_SKEW", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 22, + "description": "", + "name": "SPLL_X2_CLK_SKEW", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 27, + "description": "", + "name": "SPLL_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 28, + "bl": 29, + "description": "", + "name": "MYCLK_SOURCED_FROM_SPLL_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 30, + "bl": 30, + "description": "", + "name": "ENABLE_MYCLK_FROM_SPLL", + "value": [] + } + ], + "name": "SPLL_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000000D": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 2, + "description": "", + "name": "SCLK_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 10, + "description": "", + "name": "TCLK_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "FORCE_CP", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "FORCE_HDP", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "FORCE_DISP", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "FORCE_TOP", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 20, + "description": "", + "name": "FORCE_E2", + "value": [] + }, + { + "access": "RW", + "bf": 21, + "bl": 21, + "description": "", + "name": "FORCE_SE", + "value": [] + }, + { + "access": "RW", + "bf": 22, + "bl": 22, + "description": "", + "name": "FORCE_IDCT", + "value": [] + }, + { + "access": "RW", + "bf": 23, + "bl": 23, + "description": "", + "name": "FORCE_VIP", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 24, + "description": "", + "name": "FORCE_RE", + "value": [] + }, + { + "access": "RW", + "bf": 25, + "bl": 25, + "description": "", + "name": "FORCE_PB", + "value": [] + }, + { + "access": "RW", + "bf": 26, + "bl": 26, + "description": "", + "name": "FORCE_TAM", + "value": [] + }, + { + "access": "RW", + "bf": 27, + "bl": 27, + "description": "", + "name": "FORCE_TDM", + "value": [] + }, + { + "access": "RW", + "bf": 28, + "bl": 28, + "description": "", + "name": "FORCE_RB", + "value": [] + } + ], + "name": "SCLK_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000012": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 2, + "description": "", + "name": "MCLKA_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 6, + "description": "", + "name": "YCLKA_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 10, + "description": "", + "name": "MCLKB_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 12, + "bl": 14, + "description": "", + "name": "YCLKB_SRC_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "FORCE_MCLKA", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "FORCE_MCLKB", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "FORCE_YCLKA", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "FORCE_YCLKB", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 20, + "description": "", + "name": "FORCE_MC", + "value": [] + }, + { + "access": "RW", + "bf": 21, + "bl": 21, + "description": "", + "name": "FORCE_AIC", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 25, + "description": "", + "name": "MRDCKA0_SOUTSEL", + "value": [] + }, + { + "access": "RW", + "bf": 26, + "bl": 27, + "description": "", + "name": "MRDCKA1_SOUTSEL", + "value": [] + }, + { + "access": "RW", + "bf": 28, + "bl": 29, + "description": "", + "name": "MRDCKB0_SOUTSEL", + "value": [] + }, + { + "access": "RW", + "bf": 30, + "bl": 31, + "description": "", + "name": "MRDCKB1_SOUTSEL", + "value": [] + } + ], + "name": "MCLK_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000014": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "MPLL_PWRMGT_OFF", + "value": [] + }, + { + "access": "RW", + "bf": 1, + "bl": 1, + "description": "", + "name": "SPLL_PWRMGT_OFF", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "PPLL_PWRMGT_OFF", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "MCLK_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 5, + "description": "", + "name": "SCLK_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 6, + "bl": 6, + "description": "", + "name": "PCLK_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 8, + "description": "", + "name": "MC_CH_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 9, + "bl": 9, + "description": "", + "name": "TEST_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 10, + "bl": 10, + "description": "", + "name": "GLOBAL_PMAN_EN", + "value": [] + }, + { + "access": "RW", + "bf": 12, + "bl": 12, + "description": "", + "name": "ENGINE_DYNCLK_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "MC_BUSY", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "MC_INT_CNTL", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "MC_SWITCH", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "DLL_READY", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 31, + "description": "", + "name": "CG_NO1_DEBUG", + "value": [] + } + ], + "name": "CLK_PWRMGT_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000015": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "MPLL_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 1, + "bl": 1, + "description": "", + "name": "SPLL_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "PPLL_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 31, + "description": "", + "name": "CG_NO2_DEBUG", + "value": [] + }, + { + "access": "RW", + "bf": 3, + "bl": 3, + "description": "", + "name": "P2PLL_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "TVPLL_TURNOFF", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 8, + "description": "", + "name": "AGPCLK_DYN_STOP_LAT", + "value": [] + }, + { + "access": "RW", + "bf": 9, + "bl": 10, + "description": "", + "name": "APM_POWER_STATE", + "value": [] + }, + { + "access": "RW", + "bf": 11, + "bl": 12, + "description": "", + "name": "APM_PWRSTATE_RD", + "value": [] + }, + { + "access": "RW", + "bf": 13, + "bl": 13, + "description": "", + "name": "PM_MODE_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 14, + "bl": 14, + "description": "", + "name": "EN_PWRSEQ_DONE_COND", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "EN_DISP_PARKED_COND", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "MOBILE_SU", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "SU_SCLK_USE_BCLK", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "SU_MCLK_USE_BCLK", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "SU_SUSTAIN_DISABLE", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 20, + "description": "", + "name": "TCL_BYPASS_DISABLE", + "value": [] + }, + { + "access": "RW", + "bf": 21, + "bl": 21, + "description": "", + "name": "TCL_CLOCK_ACTIVE_RD", + "value": [] + } + ], + "name": "PLL_PWRMGT_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000001F": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 1, + "description": "", + "name": "SCLK_SOURCED_FROM_MPLL_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "MCLK_FROM_SPLL_DIV_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 3, + "bl": 3, + "description": "", + "name": "ENABLE_SCLK_FROM_MPLL", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 8, + "description": "", + "name": "DLL_READY_LAT", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "CGM_CLK_TO_OUTPIN", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 17, + "description": "", + "name": "CLK_OR_COUNT_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "EN_MCLK_TRISTATE_IN_SUSPEND", + "value": [] + }, + { + "access": "RW", + "bf": 20, + "bl": 21, + "description": "", + "name": "CGM_SPARE_RD", + "value": [] + } + ], + "name": "MCLK_MISC", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000002A": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 0, + "description": "", + "name": "P2PLL_RESET", + "value": [] + }, + { + "access": "RW", + "bf": 1, + "bl": 1, + "description": "", + "name": "P2PLL_SLEEP", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "P2PLL_TST_EN", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 4, + "description": "", + "name": "P2PLL_REFCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 5, + "bl": 5, + "description": "", + "name": "P2PLL_FBCLK_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 6, + "bl": 6, + "description": "", + "name": "P2PLL_TCPOFF", + "value": [] + }, + { + "access": "RW", + "bf": 7, + "bl": 7, + "description": "", + "name": "P2PLL_TVCOMAX", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 10, + "description": "", + "name": "P2PLL_PCP", + "value": [] + }, + { + "access": "RW", + "bf": 11, + "bl": 13, + "description": "", + "name": "P2PLL_PVG", + "value": [] + }, + { + "access": "RW", + "bf": 14, + "bl": 15, + "description": "", + "name": "P2PLL_PDC", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "P2PLL_ATOMIC_UPDATE_EN", + "value": [] + }, + { + "access": "RW", + "bf": 18, + "bl": 18, + "description": "", + "name": "P2PLL_ATOMIC_UPDATE_SYNC", + "value": [] + } + ], + "name": "P2PLL_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x0000002B": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 9, + "description": "", + "name": "P2PLL_REF_DIV", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "P2PLL_ATOMIC_UPDATE_W", + "value": [] + }, + { + "access": "RW", + "bf": 15, + "bl": 15, + "description": "", + "name": "P2PLL_ATOMIC_UPDATE_R", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 17, + 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"bf": 31, + "bl": 31, + "description": "", + "name": "DISP_HW_1F_DEBUG", + "value": [] + } + ], + "name": "DISP_HW_DEBUG", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000D60": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 1, + "description": "", + "name": "DISP_ALPHA_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 2, + "bl": 2, + "description": "", + "name": "DISP_ALPHA_INV", + "value": [] + }, + { + "access": "RW", + "bf": 3, + "bl": 3, + "description": "", + "name": "DISP_ALPHA_PREMULT", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 8, + "description": "", + "name": "DISP_RGB_OFFSET_EN", + "value": [] + }, + { + "access": "RW", + "bf": 9, + "bl": 9, + "description": "", + "name": "DISP_LIN_TRANS_BYPASS", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 23, + "description": "", + "name": "DISP_GRPH_ALPHA", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 31, + "description": "", + "name": "DISP_OV0_ALPHA", + "value": [] + } + ], + "name": "DISP_MERGE_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000D64": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 1, + "description": "", + "name": "DISP_DAC_SOURCE", + "value": [] + }, + { + "access": "RW", + "bf": 4, + "bl": 5, + "description": "", + "name": "DISP_TRANS_MATRIX_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 8, + "bl": 8, + "description": "", + "name": "DISP_RMX_SOURCE", + "value": [] + }, + { + "access": "RW", + "bf": 9, + "bl": 9, + "description": "", + "name": "DISP_RMX_HTAP_SEL", + "value": [] + }, + { + "access": "RW", + "bf": 10, + "bl": 10, + "description": "", + "name": "DISP_RMX_DITH_EN", + "value": [] + }, + { + "access": "RW", + "bf": 16, + "bl": 16, + "description": "", + "name": "DISP_TV_SOURCE", + "value": [] + }, + { + "access": "RW", + "bf": 17, + "bl": 18, + "description": "", + "name": "DISP_TV_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 19, + "bl": 19, + "description": "", + "name": "DISP_TV_YG_DITH_EN", + "value": [] + }, + { + "access": "RW", + "bf": 21, + "bl": 21, + "description": "", + "name": "DISP_TV_BIT_WIDTH", + "value": [] + }, + { + "access": "RW", + "bf": 22, + "bl": 23, + "description": "", + "name": "DISP_TV_SYNC_MODE", + "value": [] + }, + { + "access": "RW", + "bf": 24, + "bl": 24, + "description": "", + "name": "DISP_TV_SYNC_FORCE", + "value": [] + }, + { + "access": "RW", + "bf": 25, + "bl": 26, + "description": "", + "name": "DISP_TV_SYNC_COLOR", + "value": [] + }, + { + "access": "RW", + "bf": 27, + "bl": 28, + "description": "", + "name": "DISP_TV_EVEN_FLAG_CNTL", + "value": [] + }, + { + "access": "RW", + "bf": 29, + "bl": 29, + "description": "", + "name": "DISP_TV_SYNC_STATUS", + "value": [] + }, + { + "access": "RW", + "bf": 30, + "bl": 30, + "description": "", + "name": "DISP_TV_H_DOWNSCALE", + "value": [] + } + ], + "name": "DISP_OUTPUT_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000D68": { + "field": [ + { + "access": "RW", + "bf": 8, + "bl": 8, + "description": "", + "name": "DISP2_RGB_OFFSET_EN", + "value": [] + } + ], + "name": "DISP2_MERGE_CNTL", + "size": 32, + "unit": [ + "DISP" + ] + }, + "name": "MMIO" + } + ], + "unit": [ + "DISP" + ] +}
\ No newline at end of file diff --git a/json/rs600.json b/json/rs600.json index 9bb7f90..a41e829 100644 --- a/json/rs600.json +++ b/json/rs600.json @@ -116,9 +116,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "GEN_INT_CNTL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00000044": { "field": [ @@ -291,9 +293,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "GEN_INT_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x0000004C": { "field": [ @@ -314,9 +318,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "BUS_CNTL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00000070": { "field": [ @@ -401,9 +407,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "MC_IND_INDEX", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00000074": { "field": [ @@ -416,9 +424,28 @@ "value": [] } ], - "ioname": "MMIO", "name": "MC_IND_DATA", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] + }, + "0x00000134": { + "field": [ + { + "access": "RW", + "bf": 0, + "bl": 15, + "description": "", + "name": "HDP_FB_START", + "value": [] + } + ], + "name": "HDP_FB_LOCATION", + "size": 32, + "unit": [ + "MC" + ] }, "0x000007C0": { "field": [ @@ -543,9 +570,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "CP_STAT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00000E40": { "field": [ @@ -726,9 +755,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "RBBM_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x000060A4": { "field": [ @@ -741,9 +772,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D1CRTC_STATUS_FRAME_COUNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006534": { "field": [ @@ -780,9 +813,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D1MODE_VBLANK_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006540": { "field": [ @@ -835,9 +870,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DxMODE_INT_MASK", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006548": { "field": [ @@ -874,9 +911,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D1MODE_PRIORITY_A_CNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x0000654C": { "field": [ @@ -913,9 +952,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D1MODE_PRIORITY_B_CNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x000068A4": { "field": [ @@ -928,9 +969,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D2CRTC_STATUS_FRAME_COUNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006D34": { "field": [ @@ -967,9 +1010,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D2MODE_VBLANK_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006D48": { "field": [ @@ -1006,9 +1051,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D2MODE_PRIORITY_A_CNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00006D4C": { "field": [ @@ -1045,9 +1092,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "D2MODE_PRIORITY_B_CNT", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007828": { "field": [ @@ -1076,9 +1125,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DACA_AUTODETECT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007838": { "field": [ @@ -1099,9 +1150,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DACA_AUTODETECT_INT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007A28": { "field": [ @@ -1130,9 +1183,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DACB_AUTODETECT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007A38": { "field": [ @@ -1153,9 +1208,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DACB_AUTODETECT_INT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D00": { "field": [ @@ -1168,9 +1225,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT1_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D04": { "field": [ @@ -1191,9 +1250,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT1_INT_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D08": { "field": [ @@ -1222,9 +1283,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT1_INT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D10": { "field": [ @@ -1237,9 +1300,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT2_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D14": { "field": [ @@ -1260,9 +1325,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT2_INT_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007D18": { "field": [ @@ -1291,9 +1358,11 @@ "value": [] } ], - "ioname": "MMIO", "name": "DC_HOT_PLUG_DETECT2_INT_CONTROL", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, "0x00007EDC": { "field": [ @@ -1346,11 +1415,13 @@ "value": [] } ], - "ioname": "MMIO", "name": "DISP_INTERRUPT_STATUS", - "size": 32 + "size": 32, + "unit": [ + "DISP" + ] }, - "name": "DISP" + "name": "MMIO" }, { "0x00000000": { @@ -1364,9 +1435,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_STATUS", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000004": { "field": [ @@ -1387,9 +1460,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_FB_LOCATION", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000005": { "field": [ @@ -1410,9 +1485,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_AGP_LOCATION", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000006": { "field": [ @@ -1425,9 +1502,11 @@ "value": [] } ], - "ioname": "MC", "name": "AGP_BASE", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000007": { "field": [ @@ -1440,9 +1519,11 @@ "value": [] } ], - "ioname": "MC", "name": "AGP_BASE_2", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000009": { "field": [ @@ -1455,9 +1536,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_CNTL1", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000100": { "field": [ @@ -1502,9 +1585,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000102": { "field": [ @@ -1531,9 +1616,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT0_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000103": { "field": [ @@ -1560,9 +1647,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT1_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000104": { "field": [ @@ -1589,9 +1678,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT2_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000105": { "field": [ @@ -1618,9 +1709,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT3_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000106": { "field": [ @@ -1647,9 +1740,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT4_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000107": { "field": [ @@ -1676,9 +1771,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT5_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000108": { "field": [ @@ -1705,9 +1802,11 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT6_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000109": { "field": [ @@ -1734,60 +1833,59 @@ ] } ], - "ioname": "MC", "name": "MC_PT0_CONTEXT7_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000112": { "field": [], - "ioname": "MC", "name": "MC_PT0_SYSTEM_APERTURE_LOW_ADDR", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000114": { "field": [], - "ioname": "MC", "name": "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000011C": { "field": [], - "ioname": "MC", "name": "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000012C": { "field": [], - "ioname": "MC", "name": "MC_PT0_CONTEXT0_FLAT_BASE_ADDR", - "size": 32 - }, - "0x00000134": { - "field": [ - { - "access": "RW", - "bf": 0, - "bl": 15, - "description": "", - "name": "HDP_FB_START", - "value": [] - } - ], - "ioname": "MMIO", - "name": "HDP_FB_LOCATION", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000013C": { "field": [], - "ioname": "MC", "name": "MC_PT0_CONTEXT0_FLAT_START_ADDR", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000014C": { "field": [], - "ioname": "MC", "name": "MC_PT0_CONTEXT0_FLAT_END_ADDR", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000016C": { "field": [ @@ -1888,9 +1986,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT0_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000016D": { "field": [ @@ -1991,9 +2091,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT1_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000016E": { "field": [ @@ -2094,9 +2196,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT2_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000016F": { "field": [ @@ -2197,9 +2301,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT3_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000170": { "field": [ @@ -2300,9 +2406,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT4_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000171": { "field": [ @@ -2403,9 +2511,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT5_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000172": { "field": [ @@ -2506,9 +2616,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT6_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000173": { "field": [ @@ -2609,9 +2721,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT7_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000174": { "field": [ @@ -2712,9 +2826,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT8_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000175": { "field": [ @@ -2815,9 +2931,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT9_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000176": { "field": [ @@ -2918,9 +3036,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT10_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000177": { "field": [ @@ -3021,9 +3141,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT11_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000178": { "field": [ @@ -3124,9 +3246,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT12_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x00000179": { "field": [ @@ -3227,9 +3351,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT13_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000017A": { "field": [ @@ -3330,9 +3456,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT14_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000017B": { "field": [ @@ -3433,9 +3561,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT15_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000017C": { "field": [ @@ -3536,9 +3666,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT16_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000017D": { "field": [ @@ -3639,9 +3771,11 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT17_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "0x0000017E": { "field": [ @@ -3742,11 +3876,17 @@ "value": [] } ], - "ioname": "MC", "name": "MC_PT0_CLIENT18_CNTL", - "size": 32 + "size": 32, + "unit": [ + "MC" + ] }, "name": "MC" } + ], + "unit": [ + "MC", + "DISP" ] }
\ No newline at end of file diff --git a/src/Makefile.am b/src/Makefile.am index bb446ed..706d031 100644 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -30,8 +30,11 @@ noinst_HEADER = radeon.h radeon_priv.h r600_states.h mode.h radeondb_SOURCES = radeondb.c bof.c radeon_pciid.c radeon_ctx.c radeon_bof.c\ radeon_json.c r600_state.c r600_ctx.c mode.c radeon.c radeon_state.c\ radeon_draw.c radeon_bo.c radeon_pci.c radeon_reg.c rs600_reg.c\ - r600_disassembler.c + r600_disassembler.c r100_reg.c radeondb_LDADD = $(LIBJANSSON_LIBS) $(LIBDRM_LIBS) $(LIBDRM_RADEON_LIBS) $(PCIACCESS_LIBS) rs600_reg.c: ../json/rs600.json ../tools/rdb.c ../tools/rdb -j ../json/rs600.json -h rs600 > rs600_reg.c + +r100_reg.c: ../json/r100.json ../tools/rdb.c + ../tools/rdb -j ../json/r100.json -h r100 > r100_reg.c diff --git a/src/r100_reg.c b/src/r100_reg.c new file mode 100644 index 0000000..28ba1af --- /dev/null +++ b/src/r100_reg.c @@ -0,0 +1,81 @@ +/* this file is autogenerated don't edit */ +#include "radeon_reg.h" + +struct reg_block r100_block[] = { + {0x00000001, "DISP"}, +}; + +unsigned r100_nblock = 2; + +struct reg r100_reg[] = { + {0x00000001, 0x00000001, "CLK_PIN_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000000D, 0x00000001, "SCLK_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000007, 0x00000001, "PPLL_DIV_3", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000002, 0x00000001, "PPLL_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000008, 0x00000001, "VCLK_ECP_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000001F, 0x00000001, "MCLK_MISC", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000003, 0x00000001, "PPLL_REF_DIV", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000002D, 0x00000001, "PIXCLKS_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000000A, 0x00000001, "M_SPLL_REF_FB_DIV", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000000C, 0x00000001, "SPLL_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000012, 0x00000001, "MCLK_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000002A, 0x00000001, "P2PLL_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000014, 0x00000001, "CLK_PWRMGT_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000002B, 0x00000001, "P2PLL_REF_DIV", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000015, 0x00000001, "PLL_PWRMGT_CNTL", r100_CLK_rreg, r100_CLK_wreg}, + {0x0000002C, 0x00000001, "P2PLL_DIV_0", r100_CLK_rreg, r100_CLK_wreg}, + {0x00000050, 0x00000001, "CRTC_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000238, 0x00000001, "OVR_WID_TOP_BOTTOM", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000054, 0x00000001, "CRTC_EXT_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000284, 0x00000001, "FP_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000008, 0x00000001, "CLOCK_CNTL_INDEX", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000023C, 0x00000001, "DISPLAY_BASE_ADDR", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000250, 0x00000001, "FP_CRTC_H_TOTAL_DISP", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000000B0, 0x00000001, "PALETTE_INDEX", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000140, 0x00000001, "MEM_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000234, 0x00000001, "OVR_WID_LEFT_RIGHT", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000000B8, 0x00000001, "PALETTE_30_DATA", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D14, 0x00000001, "DISP_HW_DEBUG", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000002E, 0x00000001, "HTOTAL2_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000290, 0x00000001, "FP_VERT_STRETCH", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000022C, 0x00000001, "CRTC_PITCH", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000204, 0x00000001, "CRTC_H_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000009, 0x00000001, "HTOTAL_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002C8, 0x00000001, "FP_V_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000280, 0x00000001, "DAC_EXT_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000000E0, 0x00000001, "CONFIG_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000020C, 0x00000001, "CRTC_V_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000058, 0x00000001, "DAC_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000088C, 0x00000001, "TV_DAC_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000007C, 0x00000001, "DAC_CNTL2", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000888, 0x00000001, "TV_PRE_DAC_MUX_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000019C, 0x00000001, "GPIOPAD_A", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D08, 0x00000001, "DISP_PWR_MAN", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000200, 0x00000001, "CRTC_H_TOTAL_DISP", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000208, 0x00000001, "CRTC_V_TOTAL_DISP", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000224, 0x00000001, "CRTC_OFFSET", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000003F8, 0x00000001, "CRTC2_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000228, 0x00000001, "CRTC_OFFSET_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000230, 0x00000001, "OVR_CLR", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000254, 0x00000001, "FP_CRTC_V_TOTAL_DISP", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000278, 0x00000001, "FP_HORZ_VERT_ACTIVE", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000027C, 0x00000001, "CRTC_MORE_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000288, 0x00000001, "FP2_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x0000028C, 0x00000001, "FP_HORZ_STRETCH", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D64, 0x00000001, "DISP_OUTPUT_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002A4, 0x00000001, "TMDS_TRANSMITTER_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D68, 0x00000001, "DISP2_MERGE_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002A8, 0x00000001, "TMDS_PLL_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002C4, 0x00000001, "FP_H_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000003C4, 0x00000001, "FP_H2_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002D0, 0x00000001, "LVDS_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000003C8, 0x00000001, "FP_V2_SYNC_STRT_WID", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002D4, 0x00000001, "LVDS_PLL_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x000002EC, 0x00000001, "LVDS_SS_GEN_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000800, 0x00000001, "TV_MASTER_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D04, 0x00000001, "DAC_MACRO_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, + {0x00000D60, 0x00000001, "DISP_MERGE_CNTL", r100_MMIO_rreg, r100_MMIO_wreg}, +}; + +unsigned r100_nreg = 67; + diff --git a/src/radeon_pci.c b/src/radeon_pci.c index 90b1106..bdad3a8 100644 --- a/src/radeon_pci.c +++ b/src/radeon_pci.c @@ -114,6 +114,15 @@ void radeon_mmio_wr32(struct radeon *radeon, u32 offset, u32 value) *(u32 * volatile)(radeon->mmio + offset) = value; } +void radeon_mmio_wr8(struct radeon *radeon, u32 offset, u8 value) +{ + if (radeon->mmio == NULL) { + fprintf(stderr, "(%s:%d) internal error\n", __func__, __LINE__); + exit(1); + } + *(u8 * volatile)(radeon->mmio + offset) = value; +} + struct radeon *radeon_new_from_pci(void) { struct radeon *radeon; diff --git a/src/radeon_priv.h b/src/radeon_priv.h index 0067998..dc6b058 100644 --- a/src/radeon_priv.h +++ b/src/radeon_priv.h @@ -225,6 +225,7 @@ extern void *copy_object(void *ptr, unsigned size); extern u32 radeon_mmio_rd32(struct radeon *radeon, u32 offset); extern void radeon_mmio_wr32(struct radeon *radeon, u32 offset, u32 value); +extern void radeon_mmio_wr8(struct radeon *radeon, u32 offset, u8 value); struct radeon *radeon_new_from_pci(void); #define radeon_ctx_get_dst_surface(ctx, dst) (ctx)->radeon->asic->ctx_get_dst_surface((ctx), (dst)) diff --git a/src/radeon_reg.c b/src/radeon_reg.c index 781794b..a2aef70 100644 --- a/src/radeon_reg.c +++ b/src/radeon_reg.c @@ -24,6 +24,7 @@ * Jerome Glisse */ #include <string.h> +#include <unistd.h> #include "radeon_priv.h" #include "radeon_reg.h" @@ -41,6 +42,20 @@ void radeon_register_dump(const char *bname) return; } switch (radeon->family) { + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + block = r100_block; + reg = r100_reg; + nblock = r100_nblock; + nreg = r100_nreg; + break; case CHIP_RS600: block = rs600_block; reg = rs600_reg; @@ -59,15 +74,6 @@ void radeon_register_dump(const char *bname) case CHIP_RV730: case CHIP_RV710: case CHIP_RV740: - case CHIP_R100: - case CHIP_RV100: - case CHIP_RS100: - case CHIP_RV200: - case CHIP_RS200: - case CHIP_R200: - case CHIP_RV250: - case CHIP_RS300: - case CHIP_RV280: case CHIP_R300: case CHIP_R350: case CHIP_RV350: @@ -104,17 +110,74 @@ void radeon_register_dump(const char *bname) fprintf(stderr, "%s unknown block %s for chipset 0x%04X\n", __func__, bname, radeon->device); } + bid = 1 << bid; } for (i = 0; i < nreg; i++) { - if ((bname && reg[i].block_id == bid) || bname == NULL) { - bid = reg[i].block_id; - printf("%s 0x%08X 0x%08X %s\n", block[bid].name, reg[i].offset, + if ((bname && reg[i].block_id & bid) || bname == NULL) { + printf("0x%08X 0x%08X %s\n", reg[i].offset, reg[i].rreg(radeon, reg[i].offset), reg[i].name); } } radeon_decref(radeon); } +/* R100 */ +u32 r100_MMIO_rreg(struct radeon *radeon, u32 offset) +{ + return radeon_mmio_rd32(radeon, offset); +} + +void r100_MMIO_wreg(struct radeon *radeon, u32 offset, u32 value) +{ + radeon_mmio_wr32(radeon, offset, value); +} + +void r100_pll_errata_after_index(struct radeon *radeon) +{ + if (radeon->family == CHIP_RV200 || radeon->family == CHIP_RS200) { + (void)radeon_mmio_rd32(radeon, 0x000C); + (void)radeon_mmio_rd32(radeon, 0x0050); + } +} + +static void r100_pll_errata_after_data(struct radeon *radeon) +{ + /* This workarounds is necessary on RV100, RS100 and RS200 chips + * or the chip could hang on a subsequent access + */ + if (radeon->family == CHIP_RV100 || radeon->family == CHIP_RS100 || + radeon->family == CHIP_RS200) { + sleep(1); + } + + /* This function is required to workaround a hardware bug in some (all?) + * revisions of the R300. This workaround should be called after every + * CLOCK_CNTL_INDEX register access. If not, register reads afterward + * may not be correct. + */ + if (radeon->family == CHIP_R300) { + u32 save, tmp; + + save = radeon_mmio_rd32(radeon, 0x0008); + tmp = save & ~(0x3f | (1 << 7)); + radeon_mmio_wr32(radeon, 0x0008, tmp); + tmp = radeon_mmio_rd32(radeon, 0x000C); + radeon_mmio_wr32(radeon, 0x0008, save); + } +} + +u32 r100_CLK_rreg(struct radeon *radeon, u32 offset) +{ + return radeon_mmio_rd32(radeon, offset); +} + +void r100_CLK_wreg(struct radeon *radeon, u32 offset, u32 value) +{ + radeon_mmio_wr8(radeon, 0x0008, ((offset & 0x3f) | (1 << 7))); + r100_pll_errata_after_index(radeon); + radeon_mmio_wr32(radeon, 0x000C, value); + r100_pll_errata_after_data(radeon); +} /* RS600 */ u32 rs600_MMIO_rreg(struct radeon *radeon, u32 offset) @@ -127,6 +190,7 @@ void rs600_MMIO_wreg(struct radeon *radeon, u32 offset, u32 value) radeon_mmio_wr32(radeon, offset, value); } + u32 rs600_MC_rreg(struct radeon *radeon, u32 offset) { radeon_mmio_wr32(radeon, 0x0070, (offset & 0xFFFF) | (1 << 21)); diff --git a/src/radeon_reg.h b/src/radeon_reg.h index 0fd367f..62f80b6 100644 --- a/src/radeon_reg.h +++ b/src/radeon_reg.h @@ -47,6 +47,16 @@ struct reg { radeon_wreg_t wreg; }; +/* R100 */ +u32 r100_MMIO_rreg(struct radeon *radeon, u32 offset); +void r100_MMIO_wreg(struct radeon *radeon, u32 offset, u32 value); +u32 r100_CLK_rreg(struct radeon *radeon, u32 offset); +void r100_CLK_wreg(struct radeon *radeon, u32 offset, u32 value); +extern struct reg_block r100_block[]; +extern struct reg r100_reg[]; +extern unsigned r100_nblock; +extern unsigned r100_nreg; + /* RS600 */ u32 rs600_MMIO_rreg(struct radeon *radeon, u32 offset); void rs600_MMIO_wreg(struct radeon *radeon, u32 offset, u32 value); diff --git a/src/rs600_reg.c b/src/rs600_reg.c index 35e1393..b744e05 100644 --- a/src/rs600_reg.c +++ b/src/rs600_reg.c @@ -2,81 +2,81 @@ #include "radeon_reg.h" struct reg_block rs600_block[] = { - {0, "DISP"}, - {1, "MC"}, + {0x00000001, "MC"}, + {0x00000002, "DISP"}, }; unsigned rs600_nblock = 2; struct reg rs600_reg[] = { - {0x00007D08, 0, "DC_HOT_PLUG_DETECT1_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000040, 0, "GEN_INT_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006D48, 0, "D2MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x0000654C, 0, "D1MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x000060A4, 0, "D1CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000E40, 0, "RBBM_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000070, 0, "MC_IND_INDEX", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007A38, 0, "DACB_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006548, 0, "D1MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x000007C0, 0, "CP_STAT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x0000004C, 0, "BUS_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006540, 0, "DxMODE_INT_MASK", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000044, 0, "GEN_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006534, 0, "D1MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x000068A4, 0, "D2CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000074, 0, "MC_IND_DATA", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007828, 0, "DACA_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007D00, 0, "DC_HOT_PLUG_DETECT1_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006D34, 0, "D2MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00006D4C, 0, "D2MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007838, 0, "DACA_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007D04, 0, "DC_HOT_PLUG_DETECT1_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007A28, 0, "DACB_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007D10, 0, "DC_HOT_PLUG_DETECT2_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007D14, 0, "DC_HOT_PLUG_DETECT2_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007D18, 0, "DC_HOT_PLUG_DETECT2_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00007EDC, 0, "DISP_INTERRUPT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x00000005, 1, "MC_AGP_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000013C, 1, "MC_PT0_CONTEXT0_FLAT_START_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000103, 1, "MC_PT0_CONTEXT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000175, 1, "MC_PT0_CLIENT9_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000000, 1, "MC_STATUS", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000016E, 1, "MC_PT0_CLIENT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000107, 1, "MC_PT0_CONTEXT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000179, 1, "MC_PT0_CLIENT13_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000004, 1, "MC_FB_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000006, 1, "AGP_BASE", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000007, 1, "AGP_BASE_2", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000009, 1, "MC_CNTL1", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000100, 1, "MC_PT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000102, 1, "MC_PT0_CONTEXT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000104, 1, "MC_PT0_CONTEXT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000016C, 1, "MC_PT0_CLIENT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000105, 1, "MC_PT0_CONTEXT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000011C, 1, "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000016D, 1, "MC_PT0_CLIENT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000106, 1, "MC_PT0_CONTEXT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000016F, 1, "MC_PT0_CLIENT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000108, 1, "MC_PT0_CONTEXT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000109, 1, "MC_PT0_CONTEXT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000112, 1, "MC_PT0_SYSTEM_APERTURE_LOW_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000017B, 1, "MC_PT0_CLIENT15_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000114, 1, "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000012C, 1, "MC_PT0_CONTEXT0_FLAT_BASE_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000134, 1, "HDP_FB_LOCATION", rs600_MMIO_rreg, rs600_MMIO_wreg}, - {0x0000014C, 1, "MC_PT0_CONTEXT0_FLAT_END_ADDR", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000170, 1, "MC_PT0_CLIENT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000171, 1, "MC_PT0_CLIENT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000172, 1, "MC_PT0_CLIENT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000173, 1, "MC_PT0_CLIENT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000174, 1, "MC_PT0_CLIENT8_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000176, 1, "MC_PT0_CLIENT10_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000177, 1, "MC_PT0_CLIENT11_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x00000178, 1, "MC_PT0_CLIENT12_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000017A, 1, "MC_PT0_CLIENT14_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000017C, 1, "MC_PT0_CLIENT16_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000017D, 1, "MC_PT0_CLIENT17_CNTL", rs600_MC_rreg, rs600_MC_wreg}, - {0x0000017E, 1, "MC_PT0_CLIENT18_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00007D08, 0x00000002, "DC_HOT_PLUG_DETECT1_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000134, 0x00000001, "HDP_FB_LOCATION", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000040, 0x00000002, "GEN_INT_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D48, 0x00000002, "D2MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x0000654C, 0x00000002, "D1MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000060A4, 0x00000002, "D1CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000E40, 0x00000002, "RBBM_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000070, 0x00000002, "MC_IND_INDEX", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007A38, 0x00000002, "DACB_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006548, 0x00000002, "D1MODE_PRIORITY_A_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000007C0, 0x00000002, "CP_STAT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x0000004C, 0x00000002, "BUS_CNTL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006540, 0x00000002, "DxMODE_INT_MASK", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000044, 0x00000002, "GEN_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006534, 0x00000002, "D1MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x000068A4, 0x00000002, "D2CRTC_STATUS_FRAME_COUNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000074, 0x00000002, "MC_IND_DATA", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007828, 0x00000002, "DACA_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D00, 0x00000002, "DC_HOT_PLUG_DETECT1_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D34, 0x00000002, "D2MODE_VBLANK_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00006D4C, 0x00000002, "D2MODE_PRIORITY_B_CNT", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007838, 0x00000002, "DACA_AUTODETECT_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D04, 0x00000002, "DC_HOT_PLUG_DETECT1_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007A28, 0x00000002, "DACB_AUTODETECT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D10, 0x00000002, "DC_HOT_PLUG_DETECT2_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D14, 0x00000002, "DC_HOT_PLUG_DETECT2_INT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007D18, 0x00000002, "DC_HOT_PLUG_DETECT2_INT_CONTROL", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00007EDC, 0x00000002, "DISP_INTERRUPT_STATUS", rs600_MMIO_rreg, rs600_MMIO_wreg}, + {0x00000005, 0x00000001, "MC_AGP_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000013C, 0x00000001, "MC_PT0_CONTEXT0_FLAT_START_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000103, 0x00000001, "MC_PT0_CONTEXT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000175, 0x00000001, "MC_PT0_CLIENT9_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000000, 0x00000001, "MC_STATUS", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016E, 0x00000001, "MC_PT0_CLIENT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000107, 0x00000001, "MC_PT0_CONTEXT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000179, 0x00000001, "MC_PT0_CLIENT13_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000004, 0x00000001, "MC_FB_LOCATION", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000006, 0x00000001, "AGP_BASE", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000007, 0x00000001, "AGP_BASE_2", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000009, 0x00000001, "MC_CNTL1", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000100, 0x00000001, "MC_PT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000102, 0x00000001, "MC_PT0_CONTEXT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000104, 0x00000001, "MC_PT0_CONTEXT2_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016C, 0x00000001, "MC_PT0_CLIENT0_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000105, 0x00000001, "MC_PT0_CONTEXT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000011C, 0x00000001, "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016D, 0x00000001, "MC_PT0_CLIENT1_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000106, 0x00000001, "MC_PT0_CONTEXT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000016F, 0x00000001, "MC_PT0_CLIENT3_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000108, 0x00000001, "MC_PT0_CONTEXT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000109, 0x00000001, "MC_PT0_CONTEXT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000112, 0x00000001, "MC_PT0_SYSTEM_APERTURE_LOW_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017B, 0x00000001, "MC_PT0_CLIENT15_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000114, 0x00000001, "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000012C, 0x00000001, "MC_PT0_CONTEXT0_FLAT_BASE_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000014C, 0x00000001, "MC_PT0_CONTEXT0_FLAT_END_ADDR", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000170, 0x00000001, "MC_PT0_CLIENT4_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000171, 0x00000001, "MC_PT0_CLIENT5_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000172, 0x00000001, "MC_PT0_CLIENT6_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000173, 0x00000001, "MC_PT0_CLIENT7_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000174, 0x00000001, "MC_PT0_CLIENT8_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000176, 0x00000001, "MC_PT0_CLIENT10_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000177, 0x00000001, "MC_PT0_CLIENT11_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x00000178, 0x00000001, "MC_PT0_CLIENT12_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017A, 0x00000001, "MC_PT0_CLIENT14_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017C, 0x00000001, "MC_PT0_CLIENT16_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017D, 0x00000001, "MC_PT0_CLIENT17_CNTL", rs600_MC_rreg, rs600_MC_wreg}, + {0x0000017E, 0x00000001, "MC_PT0_CLIENT18_CNTL", rs600_MC_rreg, rs600_MC_wreg}, }; unsigned rs600_nreg = 68; diff --git a/tools/rdb.c b/tools/rdb.c index 090f4dc..b34321e 100644 --- a/tools/rdb.c +++ b/tools/rdb.c @@ -35,11 +35,31 @@ void usage(void) { printf("usage: rdb [arguments] [file ..]\n\n"); printf("arguments:\n"); - printf(" -j replay json command stream\n"); + printf(" -j json file\n"); printf(" -l list\n"); printf(" -h header\n"); } +static unsigned blockflag(struct rdb_json *rdb, json_t *reg) +{ + unsigned flag = 0, i, j; + json_t *tmp, *tmp2, *unit; + + unit = json_object_get(reg, "unit"); + if (unit == NULL) + return 0; + for (i = 0; i < json_array_size(unit); i++) { + tmp = json_array_get(unit, i); + for (j = 0; j < json_array_size(rdb->unit); j++) { + tmp2 = json_array_get(rdb->unit, j); + if (!strcmp(json_string_value(tmp), json_string_value(tmp2))) { + flag |= 1 << j; + } + } + } + return flag; +} + struct param { int list; int header; @@ -116,11 +136,11 @@ int main(int argc, char *argv[]) if (param.header_name) { printf("/* this file is autogenerated don't edit */\n"); printf("#include \"radeon_reg.h\"\n\n"); + printf("struct reg_block %s_block[] = {\n", param.header_name); - for (i = 0; i < json_array_size(rdb->block); i++) { - block = json_array_get(rdb->block, i); - tmp = json_object_get(block, "name"); - printf("\t{%d, \"%s\"},\n", i, json_string_value(tmp)); + for (i = 0; i < json_array_size(rdb->unit); i++) { + tmp = json_array_get(rdb->unit, i); + printf("\t{0x%08X, \"%s\"},\n", 1 << i, json_string_value(tmp)); } printf("};\n\n"); printf("unsigned %s_nblock = %d;\n\n", param.header_name, json_array_size(rdb->block)); @@ -136,11 +156,10 @@ int main(int argc, char *argv[]) if (json_is_object(reg)) { offset = strtoul(json_object_iter_key(iter), NULL, 16); tmp = json_object_get(reg, "name"); - tmp2 = json_object_get(reg, "ioname"); - printf("\t{0x%08X, %4d, \"%s\", %s_%s_rreg, %s_%s_wreg},\n", - offset, i, json_string_value(tmp), - param.header_name, json_string_value(tmp2), - param.header_name, json_string_value(tmp2)); + printf("\t{0x%08X, 0x%08X, \"%s\", %s_%s_rreg, %s_%s_wreg},\n", + offset, blockflag(rdb, reg), json_string_value(tmp), + param.header_name, json_string_value(name), + param.header_name, json_string_value(name)); c++; } iter = json_object_iter_next(block, iter); diff --git a/tools/rdb_json.c b/tools/rdb_json.c index f896379..4a62f65 100644 --- a/tools/rdb_json.c +++ b/tools/rdb_json.c @@ -96,6 +96,7 @@ struct rdb_json *rdb_json_load(const char *file) return NULL; } rdb->block = json_object_get(rdb->root, "block"); + rdb->unit = json_object_get(rdb->root, "unit"); return rdb; } diff --git a/tools/rdb_json.h b/tools/rdb_json.h index aa66722..2e46766 100644 --- a/tools/rdb_json.h +++ b/tools/rdb_json.h @@ -31,8 +31,9 @@ #include "jansson.h" struct rdb_json { - json_t *root; - json_t *block; + json_t *root; + json_t *block; + json_t *unit; }; int rdb_json_block_add(struct rdb_json *rdb, const char *name); |