radeondb: initial commit

radeondb is aimed as being a set of tools for radeon
GPU debugging. First version only include command stream
replaying.

Goal for 1.0 version:
-R1XX-R5XX command stream replay support
-JSON command stream format replay support (R1XX-R7XX)

Future goal:
-X version allowing graphical interaction and analysis
 of GPU command stream
-Blit support for "faster" replay

Signed-off-by: Jerome Glisse <jglisse@redhat.com>

29 files changed, 9837 insertions, 0 deletions

diff --git a/COPYING b/COPYING
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--- /dev/null
+++ b/COPYING
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+HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
+OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
+THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE.  THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
+IS WITH YOU.  SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
+ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
+
+  16. Limitation of Liability.
+
+  IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
+THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/INSTALL b/INSTALL
new file mode 100644
index 0000000..7d1c323
--- /dev/null
+++ b/INSTALL
@@ -0,0 +1,365 @@
+Installation Instructions
+*************************
+
+Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005,
+2006, 2007, 2008, 2009 Free Software Foundation, Inc.
+
+   Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.  This file is offered as-is,
+without warranty of any kind.
+
+Basic Installation
+==================
+
+   Briefly, the shell commands `./configure; make; make install' should
+configure, build, and install this package.  The following
+more-detailed instructions are generic; see the `README' file for
+instructions specific to this package.  Some packages provide this
+`INSTALL' file but do not implement all of the features documented
+below.  The lack of an optional feature in a given package is not
+necessarily a bug.  More recommendations for GNU packages can be found
+in *note Makefile Conventions: (standards)Makefile Conventions.
+
+   The `configure' shell script attempts to guess correct values for
+various system-dependent variables used during compilation.  It uses
+those values to create a `Makefile' in each directory of the package.
+It may also create one or more `.h' files containing system-dependent
+definitions.  Finally, it creates a shell script `config.status' that
+you can run in the future to recreate the current configuration, and a
+file `config.log' containing compiler output (useful mainly for
+debugging `configure').
+
+   It can also use an optional file (typically called `config.cache'
+and enabled with `--cache-file=config.cache' or simply `-C') that saves
+the results of its tests to speed up reconfiguring.  Caching is
+disabled by default to prevent problems with accidental use of stale
+cache files.
+
+   If you need to do unusual things to compile the package, please try
+to figure out how `configure' could check whether to do them, and mail
+diffs or instructions to the address given in the `README' so they can
+be considered for the next release.  If you are using the cache, and at
+some point `config.cache' contains results you don't want to keep, you
+may remove or edit it.
+
+   The file `configure.ac' (or `configure.in') is used to create
+`configure' by a program called `autoconf'.  You need `configure.ac' if
+you want to change it or regenerate `configure' using a newer version
+of `autoconf'.
+
+   The simplest way to compile this package is:
+
+  1. `cd' to the directory containing the package's source code and type
+     `./configure' to configure the package for your system.
+
+     Running `configure' might take a while.  While running, it prints
+     some messages telling which features it is checking for.
+
+  2. Type `make' to compile the package.
+
+  3. Optionally, type `make check' to run any self-tests that come with
+     the package, generally using the just-built uninstalled binaries.
+
+  4. Type `make install' to install the programs and any data files and
+     documentation.  When installing into a prefix owned by root, it is
+     recommended that the package be configured and built as a regular
+     user, and only the `make install' phase executed with root
+     privileges.
+
+  5. Optionally, type `make installcheck' to repeat any self-tests, but
+     this time using the binaries in their final installed location.
+     This target does not install anything.  Running this target as a
+     regular user, particularly if the prior `make install' required
+     root privileges, verifies that the installation completed
+     correctly.
+
+  6. You can remove the program binaries and object files from the
+     source code directory by typing `make clean'.  To also remove the
+     files that `configure' created (so you can compile the package for
+     a different kind of computer), type `make distclean'.  There is
+     also a `make maintainer-clean' target, but that is intended mainly
+     for the package's developers.  If you use it, you may have to get
+     all sorts of other programs in order to regenerate files that came
+     with the distribution.
+
+  7. Often, you can also type `make uninstall' to remove the installed
+     files again.  In practice, not all packages have tested that
+     uninstallation works correctly, even though it is required by the
+     GNU Coding Standards.
+
+  8. Some packages, particularly those that use Automake, provide `make
+     distcheck', which can by used by developers to test that all other
+     targets like `make install' and `make uninstall' work correctly.
+     This target is generally not run by end users.
+
+Compilers and Options
+=====================
+
+   Some systems require unusual options for compilation or linking that
+the `configure' script does not know about.  Run `./configure --help'
+for details on some of the pertinent environment variables.
+
+   You can give `configure' initial values for configuration parameters
+by setting variables in the command line or in the environment.  Here
+is an example:
+
+     ./configure CC=c99 CFLAGS=-g LIBS=-lposix
+
+   *Note Defining Variables::, for more details.
+
+Compiling For Multiple Architectures
+====================================
+
+   You can compile the package for more than one kind of computer at the
+same time, by placing the object files for each architecture in their
+own directory.  To do this, you can use GNU `make'.  `cd' to the
+directory where you want the object files and executables to go and run
+the `configure' script.  `configure' automatically checks for the
+source code in the directory that `configure' is in and in `..'.  This
+is known as a "VPATH" build.
+
+   With a non-GNU `make', it is safer to compile the package for one
+architecture at a time in the source code directory.  After you have
+installed the package for one architecture, use `make distclean' before
+reconfiguring for another architecture.
+
+   On MacOS X 10.5 and later systems, you can create libraries and
+executables that work on multiple system types--known as "fat" or
+"universal" binaries--by specifying multiple `-arch' options to the
+compiler but only a single `-arch' option to the preprocessor.  Like
+this:
+
+     ./configure CC="gcc -arch i386 -arch x86_64 -arch ppc -arch ppc64" \
+                 CXX="g++ -arch i386 -arch x86_64 -arch ppc -arch ppc64" \
+                 CPP="gcc -E" CXXCPP="g++ -E"
+
+   This is not guaranteed to produce working output in all cases, you
+may have to build one architecture at a time and combine the results
+using the `lipo' tool if you have problems.
+
+Installation Names
+==================
+
+   By default, `make install' installs the package's commands under
+`/usr/local/bin', include files under `/usr/local/include', etc.  You
+can specify an installation prefix other than `/usr/local' by giving
+`configure' the option `--prefix=PREFIX', where PREFIX must be an
+absolute file name.
+
+   You can specify separate installation prefixes for
+architecture-specific files and architecture-independent files.  If you
+pass the option `--exec-prefix=PREFIX' to `configure', the package uses
+PREFIX as the prefix for installing programs and libraries.
+Documentation and other data files still use the regular prefix.
+
+   In addition, if you use an unusual directory layout you can give
+options like `--bindir=DIR' to specify different values for particular
+kinds of files.  Run `configure --help' for a list of the directories
+you can set and what kinds of files go in them.  In general, the
+default for these options is expressed in terms of `${prefix}', so that
+specifying just `--prefix' will affect all of the other directory
+specifications that were not explicitly provided.
+
+   The most portable way to affect installation locations is to pass the
+correct locations to `configure'; however, many packages provide one or
+both of the following shortcuts of passing variable assignments to the
+`make install' command line to change installation locations without
+having to reconfigure or recompile.
+
+   The first method involves providing an override variable for each
+affected directory.  For example, `make install
+prefix=/alternate/directory' will choose an alternate location for all
+directory configuration variables that were expressed in terms of
+`${prefix}'.  Any directories that were specified during `configure',
+but not in terms of `${prefix}', must each be overridden at install
+time for the entire installation to be relocated.  The approach of
+makefile variable overrides for each directory variable is required by
+the GNU Coding Standards, and ideally causes no recompilation.
+However, some platforms have known limitations with the semantics of
+shared libraries that end up requiring recompilation when using this
+method, particularly noticeable in packages that use GNU Libtool.
+
+   The second method involves providing the `DESTDIR' variable.  For
+example, `make install DESTDIR=/alternate/directory' will prepend
+`/alternate/directory' before all installation names.  The approach of
+`DESTDIR' overrides is not required by the GNU Coding Standards, and
+does not work on platforms that have drive letters.  On the other hand,
+it does better at avoiding recompilation issues, and works well even
+when some directory options were not specified in terms of `${prefix}'
+at `configure' time.
+
+Optional Features
+=================
+
+   If the package supports it, you can cause programs to be installed
+with an extra prefix or suffix on their names by giving `configure' the
+option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
+
+   Some packages pay attention to `--enable-FEATURE' options to
+`configure', where FEATURE indicates an optional part of the package.
+They may also pay attention to `--with-PACKAGE' options, where PACKAGE
+is something like `gnu-as' or `x' (for the X Window System).  The
+`README' should mention any `--enable-' and `--with-' options that the
+package recognizes.
+
+   For packages that use the X Window System, `configure' can usually
+find the X include and library files automatically, but if it doesn't,
+you can use the `configure' options `--x-includes=DIR' and
+`--x-libraries=DIR' to specify their locations.
+
+   Some packages offer the ability to configure how verbose the
+execution of `make' will be.  For these packages, running `./configure
+--enable-silent-rules' sets the default to minimal output, which can be
+overridden with `make V=1'; while running `./configure
+--disable-silent-rules' sets the default to verbose, which can be
+overridden with `make V=0'.
+
+Particular systems
+==================
+
+   On HP-UX, the default C compiler is not ANSI C compatible.  If GNU
+CC is not installed, it is recommended to use the following options in
+order to use an ANSI C compiler:
+
+     ./configure CC="cc -Ae -D_XOPEN_SOURCE=500"
+
+and if that doesn't work, install pre-built binaries of GCC for HP-UX.
+
+   On OSF/1 a.k.a. Tru64, some versions of the default C compiler cannot
+parse its `<wchar.h>' header file.  The option `-nodtk' can be used as
+a workaround.  If GNU CC is not installed, it is therefore recommended
+to try
+
+     ./configure CC="cc"
+
+and if that doesn't work, try
+
+     ./configure CC="cc -nodtk"
+
+   On Solaris, don't put `/usr/ucb' early in your `PATH'.  This
+directory contains several dysfunctional programs; working variants of
+these programs are available in `/usr/bin'.  So, if you need `/usr/ucb'
+in your `PATH', put it _after_ `/usr/bin'.
+
+   On Haiku, software installed for all users goes in `/boot/common',
+not `/usr/local'.  It is recommended to use the following options:
+
+     ./configure --prefix=/boot/common
+
+Specifying the System Type
+==========================
+
+   There may be some features `configure' cannot figure out
+automatically, but needs to determine by the type of machine the package
+will run on.  Usually, assuming the package is built to be run on the
+_same_ architectures, `configure' can figure that out, but if it prints
+a message saying it cannot guess the machine type, give it the
+`--build=TYPE' option.  TYPE can either be a short name for the system
+type, such as `sun4', or a canonical name which has the form:
+
+     CPU-COMPANY-SYSTEM
+
+where SYSTEM can have one of these forms:
+
+     OS
+     KERNEL-OS
+
+   See the file `config.sub' for the possible values of each field.  If
+`config.sub' isn't included in this package, then this package doesn't
+need to know the machine type.
+
+   If you are _building_ compiler tools for cross-compiling, you should
+use the option `--target=TYPE' to select the type of system they will
+produce code for.
+
+   If you want to _use_ a cross compiler, that generates code for a
+platform different from the build platform, you should specify the
+"host" platform (i.e., that on which the generated programs will
+eventually be run) with `--host=TYPE'.
+
+Sharing Defaults
+================
+
+   If you want to set default values for `configure' scripts to share,
+you can create a site shell script called `config.site' that gives
+default values for variables like `CC', `cache_file', and `prefix'.
+`configure' looks for `PREFIX/share/config.site' if it exists, then
+`PREFIX/etc/config.site' if it exists.  Or, you can set the
+`CONFIG_SITE' environment variable to the location of the site script.
+A warning: not all `configure' scripts look for a site script.
+
+Defining Variables
+==================
+
+   Variables not defined in a site shell script can be set in the
+environment passed to `configure'.  However, some packages may run
+configure again during the build, and the customized values of these
+variables may be lost.  In order to avoid this problem, you should set
+them in the `configure' command line, using `VAR=value'.  For example:
+
+     ./configure CC=/usr/local2/bin/gcc
+
+causes the specified `gcc' to be used as the C compiler (unless it is
+overridden in the site shell script).
+
+Unfortunately, this technique does not work for `CONFIG_SHELL' due to
+an Autoconf bug.  Until the bug is fixed you can use this workaround:
+
+     CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash
+
+`configure' Invocation
+======================
+
+   `configure' recognizes the following options to control how it
+operates.
+
+`--help'
+`-h'
+     Print a summary of all of the options to `configure', and exit.
+
+`--help=short'
+`--help=recursive'
+     Print a summary of the options unique to this package's
+     `configure', and exit.  The `short' variant lists options used
+     only in the top level, while the `recursive' variant lists options
+     also present in any nested packages.
+
+`--version'
+`-V'
+     Print the version of Autoconf used to generate the `configure'
+     script, and exit.
+
+`--cache-file=FILE'
+     Enable the cache: use and save the results of the tests in FILE,
+     traditionally `config.cache'.  FILE defaults to `/dev/null' to
+     disable caching.
+
+`--config-cache'
+`-C'
+     Alias for `--cache-file=config.cache'.
+
+`--quiet'
+`--silent'
+`-q'
+     Do not print messages saying which checks are being made.  To
+     suppress all normal output, redirect it to `/dev/null' (any error
+     messages will still be shown).
+
+`--srcdir=DIR'
+     Look for the package's source code in directory DIR.  Usually
+     `configure' can determine that directory automatically.
+
+`--prefix=DIR'
+     Use DIR as the installation prefix.  *note Installation Names::
+     for more details, including other options available for fine-tuning
+     the installation locations.
+
+`--no-create'
+`-n'
+     Run the configure checks, but stop before creating any output
+     files.
+
+`configure' also accepts some other, not widely useful, options.  Run
+`configure --help' for more details.
+
diff --git a/Makefile.am b/Makefile.am
new file mode 100644
index 0000000..4196901
--- /dev/null
+++ b/Makefile.am
@@ -0,0 +1,23 @@
+#  Copyright 2009 Dave Airlie
+#  Copyright 2010 Jerome Glisse
+#
+#  Permission is hereby granted, free of charge, to any person obtaining a
+#  copy of this software and associated documentation files (the "Software"),
+#  to deal in the Software without restriction, including without limitation
+#  on the rights to use, copy, modify, merge, publish, distribute, sub
+#  license, and/or sell copies of the Software, and to permit persons to whom
+#  the Software is furnished to do so, subject to the following conditions:
+#
+#  The above copyright notice and this permission notice (including the next
+#  paragraph) shall be included in all copies or substantial portions of the
+#  Software.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
+#  THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+#  IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+#  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+AUTOMAKE_OPTIONS = foreign
+
+SUBDIRS = src
diff --git a/autogen.sh b/autogen.sh
new file mode 100755
index 0000000..354f254
--- /dev/null
+++ b/autogen.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+srcdir=`dirname $0`
+test -z "$srcdir" && srcdir=.
+
+ORIGDIR=`pwd`
+cd $srcdir
+
+autoreconf -v --install || exit 1
+cd $ORIGDIR || exit $?
+
+$srcdir/configure "$@"
diff --git a/configure.ac b/configure.ac
new file mode 100644
index 0000000..72f92dd
--- /dev/null
+++ b/configure.ac
@@ -0,0 +1,39 @@
+#  Copyright 2009 Dave Airlie
+#  Copyright 2010 Jerome Glisse
+#
+#  Permission is hereby granted, free of charge, to any person obtaining a
+#  copy of this software and associated documentation files (the "Software"),
+#  to deal in the Software without restriction, including without limitation
+#  on the rights to use, copy, modify, merge, publish, distribute, sub
+#  license, and/or sell copies of the Software, and to permit persons to whom
+#  the Software is furnished to do so, subject to the following conditions:
+#
+#  The above copyright notice and this permission notice (including the next
+#  paragraph) shall be included in all copies or substantial portions of the
+#  Software.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
+#  THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+#  IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+#  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+AC_PREREQ([2.60])
+AC_INIT([radeondb], 0.9.0, [xorg-driver-ati@lists.x.org], radeondb)
+AM_INIT_AUTOMAKE([])
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])],
+    [AC_SUBST([AM_DEFAULT_VERBOSITY], [1])])
+AM_CONFIG_HEADER([src/config.h])
+
+AC_PROG_LIBTOOL
+
+AC_DISABLE_STATIC
+AC_PROG_CC
+AC_PROG_INSTALL
+
+PKG_CHECK_MODULES(LIBJANSSON, jansson)
+PKG_CHECK_MODULES(LIBDRM, libdrm)
+PKG_CHECK_MODULES(LIBDRM_RADEON, libdrm_radeon)
+
+AC_OUTPUT([Makefile src/Makefile])
diff --git a/src/Makefile.am b/src/Makefile.am
new file mode 100644
index 0000000..5cefdc0
--- /dev/null
+++ b/src/Makefile.am
@@ -0,0 +1,33 @@
+#  Copyright 2009 Dave Airlie
+#  Copyright 2010 Jerome Glisse
+#
+#  Permission is hereby granted, free of charge, to any person obtaining a
+#  copy of this software and associated documentation files (the "Software"),
+#  to deal in the Software without restriction, including without limitation
+#  on the rights to use, copy, modify, merge, publish, distribute, sub
+#  license, and/or sell copies of the Software, and to permit persons to whom
+#  the Software is furnished to do so, subject to the following conditions:
+#
+#  The above copyright notice and this permission notice (including the next
+#  paragraph) shall be included in all copies or substantial portions of the
+#  Software.
+#
+#  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+#  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+#  FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
+#  THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+#  IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+#  CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+AUTOMAKE_OPTIONS = foreign
+
+bin_PROGRAMS = radeondb
+
+AM_CFLAGS = -std=c99 $(LIBJANSSON_CFLAGS) $(LIBDRM_CFLAGS)$(LIBDRM_RADEON_CFLAGS)
+
+radeondb_SOURCES = radeondb.c bof.c radeon_pciid.c radeon_ctx.c radeon_bof.c\
+	radeon_json.c r600_state.c r600_ctx.c mode.c radeon.c radeon_state.c\
+	radeon_draw.c
+radeondb_LDADD = $(LIBJANSSON_LIBS) $(LIBDRM_LIBS) $(LIBDRM_RADEON_LIBS)
+
+EXTRA_DIST = radeon.h radeon_priv.h r600_states.h mode.h
diff --git a/src/bof.c b/src/bof.c
new file mode 100644
index 0000000..0598cc6
--- /dev/null
+++ b/src/bof.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+#include "bof.h"
+
+/*
+ * helpers
+ */
+static int bof_entry_grow(bof_t *bof)
+{
+	bof_t **array;
+
+	if (bof->array_size < bof->nentry)
+		return 0;
+	array = realloc(bof->array, (bof->nentry + 16) * sizeof(void*));
+	if (array == NULL)
+		return -ENOMEM;
+	bof->array = array;
+	bof->nentry += 16;
+	return 0;
+}
+
+/*
+ * object 
+ */
+bof_t *bof_object(void)
+{
+	bof_t *object;
+
+	object = calloc(1, sizeof(bof_t));
+	if (object == NULL)
+		return NULL;
+	object->refcount = 1;
+	object->type = BOF_TYPE_OBJECT;
+	object->size = 12;
+	return object;
+}
+
+bof_t *bof_object_get(bof_t *object, const char *keyname)
+{
+	unsigned i;
+
+	for (i = 0; i < object->array_size; i += 2) {
+		if (!strcmp(object->array[i]->value, keyname)) {
+			return object->array[i + 1];
+		}
+	}
+	return NULL;
+}
+
+int bof_object_set(bof_t *object, const char *keyname, bof_t *value)
+{
+	bof_t *key;
+	int r;
+
+	if (object->type != BOF_TYPE_OBJECT)
+		return -EINVAL;
+	r = bof_entry_grow(object);
+	if (r)
+		return r;
+	key = bof_string(keyname);
+	if (key == NULL)
+		return -ENOMEM;
+	object->array[object->array_size++] = key;
+	object->array[object->array_size++] = value;
+	object->size += value->size;
+	object->size += key->size;
+	bof_incref(value);
+	return 0;
+}
+
+/*
+ * array
+ */
+bof_t *bof_array(void)
+{
+	bof_t *array = bof_object();
+
+	if (array == NULL)
+		return NULL;
+	array->type = BOF_TYPE_ARRAY;
+	array->size = 12;
+	return array;
+}
+
+int bof_array_append(bof_t *array, bof_t *value)
+{
+	int r;
+	if (array->type != BOF_TYPE_ARRAY)
+		return -EINVAL;
+	r = bof_entry_grow(array);
+	if (r)
+		return r;
+	array->array[array->array_size++] = value;
+	array->size += value->size;
+	bof_incref(value);
+	return 0;
+}
+
+bof_t *bof_array_get(bof_t *bof, unsigned i)
+{
+	if (!bof_is_array(bof) || i >= bof->array_size)
+		return NULL;
+	return bof->array[i];
+}
+
+unsigned bof_array_size(bof_t *bof)
+{
+	if (!bof_is_array(bof))
+		return 0;
+	return bof->array_size;
+}
+
+/*
+ * blob
+ */
+bof_t *bof_blob(unsigned size, void *value)
+{
+	bof_t *blob = bof_object();
+
+	if (blob == NULL)
+		return NULL;
+	blob->type = BOF_TYPE_BLOB;
+	blob->value = calloc(1, size);
+	if (blob->value == NULL) {
+		bof_decref(blob);
+		return NULL;
+	}
+	blob->size = size;
+	memcpy(blob->value, value, size);
+	blob->size += 12;
+	return blob;
+}
+
+unsigned bof_blob_size(bof_t *bof)
+{
+	if (!bof_is_blob(bof))
+		return 0;
+	return bof->size - 12;
+}
+
+void *bof_blob_value(bof_t *bof)
+{
+	if (!bof_is_blob(bof))
+		return NULL;
+	return bof->value;
+}
+
+/*
+ * string
+ */
+bof_t *bof_string(const char *value)
+{
+	bof_t *string = bof_object();
+
+	if (string == NULL)
+		return NULL;
+	string->type = BOF_TYPE_STRING;
+	string->size = strlen(value) + 1;
+	string->value = calloc(1, string->size);
+	if (string->value == NULL) {
+		bof_decref(string);
+		return NULL;
+	}
+	strcpy(string->value, value);
+	string->size += 12;
+	return string;
+}
+
+/*
+ *  int32
+ */
+bof_t *bof_int32(int32_t value)
+{
+	bof_t *int32 = bof_object();
+
+	if (int32 == NULL)
+		return NULL;
+	int32->type = BOF_TYPE_INT32;
+	int32->size = 4;
+	int32->value = calloc(1, int32->size);
+	if (int32->value == NULL) {
+		bof_decref(int32);
+		return NULL;
+	}
+	memcpy(int32->value, &value, 4);
+	int32->size += 12;
+	return int32;
+}
+
+int32_t bof_int32_value(bof_t *bof)
+{
+	return *((uint32_t*)bof->value);
+}
+
+/*
+ *  common
+ */
+static void bof_indent(int level)
+{
+	int i;
+
+	for (i = 0; i < level; i++)
+		fprintf(stderr, " ");
+}
+
+static void bof_print_bof(bof_t *bof, int level, int entry)
+{
+	bof_indent(level);
+	if (bof == NULL) {
+		fprintf(stderr, "--NULL-- for entry %d\n", entry);
+		return;
+	}
+	switch (bof->type) {
+	case BOF_TYPE_STRING:
+		fprintf(stderr, "%p string [%s %d]\n", bof, (char*)bof->value, bof->size);
+		break;
+	case BOF_TYPE_INT32:
+		fprintf(stderr, "%p int32 [%d %d]\n", bof, *(int*)bof->value, bof->size);
+		break;
+	case BOF_TYPE_BLOB:
+		fprintf(stderr, "%p blob [%d]\n", bof, bof->size);
+		break;
+	case BOF_TYPE_NULL:
+		fprintf(stderr, "%p null [%d]\n", bof, bof->size);
+		break;
+	case BOF_TYPE_OBJECT:
+		fprintf(stderr, "%p object [%d %d]\n", bof, bof->array_size / 2, bof->size);
+		break;
+	case BOF_TYPE_ARRAY:
+		fprintf(stderr, "%p array [%d %d]\n", bof, bof->array_size, bof->size);
+		break;
+	default:
+		fprintf(stderr, "%p unknown [%d]\n", bof, bof->type);
+		return;
+	}
+}
+
+static void bof_print_rec(bof_t *bof, int level, int entry)
+{
+	unsigned i;
+
+	bof_print_bof(bof, level, entry);
+	for (i = 0; i < bof->array_size; i++) {
+		bof_print_rec(bof->array[i], level + 2, i);
+	}
+}
+
+void bof_print(bof_t *bof)
+{
+	bof_print_rec(bof, 0, 0);
+}
+
+static int bof_read(bof_t *root, FILE *file, long end, int level)
+{
+	bof_t *bof = NULL;
+	int r;
+
+	if (ftell(file) >= end) {
+		return 0;
+	}
+	r = bof_entry_grow(root);
+	if (r)
+		return r;
+	bof = bof_object();
+	if (bof == NULL)
+		return -ENOMEM;
+	bof->offset = ftell(file);
+	r = fread(&bof->type, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&bof->size, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&bof->array_size, 4, 1, file);
+	if (r != 1)
+		goto out_err;
+	switch (bof->type) {
+	case BOF_TYPE_STRING:
+	case BOF_TYPE_INT32:
+	case BOF_TYPE_BLOB:
+		bof->value = calloc(1, bof->size - 12);
+		if (bof->value == NULL) {
+			goto out_err;
+		}
+		r = fread(bof->value, bof->size - 12, 1, file);
+		if (r != 1) {
+			fprintf(stderr, "error reading %d\n", bof->size - 12);
+			goto out_err;
+		}
+		break;
+	case BOF_TYPE_NULL:
+		return 0;
+	case BOF_TYPE_OBJECT:
+	case BOF_TYPE_ARRAY:
+		r = bof_read(bof, file, bof->offset + bof->size, level + 2);
+		if (r)
+			goto out_err;
+		break;
+	default:
+		fprintf(stderr, "invalid type %d\n", bof->type);
+		goto out_err;
+	}
+	root->array[root->centry++] = bof;
+	return bof_read(root, file, end, level);
+out_err:
+	bof_decref(bof);
+	return -EINVAL;
+}
+
+bof_t *bof_load_file(const char *filename)
+{
+	bof_t *root = bof_object();
+	int r;
+
+	if (root == NULL) {
+		fprintf(stderr, "%s failed to create root object\n", __func__);
+		return NULL;
+	}
+	root->file = fopen(filename, "r");
+	if (root->file == NULL)
+		goto out_err;
+	r = fseek(root->file, 0L, SEEK_SET);
+	if (r) {
+		fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename);
+		goto out_err;
+	}
+	root->offset = ftell(root->file);
+	r = fread(&root->type, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&root->size, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = fread(&root->array_size, 4, 1, root->file);
+	if (r != 1)
+		goto out_err;
+	r = bof_read(root, root->file, root->offset + root->size, 2);
+	if (r)
+		goto out_err;
+	return root;
+out_err:
+	bof_decref(root);
+	return NULL;
+}
+
+void bof_incref(bof_t *bof)
+{
+	bof->refcount++;
+}
+
+void bof_decref(bof_t *bof)
+{
+	unsigned i;
+
+	if (bof == NULL)
+		return;
+	if (--bof->refcount > 0)
+		return;
+	for (i = 0; i < bof->array_size; i++) {
+		bof_decref(bof->array[i]);
+		bof->array[i] = NULL;
+	}
+	bof->array_size = 0;
+	if (bof->file) {
+		fclose(bof->file);
+		bof->file = NULL;
+	}
+	free(bof->array);
+	free(bof->value);
+	free(bof);
+}
+
+static int bof_file_write(bof_t *bof, FILE *file)
+{
+	unsigned i;
+	int r;
+
+	r = fwrite(&bof->type, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	r = fwrite(&bof->size, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	r = fwrite(&bof->array_size, 4, 1, file);
+	if (r != 1)
+		return -EINVAL;
+	switch (bof->type) {
+	case BOF_TYPE_NULL:
+		if (bof->size)
+			return -EINVAL;
+		break;
+	case BOF_TYPE_STRING:
+	case BOF_TYPE_INT32:
+	case BOF_TYPE_BLOB:
+		r = fwrite(bof->value, bof->size - 12, 1, file);
+		if (r != 1)
+			return -EINVAL;
+		break;
+	case BOF_TYPE_OBJECT:
+	case BOF_TYPE_ARRAY:
+		for (i = 0; i < bof->array_size; i++) {
+			r = bof_file_write(bof->array[i], file);
+			if (r)
+				return r;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+int bof_dump_file(bof_t *bof, const char *filename)
+{
+	unsigned i;
+	int r = 0;
+
+	if (bof->file) {
+		fclose(bof->file);
+		bof->file = NULL;
+	}
+	bof->file = fopen(filename, "w");
+	if (bof->file == NULL) {
+		fprintf(stderr, "%s failed to open file %s\n", __func__, filename);
+		r = -EINVAL;
+		goto out_err;
+	}
+	r = fseek(bof->file, 0L, SEEK_SET);
+	if (r) {
+		fprintf(stderr, "%s failed to seek into file %s\n", __func__, filename);
+		goto out_err;
+	}
+	r = fwrite(&bof->type, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	r = fwrite(&bof->size, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	r = fwrite(&bof->array_size, 4, 1, bof->file);
+	if (r != 1)
+		goto out_err;
+	for (i = 0; i < bof->array_size; i++) {
+		r = bof_file_write(bof->array[i], bof->file);
+		if (r)
+			return r;
+	}
+out_err:
+	fclose(bof->file);
+	bof->file = NULL;
+	return r;
+}
diff --git a/src/bof.h b/src/bof.h
new file mode 100644
index 0000000..014affb
--- /dev/null
+++ b/src/bof.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef BOF_H
+#define BOF_H
+
+#include <stdio.h>
+#include <stdint.h>
+
+#define BOF_TYPE_STRING		0
+#define BOF_TYPE_NULL		1
+#define BOF_TYPE_BLOB		2
+#define BOF_TYPE_OBJECT		3
+#define BOF_TYPE_ARRAY		4
+#define BOF_TYPE_INT32		5
+
+struct bof;
+
+typedef struct bof {
+	struct bof	**array;
+	unsigned	centry;
+	unsigned	nentry;
+	unsigned	refcount;
+	FILE		*file;
+	uint32_t	type;
+	uint32_t	size;
+	uint32_t	array_size;
+	void		*value;
+	long		offset;
+} bof_t;
+
+extern int bof_file_flush(bof_t *root);
+extern bof_t *bof_file_new(const char *filename);
+extern int bof_object_dump(bof_t *object, const char *filename);
+
+/* object */
+extern bof_t *bof_object(void);
+extern bof_t *bof_object_get(bof_t *object, const char *keyname);
+extern int bof_object_set(bof_t *object, const char *keyname, bof_t *value);
+/* array */
+extern bof_t *bof_array(void);
+extern int bof_array_append(bof_t *array, bof_t *value);
+extern bof_t *bof_array_get(bof_t *bof, unsigned i);
+extern unsigned bof_array_size(bof_t *bof);
+/* blob */
+extern bof_t *bof_blob(unsigned size, void *value);
+extern unsigned bof_blob_size(bof_t *bof);
+extern void *bof_blob_value(bof_t *bof);
+/* string */
+extern bof_t *bof_string(const char *value);
+/* int32 */
+extern bof_t *bof_int32(int32_t value);
+extern int32_t bof_int32_value(bof_t *bof);
+/* common functions */
+extern void bof_decref(bof_t *bof);
+extern void bof_incref(bof_t *bof);
+extern bof_t *bof_load_file(const char *filename);
+extern int bof_dump_file(bof_t *bof, const char *filename);
+extern void bof_print(bof_t *bof);
+
+static inline int bof_is_object(bof_t *bof){return (bof->type == BOF_TYPE_OBJECT);}
+static inline int bof_is_blob(bof_t *bof){return (bof->type == BOF_TYPE_BLOB);}
+static inline int bof_is_null(bof_t *bof){return (bof->type == BOF_TYPE_NULL);}
+static inline int bof_is_int32(bof_t *bof){return (bof->type == BOF_TYPE_INT32);}
+static inline int bof_is_array(bof_t *bof){return (bof->type == BOF_TYPE_ARRAY);}
+static inline int bof_is_string(bof_t *bof){return (bof->type == BOF_TYPE_STRING);}
+
+#endif
diff --git a/src/mode.c b/src/mode.c
new file mode 100644
index 0000000..5458cbe
--- /dev/null
+++ b/src/mode.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#include "config.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <string.h>
+#include <strings.h>
+#include <errno.h>
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "radeon_priv.h"
+
+const char *connector_status(drmModeConnector *connector)
+{
+    switch (connector->connection) {
+    case DRM_MODE_CONNECTED:
+        return "connected";
+    case DRM_MODE_DISCONNECTED:
+    default:
+        return "disconnected";
+    }
+    return "unknown";
+}
+
+int radeon_mode_configure(struct radeon *radeon)
+{
+    struct radeon_mode *mode = &radeon->mode;
+    drmModeRes *resources;
+    drmModeConnector *connector;
+    drmModeEncoder *encoder;
+    u32 connector_id;
+    int r;
+
+    r = drmSetMaster(radeon->fd);
+    if (r) {
+        fprintf(stderr, "Failed to set master\n");
+        perror(NULL);
+    }
+    mode->bo = NULL;
+    mode->fb_id = 0;
+    resources = drmModeGetResources(radeon->fd);
+    if (resources == NULL) {
+            fprintf(stderr, "Failed to get resources from card\n");
+            return -EINVAL;
+    }
+    /* Iterates through connector an pick first one with a valid mode */
+    printf("%d connectors\n", resources->count_connectors);
+    for (int i = 0; i < resources->count_connectors; i++) {
+        connector = drmModeGetConnector(radeon->fd, resources->connectors[i]);
+        if (connector == NULL) {
+            fprintf(stderr, "Could not get connector %i\n",
+                    resources->connectors[i]);
+            r = -EINVAL;
+            goto out;
+        }
+        printf("connector(%d) %s to encoder(%d)\n", connector->connector_id,
+               connector_status(connector), connector->encoder_id);
+        for (int j = 0; j < connector->count_modes; j++) {
+            if (connector->modes[j].type & DRM_MODE_TYPE_PREFERRED) {
+                memcpy(&mode->info, &connector->modes[j],
+                       sizeof(drmModeModeInfo));
+                mode->connector_id = connector->connector_id;
+                mode->encoder_id = connector->encoder_id;
+                drmModeFreeConnector(connector);
+                goto setmode;
+            }
+        }
+        drmModeFreeConnector(connector);
+    }
+    fprintf(stderr, "No modes found !\n");
+    r = -EINVAL;
+    goto out;
+setmode:
+    /* Find crtc id */
+    encoder = drmModeGetEncoder(radeon->fd, mode->encoder_id);
+    if (encoder == NULL) {
+        fprintf(stderr, "Could not get encoder %i\n", mode->encoder_id);
+        r = -EINVAL;
+        goto out;
+    }
+    mode->crtc_id = resources->crtcs[ffs(encoder->possible_crtcs)-1];
+    drmModeFreeEncoder(encoder);
+    /* Allocate buffer */
+    mode->bpp = 4;
+    mode->height = mode->info.vdisplay;
+    mode->pitch = mode->info.hdisplay * mode->bpp;
+    mode->size = mode->pitch * mode->info.vdisplay;
+    mode->bo = radeon_bo_open(radeon->bom, 0, mode->size, 0,
+                              RADEON_GEM_DOMAIN_VRAM, 0);
+    if (mode->bo == NULL) {
+        fprintf(stderr, "failed to create fb: %s\n", strerror(errno));
+        goto out;
+    }
+    r = drmModeAddFB(radeon->fd, mode->info.hdisplay, mode->info.vdisplay,
+                     32, 32, mode->pitch, mode->bo->handle, &mode->fb_id);
+    if (r) {
+        fprintf(stderr, "failed to add fb: %s  0x%08X\n", strerror(errno), mode->bo->handle);
+        goto out;
+    }
+    printf("Mode: %dx%d %dbpp on CRTC(%d) connector(%d)\n", mode->info.hdisplay,
+           mode->info.vdisplay, mode->bpp*8, mode->crtc_id,
+           mode->connector_id);
+    connector_id = mode->connector_id;
+    r = drmModeSetCrtc(radeon->fd, mode->crtc_id, mode->fb_id, 0, 0,
+                       &connector_id, 1, &mode->info);
+    if (r) {
+        fprintf(stderr, "failed to set mode: %s\n", strerror(errno));
+        goto out;
+    }
+    if (connector_id != mode->connector_id) {
+        fprintf(stderr, "Set mode on different connector %d, expected %d\n",
+                connector_id, mode->connector_id);
+    }
+out:
+    if (r && mode->fb_id) {
+        drmModeRmFB(radeon->fd, mode->fb_id);
+        mode->fb_id = 0;
+    }
+    if (r && mode->bo) {
+        mode->bo = radeon_bo_unref(mode->bo);
+    }
+    drmModeFreeResources(resources);
+    return r;
+}
+
+void radeon_mode_cleanup(struct radeon *radeon)
+{
+    if (radeon->mode.fb_id) {
+        drmModeRmFB(radeon->fd, radeon->mode.fb_id);
+        radeon->mode.fb_id = 0;
+    }
+    if (radeon->mode.bo) {
+        radeon_bo_unmap(radeon->mode.bo);
+        radeon->mode.bo = radeon_bo_unref(radeon->mode.bo);
+    }
+    drmDropMaster(radeon->fd);
+}
diff --git a/src/r600.h b/src/r600.h
new file mode 100644
index 0000000..177805a
--- /dev/null
+++ b/src/r600.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_H
+#define R600_H
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "xf86drm.h"
+#include "radeon_bo.h"
+#include "radeon_drm.h"
+#include "r600_winsys.h"
+
+#define R600_MAX_WORK	256
+
+struct r600_winsys;
+struct r600_atom;
+
+struct radeon_ib {
+	u32	*ptr;
+	u32	cpkts;
+	u32	length_dw;
+	u32	*relocs;
+	u32	crelocs;
+	u32	nrelocs;
+};
+
+typedef int (*r600_atom_create_t)(struct r600_winsys*, struct r600_atom*, void*);
+typedef int (*r600_atom_emit_t)(struct r600_winsys*, struct r600_atom*, void*, struct radeon_ib*);
+
+struct r600_atom {
+	int				refcount;
+	u32				type;
+	u32				id;
+	u32				nflushes;
+	u32				npkts;
+	u32				nbo;
+	u32				pkts[1024];
+	struct radeon_bo		*bo[32];
+	u32				flags[32];
+	void				*state;
+	r600_atom_emit_t		emit;
+};
+
+struct r600_atom_flush {
+	u32			flags;
+	struct radeon_bo	*bo;
+};
+
+struct r600_work {
+	struct r600_atom		*atoms[R600_BATCH_NATOMS];
+	struct r600_atom		*emit_atoms[R600_BATCH_NATOMS];
+	u32				nemit_atoms;
+	u32				nflush;
+	struct r600_atom_flush		flush[480];
+	u32				npkts;
+	struct r600_batch		drm;
+};
+
+struct r600_scheduler {
+	struct radeon_ib		*ib;
+	u32				npkts;
+	u32				nwork;
+	struct r600_work		work[R600_MAX_WORK];
+	u32				last_id[R600_BATCH_NATOMS];
+};
+
+struct r600_winsys {
+	int				fd;
+	struct radeon_bo		*bo[32];
+	u32				nbo;
+	struct r600_scheduler		scheduler;
+	unsigned			npipes;
+	unsigned			nbanks;
+	unsigned			group_bytes;
+	struct radeon_bo_manager	*bom;
+};
+
+extern void r600_atom_ref(struct r600_atom *atom);
+extern u32 radeon_ib_reloc(struct radeon_ib *ib, struct radeon_bo *bo, u32 d);
+extern int radeon_ib_get(struct r600_winsys *rdev, struct radeon_ib **ib);
+extern void radeon_ib_free(struct radeon_ib *ib);
+extern int radeon_ib_schedule(struct r600_winsys *rdev, struct radeon_ib *ib);
+extern int r600_atom_emit_default(struct r600_winsys *rdev, struct r600_atom *atom,
+					void *data, struct radeon_ib *ib);
+extern void r600_winsys_set_bo_list(struct r600_winsys *rdev, u32 nbo, struct radeon_bo **bo);
+extern struct radeon_bo *radeon_bo_lookup(struct r600_winsys *rdev, u32 handle);
+extern u64 crc_64(void *d, size_t len);
+extern int r600_winsys_init(struct r600_winsys *rw);
+extern void r600_winsys_destroy(struct r600_winsys *rw);
+/* R700 */
+extern void r700_scheduler_states_default(struct r600_winsys *rdev, struct r600_scheduler *scheduler);
+extern int r600_scheduler_init(struct r600_winsys *rw, struct r600_scheduler *scheduler);
+extern void r600_scheduler_destroy(struct r600_winsys *rw, struct r600_scheduler *scheduler);
+extern int r600_draw_cmd_size(struct r600_batch *batch);
+extern int r600_draw_cmd_emit(struct radeon_ib *ib, struct r600_batch *batch);
+extern void r600_memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size);
+
+static inline int radeon_ib_begin(struct radeon_ib *ib, u32 ndw)
+{
+	if ((ib->cpkts + ndw) > ib->length_dw)
+		return -ENOMEM;
+	return 0;
+}
+
+static inline int radeon_ib_copy(struct radeon_ib *ib, u32 *pkts, u32 ndw)
+{
+	if ((ib->cpkts + ndw) > ib->length_dw) {
+		fprintf(stderr, "IB FULL !\n");
+		return -ENOMEM;
+	}
+	memcpy(&ib->ptr[ib->cpkts], pkts, ndw * 4);
+	ib->cpkts += ndw;
+	return 0;
+}
+
+#endif
diff --git a/src/r600_atom.c b/src/r600_atom.c
new file mode 100644
index 0000000..cc92100
--- /dev/null
+++ b/src/r600_atom.c
@@ -0,0 +1,762 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "r600.h"
+#include "r600d.h"
+
+/*
+ * framebuffer
+ */
+int r600_framebuffer_emit(struct r600_winsys *rdev,
+				struct r600_atom *atom,
+				void *data,
+				struct radeon_ib *ib)
+{
+	struct r600_framebuffer *fb = atom->state;
+	int i, j;
+
+	for (i = 0, j = 0; i < (fb->ncb * 26); i += 26, j++) {
+		atom->pkts[i + 4] = radeon_ib_reloc(ib, atom->bo[j], fb->cb[i].placements[0] | fb->cb[i].placements[1]);
+		atom->pkts[i + 18] = radeon_ib_reloc(ib, atom->bo[j], fb->cb[i].placements[0] | fb->cb[i].placements[1]);
+		atom->pkts[i + 23] = radeon_ib_reloc(ib, atom->bo[j], fb->cb[i].placements[0] | fb->cb[i].placements[1]);
+	}
+	if (fb->db_handle) {
+		atom->pkts[i + 5] = radeon_ib_reloc(ib, atom->bo[j], fb->db_placements[0] | fb->db_placements[1]);
+	}
+	return radeon_ib_copy(ib, atom->pkts, atom->npkts);
+}
+
+int r600_framebuffer_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_framebuffer *fb;
+	u32 cb_target_mask, cb_shader_mask;
+	int i;
+
+	fb = malloc(sizeof(struct r600_framebuffer));
+	if (fb == NULL)
+		return -ENOMEM;
+	memcpy(fb, data, sizeof(struct r600_framebuffer));
+	atom->state = fb;
+	atom->nflushes = 1;
+	/* take a references on the bo */
+	for (i = 0, atom->nbo = 0; i < fb->ncb; i++, atom->nbo++) {
+		atom->bo[i] = radeon_bo_lookup(rdev, fb->cb[i].handle);
+		atom->flags[i] = 0x02000040;
+		if (atom->bo[i] == NULL) {
+			return -EINVAL;
+		}
+	}
+	if (fb->db_handle) {
+		atom->bo[atom->nbo] = radeon_bo_lookup(rdev, fb->db_handle);
+		atom->flags[atom->nbo] = 0x04004000;
+		if (atom->bo[atom->nbo] == NULL) {
+			return -EINVAL;
+		}
+		atom->nbo++;
+	}
+	for (i = 0, cb_target_mask = 0, cb_shader_mask = 0; i < fb->ncb; i++) {
+		cb_target_mask |= (fb->cb[i].cb_target_mask & 0xf) << (i * 4);
+		cb_shader_mask |= (fb->cb[i].cb_shader_mask & 0xf) << (i * 4);
+		/* CB_COLOR0_BASE */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000010 + i;
+		atom->pkts[atom->npkts++] = 0x00000000;
+		atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+		atom->pkts[atom->npkts++] = 0x00000000;
+		/* CB_COLOR0_SIZE */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000018 + i;
+		atom->pkts[atom->npkts++] =
+			S_028060_PITCH_TILE_MAX((fb->cb[i].stride >> 3) - 1) |
+			S_028060_SLICE_TILE_MAX(((fb->cb[i].stride * fb->cb[i].height) >> 6) - 1);
+		/* CB_COLOR0_VIEW */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000020 + i;
+		atom->pkts[atom->npkts++] = 0x00000000;
+		/* CB_COLOR0_INFO */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000028 + i;
+		atom->pkts[atom->npkts++] = fb->cb[i].color_info;
+		/* CB_COLOR0_TILE */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000030 + i;
+		atom->pkts[atom->npkts++] = 0x00000000;
+		atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+		atom->pkts[atom->npkts++] = 0x00000000;
+		/* CB_COLOR0_FRAG */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000038 + i;
+		atom->pkts[atom->npkts++] = 0x00000000;
+		atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+		atom->pkts[atom->npkts++] = 0x00000000;
+		/* CB_COLOR0_MASK */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000040 + i;
+		atom->pkts[atom->npkts++] = 0x00000000;
+	}
+	if (fb->db_handle) {
+		/* R_02800C_DB_DEPTH_BASE */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+		atom->pkts[atom->npkts++] = 0x00000003;
+		atom->pkts[atom->npkts++] = 0x00000000;
+		atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+		atom->pkts[atom->npkts++] = 0x00000000;
+	}
+	/* R_028000_DB_DEPTH_SIZE */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000000;
+	atom->pkts[atom->npkts++] = fb->db_depth_size;
+	atom->pkts[atom->npkts++] = fb->db_depth_view;
+	/* R_028010_DB_DEPTH_INFO */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000004;
+	atom->pkts[atom->npkts++] = fb->db_depth_info;
+	/* R_028D24_DB_HTILE_SURFACE */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000349;
+	atom->pkts[atom->npkts++] = fb->db_htile_surface;
+	/* R_028D34_DB_PREFETCH_LIMIT */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x0000034D;
+	atom->pkts[atom->npkts++] = fb->db_prefetch_limit;
+	/* PA_SC_GENERIC_SCISSOR_TL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000090;
+	atom->pkts[atom->npkts++] = 0x80000000;
+	atom->pkts[atom->npkts++] = S_028244_BR_X(fb->width) | S_028244_BR_Y(fb->height);
+	/* PA_SC_SCREEN_SCISSOR_TL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000000C;
+	atom->pkts[atom->npkts++] = 0x80000000;
+	atom->pkts[atom->npkts++] = S_028034_BR_X(fb->width) | S_028034_BR_Y(fb->height);
+	/* PA_SC_WINDOW_OFFSET */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000081;
+	atom->pkts[atom->npkts++] = 0x80000000;
+	atom->pkts[atom->npkts++] = S_028208_BR_X(fb->width) | S_028208_BR_Y(fb->height);
+	/* CB_TARGET_MASK */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000008E;
+	atom->pkts[atom->npkts++] = cb_target_mask;
+	atom->pkts[atom->npkts++] = cb_shader_mask;
+	return 0;
+}
+
+/*
+ * r600_cb_cntl
+ */
+int r600_cb_cntl_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_cb_cntl *cb_cntl;
+
+	cb_cntl = malloc(sizeof(struct r600_cb_cntl));
+	if (cb_cntl == NULL)
+		return -ENOMEM;
+	memcpy(cb_cntl, data, sizeof(struct r600_cb_cntl));
+	atom->state = cb_cntl;
+	/* CB_CLRCMP_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x0000030C;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clrcmp_control;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clrcmp_src;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clrcmp_dst;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clrcmp_msk;
+	/* CB_COLOR_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000202;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_color_control;
+	/* CB_CLEAR_RED */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x00000048;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clear_red;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clear_green;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clear_blue;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_clear_alpha;
+	/* CB_BLEND_RED */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x00000105;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_blend_red;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_blend_green;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_blend_blue;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_blend_alpha;
+	/* CB_FOG_RED */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 3);
+	atom->pkts[atom->npkts++] = 0x00000109;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_fog_red;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_fog_green;
+	atom->pkts[atom->npkts++] = cb_cntl->cb_fog_blue;
+	return 0;
+}
+
+/*
+ * rasterizer
+ */
+int r600_rasterizer_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_rasterizer *rasterizer;
+
+	rasterizer = malloc(sizeof(struct r600_rasterizer));
+	if (rasterizer == NULL)
+		return -ENOMEM;
+	memcpy(rasterizer, data, sizeof(struct r600_rasterizer));
+	atom->state = rasterizer;
+	/* PA_SC_MPASS_PS_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000292;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_mpass_ps_cntl;
+	/* PA_SC_LINE_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000300;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_line_cntl;
+	/* PA_SC_AA_CONFIG */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000301;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_aa_config;
+	/* PA_SC_AA_SAMPLE_LOCS_MCTX */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000307;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_aa_sample_locs_mctx;
+	/* PA_SC_AA_MASK */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000312;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_aa_mask;
+	/* PA_CL_CLIP_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000204;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_clip_cntl;
+	/* PA_CL_VS_OUT_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000207;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_vs_out_cntl;
+	/* PA_CL_NANINF_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000208;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_naninf_cntl;
+	/* PA_CL_GB_VERT_CLIP_ADJ */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x00000303;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_gb_vert_clip_adj;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_gb_vert_disc_adj;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_gb_horz_clip_adj;
+	atom->pkts[atom->npkts++] = rasterizer->pa_cl_gb_horz_disc_adj;
+	/* PA_SU_SC_MODE_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000205;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_sc_mode_cntl;
+	/* PA_SU_POINT_SIZE */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x00000280;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_point_size;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_point_minmax;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_line_cntl;
+	atom->pkts[atom->npkts++] = rasterizer->pa_sc_line_stipple;
+	/* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000037E;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_db_fmt_cntl;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_clamp;
+	/* PA_SU_POLY_OFFSET_FRONT_SCALE */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 4);
+	atom->pkts[atom->npkts++] = 0x00000380;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_front_scale;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_front_offset;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_back_scale;
+	atom->pkts[atom->npkts++] = rasterizer->pa_su_poly_offset_back_offset;
+	return 0;
+}
+
+/*
+ * viewport state
+ */
+int r600_viewport_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_viewport *vport;
+
+	vport = malloc(sizeof(struct r600_viewport));
+	if (vport == NULL)
+		return -ENOMEM;
+	memcpy(vport, data, sizeof(struct r600_viewport));
+	atom->state = vport;
+	/* PA_CL_VPORT_XSCALE_0 */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 6);
+	atom->pkts[atom->npkts++] = 0x0000010F;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_xscale_0;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_xoffset_0;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_yscale_0;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_yoffset_0;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_zscale_0;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vport_zoffset_0;
+	/* PA_CL_VTE_CNTL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000206;
+	atom->pkts[atom->npkts++] = vport->pa_cl_vte_cntl;
+	return 0;
+}
+
+/*
+ * scissor state
+ */
+int r600_scissor_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_scissor *scissor;
+
+	scissor = malloc(sizeof(struct r600_scissor));
+	if (scissor == NULL)
+		return -ENOMEM;
+	memcpy(scissor, data, sizeof(struct r600_scissor));
+	atom->state = scissor;
+	/* PA_SC_VPORT_SCISSOR_0_BR */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000094;
+	atom->pkts[atom->npkts++] = scissor->pa_sc_vport_scissor_0_tl;
+	atom->pkts[atom->npkts++] = scissor->pa_sc_vport_scissor_0_br;
+	return 0;
+}
+
+/*
+ * blend state
+ */
+int r600_blend_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_blend *blend;
+
+	blend = malloc(sizeof(struct r600_blend));
+	if (blend == NULL)
+		return -ENOMEM;
+	memcpy(blend, data, sizeof(struct r600_blend));
+	atom->state = blend;
+	/* CB_BLEND0_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 8);
+	atom->pkts[atom->npkts++] = 0x000001E0;
+	atom->pkts[atom->npkts++] = blend->cb_blend0_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend1_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend2_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend3_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend4_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend5_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend6_control;
+	atom->pkts[atom->npkts++] = blend->cb_blend7_control;
+	/* CB_BLEND_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000201;
+	atom->pkts[atom->npkts++] = blend->cb_blend_control;
+	return 0;
+}
+
+/*
+ * r600_constant
+ */
+int r600_constants_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_constants *constants;
+
+	constants = malloc(sizeof(struct r600_constants));
+	if (constants == NULL)
+		return -ENOMEM;
+	memcpy(constants, data, sizeof(struct r600_constants));
+	atom->state = constants;
+	if ((constants->nconstants & 0x3) || (constants->offset & 0x3)) {
+		fprintf(stderr, "invalid offset or number of constants (0x%08X %d)\n",
+			constants->offset, constants->nconstants);
+			return -EINVAL;
+	}
+	/* constants */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_ALU_CONST, constants->nconstants * 4);
+	atom->pkts[atom->npkts++] = constants->offset;
+	memcpy(&atom->pkts[atom->npkts],
+		(void*)(unsigned long)constants->constants,
+		constants->nconstants * 4 * 4);
+	atom->npkts += constants->nconstants * 4;
+	return 0;
+}
+
+
+/*
+ * depth, stencil, alpha control
+ */
+int r600_dsa_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_dsa *dsa;
+
+	dsa = malloc(sizeof(struct r600_dsa));
+	if (dsa == NULL)
+		return -ENOMEM;
+	memcpy(dsa, data, sizeof(struct r600_dsa));
+	atom->state = dsa;
+	/* DB_STENCIL_CLEAR */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000000A;
+	atom->pkts[atom->npkts++] = dsa->db_stencil_clear;
+	atom->pkts[atom->npkts++] = dsa->db_depth_clear;
+	/* DB_STENCILREFMASK */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000010C;
+	atom->pkts[atom->npkts++] = dsa->db_stencilrefmask;
+	atom->pkts[atom->npkts++] = dsa->db_stencilrefmask_bf;
+	/* DB_DEPTH_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000200;
+	atom->pkts[atom->npkts++] = dsa->db_depth_control;
+	/* DB_SHADER_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000203;
+	atom->pkts[atom->npkts++] = dsa->db_shader_control;
+	/* DB_RENDER_CONTROL */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000343;
+	atom->pkts[atom->npkts++] = dsa->db_render_control;
+	atom->pkts[atom->npkts++] = dsa->db_render_override;
+	/* DB_SRESULTS_COMPARE_STATE1 */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x0000034B;
+	atom->pkts[atom->npkts++] = dsa->db_sresults_compare_state1;
+	atom->pkts[atom->npkts++] = dsa->db_preload_control;
+	/* DB_ALPHA_TO_MASK */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000351;
+	atom->pkts[atom->npkts++] = dsa->db_alpha_to_mask;
+	return 0;
+}
+
+/*
+ * vexter shader
+ */
+int r600_vs_shader_emit(struct r600_winsys *rdev,
+			struct r600_atom *atom,
+			void *data,
+			struct radeon_ib *ib)
+{
+	int r;
+
+	atom->pkts[4] = radeon_ib_reloc(ib, atom->bo[0], RADEON_GEM_DOMAIN_GTT);
+	r = radeon_ib_copy(ib, atom->pkts, atom->npkts);
+	return r;
+}
+
+int r600_vs_shader_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_vs_shader *vs_shader;
+	int i, j;
+	u32 tmp;
+
+	vs_shader = malloc(sizeof(struct r600_vs_shader));
+	if (vs_shader == NULL)
+		return -ENOMEM;
+	memcpy(vs_shader, data, sizeof(struct r600_vs_shader));
+	atom->bo[0] = radeon_bo_lookup(rdev, vs_shader->handle);
+	atom->flags[0] = 0x08000000;
+	if (atom->bo[0] == NULL) {
+		return -EINVAL;
+	}
+	atom->nbo = 1;
+	atom->nflushes = 1;
+	atom->state = vs_shader;
+	/* SQ_PGM_START_VS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000216;
+	atom->pkts[atom->npkts++] = vs_shader->offset;
+	atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+	atom->pkts[atom->npkts++] = 0x00000000;
+	/* SQ_PGM_RESOURCES_VS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x0000021A;
+	atom->pkts[atom->npkts++] = vs_shader->sq_pgm_resources_vs;
+	/* SQ_PGM_CF_OFFSET_VS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000234;
+	atom->pkts[atom->npkts++] = 0;
+	/* SPI_VS_OUT_CONFIG */
+	tmp = S_0286C4_VS_EXPORT_COUNT(vs_shader->noutputs - 1);
+	if (vs_shader->fog_output_id < 32) {
+		tmp |= S_0286C4_VS_OUT_FOG_VEC_ADDR(vs_shader->fog_output_id);
+		tmp |= S_0286C4_VS_EXPORTS_FOG(1);
+	}
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x000001B1;
+	atom->pkts[atom->npkts++] = tmp;
+	/* SPI_VS_OUT_ID_* */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 10);
+	atom->pkts[atom->npkts++] = 0x00000185;
+	/* set unused field to 255 */
+	for (i = vs_shader->noutputs; i < 32; i++) {
+		vs_shader->output_semantic[i] = 255;
+	}
+	for (i = 0; i < 8; i++) {
+		atom->pkts[atom->npkts] = 0;
+		for (j = 0; j < 4; j++) {
+			atom->pkts[atom->npkts] |= vs_shader->output_semantic[(i*4)+j] << (j * 8);
+		}
+		atom->npkts++;
+	}
+	/* FIXME: why is their 10 vector if we only have 32 outputs ? */
+	atom->pkts[atom->npkts++] = 0xFFFFFFFF;
+	atom->pkts[atom->npkts++] = 0xFFFFFFFF;
+	return 0;
+}
+
+/*
+ * fragment shader
+ */
+int r600_fs_shader_emit(struct r600_winsys *rdev,
+			struct r600_atom *atom,
+			void *data,
+			struct radeon_ib *ib)
+{
+	atom->pkts[4] = radeon_ib_reloc(ib, atom->bo[0], RADEON_GEM_DOMAIN_GTT);
+	return radeon_ib_copy(ib, atom->pkts, atom->npkts);
+}
+
+int r600_fs_shader_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_fs_shader *fs_shader;
+	u32 ninputs;
+	int i;
+
+	fs_shader = malloc(sizeof(struct r600_fs_shader));
+	if (fs_shader == NULL)
+		return -ENOMEM;
+	memcpy(fs_shader, data, sizeof(struct r600_fs_shader));
+	atom->state = fs_shader;
+	atom->bo[0] = radeon_bo_lookup(rdev, fs_shader->handle);
+	atom->flags[0] = 0x08000000;
+	if (atom->bo[0] == NULL) {
+		return -EINVAL;
+	}
+	atom->nbo = 1;
+	atom->nflushes = 1;
+	/* SQ_PGM_START_PS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000210;
+	atom->pkts[atom->npkts++] = fs_shader->offset;
+	atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+	atom->pkts[atom->npkts++] = 0x00000000;
+	/* SQ_PGM_RESOURCES_PS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x00000214;
+	atom->pkts[atom->npkts++] = fs_shader->sq_pgm_resources_ps;
+	atom->pkts[atom->npkts++] = fs_shader->sq_pgm_exports_ps;
+	/* SQ_PGM_CF_OFFSET_PS */
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	atom->pkts[atom->npkts++] = 0x00000233;
+	atom->pkts[atom->npkts++] = 0;
+	/* setup pixel shader input */
+	ninputs = G_0286CC_NUM_INTERP(fs_shader->spi_ps_in_control_0) + 1;
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, ninputs);
+	atom->pkts[atom->npkts++] = 0x00000191;
+	for (i = 0; i < ninputs; i++) {
+		atom->pkts[atom->npkts++] = fs_shader->spi_ps_input_cntl[i];
+	}
+	atom->pkts[atom->npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	atom->pkts[atom->npkts++] = 0x000001B3;
+	atom->pkts[atom->npkts++] = fs_shader->spi_ps_in_control_0;
+	atom->pkts[atom->npkts++] = fs_shader->spi_ps_in_control_1;
+	return 0;
+}
+
+/*
+ * shader resource
+ */
+int r600_shader_resource_emit(struct r600_winsys *rdev,
+			struct r600_atom *atom,
+			void *data,
+			struct radeon_ib *ib)
+{
+	struct r600_shader_resource *shader_resource = atom->state;
+	int i;
+
+	for (i = 0; i < shader_resource->nresource; i++) {
+		atom->pkts[i * 11 + 10] = radeon_ib_reloc(ib, atom->bo[i], RADEON_GEM_DOMAIN_GTT);
+	}
+	return radeon_ib_copy(ib, atom->pkts, atom->npkts);
+}
+
+int r600_shader_resource_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data)
+{
+	struct r600_shader_resource *shader_resource;
+	int i;
+
+	shader_resource = malloc(sizeof(struct r600_shader_resource));
+	if (shader_resource == NULL)
+		return -ENOMEM;
+	memcpy(shader_resource, data, sizeof(struct r600_shader_resource));
+	atom->state = shader_resource;
+	for (i = 0, atom->nbo = 0; i < shader_resource->nresource; i++, atom->nbo++) {
+		atom->bo[i] = radeon_bo_lookup(rdev, shader_resource->resource[i].handle);
+		atom->flags[i] = 0x01000000;
+		if (atom->bo[i] == NULL)
+			return -EINVAL;
+	}
+	atom->nflushes = atom->nbo;
+	for (i = 0; i < shader_resource->nresource; i++) {
+		/* SET_RESOURCE */
+		atom->pkts[atom->npkts++] = PKT3(PKT3_SET_RESOURCE, 7);
+		atom->pkts[atom->npkts++] = (shader_resource->resource[i].resource_id + 160) * 7;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word0;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word1;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word2;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word3;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word4;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word5;
+		atom->pkts[atom->npkts++] = shader_resource->resource[i].sq_vtx_constant_word6;
+		atom->pkts[atom->npkts++] = PKT3(PKT3_NOP, 0);
+		atom->pkts[atom->npkts++] = 0x00000000;
+	}
+	return 0;
+}
+
+int r600_draw_cmd_size(struct r600_batch *batch)
+{
+	switch (G_0287F0_SOURCE_SELECT(batch->vgt_draw_initiator)) {
+	case 2:
+		return 10;
+	default:
+		return 0;
+	}
+}
+
+int r600_draw_cmd_emit(struct radeon_ib *ib, struct r600_batch *batch)
+{
+	u32 pkts[32], i = 0;
+
+	switch (G_0287F0_SOURCE_SELECT(batch->vgt_draw_initiator)) {
+	case 2:
+		pkts[i++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+		pkts[i++] = 0x00000256;
+		pkts[i++] = batch->vgt_primitive_type;
+		pkts[i++] = PKT3(PKT3_INDEX_TYPE, 0);
+		pkts[i++] = batch->vgt_dma_index_type;
+		pkts[i++] = PKT3(PKT3_NUM_INSTANCES, 0);
+		pkts[i++] = batch->vgt_dma_num_instances;
+		pkts[i++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+		pkts[i++] = batch->vgt_num_indices;
+		pkts[i++] = batch->vgt_draw_initiator;
+		return radeon_ib_copy(ib, pkts, i);
+	default:
+		return 0;
+	}
+}
+
+void *r600_atom_state(struct r600_atom *atom)
+{
+	return atom->state;
+}
+
+/*
+ * r600 atom core functions
+ */
+struct r600_atom_funcs {
+	u32				type;
+	u32				size;
+	r600_atom_create_t		create;
+	r600_atom_emit_t		emit;
+};
+
+static struct r600_atom_funcs _r600_atom_funcs[] = {
+	{0, 0, NULL, NULL},
+	{R600_ATOM_FRAMEBUFFER, sizeof(struct r600_framebuffer),
+		&r600_framebuffer_create, &r600_framebuffer_emit},
+	{R600_ATOM_RASTERIZER, sizeof(struct r600_rasterizer),
+		&r600_rasterizer_create, &r600_atom_emit_default},
+	{R600_ATOM_CB_CNTL, sizeof(struct r600_cb_cntl),
+		&r600_cb_cntl_create, &r600_atom_emit_default},
+	{R600_ATOM_VIEWPORT, sizeof(struct r600_viewport),
+		&r600_viewport_create, &r600_atom_emit_default},
+	{R600_ATOM_SCISSOR, sizeof(struct r600_scissor),
+		&r600_scissor_create, &r600_atom_emit_default},
+	{R600_ATOM_BLEND, sizeof(struct r600_blend),
+		&r600_blend_create, &r600_atom_emit_default},
+	{R600_ATOM_CONSTANTS, sizeof(struct r600_constants),
+		&r600_constants_create, &r600_atom_emit_default},
+	{R600_ATOM_DSA, sizeof(struct r600_dsa),
+		&r600_dsa_create, &r600_atom_emit_default},
+	{R600_ATOM_VS_SHADER, sizeof(struct r600_vs_shader),
+		&r600_vs_shader_create, &r600_vs_shader_emit},
+	{R600_ATOM_FS_SHADER, sizeof(struct r600_fs_shader),
+		&r600_fs_shader_create, &r600_fs_shader_emit},
+	{R600_ATOM_SHADER_RESOURCE, sizeof(struct r600_shader_resource),
+		&r600_shader_resource_create, &r600_shader_resource_emit},
+};
+
+struct r600_atom *r600_atom_create(struct r600_winsys *rdev, struct r600_request *rq)
+{
+	struct r600_atom *atom;
+	int r;
+
+	if (!rq->type || rq->type >= R600_BATCH_NATOMS) {
+		fprintf(stderr, "%s %d invalid atom type %d\n", __func__, __LINE__, rq->type);
+		return NULL;
+	}
+	if (_r600_atom_funcs[rq->type].type != rq->type) {
+		fprintf(stderr, "%s %d mismatch for type %d have %d\n",
+			__func__, __LINE__, _r600_atom_funcs[rq->type].type, rq->type);
+		return NULL;
+	}
+	r600_winsys_set_bo_list(rdev, rq->nbo, rq->bo);
+	/* create the atom */
+	atom = malloc(sizeof(struct r600_atom));
+	if (atom == NULL)
+		return NULL;
+	memset(atom, 0, sizeof(struct r600_atom));
+	atom->refcount = 1;
+	atom->emit = _r600_atom_funcs[rq->type].emit;
+	atom->nflushes = 0;
+	atom->id = crc_64(rq->data, _r600_atom_funcs[rq->type].size);
+	atom->type = rq->type;
+	r = _r600_atom_funcs[rq->type].create(rdev, atom, rq->data);
+	if (r) {
+		r600_atom_destroy(atom);
+		return NULL;
+	}
+	return atom;
+}
+
+int r600_atom_emit_default(struct r600_winsys *rdev, struct r600_atom *atom,
+				void *data, struct radeon_ib *ib)
+{
+	return radeon_ib_copy(ib, atom->pkts, atom->npkts);
+}
+
+void r600_atom_ref(struct r600_atom *atom)
+{
+	if (atom == NULL)
+		return;
+	atom->refcount++;
+}
+
+struct r600_atom *r600_atom_destroy(struct r600_atom *atom)
+{
+	int i;
+
+	if (atom == NULL)
+		return NULL;
+	if (--atom->refcount > 0)
+		return NULL;
+	for (i = 0; i < atom->nbo; i++) {
+		radeon_bo_unref(atom->bo[i]);
+	}
+	free(atom->state);
+	free(atom);
+	return NULL;
+}
diff --git a/src/r600_bof.c b/src/r600_bof.c
new file mode 100644
index 0000000..ffd0ebe
--- /dev/null
+++ b/src/r600_bof.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
diff --git a/src/r600_clear.c b/src/r600_clear.c
new file mode 100644
index 0000000..7cf86c2
--- /dev/null
+++ b/src/r600_clear.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "xf86drm.h"
+#include "radeon_drm.h"
+#include "radeon_bo.h"
+#include "r600_clear.h"
+#include "r600d.h"
+
+static u32 vsconstants[16] = {
+	0x3C03126F, 0x00000000, 0x00000000, 0xBF800000,
+	0x00000000, 0x3C03126F, 0x00000000, 0xBF800000,
+	0x00000000, 0x00000000, 0xBF800000, 0x00000000,
+	0x00000000, 0x00000000, 0x00000000, 0x3F800000,
+};
+
+static u32 vsshaders[64] = {
+    0x0000001C, 0x81000400, 0x00000005, 0x80000000,
+    0x00000007, 0xA04C0000, 0xC001A03C, 0x94000688,
+    0xC0024000, 0x94200688, 0x900000F8, 0x00A80C90,
+    0x00000000, 0x00000000, 0x00200001, 0x006C2810,
+    0x00A00401, 0x206C2800, 0x01200801, 0x406C2800,
+    0x81A00C01, 0x606C2800, 0x00202001, 0x006C2800,
+    0x00A02401, 0x206C2810, 0x01202801, 0x406C2800,
+    0x81A02C01, 0x606C2800, 0x00204001, 0x006C2800,
+    0x00A04401, 0x206C2800, 0x01204801, 0x406C2810,
+    0x81A04C01, 0x606C2800, 0x00206001, 0x006C2800,
+    0x00A06401, 0x206C2800, 0x01206801, 0x406C2800,
+    0x81A06C01, 0x606C2810, 0x00000002, 0x00940C90,
+    0x00000402, 0x20940C90, 0x00000802, 0x40940C90,
+    0x80000C02, 0x60940C90, 0x00000000, 0x00000000,
+    0x7C000000, 0x1C351001, 0x00080000, 0x0BEADEAF,
+    0x7C000100, 0x18ED1002, 0x00080000, 0x0BEADEAF,
+};
+
+static u32 fsshaders[20] = {
+    0x00000003, 0x80000000, 0x00000005, 0xA00C0000,
+    0xC0008000, 0x94200688, 0x900000F8, 0x00480C90,
+    0x00000000, 0x00000000, 0x00000000, 0x00340C90,
+    0x00000400, 0x20340C90, 0x00000800, 0x40340C90,
+    0x80000C00, 0x60340C90, 0x00000000, 0x00000000,
+};
+
+static float rvbo[32] = {
+    0.000000, 0.000000, -1.000000, 0.500000,
+    0.500000, 0.500000, 0.000000, 250.000000,
+    0.000000, -1.000000, 0.500000, 0.500000,
+    0.500000, 0.000000, 250.000000, 250.000000,
+    -1.000000, 0.500000, 0.500000, 0.500000,
+    0.000000, 0.000000, 250.000000, -1.000000,
+    0.500000, 0.500000, 0.500000, 0.000000,
+    0.000000, 0.000000, 0.000000, 0.000000,
+};
+
+int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
+			struct r600_clear_data *rclear, unsigned buffers,
+			const float *rgba, float depth, unsigned stencil)
+{
+	struct r600_scissor scissor;
+	struct r600_framebuffer *pfb;
+	struct r600_request rq;
+	int r;
+
+	if (fb == NULL)
+		return -1;
+	pfb = r600_atom_state(fb);
+	rclear->batch.scissor = r600_atom_destroy(rclear->batch.scissor);
+	rclear->batch.framebuffer = fb;
+	/* scissor */
+	scissor.pa_sc_vport_scissor_0_tl = 0x80000000;
+	scissor.pa_sc_vport_scissor_0_br = S_028244_BR_X(pfb->width) | S_028244_BR_Y(pfb->height);
+	rq.type = R600_ATOM_SCISSOR;
+	rq.data = &scissor;
+	rq.nbo = 0;
+	rclear->batch.scissor = r600_atom_create(rw, &rq);
+	/* queue batch */
+	rq.type = 0;
+	rq.data = &rclear->batch;
+	rq.nbo = 0;
+	r = r600_scheduler_queue(rw, &rq);
+	if (r)
+		return r;
+	r = r600_scheduler_flush(rw);
+	return r;
+}
+
+void r600_clear_destroy(struct r600_clear_data *rclear)
+{
+	rclear->batch.framebuffer = NULL;
+	rclear->batch.scissor = r600_atom_destroy(rclear->batch.scissor);
+	rclear->batch.rasterizer = r600_atom_destroy(rclear->batch.rasterizer);
+	rclear->batch.cb_cntl = r600_atom_destroy(rclear->batch.cb_cntl);
+	rclear->batch.viewport = r600_atom_destroy(rclear->batch.viewport);
+	rclear->batch.blend = r600_atom_destroy(rclear->batch.blend);
+	rclear->batch.vs_constants = r600_atom_destroy(rclear->batch.vs_constants);
+	rclear->batch.dsa = r600_atom_destroy(rclear->batch.dsa);
+	rclear->batch.vs_shader = r600_atom_destroy(rclear->batch.vs_shader);
+	rclear->batch.fs_shader = r600_atom_destroy(rclear->batch.fs_shader);
+}
+
+int r600_clear_init(struct r600_winsys *rw,
+			struct radeon_bo_manager *bom,
+			struct r600_clear_data *rclear)
+{
+	struct r600_blend blend;
+	struct r600_cb_cntl cb_cntl;
+	struct r600_dsa dsa;
+	struct r600_rasterizer rasterizer;
+	struct r600_viewport vport;
+	struct r600_constants vs_constants;
+	struct r600_vs_shader vs_shader;
+	struct r600_fs_shader fs_shader;
+	struct r600_shader_resource vs_resource;
+	struct r600_request rq;
+	struct radeon_bo *vbo = NULL;
+	struct radeon_bo *vs = NULL;
+	struct radeon_bo *fs = NULL;
+	int r = 0;
+
+	vbo = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (vbo == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(vbo, (u32*)rvbo, 32 * 4);
+	vs = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (vs == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(vs, (u32*)vsshaders, 64 * 4);
+	fs = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	if (fs == NULL) {
+		r = -ENOMEM;
+		goto out_err;
+	}
+	r600_memcpy_bo(fs, (u32*)fsshaders, 20 * 4);
+
+	/* rasterizer state */
+	rasterizer.pa_sc_mpass_ps_cntl = 0x00000000;
+	rasterizer.pa_sc_line_cntl = 0x00000400;
+	rasterizer.pa_sc_aa_config = 0x00000000;
+	rasterizer.pa_sc_aa_sample_locs_mctx = 0x00000000;
+	rasterizer.pa_sc_aa_mask = 0xffffffff;
+	rasterizer.pa_cl_clip_cntl = 0x00000000;
+	rasterizer.pa_cl_vs_out_cntl = 0x00000000;
+	rasterizer.pa_cl_naninf_cntl = 0x00000000;
+	rasterizer.pa_cl_gb_vert_clip_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_vert_disc_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_horz_clip_adj = 0x3f800000;
+	rasterizer.pa_cl_gb_horz_disc_adj = 0x3f800000;
+	rasterizer.pa_su_sc_mode_cntl = 0x00080000;
+	rasterizer.pa_su_point_size = 0x00080008;
+	rasterizer.pa_su_point_minmax = 0x80000000;
+	rasterizer.pa_su_line_cntl = 0x00000008;
+	rasterizer.pa_sc_line_stipple = 0x00000005;
+	rasterizer.pa_su_poly_offset_db_fmt_cntl = 0x00000000;
+	rasterizer.pa_su_poly_offset_clamp = 0x00000000;
+	rasterizer.pa_su_poly_offset_front_scale = 0x00000000;
+	rasterizer.pa_su_poly_offset_front_offset = 0x00000000;
+	rasterizer.pa_su_poly_offset_back_scale = 0x00000000;
+	rasterizer.pa_su_poly_offset_back_offset = 0x00000000;
+	rq.type = R600_ATOM_RASTERIZER;
+	rq.data = &rasterizer;
+	rq.nbo = 0;
+	rclear->batch.rasterizer = r600_atom_create(rw, &rq);
+	/* cb cntl */
+	cb_cntl.cb_clrcmp_control = 0x01000000;
+	cb_cntl.cb_clrcmp_src = 0x00000000;
+	cb_cntl.cb_clrcmp_dst = 0x000000ff;
+	cb_cntl.cb_clrcmp_msk = 0xffffffff;
+	cb_cntl.cb_color_control = 0x00cc0000;
+	cb_cntl.cb_clear_alpha = 0x00000000;
+	cb_cntl.cb_clear_blue = 0x00000000;
+	cb_cntl.cb_clear_green = 0x00000000;
+	cb_cntl.cb_clear_red = 0x00000000;
+	cb_cntl.cb_blend_alpha = 0x00000000;
+	cb_cntl.cb_blend_blue = 0x00000000;
+	cb_cntl.cb_blend_green = 0x00000000;
+	cb_cntl.cb_blend_red = 0x00000000;
+	cb_cntl.cb_fog_blue = 0x00000000;
+	cb_cntl.cb_fog_green = 0x00000000;
+	cb_cntl.cb_fog_red = 0x00000000;
+	rq.type = R600_ATOM_CB_CNTL;
+	rq.data = &cb_cntl;
+	rq.nbo = 0;
+	rclear->batch.cb_cntl = r600_atom_create(rw, &rq);
+	/* viewport */
+	vport.pa_cl_vte_cntl = 0x0000043f;
+	vport.pa_cl_vport_xscale_0 = 0x42fa0000;
+	vport.pa_cl_vport_xoffset_0 = 0x42fa0000;
+	vport.pa_cl_vport_yscale_0 = 0xc2fa0000;
+	vport.pa_cl_vport_yoffset_0 = 0x42fa0000;
+	vport.pa_cl_vport_zscale_0 = 0x3f000000;
+	vport.pa_cl_vport_zoffset_0 = 0x3f000000;
+	rq.type = R600_ATOM_VIEWPORT;
+	rq.data = &vport;
+	rq.nbo = 0;
+	rclear->batch.viewport = r600_atom_create(rw, &rq);
+	/* blend */
+	blend.cb_blend0_control = 0x00010001;
+	blend.cb_blend1_control = 0x00000000;
+	blend.cb_blend2_control = 0x00000000;
+	blend.cb_blend3_control = 0x00000000;
+	blend.cb_blend4_control = 0x00000000;
+	blend.cb_blend5_control = 0x00000000;
+	blend.cb_blend6_control = 0x00000000;
+	blend.cb_blend7_control = 0x00000000;
+	blend.cb_blend_control = 0x00010001;
+	rq.type = R600_ATOM_BLEND;
+	rq.data = &blend;
+	rq.nbo = 0;
+	rclear->batch.blend = r600_atom_create(rw, &rq);
+	/* ps constant */
+	rclear->batch.ps_constants = NULL;
+	/* vs constant */
+	vs_constants.nconstants = 4;
+	vs_constants.offset = 0x400;
+	memcpy(vs_constants.constants, vsconstants, vs_constants.nconstants * 4 * 4);
+	rq.type = R600_ATOM_CONSTANTS;
+	rq.data = &vs_constants;
+	rq.nbo = 0;
+	rclear->batch.vs_constants = r600_atom_create(rw, &rq);
+	/* depth stencil alpha */
+	dsa.db_stencil_clear = 0x00000000;
+	dsa.db_depth_clear = 0x3F800000;
+	dsa.db_stencilrefmask = 0xFFFFFF00;
+	dsa.db_stencilrefmask_bf = 0xFFFFFF00;
+	dsa.db_depth_control = 0x00700700;
+	dsa.db_shader_control = 0x00000210;
+	dsa.db_render_control = 0x00000060;
+	dsa.db_render_override = 0x0000002A;
+	dsa.db_alpha_to_mask = 0x0000AA00;
+	dsa.db_sresults_compare_state1 = 0x00000000;
+	dsa.db_preload_control = 0x00000000;
+	rq.type = R600_ATOM_DSA;
+	rq.data = &dsa;
+	rq.nbo = 0;
+	rclear->batch.dsa = r600_atom_create(rw, &rq);
+	/* vs_shader */
+	vs_shader.ninputs = 2;
+	vs_shader.input_semantic[0] = 1;
+	vs_shader.input_gpr[0] = 1;
+	vs_shader.input_semantic[1] = 2;
+	vs_shader.input_gpr[1] = 2;
+	vs_shader.noutputs = 1;
+	vs_shader.output_semantic[0] = 4;
+	vs_shader.sq_pgm_resources_vs = 0x00000006;
+	vs_shader.ndwords = 64;
+	vs_shader.handle = vs->handle;
+	vs_shader.offset = 0;
+	rq.bo[0] = vs;
+	rq.nbo = 1;
+	rq.type = R600_ATOM_VS_SHADER;
+	rq.data = &vs_shader;
+	rclear->batch.vs_shader = r600_atom_create(rw, &rq);
+	/* ps_shader */
+	fs_shader.spi_ps_input_cntl[0] = 0x00000804;
+	fs_shader.spi_ps_input_cntl[1] = 0x00000000;
+	fs_shader.spi_ps_in_control_0 = 0x10000001;
+	fs_shader.spi_ps_in_control_1 = 0x00000000;
+	fs_shader.sq_pgm_resources_ps = 0x00000003;
+	fs_shader.sq_pgm_exports_ps = 0x00000002;
+	fs_shader.ndwords = 20;
+	fs_shader.handle = fs->handle;
+	fs_shader.offset = 0;
+	rq.bo[0] = fs;
+	rq.nbo = 1;
+	rq.type = R600_ATOM_FS_SHADER;
+	rq.data = &fs_shader;
+	rclear->batch.fs_shader = r600_atom_create(rw, &rq);
+	/* inputs */
+	vs_resource.nresource = 2;
+	vs_resource.resource[0].handle = vbo->handle;
+	vs_resource.resource[0].resource_id = 0;
+	vs_resource.resource[0].sq_vtx_constant_word0 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word1 = vbo->size;
+	vs_resource.resource[0].sq_vtx_constant_word2 = 0x03001C00;
+	vs_resource.resource[0].sq_vtx_constant_word3 = 0x00000001;
+	vs_resource.resource[0].sq_vtx_constant_word4 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word5 = 0x00000000;
+	vs_resource.resource[0].sq_vtx_constant_word6 = 0xC0000000;
+	vs_resource.resource[1].handle = vbo->handle;
+	vs_resource.resource[1].resource_id = 1;
+	vs_resource.resource[1].sq_vtx_constant_word0 = 0x0000000C;
+	vs_resource.resource[1].sq_vtx_constant_word1 = vbo->size - 0xC;
+	vs_resource.resource[1].sq_vtx_constant_word2 = 0x02301C00;
+	vs_resource.resource[1].sq_vtx_constant_word3 = 0x00000001;
+	vs_resource.resource[1].sq_vtx_constant_word4 = 0x00000000;
+	vs_resource.resource[1].sq_vtx_constant_word5 = 0x00000000;
+	vs_resource.resource[1].sq_vtx_constant_word6 = 0xC0000000;
+	rq.bo[0] = vbo;
+	rq.bo[1] = vbo;
+	rq.nbo = 2;
+	rq.type = R600_ATOM_SHADER_RESOURCE;
+	rq.data = &vs_resource;
+	rclear->batch.vs_resource = r600_atom_create(rw, &rq);
+	rclear->batch.vgt_primitive_type = 5;
+	rclear->batch.vgt_dma_index_type = 0;
+	rclear->batch.vgt_dma_num_instances = 1;
+	rclear->batch.vgt_num_indices = 4;
+	rclear->batch.vgt_draw_initiator = 2;
+out_err:
+	radeon_bo_unref(vbo);
+	radeon_bo_unref(fs);
+	radeon_bo_unref(vs);
+	return r;
+}
diff --git a/src/r600_clear.h b/src/r600_clear.h
new file mode 100644
index 0000000..5566297
--- /dev/null
+++ b/src/r600_clear.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600_CLEAR_H
+#define R600_CLEAR_H
+
+#include "r600_winsys.h"
+
+struct r600_clear_data {
+	struct r600_batch	batch;
+};
+
+int r600_clear_queue(struct r600_winsys *rw, struct r600_atom *fb,
+			struct r600_clear_data *rclear, unsigned buffers,
+			const float *rgba, float depth, unsigned stencil);
+void r600_clear_destroy(struct r600_clear_data *rclear);
+int r600_clear_init(struct r600_winsys *rw,
+			struct radeon_bo_manager *bom,
+			struct r600_clear_data *rclear);
+
+#endif
diff --git a/src/r600_ctx.c b/src/r600_ctx.c
new file mode 100644
index 0000000..2b5b80f
--- /dev/null
+++ b/src/r600_ctx.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <jansson.h>
+#include "radeon_priv.h"
+#include "r600d.h"
+
+struct cs_packet3 {
+	unsigned		op;
+	char			name[64];
+	int (*parse)(struct radeon_ctx *ctx);
+};
+
+int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc)
+{
+	unsigned id, count, type, op;
+
+	id = ctx->next_id;
+	type = PKT_TYPE_G(ctx->pm4[id]);
+	count = PKT_COUNT_G(ctx->pm4[id]);
+	op = PKT3_IT_OPCODE_G(ctx->pm4[id]);
+	if (type != 3 || op != PKT3_NOP)
+		return -EINVAL;
+	*reloc = ctx->pm4[id + 1];
+	ctx->next_id += count + 2;
+	return 0;
+}
+
+static int r600_bof_ctx_new_draw(struct radeon_ctx *ctx)
+{
+	struct radeon_draw *draw;
+	unsigned i, j;
+	int r;
+
+	draw = ctx->cdraw;
+	if (draw->state[R600_DB] == NULL) {
+		draw->state[R600_DB] = radeon_state(ctx->radeon, R600_DB_TYPE, R600_DB);
+		if (draw->state[R600_DB] == NULL)
+			return -ENOMEM;
+	}
+	draw->state[R600_DRAW]->nbo = 1;
+	draw->state[R600_CB0]->nbo = 3;
+	draw->state[R600_DB]->nbo = 1;
+	draw->state[R600_VS_SHADER]->nbo = 2;
+	draw->state[R600_PS_SHADER]->nbo = 1;
+	if (draw->state[R600_DB]->bo[0] == NULL) {
+		draw->state[R600_DB]->bo[0] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
+		draw->state[R600_DB]->states[R600_DB__DB_DEPTH_SIZE] =
+			draw->state[R600_CB0]->states[R600_CB0__CB_COLOR0_SIZE];
+		draw->state[R600_DB]->states[R600_DB__DB_DEPTH_VIEW] =
+			draw->state[R600_CB0]->states[R600_CB0__CB_COLOR0_VIEW];
+		draw->state[R600_DB]->placement[0] = draw->state[R600_CB0]->placement[0];
+		draw->state[R600_DB]->placement[1] = draw->state[R600_CB0]->placement[1];
+	}
+	if (draw->state[R600_DRAW]->bo[0] == NULL) {
+		draw->state[R600_DRAW]->bo[0] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
+		draw->state[R600_DRAW]->placement[0] = draw->state[R600_CB0]->placement[0];
+		draw->state[R600_DRAW]->placement[1] = draw->state[R600_CB0]->placement[1];
+	}
+	if (draw->state[R600_CB0]->bo[1] == NULL) {
+		draw->state[R600_CB0]->bo[1] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
+		draw->state[R600_CB0]->placement[2] = draw->state[R600_CB0]->placement[0];
+		draw->state[R600_CB0]->placement[3] = draw->state[R600_CB0]->placement[1];
+	}
+	if (draw->state[R600_CB0]->bo[2] == NULL) {
+		draw->state[R600_CB0]->bo[2] = radeon_object_incref(draw->state[R600_CB0]->bo[0]);
+		draw->state[R600_CB0]->placement[4] = draw->state[R600_CB0]->placement[0];
+		draw->state[R600_CB0]->placement[5] = draw->state[R600_CB0]->placement[1];
+	}
+	if (draw->state[R600_VS_SHADER]->bo[1] == NULL) {
+		draw->state[R600_VS_SHADER]->bo[1] = radeon_object_incref(draw->state[R600_VS_SHADER]->bo[0]);
+		draw->state[R600_VS_SHADER]->placement[2] = draw->state[R600_VS_SHADER]->placement[0];
+		draw->state[R600_VS_SHADER]->placement[3] = draw->state[R600_VS_SHADER]->placement[1];
+	}
+	for (i = 0; i < draw->nstate; i++) {
+		if (draw->state[i]) {
+			for (j = 0; j < draw->state[i]->nbo; j++) {
+				if (draw->state[i]->bo[j] == NULL) {
+					fprintf(stderr, "%s missing bo %d for state %s\n",
+							__func__, j, ctx->radeon->type[i].name);
+					return -EINVAL;
+				}
+			}
+		}
+	}
+	draw = radeon_draw_duplicate(ctx->cdraw);
+	if (draw == NULL) {
+		return -ENOMEM;
+	}
+	draw->state[R600_DRAW] = radeon_state_decref(draw->state[R600_DRAW]);
+	r = radeon_ctx_set_draw_new(ctx, draw);
+	if (r) {
+		radeon_draw_decref(draw);
+		return r;
+	}
+	return 0;
+}
+
+static int cs_set_config_reg(struct radeon_ctx *ctx)
+{
+	unsigned i, count, base;
+	int r;
+
+	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
+	base = (ctx->pm4[ctx->id + 1] + 0x2000) << 2;
+	for (i = 0; i < count; i++, base += 4) {
+		r = radeon_ctx_draw_set_reg(ctx, base, ctx->pm4[ctx->id + 2 + i]);
+		if (r && r != -EINVAL)
+			return r;
+	}
+	return 0;
+}
+
+static int cs_set_context_reg(struct radeon_ctx *ctx)
+{
+	unsigned i, count, base;
+	int r;
+
+	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
+	base = (ctx->pm4[ctx->id + 1] + 0xA000) << 2;
+	for (i = 0; i < count; i++, base += 4) {
+		r = radeon_ctx_draw_set_reg(ctx, base, ctx->pm4[ctx->id + 2 + i]);
+		if (r && r != -EINVAL)
+			return r;
+	}
+	return 0;
+}
+
+static int cs_draw_auto(struct radeon_ctx *ctx)
+{
+	int r;
+
+	r = radeon_ctx_draw_set_reg(ctx, R_008970_VGT_NUM_INDICES, ctx->pm4[ctx->id + 1]);
+	if (r)
+		return r;
+	r = radeon_ctx_draw_set_reg(ctx, R_0287F0_VGT_DRAW_INITIATOR, ctx->pm4[ctx->id + 2]);
+	if (r)
+		return r;
+	return r600_bof_ctx_new_draw(ctx);
+}
+
+static int cs_set_alu_const(struct radeon_ctx *ctx)
+{
+	unsigned i, count, offset;
+	int r;
+
+	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
+	offset = (ctx->pm4[ctx->id + 1] << 2) + R_030000_SQ_ALU_CONSTANT0_0;
+	for (i = 0; i < count; i++, offset += 4) {
+		r = radeon_ctx_draw_set_reg(ctx, offset, ctx->pm4[ctx->id + 2 + i]);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
+static int cs_set_resource(struct radeon_ctx *ctx)
+{
+	unsigned i, count, offset, typeid, stateid, id, reloc;
+	struct radeon_state *state;
+	struct radeon_object *bo;
+	int r;
+
+	count = PKT_COUNT_G(ctx->pm4[ctx->id]);
+	offset = (ctx->pm4[ctx->id + 1] << 2) + R_038000_SQ_TEX_RESOURCE_WORD0_0;
+	for (i = 0; i < count; i++, offset += 4) {
+		r = radeon_ctx_draw_set_reg(ctx, offset, ctx->pm4[ctx->id + 2 + i]);
+		if (r)
+			return r;
+		radeon_reg_id(ctx->radeon, offset, &typeid, &stateid, &id);
+		state = ctx->cdraw->state[stateid];
+if (id == 2)
+	printf("resource %d %d WORD2 0x%08X 0x%08X\n", typeid, stateid, ctx->pm4[ctx->id + 2 + i], state->states[2]);
+		if (id == 6) {
+			switch (G_038018_TYPE(ctx->pm4[ctx->id + 2 + i])) {
+			case 2:
+				r = radeon_ctx_next_reloc(ctx, &reloc);
+				if (r)
+					return r;
+				bo = radeon_ctx_get_bo(ctx, reloc);
+				if (bo == NULL)
+					return -ENOMEM;
+				radeon_object_decref(state->bo[0]);
+				ctx->cdraw->state[stateid]->bo[0] = bo;
+				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[0]);
+				r = radeon_ctx_next_reloc(ctx, &reloc);
+				if (r)
+					return r;
+				bo = radeon_ctx_get_bo(ctx, reloc);
+				if (bo == NULL)
+					return -ENOMEM;
+				radeon_object_decref(state->bo[1]);
+				ctx->cdraw->state[stateid]->bo[1] = bo;
+				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[2]);
+				state->nbo = 2;
+				break;
+			case 3:
+				r = radeon_ctx_next_reloc(ctx, &reloc);
+				if (r)
+					return r;
+				bo = radeon_ctx_get_bo(ctx, reloc);
+				if (bo == NULL)
+					return -ENOMEM;
+				radeon_object_decref(state->bo[0]);
+				ctx->cdraw->state[stateid]->bo[0] = bo;
+				radeon_ctx_get_placement(ctx, reloc, &ctx->cdraw->state[stateid]->placement[0]);
+				state->nbo = 1;
+				break;
+			default:
+				ctx->cdraw->state[stateid] = radeon_state_decref(state);
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static int cs_index_type(struct radeon_ctx *ctx)
+{
+	return radeon_ctx_draw_set_reg(ctx, R_028A7C_VGT_DMA_INDEX_TYPE, ctx->pm4[ctx->id + 1]);
+}
+
+static int cs_num_instances(struct radeon_ctx *ctx)
+{
+	return radeon_ctx_draw_set_reg(ctx, R_028A88_VGT_DMA_NUM_INSTANCES, ctx->pm4[ctx->id + 1]);
+}
+
+static int cs_nop(struct radeon_ctx *ctx)
+{
+	return 0;
+}
+
+struct cs_packet3 r600_packet3[] = {
+	{0x10, "NOP", &cs_nop},
+	{0x17, "INDIRECT_BUFFER_END", NULL},
+	{0x20, "SET_PREDICATION", NULL},
+	{0x21, "REG_RMW", NULL},
+	{0x22, "COND_EXEC", NULL},
+	{0x23, "PRED_EXEC", NULL},
+	{0x24, "START_3D_CMDBUF", &cs_nop},
+	{0x27, "DRAW_INDEX_2", NULL},
+	{0x28, "CONTEXT_CONTROL", &cs_nop},
+	{0x29, "DRAW_INDEX_IMMD_BE", NULL},
+	{0x2A, "INDEX_TYPE", &cs_index_type},
+	{0x2B, "DRAW_INDEX", NULL},
+	{0x2D, "DRAW_INDEX_AUTO", &cs_draw_auto},
+	{0x2E, "DRAW_INDEX_IMMD", NULL},
+	{0x2F, "NUM_INSTANCES", &cs_num_instances},
+	{0x32, "INDIRECT_BUFFER", NULL},
+	{0x34, "STRMOUT_BUFFER_UPDATE", NULL},
+	{0x38, "INDIRECT_BUFFER_MP", NULL},
+	{0x39, "MEM_SEMAPHORE", NULL},
+	{0x3A, "MPEG_INDEX", NULL},
+	{0x3C, "WAIT_REG_MEM", NULL},
+	{0x3D, "MEM_WRITE", NULL},
+	{0x40, "CP_INTERRUPT", NULL},
+	{0x43, "SURFACE_SYNC", &cs_nop},
+	{0x44, "ME_INITIALIZE", NULL},
+	{0x45, "COND_WRITE", NULL},
+	{0x46, "EVENT_WRITE", &cs_nop},
+	{0x47, "EVENT_WRITE_EOP", NULL},
+	{0x57, "ONE_REG_WRITE", NULL},
+	{0x68, "SET_CONFIG_REG", &cs_set_config_reg},
+	{0x69, "SET_CONTEXT_REG", &cs_set_context_reg},
+	{0x6A, "SET_ALU_CONST", &cs_set_alu_const},
+	{0x6B, "SET_BOOL_CONST", NULL},
+	{0x6C, "SET_LOOP_CONST", NULL},
+	{0x6D, "SET_RESOURCE", &cs_set_resource},
+	{0x6E, "SET_SAMPLER", NULL},
+	{0x6F, "SET_CTL_CONST", &cs_nop},
+	{0x73, "SURFACE_BASE_UPDATE", &cs_nop},
+};
+
+static int cs_packet3_ctx(struct radeon_ctx *ctx, unsigned op)
+{
+	unsigned i;
+
+	for (i = 0; i < (sizeof(r600_packet3)/sizeof(r600_packet3[0])); i++) {
+		if (r600_packet3[i].op == op) {
+			if (r600_packet3[i].parse)
+				return r600_packet3[i].parse(ctx);
+		}
+	}
+	fprintf(stderr, "%s Unknown packet 3 0x%02X at %d\n",
+			__func__, op, ctx->id);
+	return 0;
+}
+
+int r600_ctx_draw(struct radeon_ctx *ctx)
+{
+	unsigned type, count, index, i, op;
+	int r;
+
+	ctx->id = 0;
+	do {
+		type = PKT_TYPE_G(ctx->pm4[ctx->id]);
+		count = PKT_COUNT_G(ctx->pm4[ctx->id]);
+		ctx->next_id = ctx->id + count + 2;
+		switch (type) {
+		case 2:
+			count = 0;
+			break;
+		case 0:
+			index = PKT0_BASE_INDEX_G(ctx->pm4[ctx->id]) << 2;
+			for (i = 0; i <= count; i++, index += 4) {
+				r = radeon_ctx_draw_set_reg(ctx, index, ctx->pm4[ctx->id + i + 1]);
+				if (r)
+					return r;
+			}
+			break;
+		case 3:
+			op = PKT3_IT_OPCODE_G(ctx->pm4[ctx->id]);
+			r = cs_packet3_ctx(ctx, op);
+			if (r) {
+				fprintf(stderr, "%s error parsing 0x%02X packet3\n", __func__, op);
+				return r;
+			}
+			break;
+		default:
+			fprintf(stderr, "(%s:%d) Unknown packet type %d at %d\n",
+					__func__, __LINE__, type, ctx->id);
+			return -EINVAL;
+		}
+		ctx->id = ctx->next_id;
+	} while (ctx->id < ctx->cpm4);
+	if (ctx->cdraw->state[R600_DRAW] == NULL) {
+		ctx->ndraw--;
+		ctx->draw[ctx->ndraw] = radeon_draw_decref(ctx->draw[ctx->ndraw]);
+		ctx->cdraw = ctx->draw[ctx->ndraw - 1];
+	}
+	return 0;
+}
+
+unsigned r600_format_bpe(unsigned format)
+{
+	switch (format) {
+	case V_0280A0_COLOR_8:
+	case V_0280A0_COLOR_4_4:
+	case V_0280A0_COLOR_3_3_2:
+		return 1;
+	case V_0280A0_COLOR_16:
+	case V_0280A0_COLOR_16_FLOAT:
+	case V_0280A0_COLOR_8_8:
+	case V_0280A0_COLOR_5_6_5:
+	case V_0280A0_COLOR_6_5_5:
+	case V_0280A0_COLOR_1_5_5_5:
+	case V_0280A0_COLOR_4_4_4_4:
+	case V_0280A0_COLOR_5_5_5_1:
+		return 2;
+	case V_0280A0_COLOR_32:
+	case V_0280A0_COLOR_32_FLOAT:
+	case V_0280A0_COLOR_16_16:
+	case V_0280A0_COLOR_16_16_FLOAT:
+	case V_0280A0_COLOR_8_24:
+	case V_0280A0_COLOR_8_24_FLOAT:
+	case V_0280A0_COLOR_24_8:
+	case V_0280A0_COLOR_24_8_FLOAT:
+	case V_0280A0_COLOR_10_11_11:
+	case V_0280A0_COLOR_10_11_11_FLOAT:
+	case V_0280A0_COLOR_11_11_10:
+	case V_0280A0_COLOR_11_11_10_FLOAT:
+	case V_0280A0_COLOR_2_10_10_10:
+	case V_0280A0_COLOR_8_8_8_8:
+	case V_0280A0_COLOR_10_10_10_2:
+	case V_0280A0_COLOR_X24_8_32_FLOAT:
+		return 4;
+	case V_0280A0_COLOR_32_32:
+	case V_0280A0_COLOR_32_32_FLOAT:
+	case V_0280A0_COLOR_16_16_16_16:
+	case V_0280A0_COLOR_16_16_16_16_FLOAT:
+		return 8;
+	case V_0280A0_COLOR_32_32_32_32:
+	case V_0280A0_COLOR_32_32_32_32_FLOAT:
+		return 16;
+	default:
+		return 0;
+	}
+}
+
+int r600_ctx_get_dst_surface(struct radeon_ctx *ctx, struct radeon_surface *dst)
+{
+	struct radeon_draw *draw = ctx->draw[0];
+	struct radeon_state *state;
+	unsigned tmp;
+
+	if (draw == NULL)
+		return -EINVAL;
+	state = draw->state[R600_CB0];
+	if (state == NULL || state->states == NULL)
+		return -EINVAL;
+	tmp = state->states[R600_CB0__CB_COLOR0_SIZE];
+	dst->pitch = (G_028060_PITCH_TILE_MAX(tmp) + 1) * 8;
+	dst->width = dst->pitch;
+	dst->height = (G_028060_SLICE_TILE_MAX(tmp) + 1) * 64;
+	dst->height = dst->height / dst->pitch;
+	tmp = state->states[R600_CB0__CB_COLOR0_INFO];
+	dst->bpe = r600_format_bpe(G_0280A0_FORMAT(tmp));
+	dst->bo = state->bo[0]->bo;
+	if ((dst->height * dst->pitch * dst->bpe) >= state->bo[0]->size) {
+		dst->height = state->bo[0]->size / (dst->pitch * dst->bpe);
+	}
+	return 0;
+}
diff --git a/src/r600_scheduler.c b/src/r600_scheduler.c
new file mode 100644
index 0000000..50cf50f
--- /dev/null
+++ b/src/r600_scheduler.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "r600.h"
+#include "r600d.h"
+
+/* state creation functions prototype */
+int r600_framebuffer_emit(struct r600_winsys *rdev, struct r600_atom *atom, void *data, struct radeon_ib *ib);
+int r600_framebuffer_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_cb_cntl_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_rasterizer_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_viewport_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_scissor_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_blend_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_constants_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_dsa_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_vs_shader_emit(struct r600_winsys *rdev, struct r600_atom *atom, void *data, struct radeon_ib *ib);
+int r600_vs_shader_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_fs_shader_emit(struct r600_winsys *rdev, struct r600_atom *atom, void *data, struct radeon_ib *ib);
+int r600_fs_shader_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+int r600_shader_resource_emit(struct r600_winsys *rdev, struct r600_atom *atom, void *data, struct radeon_ib *ib);
+int r600_shader_resource_create(struct r600_winsys *rdev, struct r600_atom *atom, void *data);
+
+/*
+ * helpers functions
+ */
+static void r600_emit_flush(struct r600_winsys *rdev,
+				struct radeon_ib *ib,
+				struct radeon_bo *bo,
+				u32 flags)
+{
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SURFACE_SYNC, 3);
+	ib->ptr[ib->cpkts++] = flags;
+	ib->ptr[ib->cpkts++] = bo->size >> 8;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x0000000A;
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_NOP, 0);
+	ib->ptr[ib->cpkts++] = radeon_ib_reloc(ib, bo, RADEON_GEM_DOMAIN_VRAM |
+						RADEON_GEM_DOMAIN_GTT);
+}
+
+void r600_atom_flush_add(struct r600_work *batch, struct radeon_bo *bo, u32 flags)
+{
+	int i;
+
+	for (i = 0; i < batch->nflush; i++) {
+		if (batch->flush[i].bo == bo) {
+			batch->flush[i].flags |= flags;
+			return;
+		}
+	}
+	batch->flush[batch->nflush].bo = bo;
+	batch->flush[batch->nflush].flags = flags;
+	batch->nflush++;
+}
+
+/*
+ * r600_scheduler
+ */
+static void r600_scheduler_clear(struct r600_winsys *rw, struct r600_scheduler *scheduler)
+{
+	int i, j;
+
+	for (i = 0; i < scheduler->nwork; i++) {
+		for (j = 0; j < R600_BATCH_NATOMS; j++) {
+			r600_atom_destroy(scheduler->work[i].atoms[j]);
+		}
+	}
+	scheduler->ib->crelocs = 0;
+	scheduler->ib->cpkts = 0;
+	scheduler->nwork = 0;
+	r700_scheduler_states_default(rw, scheduler);
+	scheduler->npkts = scheduler->ib->cpkts;
+}
+
+int r600_scheduler_flush(struct r600_winsys *rw)
+{
+	struct r600_scheduler *scheduler =  &rw->scheduler;
+	int r, i, j;
+
+	for (i = 0; i < scheduler->nwork; i++) {
+		for (j = 0; j < scheduler->work[i].nflush; j++) {
+			r600_emit_flush(rw, scheduler->ib,
+					scheduler->work[i].flush[j].bo,
+					scheduler->work[i].flush[j].flags);
+		}
+		for (j = 0; j < scheduler->work[i].nemit_atoms; j++) {
+			r = scheduler->work[i].emit_atoms[j]->emit(rw,
+							scheduler->work[i].emit_atoms[j],
+							&scheduler->work[i],
+							scheduler->ib);
+			if (r)
+				goto out_err;
+		}
+		r = r600_draw_cmd_emit(scheduler->ib, &scheduler->work[i].drm);
+		/* flush + wait until */
+		scheduler->ib->ptr[scheduler->ib->cpkts++] = PKT3(PKT3_EVENT_WRITE, 0);
+		scheduler->ib->ptr[scheduler->ib->cpkts++] = 0x00000016;
+		scheduler->ib->ptr[scheduler->ib->cpkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+		scheduler->ib->ptr[scheduler->ib->cpkts++] = 0x00000010;
+		scheduler->ib->ptr[scheduler->ib->cpkts++] = 0x00028000;
+	}
+	printf("ib %d dw\n", scheduler->ib->cpkts);
+	r = radeon_ib_schedule(rw, scheduler->ib);
+out_err:
+	/* FIXME helper function */
+	scheduler->ib->cpkts = 0;
+	scheduler->ib->crelocs = 0;
+	r600_scheduler_clear(rw, scheduler);
+	return r;
+}
+
+int r600_scheduler_queue(struct r600_winsys *rw, struct r600_request *rq)
+{
+	struct r600_batch *batch = rq->data;
+	struct r600_work *rbatch;
+	struct r600_scheduler *scheduler =  &rw->scheduler;
+	int r, i, j;
+
+	if (scheduler->nwork >= R600_MAX_WORK) {
+		r = r600_scheduler_flush(rw);
+		if (r)
+			return r;
+	}
+	rbatch = &scheduler->work[scheduler->nwork];
+	memset(rbatch, 0, sizeof(struct r600_work));
+	i = 0;
+	if (batch->blend == NULL || batch->cb_cntl == NULL ||
+		batch->rasterizer == NULL || batch->viewport == NULL ||
+		batch->framebuffer == NULL || batch->dsa == NULL ||
+		batch->vs_shader == NULL || batch->fs_shader == NULL ||
+		batch->scissor == NULL || batch->vs_resource == NULL) {
+		free(rbatch);
+		fprintf(stderr, "invalid batch\n");
+		return -EINVAL;
+	}
+	rbatch->atoms[i++] = batch->blend;
+	rbatch->atoms[i++] = batch->cb_cntl;
+	rbatch->atoms[i++] = batch->rasterizer;
+	rbatch->atoms[i++] = batch->viewport;
+	rbatch->atoms[i++] = batch->scissor;
+	rbatch->atoms[i++] = batch->vs_shader;
+	rbatch->atoms[i++] = batch->fs_shader;
+	rbatch->atoms[i++] = batch->dsa;
+	rbatch->atoms[i++] = batch->vs_constants;
+	rbatch->atoms[i++] = batch->ps_constants;
+	rbatch->atoms[i++] = batch->vs_resource;
+	rbatch->atoms[i++] = batch->framebuffer;
+	for (i = 0; i < R600_BATCH_NATOMS; i++) {
+		r600_atom_ref(rbatch->atoms[i]);
+	}
+	memcpy(&rbatch->drm, batch, sizeof(struct r600_batch));
+reprocess:
+	rbatch->nflush = 0;
+	rbatch->npkts = 0;
+	/* flush + wait until = 5dw */
+	rbatch->npkts += 5;
+	rbatch->npkts += r600_draw_cmd_size(batch);
+	for (i = 0; i < R600_BATCH_NATOMS; i++) {
+		if (rbatch->atoms[i]) {
+			for (j = 0; j < rbatch->atoms[i]->nbo; j++) {
+				r600_atom_flush_add(rbatch, rbatch->atoms[i]->bo[j],  rbatch->atoms[i]->flags[j]);
+			}
+			rbatch->emit_atoms[rbatch->nemit_atoms++] = rbatch->atoms[i];
+			rbatch->npkts += rbatch->atoms[i]->npkts;
+		}
+	}
+	/* add flush */
+	rbatch->npkts += rbatch->nflush * 7;
+	/* if batch is bigger than ib size it's an invalid one, this should
+	 * not happen
+	 */
+	if (rbatch->npkts > scheduler->ib->length_dw) {
+		fprintf(stderr, "single batch to big (%d) to fit into ib (%d)\n",
+			rbatch->npkts, scheduler->ib->length_dw);
+		goto out_err;
+	}
+	/* flush or not ? */
+	if (scheduler->npkts + rbatch->npkts > scheduler->ib->length_dw) {
+		r = r600_scheduler_flush(rw);
+		if (r)
+			goto out_err;
+		goto reprocess;
+	}
+	/* batch is queued */
+	for (i = 0; i < R600_BATCH_NATOMS; i++) {
+		if (rbatch->atoms[i]) {
+			scheduler->last_id[i] = rbatch->atoms[i]->id;
+		}
+	}
+	fprintf(stderr, "batch %d dw scheduler with %d dw\n", rbatch->npkts, scheduler->npkts);
+	scheduler->npkts += rbatch->npkts;
+	scheduler->nwork++;
+	return 0;
+out_err:
+	for (i = 0; i < R600_BATCH_NATOMS; i++) {
+		if (rbatch->atoms[i])
+			r600_atom_destroy(rbatch->atoms[i]);
+	}
+	free(rbatch);
+	return r;
+}
+
+int r600_scheduler_init(struct r600_winsys *rw, struct r600_scheduler *scheduler)
+{
+	int r;
+
+	memset(scheduler, 0 , sizeof(struct r600_scheduler));
+	r = radeon_ib_get(rw, &scheduler->ib);
+	if (r)
+		return r;
+	r600_scheduler_clear(rw, scheduler);
+	return 0;
+}
+
+void r600_scheduler_destroy(struct r600_winsys *rw, struct r600_scheduler *scheduler)
+{
+	r600_scheduler_clear(rw, scheduler);
+	radeon_ib_free(scheduler->ib);
+	scheduler->ib = NULL;
+}
diff --git a/src/r600_state.c b/src/r600_state.c
new file mode 100644
index 0000000..86f3fa8
--- /dev/null
+++ b/src/r600_state.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "radeon_priv.h"
+#include "r600d.h"
+
+static int r600_state_pm4_resource(struct radeon_state *state);
+static int r600_state_pm4_cb0(struct radeon_state *state);
+static int r600_state_pm4_vgt(struct radeon_state *state);
+static int r600_state_pm4_db(struct radeon_state *state);
+static int r600_state_pm4_shader(struct radeon_state *state);
+static int r600_state_pm4_draw(struct radeon_state *state);
+static int r600_state_pm4_config(struct radeon_state *state);
+static int r600_state_pm4_generic(struct radeon_state *state);
+static int r700_state_pm4_config(struct radeon_state *state);
+static int r700_state_pm4_cb0(struct radeon_state *state);
+static int r700_state_pm4_db(struct radeon_state *state);
+
+#include "r600_states.h"
+
+/*
+ * r600/r700 state functions
+ */
+static int r600_state_pm4_bytecode(struct radeon_state *state, unsigned offset, unsigned id, unsigned nreg)
+{
+	const struct radeon_register *regs = state->radeon->type[state->type].regs;
+	unsigned i;
+	int r;
+
+	if (!offset) {
+		fprintf(stderr, "%s invalid register for state %d %d\n",
+			__func__, state->type, id);
+		return -EINVAL;
+	}
+	if (offset >= R600_CONFIG_REG_OFFSET && offset < R600_CONFIG_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONFIG_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= R600_CONTEXT_REG_OFFSET && offset < R600_CONTEXT_REG_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONTEXT_REG, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_CONTEXT_REG_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		for (i = 0; i < nreg; i++) {
+			if (regs[id + i].need_reloc) {
+				state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+				r = radeon_state_reloc(state, state->cpm4, regs[id + i].bo_id);
+				if (r)
+					return r;
+				state->pm4[state->cpm4++] = state->bo[regs[id + i].bo_id]->handle;
+			}
+		}
+		return 0;
+	}
+	if (offset >= R600_ALU_CONST_OFFSET && offset < R600_ALU_CONST_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_ALU_CONST, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_ALU_CONST_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	if (offset >= R600_SAMPLER_OFFSET && offset < R600_SAMPLER_END) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_SET_SAMPLER, nreg);
+		state->pm4[state->cpm4++] = (offset - R600_SAMPLER_OFFSET) >> 2;
+		for (i = 0; i < nreg; i++) {
+			state->pm4[state->cpm4++] = state->states[id + i];
+		}
+		return 0;
+	}
+	fprintf(stderr, "%s unsupported offset 0x%08X\n", __func__, offset);
+	return -EINVAL;
+}
+
+static int r600_state_pm4_generic(struct radeon_state *state)
+{
+	struct radeon *radeon = state->radeon;
+	unsigned i, offset, nreg, type, coffset, loffset, soffset;
+	unsigned start;
+	int r;
+
+	if (!state->nstates)
+		return 0;
+	type = state->type;
+	soffset = (state->id - radeon->type[type].id) * radeon->type[type].stride;
+	offset = loffset = radeon->type[type].regs[0].offset + soffset;
+	start = 0;
+	for (i = 1, nreg = 1; i < state->nstates; i++) {
+		coffset = radeon->type[type].regs[i].offset + soffset;
+		if (coffset == (loffset + 4)) {
+			nreg++;
+			loffset = coffset;
+		} else {
+			r = r600_state_pm4_bytecode(state, offset, start, nreg);
+			if (r) {
+				fprintf(stderr, "%s invalid 0x%08X %d\n", __func__, start, nreg);
+				return r;
+			}
+			offset = loffset = coffset;
+			nreg = 1;
+			start = i;
+		}
+	}
+	return r600_state_pm4_bytecode(state, offset, start, nreg);
+}
+
+static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
+{
+	unsigned i, j, add, size;
+
+	state->nreloc = 0;
+	for (i = 0; i < state->nbo; i++) {
+		for (j = 0, add = 1; j < state->nreloc; j++) {
+			if (state->bo[state->reloc_bo_id[j]] == state->bo[i]) {
+				add = 0;
+				break;
+			}
+		}
+		if (add) {
+			state->reloc_bo_id[state->nreloc++] = i;
+		}
+	}
+	for (i = 0; i < state->nreloc; i++) {
+		size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8;
+		state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
+		state->pm4[state->cpm4++] = flags;
+		state->pm4[state->cpm4++] = size;
+		state->pm4[state->cpm4++] = 0x00000000;
+		state->pm4[state->cpm4++] = 0x0000000A;
+		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+		state->reloc_pm4_id[i] = state->cpm4;
+		state->pm4[state->cpm4++] = state->bo[state->reloc_bo_id[i]]->handle;
+	}
+}
+
+static int r600_state_pm4_cb0(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
+				S_0085F0_CB0_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
+	state->pm4[state->cpm4++] = 0x00000002;
+	return 0;
+}
+
+static int r700_state_pm4_cb0(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
+				S_0085F0_CB0_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	return 0;
+}
+
+static int r600_state_pm4_db(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0);
+	state->pm4[state->cpm4++] = 0x00000001;
+	return 0;
+}
+
+static int r700_state_pm4_db(struct radeon_state *state)
+{
+	int r;
+
+	r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
+				S_0085F0_DB_DEST_BASE_ENA(1));
+	r = r600_state_pm4_generic(state);
+	if (r)
+		return r;
+	return 0;
+}
+
+static int r600_state_pm4_config(struct radeon_state *state)
+{
+	state->pm4[state->cpm4++] = PKT3(PKT3_START_3D_CMDBUF, 0);
+	state->pm4[state->cpm4++] = 0x00000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = 0x00000016;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	state->pm4[state->cpm4++] = 0x00000010;
+	state->pm4[state->cpm4++] = 0x00028000;
+	return r600_state_pm4_generic(state);
+}
+
+static int r700_state_pm4_config(struct radeon_state *state)
+{
+	state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = 0x80000000;
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = 0x00000016;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	state->pm4[state->cpm4++] = 0x00000010;
+	state->pm4[state->cpm4++] = 0x00028000;
+	return r600_state_pm4_generic(state);
+}
+
+static int r600_state_pm4_shader(struct radeon_state *state)
+{
+	r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1));
+	return r600_state_pm4_generic(state);
+}
+
+static int r600_state_pm4_vgt(struct radeon_state *state)
+{
+	int r;
+
+	r = r600_state_pm4_bytecode(state, R_028400_VGT_MAX_VTX_INDX, R600_VGT__VGT_MAX_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_028404_VGT_MIN_VTX_INDX, R600_VGT__VGT_MIN_VTX_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_028408_VGT_INDX_OFFSET, R600_VGT__VGT_INDX_OFFSET, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX, 1);
+	if (r)
+		return r;
+	r = r600_state_pm4_bytecode(state, R_008958_VGT_PRIMITIVE_TYPE, R600_VGT__VGT_PRIMITIVE_TYPE, 1);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = PKT3(PKT3_INDEX_TYPE, 0);
+	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_INDEX_TYPE];
+	state->pm4[state->cpm4++] = PKT3(PKT3_NUM_INSTANCES, 0);
+	state->pm4[state->cpm4++] = state->states[R600_VGT__VGT_DMA_NUM_INSTANCES];
+	return 0;
+}
+
+static int r600_state_pm4_draw(struct radeon_state *state)
+{
+	state->pm4[state->cpm4++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1);
+	state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_NUM_INDICES];
+	state->pm4[state->cpm4++] = state->states[R600_DRAW__VGT_DRAW_INITIATOR];
+	state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 0);
+	state->pm4[state->cpm4++] = 0x00000016;
+	return 0;
+}
+
+static int r600_state_pm4_resource(struct radeon_state *state)
+{
+	u32 flags, type, nbo, offset, soffset;
+	int r;
+
+	soffset = (state->id - state->radeon->type[state->type].id) * state->radeon->type[state->type].stride;
+	type = G_038018_TYPE(state->states[6]);
+	switch (type) {
+	case 2:
+		flags = S_0085F0_TC_ACTION_ENA(1);
+		nbo = 2;
+		break;
+	case 3:
+		flags = S_0085F0_VC_ACTION_ENA(1);
+		nbo = 1;
+		break;
+	default:
+		return 0;
+	}
+	if (state->nbo != nbo) {
+		fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo);
+		return -EINVAL;
+	}
+	r600_state_pm4_with_flush(state, flags);
+	offset = state->radeon->type[state->type].regs[0].offset + soffset;
+	state->pm4[state->cpm4++] = PKT3(PKT3_SET_RESOURCE, 7);
+	state->pm4[state->cpm4++] = (offset - R_038000_SQ_TEX_RESOURCE_WORD0_0) >> 2;
+	state->pm4[state->cpm4++] = state->states[0];
+	state->pm4[state->cpm4++] = state->states[1];
+	state->pm4[state->cpm4++] = state->states[2];
+	state->pm4[state->cpm4++] = state->states[3];
+	state->pm4[state->cpm4++] = state->states[4];
+	state->pm4[state->cpm4++] = state->states[5];
+	state->pm4[state->cpm4++] = state->states[6];
+	state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+	r = radeon_state_reloc(state, state->cpm4, 0);
+	if (r)
+		return r;
+	state->pm4[state->cpm4++] = state->bo[0]->handle;
+	if (type == 2) {
+		state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
+		r = radeon_state_reloc(state, state->cpm4, 1);
+		if (r)
+			return r;
+		state->pm4[state->cpm4++] = state->bo[1]->handle;
+	}
+	return 0;
+}
+
+const static struct radeon_asic r600_asic = {
+	.ctx_draw = r600_ctx_draw,
+	.ctx_get_dst_surface = r600_ctx_get_dst_surface,
+	.ctx_next_reloc = r600_ctx_next_reloc,
+};
+
+int r600_init(struct radeon *radeon)
+{
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+		radeon->asic = &r600_asic;
+		radeon->ntype = R600_NTYPE;
+		radeon->nstate = R600_NSTATE;
+		radeon->type = R600_types;
+		break;
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		radeon->asic = &r600_asic;
+		radeon->ntype = R600_NTYPE;
+		radeon->nstate = R600_NSTATE;
+		radeon->type = R700_types;
+		break;
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		return -EINVAL;
+	}
+	return 0;
+}
diff --git a/src/r600_states.h b/src/r600_states.h
new file mode 100644
index 0000000..722b01d
--- /dev/null
+++ b/src/r600_states.h
@@ -0,0 +1,459 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef R600_STATES_H
+#define R600_STATES_H
+
+static const struct radeon_register R600_CONFIG_names[] = {
+	{0x00028A10, 0, 0, "VGT_OUTPUT_PATH_CNTL"},
+	{0x00028A14, 0, 0, "VGT_HOS_CNTL"},
+	{0x00028A18, 0, 0, "VGT_HOS_MAX_TESS_LEVEL"},
+	{0x00028A1C, 0, 0, "VGT_HOS_MIN_TESS_LEVEL"},
+	{0x00028A20, 0, 0, "VGT_HOS_REUSE_DEPTH"},
+	{0x00028A24, 0, 0, "VGT_GROUP_PRIM_TYPE"},
+	{0x00028A28, 0, 0, "VGT_GROUP_FIRST_DECR"},
+	{0x00028A2C, 0, 0, "VGT_GROUP_DECR"},
+	{0x00028A30, 0, 0, "VGT_GROUP_VECT_0_CNTL"},
+	{0x00028A34, 0, 0, "VGT_GROUP_VECT_1_CNTL"},
+	{0x00028A38, 0, 0, "VGT_GROUP_VECT_0_FMT_CNTL"},
+	{0x00028A3C, 0, 0, "VGT_GROUP_VECT_1_FMT_CNTL"},
+	{0x00028A40, 0, 0, "VGT_GS_MODE"},
+	{0x00028A4C, 0, 0, "PA_SC_MODE_CNTL"},
+	{0x00028A84, 0, 0, "VGT_PRIMITIVEID_EN"},
+	{0x00028A94, 0, 0, "VGT_MULTI_PRIM_IB_RESET_EN"},
+	{0x00028AA0, 0, 0, "VGT_INSTANCE_STEP_RATE_0"},
+	{0x00028AA4, 0, 0, "VGT_INSTANCE_STEP_RATE_1"},
+	{0x00028AB0, 0, 0, "VGT_STRMOUT_EN"},
+	{0x00028AB4, 0, 0, "VGT_REUSE_OFF"},
+	{0x00028AB8, 0, 0, "VGT_VTX_CNT_EN"},
+	{0x00028B20, 0, 0, "VGT_STRMOUT_BUFFER_EN"},
+	{0x00008C00, 0, 0, "SQ_CONFIG"},
+	{0x00008C04, 0, 0, "SQ_GPR_RESOURCE_MGMT_1"},
+	{0x00008C08, 0, 0, "SQ_GPR_RESOURCE_MGMT_2"},
+	{0x00008C0C, 0, 0, "SQ_THREAD_RESOURCE_MGMT"},
+	{0x00008C10, 0, 0, "SQ_STACK_RESOURCE_MGMT_1"},
+	{0x00008C14, 0, 0, "SQ_STACK_RESOURCE_MGMT_2"},
+	{0x00008D8C, 0, 0, "SQ_DYN_GPR_CNTL_PS_FLUSH_REQ"},
+	{0x00009508, 0, 0, "TA_CNTL_AUX"},
+	{0x00009714, 0, 0, "VC_ENHANCE"},
+	{0x00009830, 0, 0, "DB_DEBUG"},
+	{0x00009838, 0, 0, "DB_WATERMARKS"},
+	{0x00028350, 0, 0, "SX_MISC"},
+	{0x000286C8, 0, 0, "SPI_THREAD_GROUPING"},
+	{0x000287A0, 0, 0, "CB_SHADER_CONTROL"},
+	{0x000288A8, 0, 0, "SQ_ESGS_RING_ITEMSIZE"},
+	{0x000288AC, 0, 0, "SQ_GSVS_RING_ITEMSIZE"},
+	{0x000288B0, 0, 0, "SQ_ESTMP_RING_ITEMSIZE"},
+	{0x000288B4, 0, 0, "SQ_GSTMP_RING_ITEMSIZE"},
+	{0x000288B8, 0, 0, "SQ_VSTMP_RING_ITEMSIZE"},
+	{0x000288BC, 0, 0, "SQ_PSTMP_RING_ITEMSIZE"},
+	{0x000288C0, 0, 0, "SQ_FBUF_RING_ITEMSIZE"},
+	{0x000288C4, 0, 0, "SQ_REDUC_RING_ITEMSIZE"},
+	{0x000288C8, 0, 0, "SQ_GS_VERT_ITEMSIZE"},
+};
+
+static const struct radeon_register R600_CB_CNTL_names[] = {
+	{0x00028808, 0, 0, "CB_COLOR_CONTROL"},
+	{0x0002823C, 0, 0, "CB_SHADER_MASK"},
+	{0x00028238, 0, 0, "CB_TARGET_MASK"},
+	{0x00028C04, 0, 0, "PA_SC_AA_CONFIG"},
+	{0x00028C1C, 0, 0, "PA_SC_AA_SAMPLE_LOCS_MCTX"},
+	{0x00028C48, 0, 0, "PA_SC_AA_MASK"},
+	{0x00028C20, 0, 0, "PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX"},
+	{0x00028C30, 0, 0, "CB_CLRCMP_CONTROL"},
+	{0x00028C34, 0, 0, "CB_CLRCMP_SRC"},
+	{0x00028C38, 0, 0, "CB_CLRCMP_DST"},
+	{0x00028C3C, 0, 0, "CB_CLRCMP_MSK"},
+	{0x0002812C, 0, 0, "CB_CLEAR_ALPHA"},
+	{0x00028128, 0, 0, "CB_CLEAR_BLUE"},
+	{0x00028124, 0, 0, "CB_CLEAR_GREEN"},
+	{0x00028120, 0, 0, "CB_CLEAR_RED"},
+	{0x0002842C, 0, 0, "CB_FOG_BLUE"},
+	{0x00028428, 0, 0, "CB_FOG_GREEN"},
+	{0x00028424, 0, 0, "CB_FOG_RED"},
+};
+
+static const struct radeon_register R600_RASTERIZER_names[] = {
+	{0x000286D4, 0, 0, "SPI_INTERP_CONTROL_0"},
+	{0x00028A48, 0, 0, "PA_SC_MPASS_PS_CNTL"},
+	{0x00028C00, 0, 0, "PA_SC_LINE_CNTL"},
+	{0x00028810, 0, 0, "PA_CL_CLIP_CNTL"},
+	{0x0002881C, 0, 0, "PA_CL_VS_OUT_CNTL"},
+	{0x00028820, 0, 0, "PA_CL_NANINF_CNTL"},
+	{0x00028C0C, 0, 0, "PA_CL_GB_VERT_CLIP_ADJ"},
+	{0x00028C10, 0, 0, "PA_CL_GB_VERT_DISC_ADJ"},
+	{0x00028C14, 0, 0, "PA_CL_GB_HORZ_CLIP_ADJ"},
+	{0x00028C18, 0, 0, "PA_CL_GB_HORZ_DISC_ADJ"},
+	{0x00028814, 0, 0, "PA_SU_SC_MODE_CNTL"},
+	{0x00028A00, 0, 0, "PA_SU_POINT_SIZE"},
+	{0x00028A04, 0, 0, "PA_SU_POINT_MINMAX"},
+	{0x00028A08, 0, 0, "PA_SU_LINE_CNTL"},
+	{0x00028A0C, 0, 0, "PA_SC_LINE_STIPPLE"},
+	{0x00028DF8, 0, 0, "PA_SU_POLY_OFFSET_DB_FMT_CNTL"},
+	{0x00028DFC, 0, 0, "PA_SU_POLY_OFFSET_CLAMP"},
+	{0x00028E00, 0, 0, "PA_SU_POLY_OFFSET_FRONT_SCALE"},
+	{0x00028E04, 0, 0, "PA_SU_POLY_OFFSET_FRONT_OFFSET"},
+	{0x00028E08, 0, 0, "PA_SU_POLY_OFFSET_BACK_SCALE"},
+	{0x00028E0C, 0, 0, "PA_SU_POLY_OFFSET_BACK_OFFSET"},
+};
+
+static const struct radeon_register R600_VIEWPORT_names[] = {
+	{0x00028818, 0, 0, "PA_CL_VTE_CNTL"},
+	{0x0002843C, 0, 0, "PA_CL_VPORT_XSCALE_0"},
+	{0x00028444, 0, 0, "PA_CL_VPORT_YSCALE_0"},
+	{0x0002844C, 0, 0, "PA_CL_VPORT_ZSCALE_0"},
+	{0x00028440, 0, 0, "PA_CL_VPORT_XOFFSET_0"},
+	{0x00028448, 0, 0, "PA_CL_VPORT_YOFFSET_0"},
+	{0x00028450, 0, 0, "PA_CL_VPORT_ZOFFSET_0"},
+	{0x000282D0, 0, 0, "PA_SC_VPORT_ZMIN_0"},
+	{0x000282D4, 0, 0, "PA_SC_VPORT_ZMAX_0"},
+};
+
+static const struct radeon_register R600_SCISSOR_names[] = {
+	{0x00028250, 0, 0, "PA_SC_VPORT_SCISSOR_0_TL"},
+	{0x00028254, 0, 0, "PA_SC_VPORT_SCISSOR_0_BR"},
+	{0x00028030, 0, 0, "PA_SC_SCREEN_SCISSOR_TL"},
+	{0x00028034, 0, 0, "PA_SC_SCREEN_SCISSOR_BR"},
+	{0x00028200, 0, 0, "PA_SC_WINDOW_OFFSET"},
+	{0x00028204, 0, 0, "PA_SC_WINDOW_SCISSOR_TL"},
+	{0x00028208, 0, 0, "PA_SC_WINDOW_SCISSOR_BR"},
+	{0x0002820C, 0, 0, "PA_SC_CLIPRECT_RULE"},
+	{0x00028210, 0, 0, "PA_SC_CLIPRECT_0_TL"},
+	{0x00028214, 0, 0, "PA_SC_CLIPRECT_0_BR"},
+	{0x00028218, 0, 0, "PA_SC_CLIPRECT_1_TL"},
+	{0x0002821C, 0, 0, "PA_SC_CLIPRECT_1_BR"},
+	{0x00028220, 0, 0, "PA_SC_CLIPRECT_2_TL"},
+	{0x00028224, 0, 0, "PA_SC_CLIPRECT_2_BR"},
+	{0x00028228, 0, 0, "PA_SC_CLIPRECT_3_TL"},
+	{0x0002822C, 0, 0, "PA_SC_CLIPRECT_3_BR"},
+	{0x00028230, 0, 0, "PA_SC_EDGERULE"},
+	{0x00028240, 0, 0, "PA_SC_GENERIC_SCISSOR_TL"},
+	{0x00028244, 0, 0, "PA_SC_GENERIC_SCISSOR_BR"},
+};
+
+static const struct radeon_register R600_BLEND_names[] = {
+	{0x00028780, 0, 0, "CB_BLEND0_CONTROL"},
+	{0x00028784, 0, 0, "CB_BLEND1_CONTROL"},
+	{0x00028788, 0, 0, "CB_BLEND2_CONTROL"},
+	{0x0002878C, 0, 0, "CB_BLEND3_CONTROL"},
+	{0x00028790, 0, 0, "CB_BLEND4_CONTROL"},
+	{0x00028794, 0, 0, "CB_BLEND5_CONTROL"},
+	{0x00028798, 0, 0, "CB_BLEND6_CONTROL"},
+	{0x0002879C, 0, 0, "CB_BLEND7_CONTROL"},
+	{0x00028804, 0, 0, "CB_BLEND_CONTROL"},
+	{0x00028414, 0, 0, "CB_BLEND_RED"},
+	{0x00028418, 0, 0, "CB_BLEND_GREEN"},
+	{0x0002841C, 0, 0, "CB_BLEND_BLUE"},
+	{0x00028420, 0, 0, "CB_BLEND_ALPHA"},
+};
+
+static const struct radeon_register R600_DSA_names[] = {
+	{0x00028028, 0, 0, "DB_STENCIL_CLEAR"},
+	{0x0002802C, 0, 0, "DB_DEPTH_CLEAR"},
+	{0x00028430, 0, 0, "DB_STENCILREFMASK"},
+	{0x00028434, 0, 0, "DB_STENCILREFMASK_BF"},
+	{0x00028800, 0, 0, "DB_DEPTH_CONTROL"},
+	{0x0002880C, 0, 0, "DB_SHADER_CONTROL"},
+	{0x00028D0C, 0, 0, "DB_RENDER_CONTROL"},
+	{0x00028D10, 0, 0, "DB_RENDER_OVERRIDE"},
+	{0x00028D2C, 0, 0, "DB_SRESULTS_COMPARE_STATE1"},
+	{0x00028D30, 0, 0, "DB_PRELOAD_CONTROL"},
+	{0x00028D44, 0, 0, "DB_ALPHA_TO_MASK"},
+	{0x00028410, 0, 0, "SX_ALPHA_TEST_CONTROL"},
+	{0x00028438, 0, 0, "SX_ALPHA_REF"},
+	{0x000286DC, 0, 0, "SPI_FOG_CNTL"},
+	{0x000286E0, 0, 0, "SPI_FOG_FUNC_SCALE"},
+	{0x000286E4, 0, 0, "SPI_FOG_FUNC_BIAS"},
+};
+
+static const struct radeon_register R600_VS_SHADER_names[] = {
+	{0x00028868, 0, 0, "SQ_PGM_RESOURCES_VS"},
+	{0x000286C4, 0, 0, "SPI_VS_OUT_CONFIG"},
+	{0x00028858, 1, 0, "SQ_PGM_START_VS"},
+	{0x000288D0, 0, 0, "SQ_PGM_CF_OFFSET_VS"},
+	{0x00028894, 1, 1, "SQ_PGM_START_FS"},
+	{0x000288DC, 0, 0, "SQ_PGM_CF_OFFSET_FS"},
+	{0x000288A4, 0, 0, "SQ_PGM_RESOURCES_FS"},
+	{0x00028614, 0, 0, "SPI_VS_OUT_ID_0"},
+	{0x00028618, 0, 0, "SPI_VS_OUT_ID_1"},
+	{0x0002861C, 0, 0, "SPI_VS_OUT_ID_2"},
+	{0x00028620, 0, 0, "SPI_VS_OUT_ID_3"},
+	{0x00028624, 0, 0, "SPI_VS_OUT_ID_4"},
+	{0x00028628, 0, 0, "SPI_VS_OUT_ID_5"},
+	{0x0002862C, 0, 0, "SPI_VS_OUT_ID_6"},
+	{0x00028630, 0, 0, "SPI_VS_OUT_ID_7"},
+	{0x00028634, 0, 0, "SPI_VS_OUT_ID_8"},
+	{0x00028638, 0, 0, "SPI_VS_OUT_ID_9"},
+	{0x00028380, 0, 0, "SQ_VTX_SEMANTIC_0"},
+	{0x00028384, 0, 0, "SQ_VTX_SEMANTIC_1"},
+	{0x00028388, 0, 0, "SQ_VTX_SEMANTIC_2"},
+	{0x0002838C, 0, 0, "SQ_VTX_SEMANTIC_3"},
+	{0x00028390, 0, 0, "SQ_VTX_SEMANTIC_4"},
+	{0x00028394, 0, 0, "SQ_VTX_SEMANTIC_5"},
+	{0x00028398, 0, 0, "SQ_VTX_SEMANTIC_6"},
+	{0x0002839C, 0, 0, "SQ_VTX_SEMANTIC_7"},
+	{0x000283A0, 0, 0, "SQ_VTX_SEMANTIC_8"},
+	{0x000283A4, 0, 0, "SQ_VTX_SEMANTIC_9"},
+	{0x000283A8, 0, 0, "SQ_VTX_SEMANTIC_10"},
+	{0x000283AC, 0, 0, "SQ_VTX_SEMANTIC_11"},
+	{0x000283B0, 0, 0, "SQ_VTX_SEMANTIC_12"},
+	{0x000283B4, 0, 0, "SQ_VTX_SEMANTIC_13"},
+	{0x000283B8, 0, 0, "SQ_VTX_SEMANTIC_14"},
+	{0x000283BC, 0, 0, "SQ_VTX_SEMANTIC_15"},
+	{0x000283C0, 0, 0, "SQ_VTX_SEMANTIC_16"},
+	{0x000283C4, 0, 0, "SQ_VTX_SEMANTIC_17"},
+	{0x000283C8, 0, 0, "SQ_VTX_SEMANTIC_18"},
+	{0x000283CC, 0, 0, "SQ_VTX_SEMANTIC_19"},
+	{0x000283D0, 0, 0, "SQ_VTX_SEMANTIC_20"},
+	{0x000283D4, 0, 0, "SQ_VTX_SEMANTIC_21"},
+	{0x000283D8, 0, 0, "SQ_VTX_SEMANTIC_22"},
+	{0x000283DC, 0, 0, "SQ_VTX_SEMANTIC_23"},
+	{0x000283E0, 0, 0, "SQ_VTX_SEMANTIC_24"},
+	{0x000283E4, 0, 0, "SQ_VTX_SEMANTIC_25"},
+	{0x000283E8, 0, 0, "SQ_VTX_SEMANTIC_26"},
+	{0x000283EC, 0, 0, "SQ_VTX_SEMANTIC_27"},
+	{0x000283F0, 0, 0, "SQ_VTX_SEMANTIC_28"},
+	{0x000283F4, 0, 0, "SQ_VTX_SEMANTIC_29"},
+	{0x000283F8, 0, 0, "SQ_VTX_SEMANTIC_30"},
+	{0x000283FC, 0, 0, "SQ_VTX_SEMANTIC_31"},
+};
+
+static const struct radeon_register R600_PS_SHADER_names[] = {
+	{0x000286CC, 0, 0, "SPI_PS_IN_CONTROL_0"},
+	{0x000286D0, 0, 0, "SPI_PS_IN_CONTROL_1"},
+	{0x00028850, 0, 0, "SQ_PGM_RESOURCES_PS"},
+	{0x00028854, 0, 0, "SQ_PGM_EXPORTS_PS"},
+	{0x00028840, 1, 0, "SQ_PGM_START_PS"},
+	{0x000288CC, 0, 0, "SQ_PGM_CF_OFFSET_PS"},
+	{0x00028644, 0, 0, "SPI_PS_INPUT_CNTL_0"},
+	{0x00028648, 0, 0, "SPI_PS_INPUT_CNTL_1"},
+	{0x0002864C, 0, 0, "SPI_PS_INPUT_CNTL_2"},
+	{0x00028650, 0, 0, "SPI_PS_INPUT_CNTL_3"},
+	{0x00028654, 0, 0, "SPI_PS_INPUT_CNTL_4"},
+	{0x00028658, 0, 0, "SPI_PS_INPUT_CNTL_5"},
+	{0x0002865C, 0, 0, "SPI_PS_INPUT_CNTL_6"},
+	{0x00028660, 0, 0, "SPI_PS_INPUT_CNTL_7"},
+	{0x00028664, 0, 0, "SPI_PS_INPUT_CNTL_8"},
+	{0x00028668, 0, 0, "SPI_PS_INPUT_CNTL_9"},
+	{0x0002866C, 0, 0, "SPI_PS_INPUT_CNTL_10"},
+	{0x00028670, 0, 0, "SPI_PS_INPUT_CNTL_11"},
+	{0x00028674, 0, 0, "SPI_PS_INPUT_CNTL_12"},
+	{0x00028678, 0, 0, "SPI_PS_INPUT_CNTL_13"},
+	{0x0002867C, 0, 0, "SPI_PS_INPUT_CNTL_14"},
+	{0x00028680, 0, 0, "SPI_PS_INPUT_CNTL_15"},
+	{0x00028684, 0, 0, "SPI_PS_INPUT_CNTL_16"},
+	{0x00028688, 0, 0, "SPI_PS_INPUT_CNTL_17"},
+	{0x0002868C, 0, 0, "SPI_PS_INPUT_CNTL_18"},
+	{0x00028690, 0, 0, "SPI_PS_INPUT_CNTL_19"},
+	{0x00028694, 0, 0, "SPI_PS_INPUT_CNTL_20"},
+	{0x00028698, 0, 0, "SPI_PS_INPUT_CNTL_21"},
+	{0x0002869C, 0, 0, "SPI_PS_INPUT_CNTL_22"},
+	{0x000286A0, 0, 0, "SPI_PS_INPUT_CNTL_23"},
+	{0x000286A4, 0, 0, "SPI_PS_INPUT_CNTL_24"},
+	{0x000286A8, 0, 0, "SPI_PS_INPUT_CNTL_25"},
+	{0x000286AC, 0, 0, "SPI_PS_INPUT_CNTL_26"},
+	{0x000286B0, 0, 0, "SPI_PS_INPUT_CNTL_27"},
+	{0x000286B4, 0, 0, "SPI_PS_INPUT_CNTL_28"},
+	{0x000286B8, 0, 0, "SPI_PS_INPUT_CNTL_29"},
+	{0x000286BC, 0, 0, "SPI_PS_INPUT_CNTL_30"},
+	{0x000286C0, 0, 0, "SPI_PS_INPUT_CNTL_31"},
+	{0x000286D8, 0, 0, "SPI_INPUT_Z"},
+};
+
+static const struct radeon_register R600_PS_CONSTANT_names[] = {
+	{0x00030000, 0, 0, "SQ_ALU_CONSTANT0_0"},
+	{0x00030004, 0, 0, "SQ_ALU_CONSTANT1_0"},
+	{0x00030008, 0, 0, "SQ_ALU_CONSTANT2_0"},
+	{0x0003000C, 0, 0, "SQ_ALU_CONSTANT3_0"},
+};
+
+static const struct radeon_register R600_VS_CONSTANT_names[] = {
+	{0x00031000, 0, 0, "SQ_ALU_CONSTANT0_256"},
+	{0x00031004, 0, 0, "SQ_ALU_CONSTANT1_256"},
+	{0x00031008, 0, 0, "SQ_ALU_CONSTANT2_256"},
+	{0x0003100C, 0, 0, "SQ_ALU_CONSTANT3_256"},
+};
+
+static const struct radeon_register R600_PS_RESOURCE_names[] = {
+	{0x00038000, 0, 0, "RESOURCE0_WORD0"},
+	{0x00038004, 0, 0, "RESOURCE0_WORD1"},
+	{0x00038008, 0, 0, "RESOURCE0_WORD2"},
+	{0x0003800C, 0, 0, "RESOURCE0_WORD3"},
+	{0x00038010, 0, 0, "RESOURCE0_WORD4"},
+	{0x00038014, 0, 0, "RESOURCE0_WORD5"},
+	{0x00038018, 0, 0, "RESOURCE0_WORD6"},
+};
+
+static const struct radeon_register R600_VS_RESOURCE_names[] = {
+	{0x00039180, 0, 0, "RESOURCE160_WORD0"},
+	{0x00039184, 0, 0, "RESOURCE160_WORD1"},
+	{0x00039188, 0, 0, "RESOURCE160_WORD2"},
+	{0x0003918C, 0, 0, "RESOURCE160_WORD3"},
+	{0x00039190, 0, 0, "RESOURCE160_WORD4"},
+	{0x00039194, 0, 0, "RESOURCE160_WORD5"},
+	{0x00039198, 0, 0, "RESOURCE160_WORD6"},
+};
+
+static const struct radeon_register R600_FS_RESOURCE_names[] = {
+	{0x0003A300, 0, 0, "RESOURCE320_WORD0"},
+	{0x0003A304, 0, 0, "RESOURCE320_WORD1"},
+	{0x0003A308, 0, 0, "RESOURCE320_WORD2"},
+	{0x0003A30C, 0, 0, "RESOURCE320_WORD3"},
+	{0x0003A310, 0, 0, "RESOURCE320_WORD4"},
+	{0x0003A314, 0, 0, "RESOURCE320_WORD5"},
+	{0x0003A318, 0, 0, "RESOURCE320_WORD6"},
+};
+
+static const struct radeon_register R600_GS_RESOURCE_names[] = {
+	{0x0003A4C0, 0, 0, "RESOURCE336_WORD0"},
+	{0x0003A4C4, 0, 0, "RESOURCE336_WORD1"},
+	{0x0003A4C8, 0, 0, "RESOURCE336_WORD2"},
+	{0x0003A4CC, 0, 0, "RESOURCE336_WORD3"},
+	{0x0003A4D0, 0, 0, "RESOURCE336_WORD4"},
+	{0x0003A4D4, 0, 0, "RESOURCE336_WORD5"},
+	{0x0003A4D8, 0, 0, "RESOURCE336_WORD6"},
+};
+
+static const struct radeon_register R600_PS_SAMPLER_names[] = {
+	{0x0003C000, 0, 0, "SQ_TEX_SAMPLER_WORD0_0"},
+	{0x0003C004, 0, 0, "SQ_TEX_SAMPLER_WORD1_0"},
+	{0x0003C008, 0, 0, "SQ_TEX_SAMPLER_WORD2_0"},
+};
+
+static const struct radeon_register R600_VS_SAMPLER_names[] = {
+	{0x0003C0D8, 0, 0, "SQ_TEX_SAMPLER_WORD0_18"},
+	{0x0003C0DC, 0, 0, "SQ_TEX_SAMPLER_WORD1_18"},
+	{0x0003C0E0, 0, 0, "SQ_TEX_SAMPLER_WORD2_18"},
+};
+
+static const struct radeon_register R600_GS_SAMPLER_names[] = {
+	{0x0003C1B0, 0, 0, "SQ_TEX_SAMPLER_WORD0_36"},
+	{0x0003C1B4, 0, 0, "SQ_TEX_SAMPLER_WORD1_36"},
+	{0x0003C1B8, 0, 0, "SQ_TEX_SAMPLER_WORD2_36"},
+};
+
+static const struct radeon_register R600_PS_SAMPLER_BORDER_names[] = {
+	{0x0000A400, 0, 0, "TD_PS_SAMPLER0_BORDER_RED"},
+	{0x0000A404, 0, 0, "TD_PS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A408, 0, 0, "TD_PS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A40C, 0, 0, "TD_PS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_VS_SAMPLER_BORDER_names[] = {
+	{0x0000A600, 0, 0, "TD_VS_SAMPLER0_BORDER_RED"},
+	{0x0000A604, 0, 0, "TD_VS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A608, 0, 0, "TD_VS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A60C, 0, 0, "TD_VS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_GS_SAMPLER_BORDER_names[] = {
+	{0x0000A800, 0, 0, "TD_GS_SAMPLER0_BORDER_RED"},
+	{0x0000A804, 0, 0, "TD_GS_SAMPLER0_BORDER_GREEN"},
+	{0x0000A808, 0, 0, "TD_GS_SAMPLER0_BORDER_BLUE"},
+	{0x0000A80C, 0, 0, "TD_GS_SAMPLER0_BORDER_ALPHA"},
+};
+
+static const struct radeon_register R600_CB0_names[] = {
+	{0x000280A0, 0, 0, "CB_COLOR0_INFO"},
+	{0x00028060, 0, 0, "CB_COLOR0_SIZE"},
+	{0x00028080, 0, 0, "CB_COLOR0_VIEW"},
+	{0x00028100, 0, 0, "CB_COLOR0_MASK"},
+	{0x00028040, 1, 0, "CB_COLOR0_BASE"},
+	{0x000280E0, 1, 1, "CB_COLOR0_FRAG"},
+	{0x000280C0, 1, 2, "CB_COLOR0_TILE"},
+};
+
+static const struct radeon_register R600_DB_names[] = {
+	{0x0002800C, 1, 0, "DB_DEPTH_BASE"},
+	{0x00028000, 0, 0, "DB_DEPTH_SIZE"},
+	{0x00028004, 0, 0, "DB_DEPTH_VIEW"},
+	{0x00028010, 0, 0, "DB_DEPTH_INFO"},
+	{0x00028D24, 0, 0, "DB_HTILE_SURFACE"},
+	{0x00028D34, 0, 0, "DB_PREFETCH_LIMIT"},
+};
+
+static const struct radeon_register R600_VGT_names[] = {
+	{0x00008958, 0, 0, "VGT_PRIMITIVE_TYPE"},
+	{0x00028400, 0, 0, "VGT_MAX_VTX_INDX"},
+	{0x00028404, 0, 0, "VGT_MIN_VTX_INDX"},
+	{0x00028408, 0, 0, "VGT_INDX_OFFSET"},
+	{0x00028A88, 0, 0, "VGT_DMA_NUM_INSTANCES"},
+	{0x00028A7C, 0, 0, "VGT_DMA_INDEX_TYPE"},
+	{0x0002840C, 0, 0, "VGT_MULTI_PRIM_IB_RESET_INDX"},
+};
+
+static const struct radeon_register R600_DRAW_names[] = {
+	{0x00008970, 0, 0, "VGT_NUM_INDICES"},
+	{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
+};
+
+static struct radeon_type R600_types[] = {
+	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 45, r600_state_pm4_config, R600_CONFIG_names},
+	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
+	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
+	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
+	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
+	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
+	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
+	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
+	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
+	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
+	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
+	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
+	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
+	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
+	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
+	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
+	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
+	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
+	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
+	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
+	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
+	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r600_state_pm4_cb0, R600_CB0_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 7, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 2, r600_state_pm4_draw, R600_DRAW_names},
+};
+
+static struct radeon_type R700_types[] = {
+	{ 128,    0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 45, r700_state_pm4_config, R600_CONFIG_names},
+	{ 128,    1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
+	{ 128,    2, 0x00000000, 0x00000000, 0x0000, 0, "R600_RASTERIZER", 21, r600_state_pm4_generic, R600_RASTERIZER_names},
+	{ 128,    3, 0x00000000, 0x00000000, 0x0000, 0, "R600_VIEWPORT", 9, r600_state_pm4_generic, R600_VIEWPORT_names},
+	{ 128,    4, 0x00000000, 0x00000000, 0x0000, 0, "R600_SCISSOR", 19, r600_state_pm4_generic, R600_SCISSOR_names},
+	{ 128,    5, 0x00000000, 0x00000000, 0x0000, 0, "R600_BLEND", 13, r600_state_pm4_generic, R600_BLEND_names},
+	{ 128,    6, 0x00000000, 0x00000000, 0x0000, 0, "R600_DSA", 16, r600_state_pm4_generic, R600_DSA_names},
+	{ 128,    7, 0x00000000, 0x00000000, 0x0000, 0, "R600_VS_SHADER", 49, r600_state_pm4_shader, R600_VS_SHADER_names},
+	{ 128,    8, 0x00000000, 0x00000000, 0x0000, 0, "R600_PS_SHADER", 39, r600_state_pm4_shader, R600_PS_SHADER_names},
+	{ 128,    9, 0x00030000, 0x00031000, 0x0010, 0, "R600_PS_CONSTANT", 4, r600_state_pm4_generic, R600_PS_CONSTANT_names},
+	{ 128,  265, 0x00031000, 0x00032000, 0x0010, 0, "R600_VS_CONSTANT", 4, r600_state_pm4_generic, R600_VS_CONSTANT_names},
+	{ 128,  521, 0x00038000, 0x00039180, 0x001C, 0, "R600_PS_RESOURCE", 7, r600_state_pm4_resource, R600_PS_RESOURCE_names},
+	{ 128,  681, 0x00039180, 0x0003A300, 0x001C, 0, "R600_VS_RESOURCE", 7, r600_state_pm4_resource, R600_VS_RESOURCE_names},
+	{ 128,  841, 0x00039180, 0x0003A300, 0x001C, 0, "R600_FS_RESOURCE", 7, r600_state_pm4_resource, R600_FS_RESOURCE_names},
+	{ 128, 1001, 0x00039180, 0x0003A300, 0x001C, 0, "R600_GS_RESOURCE", 7, r600_state_pm4_resource, R600_GS_RESOURCE_names},
+	{ 128, 1161, 0x0003C000, 0x0003C0D8, 0x000C, 0, "R600_PS_SAMPLER", 3, r600_state_pm4_generic, R600_PS_SAMPLER_names},
+	{ 128, 1179, 0x0003C0D8, 0x0003C1B0, 0x000C, 0, "R600_VS_SAMPLER", 3, r600_state_pm4_generic, R600_VS_SAMPLER_names},
+	{ 128, 1197, 0x0003C1B0, 0x0003C288, 0x000C, 0, "R600_GS_SAMPLER", 3, r600_state_pm4_generic, R600_GS_SAMPLER_names},
+	{ 128, 1215, 0x0000A400, 0x0000A520, 0x0010, 0, "R600_PS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_PS_SAMPLER_BORDER_names},
+	{ 128, 1233, 0x0000A600, 0x0000A720, 0x0010, 0, "R600_VS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_VS_SAMPLER_BORDER_names},
+	{ 128, 1251, 0x0000A800, 0x0000A920, 0x0010, 0, "R600_GS_SAMPLER_BORDER", 4, r600_state_pm4_generic, R600_GS_SAMPLER_BORDER_names},
+	{ 128, 1269, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB0", 7, r700_state_pm4_cb0, R600_CB0_names},
+	{ 128, 1270, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
+	{ 128, 1271, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 7, r600_state_pm4_vgt, R600_VGT_names},
+	{ 128, 1272, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 2, r600_state_pm4_draw, R600_DRAW_names},
+};
+
+#endif
diff --git a/src/r600d.h b/src/r600d.h
new file mode 100644
index 0000000..ddc4948
--- /dev/null
+++ b/src/r600d.h
@@ -0,0 +1,2120 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef R600D_H
+#define R600D_H
+
+#define R600_CONFIG_REG_OFFSET                 0X00008000
+#define R600_CONFIG_REG_END                    0X0000AC00
+#define R600_CONTEXT_REG_OFFSET                0X00028000
+#define R600_CONTEXT_REG_END                   0X00029000
+#define R600_ALU_CONST_OFFSET                  0X00030000
+#define R600_ALU_CONST_END                     0X00032000
+#define R600_RESOURCE_OFFSET                   0X00038000
+#define R600_RESOURCE_END                      0X0003C000
+#define R600_SAMPLER_OFFSET                    0X0003C000
+#define R600_SAMPLER_END                       0X0003CFF0
+#define R600_CTL_CONST_OFFSET                  0X0003CFF0
+#define R600_CTL_CONST_END                     0X0003E200
+#define R600_LOOP_CONST_OFFSET                 0X0003E200
+#define R600_LOOP_CONST_END                    0X0003E380
+#define R600_BOOL_CONST_OFFSET                 0X0003E380
+#define R600_BOOL_CONST_END                    0X00040000
+
+#define PKT3_NOP                               0x10
+#define PKT3_INDIRECT_BUFFER_END               0x17
+#define PKT3_SET_PREDICATION                   0x20
+#define PKT3_REG_RMW                           0x21
+#define PKT3_COND_EXEC                         0x22
+#define PKT3_PRED_EXEC                         0x23
+#define PKT3_START_3D_CMDBUF                   0x24
+#define PKT3_DRAW_INDEX_2                      0x27
+#define PKT3_CONTEXT_CONTROL                   0x28
+#define PKT3_DRAW_INDEX_IMMD_BE                0x29
+#define PKT3_INDEX_TYPE                        0x2A
+#define PKT3_DRAW_INDEX                        0x2B
+#define PKT3_DRAW_INDEX_AUTO                   0x2D
+#define PKT3_DRAW_INDEX_IMMD                   0x2E
+#define PKT3_NUM_INSTANCES                     0x2F
+#define PKT3_STRMOUT_BUFFER_UPDATE             0x34
+#define PKT3_INDIRECT_BUFFER_MP                0x38
+#define PKT3_MEM_SEMAPHORE                     0x39
+#define PKT3_MPEG_INDEX                        0x3A
+#define PKT3_WAIT_REG_MEM                      0x3C
+#define PKT3_MEM_WRITE                         0x3D
+#define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_CP_INTERRUPT                      0x40
+#define PKT3_SURFACE_SYNC                      0x43
+#define PKT3_ME_INITIALIZE                     0x44
+#define PKT3_COND_WRITE                        0x45
+#define PKT3_EVENT_WRITE                       0x46
+#define PKT3_EVENT_WRITE_EOP                   0x47
+#define PKT3_ONE_REG_WRITE                     0x57
+#define PKT3_SET_CONFIG_REG                    0x68
+#define PKT3_SET_CONTEXT_REG                   0x69
+#define PKT3_SET_ALU_CONST                     0x6A
+#define PKT3_SET_BOOL_CONST                    0x6B
+#define PKT3_SET_LOOP_CONST                    0x6C
+#define PKT3_SET_RESOURCE                      0x6D
+#define PKT3_SET_SAMPLER                       0x6E
+#define PKT3_SET_CTL_CONST                     0x6F
+#define PKT3_SURFACE_BASE_UPDATE               0x73
+
+#define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
+#define PKT_TYPE_G(x)                   (((x) >> 30) & 0x3)
+#define PKT_TYPE_C                      0x3FFFFFFF
+#define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
+#define PKT_COUNT_G(x)                  (((x) >> 16) & 0x3FFF)
+#define PKT_COUNT_C                     0xC000FFFF
+#define PKT0_BASE_INDEX_S(x)            (((x) & 0xFFFF) << 0)
+#define PKT0_BASE_INDEX_G(x)            (((x) >> 0) & 0xFFFF)
+#define PKT0_BASE_INDEX_C               0xFFFF0000
+#define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
+#define PKT3_IT_OPCODE_G(x)             (((x) >> 8) & 0xFF)
+#define PKT3_IT_OPCODE_C                0xFFFF00FF
+#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
+#define PKT3(op, count) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count))
+
+/* Registers */
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define   S_0280A0_ENDIAN(x)                           (((x) & 0x3) << 0)
+#define   G_0280A0_ENDIAN(x)                           (((x) >> 0) & 0x3)
+#define   C_0280A0_ENDIAN                              0xFFFFFFFC
+#define   S_0280A0_FORMAT(x)                           (((x) & 0x3F) << 2)
+#define   G_0280A0_FORMAT(x)                           (((x) >> 2) & 0x3F)
+#define   C_0280A0_FORMAT                              0xFFFFFF03
+#define     V_0280A0_COLOR_INVALID                     0x00000000
+#define     V_0280A0_COLOR_8                           0x00000001
+#define     V_0280A0_COLOR_4_4                         0x00000002
+#define     V_0280A0_COLOR_3_3_2                       0x00000003
+#define     V_0280A0_COLOR_16                          0x00000005
+#define     V_0280A0_COLOR_16_FLOAT                    0x00000006
+#define     V_0280A0_COLOR_8_8                         0x00000007
+#define     V_0280A0_COLOR_5_6_5                       0x00000008
+#define     V_0280A0_COLOR_6_5_5                       0x00000009
+#define     V_0280A0_COLOR_1_5_5_5                     0x0000000A
+#define     V_0280A0_COLOR_4_4_4_4                     0x0000000B
+#define     V_0280A0_COLOR_5_5_5_1                     0x0000000C
+#define     V_0280A0_COLOR_32                          0x0000000D
+#define     V_0280A0_COLOR_32_FLOAT                    0x0000000E
+#define     V_0280A0_COLOR_16_16                       0x0000000F
+#define     V_0280A0_COLOR_16_16_FLOAT                 0x00000010
+#define     V_0280A0_COLOR_8_24                        0x00000011
+#define     V_0280A0_COLOR_8_24_FLOAT                  0x00000012
+#define     V_0280A0_COLOR_24_8                        0x00000013
+#define     V_0280A0_COLOR_24_8_FLOAT                  0x00000014
+#define     V_0280A0_COLOR_10_11_11                    0x00000015
+#define     V_0280A0_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_0280A0_COLOR_11_11_10                    0x00000017
+#define     V_0280A0_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_0280A0_COLOR_2_10_10_10                  0x00000019
+#define     V_0280A0_COLOR_8_8_8_8                     0x0000001A
+#define     V_0280A0_COLOR_10_10_10_2                  0x0000001B
+#define     V_0280A0_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_0280A0_COLOR_32_32                       0x0000001D
+#define     V_0280A0_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_0280A0_COLOR_16_16_16_16                 0x0000001F
+#define     V_0280A0_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_0280A0_COLOR_32_32_32_32                 0x00000022
+#define     V_0280A0_COLOR_32_32_32_32_FLOAT           0x00000023
+#define   S_0280A0_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
+#define   G_0280A0_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
+#define   C_0280A0_ARRAY_MODE                          0xFFFFF0FF
+#define     V_0280A0_ARRAY_LINEAR_GENERAL              0x00000000
+#define     V_0280A0_ARRAY_LINEAR_ALIGNED              0x00000001
+#define     V_0280A0_ARRAY_1D_TILED_THIN1              0x00000002
+#define     V_0280A0_ARRAY_2D_TILED_THIN1              0x00000004
+#define   S_0280A0_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
+#define   G_0280A0_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
+#define   C_0280A0_NUMBER_TYPE                         0xFFFF8FFF
+#define   S_0280A0_READ_SIZE(x)                        (((x) & 0x1) << 15)
+#define   G_0280A0_READ_SIZE(x)                        (((x) >> 15) & 0x1)
+#define   C_0280A0_READ_SIZE                           0xFFFF7FFF
+#define   S_0280A0_COMP_SWAP(x)                        (((x) & 0x3) << 16)
+#define   G_0280A0_COMP_SWAP(x)                        (((x) >> 16) & 0x3)
+#define   C_0280A0_COMP_SWAP                           0xFFFCFFFF
+#define   S_0280A0_TILE_MODE(x)                        (((x) & 0x3) << 18)
+#define   G_0280A0_TILE_MODE(x)                        (((x) >> 18) & 0x3)
+#define   C_0280A0_TILE_MODE                           0xFFF3FFFF
+#define   S_0280A0_BLEND_CLAMP(x)                      (((x) & 0x1) << 20)
+#define   G_0280A0_BLEND_CLAMP(x)                      (((x) >> 20) & 0x1)
+#define   C_0280A0_BLEND_CLAMP                         0xFFEFFFFF
+#define   S_0280A0_CLEAR_COLOR(x)                      (((x) & 0x1) << 21)
+#define   G_0280A0_CLEAR_COLOR(x)                      (((x) >> 21) & 0x1)
+#define   C_0280A0_CLEAR_COLOR                         0xFFDFFFFF
+#define   S_0280A0_BLEND_BYPASS(x)                     (((x) & 0x1) << 22)
+#define   G_0280A0_BLEND_BYPASS(x)                     (((x) >> 22) & 0x1)
+#define   C_0280A0_BLEND_BYPASS                        0xFFBFFFFF
+#define   S_0280A0_BLEND_FLOAT32(x)                    (((x) & 0x1) << 23)
+#define   G_0280A0_BLEND_FLOAT32(x)                    (((x) >> 23) & 0x1)
+#define   C_0280A0_BLEND_FLOAT32                       0xFF7FFFFF
+#define   S_0280A0_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 24)
+#define   G_0280A0_SIMPLE_FLOAT(x)                     (((x) >> 24) & 0x1)
+#define   C_0280A0_SIMPLE_FLOAT                        0xFEFFFFFF
+#define   S_0280A0_ROUND_MODE(x)                       (((x) & 0x1) << 25)
+#define   G_0280A0_ROUND_MODE(x)                       (((x) >> 25) & 0x1)
+#define   C_0280A0_ROUND_MODE                          0xFDFFFFFF
+#define   S_0280A0_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_0280A0_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_0280A0_TILE_COMPACT                        0xFBFFFFFF
+#define   S_0280A0_SOURCE_FORMAT(x)                    (((x) & 0x1) << 27)
+#define   G_0280A0_SOURCE_FORMAT(x)                    (((x) >> 27) & 0x1)
+#define   C_0280A0_SOURCE_FORMAT                       0xF7FFFFFF
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
+#define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
+#define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
+#define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
+#define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
+#define   C_028800_Z_ENABLE                            0xFFFFFFFD
+#define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
+#define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
+#define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
+#define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
+#define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
+#define   C_028800_ZFUNC                               0xFFFFFF8F
+#define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
+#define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
+#define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
+#define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
+#define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
+#define   C_028800_STENCILFUNC                         0xFFFFF8FF
+#define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
+#define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
+#define   C_028800_STENCILFAIL                         0xFFFFC7FF
+#define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
+#define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
+#define   C_028800_STENCILZPASS                        0xFFFE3FFF
+#define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
+#define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
+#define   C_028800_STENCILZFAIL                        0xFFF1FFFF
+#define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
+#define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
+#define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
+#define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
+#define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
+#define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
+#define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
+#define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
+#define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
+#define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
+#define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
+#define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define   S_028010_FORMAT(x)                           (((x) & 0x7) << 0)
+#define   G_028010_FORMAT(x)                           (((x) >> 0) & 0x7)
+#define   C_028010_FORMAT                              0xFFFFFFF8
+#define     V_028010_DEPTH_INVALID                     0x00000000
+#define     V_028010_DEPTH_16                          0x00000001
+#define     V_028010_DEPTH_X8_24                       0x00000002
+#define     V_028010_DEPTH_8_24                        0x00000003
+#define     V_028010_DEPTH_X8_24_FLOAT                 0x00000004
+#define     V_028010_DEPTH_8_24_FLOAT                  0x00000005
+#define     V_028010_DEPTH_32_FLOAT                    0x00000006
+#define     V_028010_DEPTH_X24_8_32_FLOAT              0x00000007
+#define   S_028010_READ_SIZE(x)                        (((x) & 0x1) << 3)
+#define   G_028010_READ_SIZE(x)                        (((x) >> 3) & 0x1)
+#define   C_028010_READ_SIZE                           0xFFFFFFF7
+#define   S_028010_ARRAY_MODE(x)                       (((x) & 0xF) << 15)
+#define   G_028010_ARRAY_MODE(x)                       (((x) >> 15) & 0xF)
+#define   C_028010_ARRAY_MODE                          0xFFF87FFF
+#define   S_028010_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 25)
+#define   G_028010_TILE_SURFACE_ENABLE(x)              (((x) >> 25) & 0x1)
+#define   C_028010_TILE_SURFACE_ENABLE                 0xFDFFFFFF
+#define   S_028010_TILE_COMPACT(x)                     (((x) & 0x1) << 26)
+#define   G_028010_TILE_COMPACT(x)                     (((x) >> 26) & 0x1)
+#define   C_028010_TILE_COMPACT                        0xFBFFFFFF
+#define   S_028010_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
+#define   G_028010_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
+#define   C_028010_ZRANGE_PRECISION                    0x7FFFFFFF
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define   S_028000_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028000_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028000_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028000_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028000_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028000_SLICE_TILE_MAX                      0xC00003FF
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define   S_028004_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028004_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028004_SLICE_START                         0xFFFFF800
+#define   S_028004_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028004_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028004_SLICE_MAX                           0xFF001FFF
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define   S_028D24_HTILE_WIDTH(x)                      (((x) & 0x1) << 0)
+#define   G_028D24_HTILE_WIDTH(x)                      (((x) >> 0) & 0x1)
+#define   C_028D24_HTILE_WIDTH                         0xFFFFFFFE
+#define   S_028D24_HTILE_HEIGHT(x)                     (((x) & 0x1) << 1)
+#define   G_028D24_HTILE_HEIGHT(x)                     (((x) >> 1) & 0x1)
+#define   C_028D24_HTILE_HEIGHT                        0xFFFFFFFD
+#define   S_028D24_LINEAR(x)                           (((x) & 0x1) << 2)
+#define   G_028D24_LINEAR(x)                           (((x) >> 2) & 0x1)
+#define   C_028D24_LINEAR                              0xFFFFFFFB
+#define   S_028D24_FULL_CACHE(x)                       (((x) & 0x1) << 3)
+#define   G_028D24_FULL_CACHE(x)                       (((x) >> 3) & 0x1)
+#define   C_028D24_FULL_CACHE                          0xFFFFFFF7
+#define   S_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) & 0x1) << 4)
+#define   G_028D24_HTILE_USES_PRELOAD_WIN(x)           (((x) >> 4) & 0x1)
+#define   C_028D24_HTILE_USES_PRELOAD_WIN              0xFFFFFFEF
+#define   S_028D24_PRELOAD(x)                          (((x) & 0x1) << 5)
+#define   G_028D24_PRELOAD(x)                          (((x) >> 5) & 0x1)
+#define   C_028D24_PRELOAD                             0xFFFFFFDF
+#define   S_028D24_PREFETCH_WIDTH(x)                   (((x) & 0x3F) << 6)
+#define   G_028D24_PREFETCH_WIDTH(x)                   (((x) >> 6) & 0x3F)
+#define   C_028D24_PREFETCH_WIDTH                      0xFFFFF03F
+#define   S_028D24_PREFETCH_HEIGHT(x)                  (((x) & 0x3F) << 12)
+#define   G_028D24_PREFETCH_HEIGHT(x)                  (((x) >> 12) & 0x3F)
+#define   C_028D24_PREFETCH_HEIGHT                     0xFFFC0FFF
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define   S_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) & 0x3FF) << 0)
+#define   G_028D34_DEPTH_HEIGHT_TILE_MAX(x)            (((x) >> 0) & 0x3FF)
+#define   C_028D34_DEPTH_HEIGHT_TILE_MAX               0xFFFFFC00
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define   S_028D10_FORCE_HIZ_ENABLE(x)                 (((x) & 0x3) << 0)
+#define   G_028D10_FORCE_HIZ_ENABLE(x)                 (((x) >> 0) & 0x3)
+#define   C_028D10_FORCE_HIZ_ENABLE                    0xFFFFFFFC
+#define   S_028D10_FORCE_HIS_ENABLE0(x)                (((x) & 0x3) << 2)
+#define   G_028D10_FORCE_HIS_ENABLE0(x)                (((x) >> 2) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE0                   0xFFFFFFF3
+#define   S_028D10_FORCE_HIS_ENABLE1(x)                (((x) & 0x3) << 4)
+#define   G_028D10_FORCE_HIS_ENABLE1(x)                (((x) >> 4) & 0x3)
+#define   C_028D10_FORCE_HIS_ENABLE1                   0xFFFFFFCF
+#define   S_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) & 0x1) << 6)
+#define   G_028D10_FORCE_SHADER_Z_ORDER(x)             (((x) >> 6) & 0x1)
+#define   C_028D10_FORCE_SHADER_Z_ORDER                0xFFFFFFBF
+#define   S_028D10_FAST_Z_DISABLE(x)                   (((x) & 0x1) << 7)
+#define   G_028D10_FAST_Z_DISABLE(x)                   (((x) >> 7) & 0x1)
+#define   C_028D10_FAST_Z_DISABLE                      0xFFFFFF7F
+#define   S_028D10_FAST_STENCIL_DISABLE(x)             (((x) & 0x1) << 8)
+#define   G_028D10_FAST_STENCIL_DISABLE(x)             (((x) >> 8) & 0x1)
+#define   C_028D10_FAST_STENCIL_DISABLE                0xFFFFFEFF
+#define   S_028D10_NOOP_CULL_DISABLE(x)                (((x) & 0x1) << 9)
+#define   G_028D10_NOOP_CULL_DISABLE(x)                (((x) >> 9) & 0x1)
+#define   C_028D10_NOOP_CULL_DISABLE                   0xFFFFFDFF
+#define   S_028D10_FORCE_COLOR_KILL(x)                 (((x) & 0x1) << 10)
+#define   G_028D10_FORCE_COLOR_KILL(x)                 (((x) >> 10) & 0x1)
+#define   C_028D10_FORCE_COLOR_KILL                    0xFFFFFBFF
+#define   S_028D10_FORCE_Z_READ(x)                     (((x) & 0x1) << 11)
+#define   G_028D10_FORCE_Z_READ(x)                     (((x) >> 11) & 0x1)
+#define   C_028D10_FORCE_Z_READ                        0xFFFFF7FF
+#define   S_028D10_FORCE_STENCIL_READ(x)               (((x) & 0x1) << 12)
+#define   G_028D10_FORCE_STENCIL_READ(x)               (((x) >> 12) & 0x1)
+#define   C_028D10_FORCE_STENCIL_READ                  0xFFFFEFFF
+#define   S_028D10_FORCE_FULL_Z_RANGE(x)               (((x) & 0x3) << 13)
+#define   G_028D10_FORCE_FULL_Z_RANGE(x)               (((x) >> 13) & 0x3)
+#define   C_028D10_FORCE_FULL_Z_RANGE                  0xFFFF9FFF
+#define   S_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) & 0x1) << 15)
+#define   G_028D10_FORCE_QC_SMASK_CONFLICT(x)          (((x) >> 15) & 0x1)
+#define   C_028D10_FORCE_QC_SMASK_CONFLICT             0xFFFF7FFF
+#define   S_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) & 0x1) << 16)
+#define   G_028D10_DISABLE_VIEWPORT_CLAMP(x)           (((x) >> 16) & 0x1)
+#define   C_028D10_DISABLE_VIEWPORT_CLAMP              0xFFFEFFFF
+#define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
+#define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
+#define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_008DFC_SQ_CF_WORD0                         0x008DFC
+#define   S_008DFC_ADDR(x)                             (((x) & 0xFFFFFFFF) << 0)
+#define   G_008DFC_ADDR(x)                             (((x) >> 0) & 0xFFFFFFFF)
+#define   C_008DFC_ADDR                                0x00000000
+#define R_008DFC_SQ_CF_WORD1                         0x008DFC
+#define   S_008DFC_POP_COUNT(x)                        (((x) & 0x7) << 0)
+#define   G_008DFC_POP_COUNT(x)                        (((x) >> 0) & 0x7)
+#define   C_008DFC_POP_COUNT                           0xFFFFFFF8
+#define   S_008DFC_CF_CONST(x)                         (((x) & 0x1F) << 3)
+#define   G_008DFC_CF_CONST(x)                         (((x) >> 3) & 0x1F)
+#define   C_008DFC_CF_CONST                            0xFFFFFF07
+#define   S_008DFC_COND(x)                             (((x) & 0x3) << 8)
+#define   G_008DFC_COND(x)                             (((x) >> 8) & 0x3)
+#define   C_008DFC_COND                                0xFFFFFCFF
+#define   S_008DFC_COUNT(x)                            (((x) & 0x7) << 10)
+#define   G_008DFC_COUNT(x)                            (((x) >> 10) & 0x7)
+#define   C_008DFC_COUNT                               0xFFFFE3FF
+#define   S_008DFC_CALL_COUNT(x)                       (((x) & 0x3F) << 13)
+#define   G_008DFC_CALL_COUNT(x)                       (((x) >> 13) & 0x3F)
+#define   C_008DFC_CALL_COUNT                          0xFFF81FFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_NOP                    0x00000000
+#define     V_008DFC_SQ_CF_INST_TEX                    0x00000001
+#define     V_008DFC_SQ_CF_INST_VTX                    0x00000002
+#define     V_008DFC_SQ_CF_INST_VTX_TC                 0x00000003
+#define     V_008DFC_SQ_CF_INST_LOOP_START             0x00000004
+#define     V_008DFC_SQ_CF_INST_LOOP_END               0x00000005
+#define     V_008DFC_SQ_CF_INST_LOOP_START_DX10        0x00000006
+#define     V_008DFC_SQ_CF_INST_LOOP_START_NO_AL       0x00000007
+#define     V_008DFC_SQ_CF_INST_LOOP_CONTINUE          0x00000008
+#define     V_008DFC_SQ_CF_INST_LOOP_BREAK             0x00000009
+#define     V_008DFC_SQ_CF_INST_JUMP                   0x0000000A
+#define     V_008DFC_SQ_CF_INST_PUSH                   0x0000000B
+#define     V_008DFC_SQ_CF_INST_PUSH_ELSE              0x0000000C
+#define     V_008DFC_SQ_CF_INST_ELSE                   0x0000000D
+#define     V_008DFC_SQ_CF_INST_POP                    0x0000000E
+#define     V_008DFC_SQ_CF_INST_POP_JUMP               0x0000000F
+#define     V_008DFC_SQ_CF_INST_POP_PUSH               0x00000010
+#define     V_008DFC_SQ_CF_INST_POP_PUSH_ELSE          0x00000011
+#define     V_008DFC_SQ_CF_INST_CALL                   0x00000012
+#define     V_008DFC_SQ_CF_INST_CALL_FS                0x00000013
+#define     V_008DFC_SQ_CF_INST_RETURN                 0x00000014
+#define     V_008DFC_SQ_CF_INST_EMIT_VERTEX            0x00000015
+#define     V_008DFC_SQ_CF_INST_EMIT_CUT_VERTEX        0x00000016
+#define     V_008DFC_SQ_CF_INST_CUT_VERTEX             0x00000017
+#define     V_008DFC_SQ_CF_INST_KILL                   0x00000018
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD0                     0x008DFC
+#define   S_008DFC_ALU_ADDR(x)                         (((x) & 0x3FFFFF) << 0)
+#define   G_008DFC_ALU_ADDR(x)                         (((x) >> 0) & 0x3FFFFF)
+#define   C_008DFC_ALU_ADDR                            0xFFC00000
+#define   S_008DFC_KCACHE_BANK0(x)                     (((x) & 0xF) << 22)
+#define   G_008DFC_KCACHE_BANK0(x)                     (((x) >> 22) & 0xF)
+#define   C_008DFC_KCACHE_BANK0                        0xFC3FFFFF
+#define   S_008DFC_KCACHE_BANK1(x)                     (((x) & 0xF) << 26)
+#define   G_008DFC_KCACHE_BANK1(x)                     (((x) >> 26) & 0xF)
+#define   C_008DFC_KCACHE_BANK1                        0xC3FFFFFF
+#define   S_008DFC_KCACHE_MODE0(x)                     (((x) & 0x3) << 30)
+#define   G_008DFC_KCACHE_MODE0(x)                     (((x) >> 30) & 0x3)
+#define   C_008DFC_KCACHE_MODE0                        0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALU_WORD1                     0x008DFC
+#define   S_008DFC_KCACHE_MODE1(x)                     (((x) & 0x3) << 0)
+#define   G_008DFC_KCACHE_MODE1(x)                     (((x) >> 0) & 0x3)
+#define   C_008DFC_KCACHE_MODE1                        0xFFFFFFFC
+#define   S_008DFC_KCACHE_ADDR0(x)                     (((x) & 0xFF) << 2)
+#define   G_008DFC_KCACHE_ADDR0(x)                     (((x) >> 2) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR0                        0xFFFFFC03
+#define   S_008DFC_KCACHE_ADDR1(x)                     (((x) & 0xFF) << 10)
+#define   G_008DFC_KCACHE_ADDR1(x)                     (((x) >> 10) & 0xFF)
+#define   C_008DFC_KCACHE_ADDR1                        0xFFFC03FF
+#define   S_008DFC_ALU_COUNT(x)                        (((x) & 0x7F) << 18)
+#define   G_008DFC_ALU_COUNT(x)                        (((x) >> 18) & 0x7F)
+#define   C_008DFC_ALU_COUNT                           0xFE03FFFF
+#define   S_008DFC_USES_WATERFALL(x)                   (((x) & 0x1) << 25)
+#define   G_008DFC_USES_WATERFALL(x)                   (((x) >> 25) & 0x1)
+#define   C_008DFC_USES_WATERFALL                      0xFDFFFFFF
+#define   S_008DFC_CF_ALU_INST(x)                      (((x) & 0xF) << 26)
+#define   G_008DFC_CF_ALU_INST(x)                      (((x) >> 26) & 0xF)
+#define   C_008DFC_CF_ALU_INST                         0xC3FFFFFF
+#define     V_008DFC_SQ_CF_INST_ALU                    0x00000008
+#define     V_008DFC_SQ_CF_INST_ALU_PUSH_BEFORE        0x00000009
+#define     V_008DFC_SQ_CF_INST_ALU_POP_AFTER          0x0000000A
+#define     V_008DFC_SQ_CF_INST_ALU_POP2_AFTER         0x0000000B
+#define     V_008DFC_SQ_CF_INST_ALU_CONTINUE           0x0000000D
+#define     V_008DFC_SQ_CF_INST_ALU_BREAK              0x0000000E
+#define     V_008DFC_SQ_CF_INST_ALU_ELSE_AFTER         0x0000000F
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD0            0x008DFC
+#define   S_008DFC_ARRAY_BASE(x)                       (((x) & 0x1FFF) << 0)
+#define   G_008DFC_ARRAY_BASE(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_008DFC_ARRAY_BASE                          0xFFFFE000
+#define   S_008DFC_TYPE(x)                             (((x) & 0x3) << 13)
+#define   G_008DFC_TYPE(x)                             (((x) >> 13) & 0x3)
+#define   C_008DFC_TYPE                                0xFFFF9FFF
+#define   S_008DFC_RW_GPR(x)                           (((x) & 0x7F) << 15)
+#define   G_008DFC_RW_GPR(x)                           (((x) >> 15) & 0x7F)
+#define   C_008DFC_RW_GPR                              0xFFC07FFF
+#define   S_008DFC_RW_REL(x)                           (((x) & 0x1) << 22)
+#define   G_008DFC_RW_REL(x)                           (((x) >> 22) & 0x1)
+#define   C_008DFC_RW_REL                              0xFFBFFFFF
+#define   S_008DFC_INDEX_GPR(x)                        (((x) & 0x7F) << 23)
+#define   G_008DFC_INDEX_GPR(x)                        (((x) >> 23) & 0x7F)
+#define   C_008DFC_INDEX_GPR                           0xC07FFFFF
+#define   S_008DFC_ELEM_SIZE(x)                        (((x) & 0x3) << 30)
+#define   G_008DFC_ELEM_SIZE(x)                        (((x) >> 30) & 0x3)
+#define   C_008DFC_ELEM_SIZE                           0x3FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1            0x008DFC
+#define   S_008DFC_BURST_COUNT(x)                      (((x) & 0xF) << 17)
+#define   G_008DFC_BURST_COUNT(x)                      (((x) >> 17) & 0xF)
+#define   C_008DFC_BURST_COUNT                         0xFFE1FFFF
+#define   S_008DFC_END_OF_PROGRAM(x)                   (((x) & 0x1) << 21)
+#define   G_008DFC_END_OF_PROGRAM(x)                   (((x) >> 21) & 0x1)
+#define   C_008DFC_END_OF_PROGRAM                      0xFFDFFFFF
+#define   S_008DFC_VALID_PIXEL_MODE(x)                 (((x) & 0x1) << 22)
+#define   G_008DFC_VALID_PIXEL_MODE(x)                 (((x) >> 22) & 0x1)
+#define   C_008DFC_VALID_PIXEL_MODE                    0xFFBFFFFF
+#define   S_008DFC_CF_INST(x)                          (((x) & 0x7F) << 23)
+#define   G_008DFC_CF_INST(x)                          (((x) >> 23) & 0x7F)
+#define   C_008DFC_CF_INST                             0xC07FFFFF
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM0            0x00000020
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM1            0x00000021
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM2            0x00000022
+#define     V_008DFC_SQ_CF_INST_MEM_STREAM3            0x00000023
+#define     V_008DFC_SQ_CF_INST_MEM_SCRATCH            0x00000024
+#define     V_008DFC_SQ_CF_INST_MEM_REDUCTION          0x00000025
+#define     V_008DFC_SQ_CF_INST_MEM_RING               0x00000026
+#define     V_008DFC_SQ_CF_INST_EXPORT                 0x00000027
+#define     V_008DFC_SQ_CF_INST_EXPORT_DONE            0x00000028
+#define   S_008DFC_WHOLE_QUAD_MODE(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_WHOLE_QUAD_MODE(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_WHOLE_QUAD_MODE                     0xBFFFFFFF
+#define   S_008DFC_BARRIER(x)                          (((x) & 0x1) << 31)
+#define   G_008DFC_BARRIER(x)                          (((x) >> 31) & 0x1)
+#define   C_008DFC_BARRIER                             0x7FFFFFFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_BUF        0x008DFC
+#define   S_008DFC_ARRAY_SIZE(x)                       (((x) & 0xFFF) << 0)
+#define   G_008DFC_ARRAY_SIZE(x)                       (((x) >> 0) & 0xFFF)
+#define   C_008DFC_ARRAY_SIZE                          0xFFFFF000
+#define   S_008DFC_COMP_MASK(x)                        (((x) & 0xF) << 12)
+#define   G_008DFC_COMP_MASK(x)                        (((x) >> 12) & 0xF)
+#define   C_008DFC_COMP_MASK                           0xFFFF0FFF
+#define R_008DFC_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ       0x008DFC
+#define   S_008DFC_SEL_X(x)                            (((x) & 0x7) << 0)
+#define   G_008DFC_SEL_X(x)                            (((x) >> 0) & 0x7)
+#define   C_008DFC_SEL_X                               0xFFFFFFF8
+#define   S_008DFC_SEL_Y(x)                            (((x) & 0x7) << 3)
+#define   G_008DFC_SEL_Y(x)                            (((x) >> 3) & 0x7)
+#define   C_008DFC_SEL_Y                               0xFFFFFFC7
+#define   S_008DFC_SEL_Z(x)                            (((x) & 0x7) << 6)
+#define   G_008DFC_SEL_Z(x)                            (((x) >> 6) & 0x7)
+#define   C_008DFC_SEL_Z                               0xFFFFFE3F
+#define   S_008DFC_SEL_W(x)                            (((x) & 0x7) << 9)
+#define   G_008DFC_SEL_W(x)                            (((x) >> 9) & 0x7)
+#define   C_008DFC_SEL_W                               0xFFFFF1FF
+#define R_008DFC_SQ_VTX_WORD0                        0x008DFC
+#define   S_008DFC_VTX_INST(x)                         (((x) & 0x1F) << 0)
+#define   G_008DFC_VTX_INST(x)                         (((x) >> 0) & 0x1F)
+#define   C_008DFC_VTX_INST                            0xFFFFFFE0
+#define   S_008DFC_FETCH_TYPE(x)                       (((x) & 0x3) << 5)
+#define   G_008DFC_FETCH_TYPE(x)                       (((x) >> 5) & 0x3)
+#define   C_008DFC_FETCH_TYPE                          0xFFFFFF9F
+#define   S_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) & 0x1) << 7)
+#define   G_008DFC_FETCH_WHOLE_QUAD(x)                 (((x) >> 7) & 0x1)
+#define   C_008DFC_FETCH_WHOLE_QUAD                    0xFFFFFF7F
+#define   S_008DFC_BUFFER_ID(x)                        (((x) & 0xFF) << 8)
+#define   G_008DFC_BUFFER_ID(x)                        (((x) >> 8) & 0xFF)
+#define   C_008DFC_BUFFER_ID                           0xFFFF00FF
+#define   S_008DFC_SRC_GPR(x)                          (((x) & 0x7F) << 16)
+#define   G_008DFC_SRC_GPR(x)                          (((x) >> 16) & 0x7F)
+#define   C_008DFC_SRC_GPR                             0xFF80FFFF
+#define   S_008DFC_SRC_REL(x)                          (((x) & 0x1) << 23)
+#define   G_008DFC_SRC_REL(x)                          (((x) >> 23) & 0x1)
+#define   C_008DFC_SRC_REL                             0xFF7FFFFF
+#define   S_008DFC_SRC_SEL_X(x)                        (((x) & 0x3) << 24)
+#define   G_008DFC_SRC_SEL_X(x)                        (((x) >> 24) & 0x3)
+#define   C_008DFC_SRC_SEL_X                           0xFCFFFFFF
+#define   S_008DFC_MEGA_FETCH_COUNT(x)                 (((x) & 0x3F) << 26)
+#define   G_008DFC_MEGA_FETCH_COUNT(x)                 (((x) >> 26) & 0x3F)
+#define   C_008DFC_MEGA_FETCH_COUNT                    0x03FFFFFF
+#define R_008DFC_SQ_VTX_WORD1                        0x008DFC
+#define   S_008DFC_DST_SEL_X(x)                        (((x) & 0x7) << 9)
+#define   G_008DFC_DST_SEL_X(x)                        (((x) >> 9) & 0x7)
+#define   C_008DFC_DST_SEL_X                           0xFFFFF1FF
+#define   S_008DFC_DST_SEL_Y(x)                        (((x) & 0x7) << 12)
+#define   G_008DFC_DST_SEL_Y(x)                        (((x) >> 12) & 0x7)
+#define   C_008DFC_DST_SEL_Y                           0xFFFF8FFF
+#define   S_008DFC_DST_SEL_Z(x)                        (((x) & 0x7) << 15)
+#define   G_008DFC_DST_SEL_Z(x)                        (((x) >> 15) & 0x7)
+#define   C_008DFC_DST_SEL_Z                           0xFFFC7FFF
+#define   S_008DFC_DST_SEL_W(x)                        (((x) & 0x7) << 18)
+#define   G_008DFC_DST_SEL_W(x)                        (((x) >> 18) & 0x7)
+#define   C_008DFC_DST_SEL_W                           0xFFE3FFFF
+#define   S_008DFC_USE_CONST_FIELDS(x)                 (((x) & 0x1) << 21)
+#define   G_008DFC_USE_CONST_FIELDS(x)                 (((x) >> 21) & 0x1)
+#define   C_008DFC_USE_CONST_FIELDS                    0xFFDFFFFF
+#define   S_008DFC_DATA_FORMAT(x)                      (((x) & 0x3F) << 22)
+#define   G_008DFC_DATA_FORMAT(x)                      (((x) >> 22) & 0x3F)
+#define   C_008DFC_DATA_FORMAT                         0xF03FFFFF
+#define   S_008DFC_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 28)
+#define   G_008DFC_NUM_FORMAT_ALL(x)                   (((x) >> 28) & 0x3)
+#define   C_008DFC_NUM_FORMAT_ALL                      0xCFFFFFFF
+#define   S_008DFC_FORMAT_COMP_ALL(x)                  (((x) & 0x1) << 30)
+#define   G_008DFC_FORMAT_COMP_ALL(x)                  (((x) >> 30) & 0x1)
+#define   C_008DFC_FORMAT_COMP_ALL                     0xBFFFFFFF
+#define   S_008DFC_SRF_MODE_ALL(x)                     (((x) & 0x1) << 31)
+#define   G_008DFC_SRF_MODE_ALL(x)                     (((x) >> 31) & 0x1)
+#define   C_008DFC_SRF_MODE_ALL                        0x7FFFFFFF
+#define R_008DFC_SQ_VTX_WORD1_GPR                    0x008DFC
+#define   S_008DFC_DST_GPR(x)                          (((x) & 0x7F) << 0)
+#define   G_008DFC_DST_GPR(x)                          (((x) >> 0) & 0x7F)
+#define   C_008DFC_DST_GPR                             0xFFFFFF80
+#define   S_008DFC_DST_REL(x)                          (((x) & 0x1) << 7)
+#define   G_008DFC_DST_REL(x)                          (((x) >> 7) & 0x1)
+#define   C_008DFC_DST_REL                             0xFFFFFF7F
+#define R_008DFC_SQ_VTX_WORD2                        0x008DFC
+#define   S_008DFC_OFFSET(x)                           (((x) & 0xFFFF) << 0)
+#define   G_008DFC_OFFSET(x)                           (((x) >> 0) & 0xFFFF)
+#define   C_008DFC_OFFSET                              0xFFFF0000
+#define   S_008DFC_ENDIAN_SWAP(x)                      (((x) & 0x3) << 16)
+#define   G_008DFC_ENDIAN_SWAP(x)                      (((x) >> 16) & 0x3)
+#define   C_008DFC_ENDIAN_SWAP                         0xFFFCFFFF
+#define   S_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) & 0x1) << 18)
+#define   G_008DFC_CONST_BUF_NO_STRIDE(x)              (((x) >> 18) & 0x1)
+#define   C_008DFC_CONST_BUF_NO_STRIDE                 0xFFFBFFFF
+#define   S_008DFC_MEGA_FETCH(x)                       (((x) & 0x1) << 19)
+#define   G_008DFC_MEGA_FETCH(x)                       (((x) >> 19) & 0x1)
+#define   C_008DFC_MEGA_FETCH                          0xFFF7FFFF
+#define   S_008DFC_ALT_CONST(x)                        (((x) & 0x1) << 20)
+#define   G_008DFC_ALT_CONST(x)                        (((x) >> 20) & 0x1)
+#define   C_008DFC_ALT_CONST                           0xFFEFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PARAM_GEN_ADDR(x)                   (((x) & 0x7F) << 19)
+#define   G_0286CC_PARAM_GEN_ADDR(x)                   (((x) >> 19) & 0x7F)
+#define   C_0286CC_PARAM_GEN_ADDR                      0xFC07FFFF
+#define   S_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) & 0x3) << 26)
+#define   G_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) >> 26) & 0x3)
+#define   C_0286CC_BARYC_SAMPLE_CNTL                   0xF3FFFFFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define   S_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) & 0x1) << 31)
+#define   G_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) >> 31) & 0x1)
+#define   C_0286CC_BARYC_AT_SAMPLE_ENA                 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_GEN_INDEX_PIX(x)                    (((x) & 0x1) << 0)
+#define   G_0286D0_GEN_INDEX_PIX(x)                    (((x) >> 0) & 0x1)
+#define   C_0286D0_GEN_INDEX_PIX                       0xFFFFFFFE
+#define   S_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) & 0x7F) << 1)
+#define   G_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) >> 1) & 0x7F)
+#define   C_0286D0_GEN_INDEX_PIX_ADDR                  0xFFFFFF01
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define   S_0287F0_SOURCE_SELECT(x)                    (((x) & 0x3) << 0)
+#define   G_0287F0_SOURCE_SELECT(x)                    (((x) >> 0) & 0x3)
+#define   C_0287F0_SOURCE_SELECT                       0xFFFFFFFC
+#define   S_0287F0_MAJOR_MODE(x)                       (((x) & 0x3) << 2)
+#define   G_0287F0_MAJOR_MODE(x)                       (((x) >> 2) & 0x3)
+#define   C_0287F0_MAJOR_MODE                          0xFFFFFFF3
+#define   S_0287F0_SPRITE_EN(x)                        (((x) & 0x1) << 4)
+#define   G_0287F0_SPRITE_EN(x)                        (((x) >> 4) & 0x1)
+#define   C_0287F0_SPRITE_EN                           0xFFFFFFEF
+#define   S_0287F0_NOT_EOP(x)                          (((x) & 0x1) << 5)
+#define   G_0287F0_NOT_EOP(x)                          (((x) >> 5) & 0x1)
+#define   C_0287F0_NOT_EOP                             0xFFFFFFDF
+#define   S_0287F0_USE_OPAQUE(x)                       (((x) & 0x1) << 6)
+#define   G_0287F0_USE_OPAQUE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287F0_USE_OPAQUE                          0xFFFFFFBF
+#define R_0280A0_CB_COLOR0_INFO                      0x0280A0
+#define R_0280A4_CB_COLOR1_INFO                      0x0280A4
+#define R_0280A8_CB_COLOR2_INFO                      0x0280A8
+#define R_0280AC_CB_COLOR3_INFO                      0x0280AC
+#define R_0280B0_CB_COLOR4_INFO                      0x0280B0
+#define R_0280B4_CB_COLOR5_INFO                      0x0280B4
+#define R_0280B8_CB_COLOR6_INFO                      0x0280B8
+#define R_0280BC_CB_COLOR7_INFO                      0x0280BC
+#define R_02800C_DB_DEPTH_BASE                       0x02800C
+#define R_028000_DB_DEPTH_SIZE                       0x028000
+#define R_028004_DB_DEPTH_VIEW                       0x028004
+#define R_028010_DB_DEPTH_INFO                       0x028010
+#define R_028D24_DB_HTILE_SURFACE                    0x028D24
+#define R_028D34_DB_PREFETCH_LIMIT                   0x028D34
+#define R_0286D4_SPI_INTERP_CONTROL_0                0x0286D4
+#define R_028A48_PA_SC_MPASS_PS_CNTL                 0x028A48
+#define R_028C00_PA_SC_LINE_CNTL                     0x028C00
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX           0x028C1C
+#define R_028C48_PA_SC_AA_MASK                       0x028C48
+#define R_028810_PA_CL_CLIP_CNTL                     0x028810
+#define R_02881C_PA_CL_VS_OUT_CNTL                   0x02881C
+#define R_028820_PA_CL_NANINF_CNTL                   0x028820
+#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ              0x028C0C
+#define R_028C10_PA_CL_GB_VERT_DISC_ADJ              0x028C10
+#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ              0x028C14
+#define R_028C18_PA_CL_GB_HORZ_DISC_ADJ              0x028C18
+#define R_028814_PA_SU_SC_MODE_CNTL                  0x028814
+#define R_028A00_PA_SU_POINT_SIZE                    0x028A00
+#define R_028A04_PA_SU_POINT_MINMAX                  0x028A04
+#define R_028A08_PA_SU_LINE_CNTL                     0x028A08
+#define R_028A0C_PA_SC_LINE_STIPPLE                  0x028A0C
+#define R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL       0x028DF8
+#define R_028DFC_PA_SU_POLY_OFFSET_CLAMP             0x028DFC
+#define R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE       0x028E00
+#define R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET      0x028E04
+#define R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE        0x028E08
+#define R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET       0x028E0C
+#define R_028818_PA_CL_VTE_CNTL                      0x028818
+#define R_02843C_PA_CL_VPORT_XSCALE_0                0x02843C
+#define R_028444_PA_CL_VPORT_YSCALE_0                0x028444
+#define R_02844C_PA_CL_VPORT_ZSCALE_0                0x02844C
+#define R_028440_PA_CL_VPORT_XOFFSET_0               0x028440
+#define R_028448_PA_CL_VPORT_YOFFSET_0               0x028448
+#define R_028450_PA_CL_VPORT_ZOFFSET_0               0x028450
+#define R_028250_PA_SC_VPORT_SCISSOR_0_TL            0x028250
+#define R_028254_PA_SC_VPORT_SCISSOR_0_BR            0x028254
+#define R_028780_CB_BLEND0_CONTROL                   0x028780
+#define R_028784_CB_BLEND1_CONTROL                   0x028784
+#define R_028788_CB_BLEND2_CONTROL                   0x028788
+#define R_02878C_CB_BLEND3_CONTROL                   0x02878C
+#define R_028790_CB_BLEND4_CONTROL                   0x028790
+#define R_028794_CB_BLEND5_CONTROL                   0x028794
+#define R_028798_CB_BLEND6_CONTROL                   0x028798
+#define R_02879C_CB_BLEND7_CONTROL                   0x02879C
+#define R_028804_CB_BLEND_CONTROL                    0x028804
+#define R_028028_DB_STENCIL_CLEAR                    0x028028
+#define R_02802C_DB_DEPTH_CLEAR                      0x02802C
+#define R_028430_DB_STENCILREFMASK                   0x028430
+#define R_028434_DB_STENCILREFMASK_BF                0x028434
+#define R_028800_DB_DEPTH_CONTROL                    0x028800
+#define R_02880C_DB_SHADER_CONTROL                   0x02880C
+#define R_028D0C_DB_RENDER_CONTROL                   0x028D0C
+#define R_028D10_DB_RENDER_OVERRIDE                  0x028D10
+#define R_028D2C_DB_SRESULTS_COMPARE_STATE1          0x028D2C
+#define R_028D30_DB_PRELOAD_CONTROL                  0x028D30
+#define R_028D44_DB_ALPHA_TO_MASK                    0x028D44
+#define R_028868_SQ_PGM_RESOURCES_VS                 0x028868
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define R_028644_SPI_PS_INPUT_CNTL_0                 0x028644
+#define R_028648_SPI_PS_INPUT_CNTL_1                 0x028648
+#define R_02864C_SPI_PS_INPUT_CNTL_2                 0x02864C
+#define R_028650_SPI_PS_INPUT_CNTL_3                 0x028650
+#define R_028654_SPI_PS_INPUT_CNTL_4                 0x028654
+#define R_028658_SPI_PS_INPUT_CNTL_5                 0x028658
+#define R_02865C_SPI_PS_INPUT_CNTL_6                 0x02865C
+#define R_028660_SPI_PS_INPUT_CNTL_7                 0x028660
+#define R_028664_SPI_PS_INPUT_CNTL_8                 0x028664
+#define R_028668_SPI_PS_INPUT_CNTL_9                 0x028668
+#define R_02866C_SPI_PS_INPUT_CNTL_10                0x02866C
+#define R_028670_SPI_PS_INPUT_CNTL_11                0x028670
+#define R_028674_SPI_PS_INPUT_CNTL_12                0x028674
+#define R_028678_SPI_PS_INPUT_CNTL_13                0x028678
+#define R_02867C_SPI_PS_INPUT_CNTL_14                0x02867C
+#define R_028680_SPI_PS_INPUT_CNTL_15                0x028680
+#define R_028684_SPI_PS_INPUT_CNTL_16                0x028684
+#define R_028688_SPI_PS_INPUT_CNTL_17                0x028688
+#define R_02868C_SPI_PS_INPUT_CNTL_18                0x02868C
+#define R_028690_SPI_PS_INPUT_CNTL_19                0x028690
+#define R_028694_SPI_PS_INPUT_CNTL_20                0x028694
+#define R_028698_SPI_PS_INPUT_CNTL_21                0x028698
+#define R_02869C_SPI_PS_INPUT_CNTL_22                0x02869C
+#define R_0286A0_SPI_PS_INPUT_CNTL_23                0x0286A0
+#define R_0286A4_SPI_PS_INPUT_CNTL_24                0x0286A4
+#define R_0286A8_SPI_PS_INPUT_CNTL_25                0x0286A8
+#define R_0286AC_SPI_PS_INPUT_CNTL_26                0x0286AC
+#define R_0286B0_SPI_PS_INPUT_CNTL_27                0x0286B0
+#define R_0286B4_SPI_PS_INPUT_CNTL_28                0x0286B4
+#define R_0286B8_SPI_PS_INPUT_CNTL_29                0x0286B8
+#define R_0286BC_SPI_PS_INPUT_CNTL_30                0x0286BC
+#define R_0286C0_SPI_PS_INPUT_CNTL_31                0x0286C0
+#define R_028850_SQ_PGM_RESOURCES_PS                 0x028850
+#define R_028854_SQ_PGM_EXPORTS_PS                   0x028854
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define R_028A7C_VGT_DMA_INDEX_TYPE                  0x028A7C
+#define R_028A88_VGT_DMA_NUM_INSTANCES               0x028A88
+#define R_008970_VGT_NUM_INDICES                     0x008970
+#define R_0287F0_VGT_DRAW_INITIATOR                  0x0287F0
+#define R_028238_CB_TARGET_MASK                      0x028238
+#define R_02823C_CB_SHADER_MASK                      0x02823C
+#define R_028060_CB_COLOR0_SIZE                      0x028060
+#define   S_028060_PITCH_TILE_MAX(x)                   (((x) & 0x3FF) << 0)
+#define   G_028060_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x3FF)
+#define   C_028060_PITCH_TILE_MAX                      0xFFFFFC00
+#define   S_028060_SLICE_TILE_MAX(x)                   (((x) & 0xFFFFF) << 10)
+#define   G_028060_SLICE_TILE_MAX(x)                   (((x) >> 10) & 0xFFFFF)
+#define   C_028060_SLICE_TILE_MAX                      0xC00003FF
+#define R_028064_CB_COLOR1_SIZE                      0x028064
+#define R_028068_CB_COLOR2_SIZE                      0x028068
+#define R_02806C_CB_COLOR3_SIZE                      0x02806C
+#define R_028070_CB_COLOR4_SIZE                      0x028070
+#define R_028074_CB_COLOR5_SIZE                      0x028074
+#define R_028078_CB_COLOR6_SIZE                      0x028078
+#define R_02807C_CB_COLOR7_SIZE                      0x02807C
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define R_028044_CB_COLOR1_BASE                      0x028044
+#define R_028048_CB_COLOR2_BASE                      0x028048
+#define R_02804C_CB_COLOR3_BASE                      0x02804C
+#define R_028050_CB_COLOR4_BASE                      0x028050
+#define R_028054_CB_COLOR5_BASE                      0x028054
+#define R_028058_CB_COLOR6_BASE                      0x028058
+#define R_02805C_CB_COLOR7_BASE                      0x02805C
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define R_028C04_PA_SC_AA_CONFIG                     0x028C04
+#define   S_028C04_MSAA_NUM_SAMPLES(x)                 (((x) & 0x3) << 0)
+#define   G_028C04_MSAA_NUM_SAMPLES(x)                 (((x) >> 0) & 0x3)
+#define   C_028C04_MSAA_NUM_SAMPLES                    0xFFFFFFFC
+#define   S_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) & 0x1) << 4)
+#define   G_028C04_AA_MASK_CENTROID_DTMN(x)            (((x) >> 4) & 0x1)
+#define   C_028C04_AA_MASK_CENTROID_DTMN               0xFFFFFFEF
+#define   S_028C04_MAX_SAMPLE_DIST(x)                  (((x) & 0xF) << 13)
+#define   G_028C04_MAX_SAMPLE_DIST(x)                  (((x) >> 13) & 0xF)
+#define   C_028C04_MAX_SAMPLE_DIST                     0xFFFE1FFF
+#define R_0288CC_SQ_PGM_CF_OFFSET_PS                 0x0288CC
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define R_0288D0_SQ_PGM_CF_OFFSET_VS                 0x0288D0
+#define R_028840_SQ_PGM_START_PS                     0x028840
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define R_028858_SQ_PGM_START_VS                     0x028858
+#define R_028080_CB_COLOR0_VIEW                      0x028080
+#define   S_028080_SLICE_START(x)                      (((x) & 0x7FF) << 0)
+#define   G_028080_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
+#define   C_028080_SLICE_START                         0xFFFFF800
+#define   S_028080_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
+#define   G_028080_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
+#define   C_028080_SLICE_MAX                           0xFF001FFF
+#define R_028100_CB_COLOR0_MASK                      0x028100
+#define   S_028100_CMASK_BLOCK_MAX(x)                  (((x) & 0xFFF) << 0)
+#define   G_028100_CMASK_BLOCK_MAX(x)                  (((x) >> 0) & 0xFFF)
+#define   C_028100_CMASK_BLOCK_MAX                     0xFFFFF000
+#define   S_028100_FMASK_TILE_MAX(x)                   (((x) & 0xFFFFF) << 12)
+#define   G_028100_FMASK_TILE_MAX(x)                   (((x) >> 12) & 0xFFFFF)
+#define   C_028100_FMASK_TILE_MAX                      0x00000FFF
+#define R_028040_CB_COLOR0_BASE                      0x028040
+#define   S_028040_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028040_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028040_BASE_256B                           0x00000000
+#define R_0280E0_CB_COLOR0_FRAG                      0x0280E0
+#define   S_0280E0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280E0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280E0_BASE_256B                           0x00000000
+#define R_0280C0_CB_COLOR0_TILE                      0x0280C0
+#define   S_0280C0_BASE_256B(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_0280C0_BASE_256B(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0280C0_BASE_256B                           0x00000000
+#define R_028808_CB_COLOR_CONTROL                    0x028808
+#define   S_028808_FOG_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_028808_FOG_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_028808_FOG_ENABLE                          0xFFFFFFFE
+#define   S_028808_MULTIWRITE_ENABLE(x)                (((x) & 0x1) << 1)
+#define   G_028808_MULTIWRITE_ENABLE(x)                (((x) >> 1) & 0x1)
+#define   C_028808_MULTIWRITE_ENABLE                   0xFFFFFFFD
+#define   S_028808_DITHER_ENABLE(x)                    (((x) & 0x1) << 2)
+#define   G_028808_DITHER_ENABLE(x)                    (((x) >> 2) & 0x1)
+#define   C_028808_DITHER_ENABLE                       0xFFFFFFFB
+#define   S_028808_DEGAMMA_ENABLE(x)                   (((x) & 0x1) << 3)
+#define   G_028808_DEGAMMA_ENABLE(x)                   (((x) >> 3) & 0x1)
+#define   C_028808_DEGAMMA_ENABLE                      0xFFFFFFF7
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define   S_028808_PER_MRT_BLEND(x)                    (((x) & 0x1) << 7)
+#define   G_028808_PER_MRT_BLEND(x)                    (((x) >> 7) & 0x1)
+#define   C_028808_PER_MRT_BLEND                       0xFFFFFF7F
+#define   S_028808_TARGET_BLEND_ENABLE(x)              (((x) & 0xFF) << 8)
+#define   G_028808_TARGET_BLEND_ENABLE(x)              (((x) >> 8) & 0xFF)
+#define   C_028808_TARGET_BLEND_ENABLE                 0xFFFF00FF
+#define   S_028808_ROP3(x)                             (((x) & 0xFF) << 16)
+#define   G_028808_ROP3(x)                             (((x) >> 16) & 0xFF)
+#define   C_028808_ROP3                                0xFF00FFFF
+#define R_028614_SPI_VS_OUT_ID_0                     0x028614
+#define   S_028614_SEMANTIC_0(x)                       (((x) & 0xFF) << 0)
+#define   G_028614_SEMANTIC_0(x)                       (((x) >> 0) & 0xFF)
+#define   C_028614_SEMANTIC_0                          0xFFFFFF00
+#define   S_028614_SEMANTIC_1(x)                       (((x) & 0xFF) << 8)
+#define   G_028614_SEMANTIC_1(x)                       (((x) >> 8) & 0xFF)
+#define   C_028614_SEMANTIC_1                          0xFFFF00FF
+#define   S_028614_SEMANTIC_2(x)                       (((x) & 0xFF) << 16)
+#define   G_028614_SEMANTIC_2(x)                       (((x) >> 16) & 0xFF)
+#define   C_028614_SEMANTIC_2                          0xFF00FFFF
+#define   S_028614_SEMANTIC_3(x)                       (((x) & 0xFF) << 24)
+#define   G_028614_SEMANTIC_3(x)                       (((x) >> 24) & 0xFF)
+#define   C_028614_SEMANTIC_3                          0x00FFFFFF
+#define R_028618_SPI_VS_OUT_ID_1                     0x028618
+#define R_02861C_SPI_VS_OUT_ID_2                     0x02861C
+#define R_028620_SPI_VS_OUT_ID_3                     0x028620
+#define R_028624_SPI_VS_OUT_ID_4                     0x028624
+#define R_028628_SPI_VS_OUT_ID_5                     0x028628
+#define R_02862C_SPI_VS_OUT_ID_6                     0x02862C
+#define R_028630_SPI_VS_OUT_ID_7                     0x028630
+#define R_028634_SPI_VS_OUT_ID_8                     0x028634
+#define R_028638_SPI_VS_OUT_ID_9                     0x028638
+#define R_038000_SQ_TEX_RESOURCE_WORD0_0             0x038000
+#define   S_038000_DIM(x)                              (((x) & 0x7) << 0)
+#define   G_038000_DIM(x)                              (((x) >> 0) & 0x7)
+#define   C_038000_DIM                                 0xFFFFFFF8
+#define   S_038000_TILE_MODE(x)                        (((x) & 0xF) << 3)
+#define   G_038000_TILE_MODE(x)                        (((x) >> 3) & 0xF)
+#define   C_038000_TILE_MODE                           0xFFFFFF87
+#define   S_038000_TILE_TYPE(x)                        (((x) & 0x1) << 7)
+#define   G_038000_TILE_TYPE(x)                        (((x) >> 7) & 0x1)
+#define   C_038000_TILE_TYPE                           0xFFFFFF7F
+#define   S_038000_PITCH(x)                            (((x) & 0x7FF) << 8)
+#define   G_038000_PITCH(x)                            (((x) >> 8) & 0x7FF)
+#define   C_038000_PITCH                               0xFFF800FF
+#define   S_038000_TEX_WIDTH(x)                        (((x) & 0x1FFF) << 19)
+#define   G_038000_TEX_WIDTH(x)                        (((x) >> 19) & 0x1FFF)
+#define   C_038000_TEX_WIDTH                           0x0007FFFF
+#define R_038004_SQ_TEX_RESOURCE_WORD1_0             0x038004
+#define   S_038004_TEX_HEIGHT(x)                       (((x) & 0x1FFF) << 0)
+#define   G_038004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x1FFF)
+#define   C_038004_TEX_HEIGHT                          0xFFFFE000
+#define   S_038004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 13)
+#define   G_038004_TEX_DEPTH(x)                        (((x) >> 13) & 0x1FFF)
+#define   C_038004_TEX_DEPTH                           0xFC001FFF
+#define   S_038004_DATA_FORMAT(x)                      (((x) & 0x3F) << 26)
+#define   G_038004_DATA_FORMAT(x)                      (((x) >> 26) & 0x3F)
+#define   C_038004_DATA_FORMAT                         0x03FFFFFF
+#define     V_038004_COLOR_INVALID                     0x00000000
+#define     V_038004_COLOR_8                           0x00000001
+#define     V_038004_COLOR_4_4                         0x00000002
+#define     V_038004_COLOR_3_3_2                       0x00000003
+#define     V_038004_COLOR_16                          0x00000005
+#define     V_038004_COLOR_16_FLOAT                    0x00000006
+#define     V_038004_COLOR_8_8                         0x00000007
+#define     V_038004_COLOR_5_6_5                       0x00000008
+#define     V_038004_COLOR_6_5_5                       0x00000009
+#define     V_038004_COLOR_1_5_5_5                     0x0000000A
+#define     V_038004_COLOR_4_4_4_4                     0x0000000B
+#define     V_038004_COLOR_5_5_5_1                     0x0000000C
+#define     V_038004_COLOR_32                          0x0000000D
+#define     V_038004_COLOR_32_FLOAT                    0x0000000E
+#define     V_038004_COLOR_16_16                       0x0000000F
+#define     V_038004_COLOR_16_16_FLOAT                 0x00000010
+#define     V_038004_COLOR_8_24                        0x00000011
+#define     V_038004_COLOR_8_24_FLOAT                  0x00000012
+#define     V_038004_COLOR_24_8                        0x00000013
+#define     V_038004_COLOR_24_8_FLOAT                  0x00000014
+#define     V_038004_COLOR_10_11_11                    0x00000015
+#define     V_038004_COLOR_10_11_11_FLOAT              0x00000016
+#define     V_038004_COLOR_11_11_10                    0x00000017
+#define     V_038004_COLOR_11_11_10_FLOAT              0x00000018
+#define     V_038004_COLOR_2_10_10_10                  0x00000019
+#define     V_038004_COLOR_8_8_8_8                     0x0000001A
+#define     V_038004_COLOR_10_10_10_2                  0x0000001B
+#define     V_038004_COLOR_X24_8_32_FLOAT              0x0000001C
+#define     V_038004_COLOR_32_32                       0x0000001D
+#define     V_038004_COLOR_32_32_FLOAT                 0x0000001E
+#define     V_038004_COLOR_16_16_16_16                 0x0000001F
+#define     V_038004_COLOR_16_16_16_16_FLOAT           0x00000020
+#define     V_038004_COLOR_32_32_32_32                 0x00000022
+#define     V_038004_COLOR_32_32_32_32_FLOAT           0x00000023
+#define R_038008_SQ_TEX_RESOURCE_WORD2_0             0x038008
+#define   S_038008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_038008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_038008_BASE_ADDRESS                        0x00000000
+#define R_03800C_SQ_TEX_RESOURCE_WORD3_0             0x03800C
+#define   S_03800C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_03800C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03800C_MIP_ADDRESS                         0x00000000
+#define R_038010_SQ_TEX_RESOURCE_WORD4_0             0x038010
+#define   S_038010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
+#define   G_038010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
+#define   C_038010_FORMAT_COMP_X                       0xFFFFFFFC
+#define   S_038010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
+#define   G_038010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
+#define   C_038010_FORMAT_COMP_Y                       0xFFFFFFF3
+#define   S_038010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
+#define   G_038010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
+#define   C_038010_FORMAT_COMP_Z                       0xFFFFFFCF
+#define   S_038010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
+#define   G_038010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
+#define   C_038010_FORMAT_COMP_W                       0xFFFFFF3F
+#define   S_038010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
+#define   G_038010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
+#define   C_038010_NUM_FORMAT_ALL                      0xFFFFFCFF
+#define   S_038010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
+#define   G_038010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
+#define   C_038010_SRF_MODE_ALL                        0xFFFFFBFF
+#define   S_038010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
+#define   G_038010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
+#define   C_038010_FORCE_DEGAMMA                       0xFFFFF7FF
+#define   S_038010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
+#define   G_038010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
+#define   C_038010_ENDIAN_SWAP                         0xFFFFCFFF
+#define   S_038010_REQUEST_SIZE(x)                     (((x) & 0x3) << 14)
+#define   G_038010_REQUEST_SIZE(x)                     (((x) >> 14) & 0x3)
+#define   C_038010_REQUEST_SIZE                        0xFFFF3FFF
+#define   S_038010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
+#define   G_038010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
+#define   C_038010_DST_SEL_X                           0xFFF8FFFF
+#define   S_038010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
+#define   G_038010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
+#define   C_038010_DST_SEL_Y                           0xFFC7FFFF
+#define   S_038010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
+#define   G_038010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
+#define   C_038010_DST_SEL_Z                           0xFE3FFFFF
+#define   S_038010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
+#define   G_038010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
+#define   C_038010_DST_SEL_W                           0xF1FFFFFF
+#define   S_038010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
+#define   G_038010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
+#define   C_038010_BASE_LEVEL                          0x0FFFFFFF
+#define R_038014_SQ_TEX_RESOURCE_WORD5_0             0x038014
+#define   S_038014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
+#define   G_038014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
+#define   C_038014_LAST_LEVEL                          0xFFFFFFF0
+#define   S_038014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
+#define   G_038014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
+#define   C_038014_BASE_ARRAY                          0xFFFE000F
+#define   S_038014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
+#define   G_038014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
+#define   C_038014_LAST_ARRAY                          0xC001FFFF
+#define R_038018_SQ_TEX_RESOURCE_WORD6_0             0x038018
+#define   S_038018_MPEG_CLAMP(x)                       (((x) & 0x3) << 0)
+#define   G_038018_MPEG_CLAMP(x)                       (((x) >> 0) & 0x3)
+#define   C_038018_MPEG_CLAMP                          0xFFFFFFFC
+#define   S_038018_PERF_MODULATION(x)                  (((x) & 0x7) << 5)
+#define   G_038018_PERF_MODULATION(x)                  (((x) >> 5) & 0x7)
+#define   C_038018_PERF_MODULATION                     0xFFFFFF1F
+#define   S_038018_INTERLACED(x)                       (((x) & 0x1) << 8)
+#define   G_038018_INTERLACED(x)                       (((x) >> 8) & 0x1)
+#define   C_038018_INTERLACED                          0xFFFFFEFF
+#define   S_038018_TYPE(x)                             (((x) & 0x3) << 30)
+#define   G_038018_TYPE(x)                             (((x) >> 30) & 0x3)
+#define   C_038018_TYPE                                0x3FFFFFFF
+#define R_008040_WAIT_UNTIL                          0x008040
+#define   S_008040_WAIT_CP_DMA_IDLE(x)                 (((x) & 0x1) << 8)
+#define   G_008040_WAIT_CP_DMA_IDLE(x)                 (((x) >> 8) & 0x1)
+#define   C_008040_WAIT_CP_DMA_IDLE                    0xFFFFFEFF
+#define   S_008040_WAIT_CMDFIFO(x)                     (((x) & 0x1) << 10)
+#define   G_008040_WAIT_CMDFIFO(x)                     (((x) >> 10) & 0x1)
+#define   C_008040_WAIT_CMDFIFO                        0xFFFFFBFF
+#define   S_008040_WAIT_2D_IDLE(x)                     (((x) & 0x1) << 14)
+#define   G_008040_WAIT_2D_IDLE(x)                     (((x) >> 14) & 0x1)
+#define   C_008040_WAIT_2D_IDLE                        0xFFFFBFFF
+#define   S_008040_WAIT_3D_IDLE(x)                     (((x) & 0x1) << 15)
+#define   G_008040_WAIT_3D_IDLE(x)                     (((x) >> 15) & 0x1)
+#define   C_008040_WAIT_3D_IDLE                        0xFFFF7FFF
+#define   S_008040_WAIT_2D_IDLECLEAN(x)                (((x) & 0x1) << 16)
+#define   G_008040_WAIT_2D_IDLECLEAN(x)                (((x) >> 16) & 0x1)
+#define   C_008040_WAIT_2D_IDLECLEAN                   0xFFFEFFFF
+#define   S_008040_WAIT_3D_IDLECLEAN(x)                (((x) & 0x1) << 17)
+#define   G_008040_WAIT_3D_IDLECLEAN(x)                (((x) >> 17) & 0x1)
+#define   C_008040_WAIT_3D_IDLECLEAN                   0xFFFDFFFF
+#define   S_008040_WAIT_EXTERN_SIG(x)                  (((x) & 0x1) << 19)
+#define   G_008040_WAIT_EXTERN_SIG(x)                  (((x) >> 19) & 0x1)
+#define   C_008040_WAIT_EXTERN_SIG                     0xFFF7FFFF
+#define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
+#define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
+#define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_008958_VGT_PRIMITIVE_TYPE                  0x008958
+#define   S_008958_PRIM_TYPE(x)                        (((x) & 0x3F) << 0)
+#define   G_008958_PRIM_TYPE(x)                        (((x) >> 0) & 0x3F)
+#define   C_008958_PRIM_TYPE                           0xFFFFFFC0
+#define R_008C00_SQ_CONFIG                           0x008C00
+#define   S_008C00_VC_ENABLE(x)                        (((x) & 0x1) << 0)
+#define   G_008C00_VC_ENABLE(x)                        (((x) >> 0) & 0x1)
+#define   C_008C00_VC_ENABLE                           0xFFFFFFFE
+#define   S_008C00_EXPORT_SRC_C(x)                     (((x) & 0x1) << 1)
+#define   G_008C00_EXPORT_SRC_C(x)                     (((x) >> 1) & 0x1)
+#define   C_008C00_EXPORT_SRC_C                        0xFFFFFFFD
+#define   S_008C00_DX9_CONSTS(x)                       (((x) & 0x1) << 2)
+#define   G_008C00_DX9_CONSTS(x)                       (((x) >> 2) & 0x1)
+#define   C_008C00_DX9_CONSTS                          0xFFFFFFFB
+#define   S_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) & 0x1) << 3)
+#define   G_008C00_ALU_INST_PREFER_VECTOR(x)           (((x) >> 3) & 0x1)
+#define   C_008C00_ALU_INST_PREFER_VECTOR              0xFFFFFFF7
+#define   S_008C00_DX10_CLAMP(x)                       (((x) & 0x1) << 4)
+#define   G_008C00_DX10_CLAMP(x)                       (((x) >> 4) & 0x1)
+#define   C_008C00_DX10_CLAMP                          0xFFFFFFEF
+#define   S_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) & 0x1) << 5)
+#define   G_008C00_ALU_PREFER_ONE_WATERFALL(x)         (((x) >> 5) & 0x1)
+#define   C_008C00_ALU_PREFER_ONE_WATERFALL            0xFFFFFFDF
+#define   S_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) & 0x1) << 6)
+#define   G_008C00_ALU_MAX_ONE_WATERFALL(x)            (((x) >> 6) & 0x1)
+#define   C_008C00_ALU_MAX_ONE_WATERFALL               0xFFFFFFBF
+#define   S_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) & 0x3) << 8)
+#define   G_008C00_CLAUSE_SEQ_PRIO(x)                  (((x) >> 8) & 0x3)
+#define   C_008C00_CLAUSE_SEQ_PRIO                     0xFFFFFCFF
+#define   S_008C00_PS_PRIO(x)                          (((x) & 0x3) << 24)
+#define   G_008C00_PS_PRIO(x)                          (((x) >> 24) & 0x3)
+#define   C_008C00_PS_PRIO                             0xFCFFFFFF
+#define   S_008C00_VS_PRIO(x)                          (((x) & 0x3) << 26)
+#define   G_008C00_VS_PRIO(x)                          (((x) >> 26) & 0x3)
+#define   C_008C00_VS_PRIO                             0xF3FFFFFF
+#define   S_008C00_GS_PRIO(x)                          (((x) & 0x3) << 28)
+#define   G_008C00_GS_PRIO(x)                          (((x) >> 28) & 0x3)
+#define   C_008C00_GS_PRIO                             0xCFFFFFFF
+#define   S_008C00_ES_PRIO(x)                          (((x) & 0x3) << 30)
+#define   G_008C00_ES_PRIO(x)                          (((x) >> 30) & 0x3)
+#define   C_008C00_ES_PRIO                             0x3FFFFFFF
+#define R_008C04_SQ_GPR_RESOURCE_MGMT_1              0x008C04
+#define   S_008C04_NUM_PS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C04_NUM_PS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C04_NUM_PS_GPRS                         0xFFFFFF00
+#define   S_008C04_NUM_VS_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C04_NUM_VS_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C04_NUM_VS_GPRS                         0xFF00FFFF
+#define   S_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) & 0xF) << 28)
+#define   G_008C04_NUM_CLAUSE_TEMP_GPRS(x)             (((x) >> 28) & 0xF)
+#define   C_008C04_NUM_CLAUSE_TEMP_GPRS                0x0FFFFFFF
+#define R_008C08_SQ_GPR_RESOURCE_MGMT_2              0x008C08
+#define   S_008C08_NUM_GS_GPRS(x)                      (((x) & 0xFF) << 0)
+#define   G_008C08_NUM_GS_GPRS(x)                      (((x) >> 0) & 0xFF)
+#define   C_008C08_NUM_GS_GPRS                         0xFFFFFF00
+#define   S_008C08_NUM_ES_GPRS(x)                      (((x) & 0xFF) << 16)
+#define   G_008C08_NUM_ES_GPRS(x)                      (((x) >> 16) & 0xFF)
+#define   C_008C08_NUM_ES_GPRS                         0xFF00FFFF
+#define R_008C0C_SQ_THREAD_RESOURCE_MGMT             0x008C0C
+#define   S_008C0C_NUM_PS_THREADS(x)                   (((x) & 0xFF) << 0)
+#define   G_008C0C_NUM_PS_THREADS(x)                   (((x) >> 0) & 0xFF)
+#define   C_008C0C_NUM_PS_THREADS                      0xFFFFFF00
+#define   S_008C0C_NUM_VS_THREADS(x)                   (((x) & 0xFF) << 8)
+#define   G_008C0C_NUM_VS_THREADS(x)                   (((x) >> 8) & 0xFF)
+#define   C_008C0C_NUM_VS_THREADS                      0xFFFF00FF
+#define   S_008C0C_NUM_GS_THREADS(x)                   (((x) & 0xFF) << 16)
+#define   G_008C0C_NUM_GS_THREADS(x)                   (((x) >> 16) & 0xFF)
+#define   C_008C0C_NUM_GS_THREADS                      0xFF00FFFF
+#define   S_008C0C_NUM_ES_THREADS(x)                   (((x) & 0xFF) << 24)
+#define   G_008C0C_NUM_ES_THREADS(x)                   (((x) >> 24) & 0xFF)
+#define   C_008C0C_NUM_ES_THREADS                      0x00FFFFFF
+#define R_008C10_SQ_STACK_RESOURCE_MGMT_1            0x008C10
+#define   S_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C10_NUM_PS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C10_NUM_PS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C10_NUM_VS_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C10_NUM_VS_STACK_ENTRIES                0xF000FFFF
+#define R_008C14_SQ_STACK_RESOURCE_MGMT_2            0x008C14
+#define   S_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) & 0xFFF) << 0)
+#define   G_008C14_NUM_GS_STACK_ENTRIES(x)             (((x) >> 0) & 0xFFF)
+#define   C_008C14_NUM_GS_STACK_ENTRIES                0xFFFFF000
+#define   S_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) & 0xFFF) << 16)
+#define   G_008C14_NUM_ES_STACK_ENTRIES(x)             (((x) >> 16) & 0xFFF)
+#define   C_008C14_NUM_ES_STACK_ENTRIES                0xF000FFFF
+#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ        0x008D8C
+#define   S_008D8C_RING0_OFFSET(x)                     (((x) & 0xFF) << 0)
+#define   G_008D8C_RING0_OFFSET(x)                     (((x) >> 0) & 0xFF)
+#define   C_008D8C_RING0_OFFSET                        0xFFFFFF00
+#define   S_008D8C_ISOLATE_ES_ENABLE(x)                (((x) & 0x1) << 12)
+#define   G_008D8C_ISOLATE_ES_ENABLE(x)                (((x) >> 12) & 0x1)
+#define   C_008D8C_ISOLATE_ES_ENABLE                   0xFFFFEFFF
+#define   S_008D8C_ISOLATE_GS_ENABLE(x)                (((x) & 0x1) << 13)
+#define   G_008D8C_ISOLATE_GS_ENABLE(x)                (((x) >> 13) & 0x1)
+#define   C_008D8C_ISOLATE_GS_ENABLE                   0xFFFFDFFF
+#define   S_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) & 0x1) << 14)
+#define   G_008D8C_VS_PC_LIMIT_ENABLE(x)               (((x) >> 14) & 0x1)
+#define   C_008D8C_VS_PC_LIMIT_ENABLE                  0xFFFFBFFF
+#define R_009508_TA_CNTL_AUX                         0x009508
+#define   S_009508_DISABLE_CUBE_WRAP(x)                (((x) & 0x1) << 0)
+#define   G_009508_DISABLE_CUBE_WRAP(x)                (((x) >> 0) & 0x1)
+#define   C_009508_DISABLE_CUBE_WRAP                   0xFFFFFFFE
+#define   S_009508_SYNC_GRADIENT(x)                    (((x) & 0x1) << 24)
+#define   G_009508_SYNC_GRADIENT(x)                    (((x) >> 24) & 0x1)
+#define   C_009508_SYNC_GRADIENT                       0xFEFFFFFF
+#define   S_009508_SYNC_WALKER(x)                      (((x) & 0x1) << 25)
+#define   G_009508_SYNC_WALKER(x)                      (((x) >> 25) & 0x1)
+#define   C_009508_SYNC_WALKER                         0xFDFFFFFF
+#define   S_009508_SYNC_ALIGNER(x)                     (((x) & 0x1) << 26)
+#define   G_009508_SYNC_ALIGNER(x)                     (((x) >> 26) & 0x1)
+#define   C_009508_SYNC_ALIGNER                        0xFBFFFFFF
+#define   S_009508_BILINEAR_PRECISION(x)               (((x) & 0x1) << 31)
+#define   G_009508_BILINEAR_PRECISION(x)               (((x) >> 31) & 0x1)
+#define   C_009508_BILINEAR_PRECISION                  0x7FFFFFFF
+#define R_009714_VC_ENHANCE                          0x009714
+#define R_009830_DB_DEBUG                            0x009830
+#define R_009838_DB_WATERMARKS                       0x009838
+#define   S_009838_DEPTH_FREE(x)                       (((x) & 0x1F) << 0)
+#define   G_009838_DEPTH_FREE(x)                       (((x) >> 0) & 0x1F)
+#define   C_009838_DEPTH_FREE                          0xFFFFFFE0
+#define   S_009838_DEPTH_FLUSH(x)                      (((x) & 0x3F) << 5)
+#define   G_009838_DEPTH_FLUSH(x)                      (((x) >> 5) & 0x3F)
+#define   C_009838_DEPTH_FLUSH                         0xFFFFF81F
+#define   S_009838_FORCE_SUMMARIZE(x)                  (((x) & 0xF) << 11)
+#define   G_009838_FORCE_SUMMARIZE(x)                  (((x) >> 11) & 0xF)
+#define   C_009838_FORCE_SUMMARIZE                     0xFFFF87FF
+#define   S_009838_DEPTH_PENDING_FREE(x)               (((x) & 0x1F) << 15)
+#define   G_009838_DEPTH_PENDING_FREE(x)               (((x) >> 15) & 0x1F)
+#define   C_009838_DEPTH_PENDING_FREE                  0xFFF07FFF
+#define   S_009838_DEPTH_CACHELINE_FREE(x)             (((x) & 0x1F) << 20)
+#define   G_009838_DEPTH_CACHELINE_FREE(x)             (((x) >> 20) & 0x1F)
+#define   C_009838_DEPTH_CACHELINE_FREE                0xFE0FFFFF
+#define   S_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) & 0x1) << 25)
+#define   G_009838_EARLY_Z_PANIC_DISABLE(x)            (((x) >> 25) & 0x1)
+#define   C_009838_EARLY_Z_PANIC_DISABLE               0xFDFFFFFF
+#define   S_009838_LATE_Z_PANIC_DISABLE(x)             (((x) & 0x1) << 26)
+#define   G_009838_LATE_Z_PANIC_DISABLE(x)             (((x) >> 26) & 0x1)
+#define   C_009838_LATE_Z_PANIC_DISABLE                0xFBFFFFFF
+#define   S_009838_RE_Z_PANIC_DISABLE(x)               (((x) & 0x1) << 27)
+#define   G_009838_RE_Z_PANIC_DISABLE(x)               (((x) >> 27) & 0x1)
+#define   C_009838_RE_Z_PANIC_DISABLE                  0xF7FFFFFF
+#define   S_009838_DB_EXTRA_DEBUG(x)                   (((x) & 0xF) << 28)
+#define   G_009838_DB_EXTRA_DEBUG(x)                   (((x) >> 28) & 0xF)
+#define   C_009838_DB_EXTRA_DEBUG                      0x0FFFFFFF
+#define R_028030_PA_SC_SCREEN_SCISSOR_TL             0x028030
+#define   S_028030_TL_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028030_TL_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028030_TL_X                                0xFFFF8000
+#define   S_028030_TL_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028030_TL_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028030_TL_Y                                0x8000FFFF
+#define R_028034_PA_SC_SCREEN_SCISSOR_BR             0x028034
+#define   S_028034_BR_X(x)                             (((x) & 0x7FFF) << 0)
+#define   G_028034_BR_X(x)                             (((x) >> 0) & 0x7FFF)
+#define   C_028034_BR_X                                0xFFFF8000
+#define   S_028034_BR_Y(x)                             (((x) & 0x7FFF) << 16)
+#define   G_028034_BR_Y(x)                             (((x) >> 16) & 0x7FFF)
+#define   C_028034_BR_Y                                0x8000FFFF
+#define R_028200_PA_SC_WINDOW_OFFSET                 0x028200
+#define   S_028200_WINDOW_X_OFFSET(x)                  (((x) & 0x7FFF) << 0)
+#define   G_028200_WINDOW_X_OFFSET(x)                  (((x) >> 0) & 0x7FFF)
+#define   C_028200_WINDOW_X_OFFSET                     0xFFFF8000
+#define   S_028200_WINDOW_Y_OFFSET(x)                  (((x) & 0x7FFF) << 16)
+#define   G_028200_WINDOW_Y_OFFSET(x)                  (((x) >> 16) & 0x7FFF)
+#define   C_028200_WINDOW_Y_OFFSET                     0x8000FFFF
+#define R_028204_PA_SC_WINDOW_SCISSOR_TL             0x028204
+#define   S_028204_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028204_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028204_TL_X                                0xFFFFC000
+#define   S_028204_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028204_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028204_TL_Y                                0xC000FFFF
+#define   S_028204_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028204_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028204_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028208_PA_SC_WINDOW_SCISSOR_BR             0x028208
+#define   S_028208_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028208_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028208_BR_X                                0xFFFFC000
+#define   S_028208_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028208_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028208_BR_Y                                0xC000FFFF
+#define R_02820C_PA_SC_CLIPRECT_RULE                 0x02820C
+#define   S_02820C_CLIP_RULE(x)                        (((x) & 0xFFFF) << 0)
+#define   G_02820C_CLIP_RULE(x)                        (((x) >> 0) & 0xFFFF)
+#define   C_02820C_CLIP_RULE                           0xFFFF0000
+#define R_028210_PA_SC_CLIPRECT_0_TL                 0x028210
+#define   S_028210_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028210_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028210_TL_X                                0xFFFFC000
+#define   S_028210_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028210_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028210_TL_Y                                0xC000FFFF
+#define R_028214_PA_SC_CLIPRECT_0_BR                 0x028214
+#define   S_028214_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028214_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028214_BR_X                                0xFFFFC000
+#define   S_028214_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028214_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028214_BR_Y                                0xC000FFFF
+#define R_028218_PA_SC_CLIPRECT_1_TL                 0x028218
+#define R_02821C_PA_SC_CLIPRECT_1_BR                 0x02821C
+#define R_028220_PA_SC_CLIPRECT_2_TL                 0x028220
+#define R_028224_PA_SC_CLIPRECT_2_BR                 0x028224
+#define R_028228_PA_SC_CLIPRECT_3_TL                 0x028228
+#define R_02822C_PA_SC_CLIPRECT_3_BR                 0x02822C
+#define R_028230_PA_SC_EDGERULE                      0x028230
+#define R_028240_PA_SC_GENERIC_SCISSOR_TL            0x028240
+#define   S_028240_TL_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028240_TL_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028240_TL_X                                0xFFFFC000
+#define   S_028240_TL_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028240_TL_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028240_TL_Y                                0xC000FFFF
+#define   S_028240_WINDOW_OFFSET_DISABLE(x)            (((x) & 0x1) << 31)
+#define   G_028240_WINDOW_OFFSET_DISABLE(x)            (((x) >> 31) & 0x1)
+#define   C_028240_WINDOW_OFFSET_DISABLE               0x7FFFFFFF
+#define R_028244_PA_SC_GENERIC_SCISSOR_BR            0x028244
+#define   S_028244_BR_X(x)                             (((x) & 0x3FFF) << 0)
+#define   G_028244_BR_X(x)                             (((x) >> 0) & 0x3FFF)
+#define   C_028244_BR_X                                0xFFFFC000
+#define   S_028244_BR_Y(x)                             (((x) & 0x3FFF) << 16)
+#define   G_028244_BR_Y(x)                             (((x) >> 16) & 0x3FFF)
+#define   C_028244_BR_Y                                0xC000FFFF
+#define R_0282D0_PA_SC_VPORT_ZMIN_0                  0x0282D0
+#define   S_0282D0_VPORT_ZMIN(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D0_VPORT_ZMIN(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D0_VPORT_ZMIN                          0x00000000
+#define R_0282D4_PA_SC_VPORT_ZMAX_0                  0x0282D4
+#define   S_0282D4_VPORT_ZMAX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_0282D4_VPORT_ZMAX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0282D4_VPORT_ZMAX                          0x00000000
+#define R_028350_SX_MISC                             0x028350
+#define   S_028350_MULTIPASS(x)                        (((x) & 0x1) << 0)
+#define   G_028350_MULTIPASS(x)                        (((x) >> 0) & 0x1)
+#define   C_028350_MULTIPASS                           0xFFFFFFFE
+#define R_028380_SQ_VTX_SEMANTIC_0                   0x028380
+#define   S_028380_SEMANTIC_ID(x)                      (((x) & 0xFF) << 0)
+#define   G_028380_SEMANTIC_ID(x)                      (((x) >> 0) & 0xFF)
+#define   C_028380_SEMANTIC_ID                         0xFFFFFF00
+#define R_028384_SQ_VTX_SEMANTIC_1                   0x028384
+#define R_028388_SQ_VTX_SEMANTIC_2                   0x028388
+#define R_02838C_SQ_VTX_SEMANTIC_3                   0x02838C
+#define R_028390_SQ_VTX_SEMANTIC_4                   0x028390
+#define R_028394_SQ_VTX_SEMANTIC_5                   0x028394
+#define R_028398_SQ_VTX_SEMANTIC_6                   0x028398
+#define R_02839C_SQ_VTX_SEMANTIC_7                   0x02839C
+#define R_0283A0_SQ_VTX_SEMANTIC_8                   0x0283A0
+#define R_0283A4_SQ_VTX_SEMANTIC_9                   0x0283A4
+#define R_0283A8_SQ_VTX_SEMANTIC_10                  0x0283A8
+#define R_0283AC_SQ_VTX_SEMANTIC_11                  0x0283AC
+#define R_0283B0_SQ_VTX_SEMANTIC_12                  0x0283B0
+#define R_0283B4_SQ_VTX_SEMANTIC_13                  0x0283B4
+#define R_0283B8_SQ_VTX_SEMANTIC_14                  0x0283B8
+#define R_0283BC_SQ_VTX_SEMANTIC_15                  0x0283BC
+#define R_0283C0_SQ_VTX_SEMANTIC_16                  0x0283C0
+#define R_0283C4_SQ_VTX_SEMANTIC_17                  0x0283C4
+#define R_0283C8_SQ_VTX_SEMANTIC_18                  0x0283C8
+#define R_0283CC_SQ_VTX_SEMANTIC_19                  0x0283CC
+#define R_0283D0_SQ_VTX_SEMANTIC_20                  0x0283D0
+#define R_0283D4_SQ_VTX_SEMANTIC_21                  0x0283D4
+#define R_0283D8_SQ_VTX_SEMANTIC_22                  0x0283D8
+#define R_0283DC_SQ_VTX_SEMANTIC_23                  0x0283DC
+#define R_0283E0_SQ_VTX_SEMANTIC_24                  0x0283E0
+#define R_0283E4_SQ_VTX_SEMANTIC_25                  0x0283E4
+#define R_0283E8_SQ_VTX_SEMANTIC_26                  0x0283E8
+#define R_0283EC_SQ_VTX_SEMANTIC_27                  0x0283EC
+#define R_0283F0_SQ_VTX_SEMANTIC_28                  0x0283F0
+#define R_0283F4_SQ_VTX_SEMANTIC_29                  0x0283F4
+#define R_0283F8_SQ_VTX_SEMANTIC_30                  0x0283F8
+#define R_0283FC_SQ_VTX_SEMANTIC_31                  0x0283FC
+#define R_028400_VGT_MAX_VTX_INDX                    0x028400
+#define   S_028400_MAX_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028400_MAX_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028400_MAX_INDX                            0x00000000
+#define R_028404_VGT_MIN_VTX_INDX                    0x028404
+#define   S_028404_MIN_INDX(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028404_MIN_INDX(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028404_MIN_INDX                            0x00000000
+#define R_028408_VGT_INDX_OFFSET                     0x028408
+#define   S_028408_INDX_OFFSET(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028408_INDX_OFFSET(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028408_INDX_OFFSET                         0x00000000
+#define R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX        0x02840C
+#define   S_02840C_RESET_INDX(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02840C_RESET_INDX(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02840C_RESET_INDX                          0x00000000
+#define R_028410_SX_ALPHA_TEST_CONTROL               0x028410
+#define   S_028410_ALPHA_FUNC(x)                       (((x) & 0x7) << 0)
+#define   G_028410_ALPHA_FUNC(x)                       (((x) >> 0) & 0x7)
+#define   C_028410_ALPHA_FUNC                          0xFFFFFFF8
+#define   S_028410_ALPHA_TEST_ENABLE(x)                (((x) & 0x1) << 3)
+#define   G_028410_ALPHA_TEST_ENABLE(x)                (((x) >> 3) & 0x1)
+#define   C_028410_ALPHA_TEST_ENABLE                   0xFFFFFFF7
+#define   S_028410_ALPHA_TEST_BYPASS(x)                (((x) & 0x1) << 8)
+#define   G_028410_ALPHA_TEST_BYPASS(x)                (((x) >> 8) & 0x1)
+#define   C_028410_ALPHA_TEST_BYPASS                   0xFFFFFEFF
+#define R_028414_CB_BLEND_RED                        0x028414
+#define   S_028414_BLEND_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028414_BLEND_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028414_BLEND_RED                           0x00000000
+#define R_028418_CB_BLEND_GREEN                      0x028418
+#define   S_028418_BLEND_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028418_BLEND_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028418_BLEND_GREEN                         0x00000000
+#define R_02841C_CB_BLEND_BLUE                       0x02841C
+#define   S_02841C_BLEND_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_02841C_BLEND_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02841C_BLEND_BLUE                          0x00000000
+#define R_028420_CB_BLEND_ALPHA                      0x028420
+#define   S_028420_BLEND_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028420_BLEND_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028420_BLEND_ALPHA                         0x00000000
+#define R_028438_SX_ALPHA_REF                        0x028438
+#define   S_028438_ALPHA_REF(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028438_ALPHA_REF(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028438_ALPHA_REF                           0x00000000
+#define R_0286C8_SPI_THREAD_GROUPING                 0x0286C8
+#define   S_0286C8_PS_GROUPING(x)                      (((x) & 0x1F) << 0)
+#define   G_0286C8_PS_GROUPING(x)                      (((x) >> 0) & 0x1F)
+#define   C_0286C8_PS_GROUPING                         0xFFFFFFE0
+#define   S_0286C8_VS_GROUPING(x)                      (((x) & 0x1F) << 8)
+#define   G_0286C8_VS_GROUPING(x)                      (((x) >> 8) & 0x1F)
+#define   C_0286C8_VS_GROUPING                         0xFFFFE0FF
+#define   S_0286C8_GS_GROUPING(x)                      (((x) & 0x1F) << 16)
+#define   G_0286C8_GS_GROUPING(x)                      (((x) >> 16) & 0x1F)
+#define   C_0286C8_GS_GROUPING                         0xFFE0FFFF
+#define   S_0286C8_ES_GROUPING(x)                      (((x) & 0x1F) << 24)
+#define   G_0286C8_ES_GROUPING(x)                      (((x) >> 24) & 0x1F)
+#define   C_0286C8_ES_GROUPING                         0xE0FFFFFF
+#define R_0286D8_SPI_INPUT_Z                         0x0286D8
+#define   S_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) & 0x1) << 0)
+#define   G_0286D8_PROVIDE_Z_TO_SPI(x)                 (((x) >> 0) & 0x1)
+#define   C_0286D8_PROVIDE_Z_TO_SPI                    0xFFFFFFFE
+#define R_0286DC_SPI_FOG_CNTL                        0x0286DC
+#define   S_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) & 0x1) << 0)
+#define   G_0286DC_PASS_FOG_THROUGH_PS(x)              (((x) >> 0) & 0x1)
+#define   C_0286DC_PASS_FOG_THROUGH_PS                 0xFFFFFFFE
+#define   S_0286DC_PIXEL_FOG_FUNC(x)                   (((x) & 0x3) << 1)
+#define   G_0286DC_PIXEL_FOG_FUNC(x)                   (((x) >> 1) & 0x3)
+#define   C_0286DC_PIXEL_FOG_FUNC                      0xFFFFFFF9
+#define   S_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) & 0x1) << 3)
+#define   G_0286DC_PIXEL_FOG_SRC_SEL(x)                (((x) >> 3) & 0x1)
+#define   C_0286DC_PIXEL_FOG_SRC_SEL                   0xFFFFFFF7
+#define   S_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) & 0x1) << 4)
+#define   G_0286DC_VS_FOG_CLAMP_DISABLE(x)             (((x) >> 4) & 0x1)
+#define   C_0286DC_VS_FOG_CLAMP_DISABLE                0xFFFFFFEF
+#define R_0286E0_SPI_FOG_FUNC_SCALE                  0x0286E0
+#define   S_0286E0_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E0_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E0_VALUE                               0x00000000
+#define R_0286E4_SPI_FOG_FUNC_BIAS                   0x0286E4
+#define   S_0286E4_VALUE(x)                            (((x) & 0xFFFFFFFF) << 0)
+#define   G_0286E4_VALUE(x)                            (((x) >> 0) & 0xFFFFFFFF)
+#define   C_0286E4_VALUE                               0x00000000
+#define R_0287A0_CB_SHADER_CONTROL                   0x0287A0
+#define   S_0287A0_RT0_ENABLE(x)                       (((x) & 0x1) << 0)
+#define   G_0287A0_RT0_ENABLE(x)                       (((x) >> 0) & 0x1)
+#define   C_0287A0_RT0_ENABLE                          0xFFFFFFFE
+#define   S_0287A0_RT1_ENABLE(x)                       (((x) & 0x1) << 1)
+#define   G_0287A0_RT1_ENABLE(x)                       (((x) >> 1) & 0x1)
+#define   C_0287A0_RT1_ENABLE                          0xFFFFFFFD
+#define   S_0287A0_RT2_ENABLE(x)                       (((x) & 0x1) << 2)
+#define   G_0287A0_RT2_ENABLE(x)                       (((x) >> 2) & 0x1)
+#define   C_0287A0_RT2_ENABLE                          0xFFFFFFFB
+#define   S_0287A0_RT3_ENABLE(x)                       (((x) & 0x1) << 3)
+#define   G_0287A0_RT3_ENABLE(x)                       (((x) >> 3) & 0x1)
+#define   C_0287A0_RT3_ENABLE                          0xFFFFFFF7
+#define   S_0287A0_RT4_ENABLE(x)                       (((x) & 0x1) << 4)
+#define   G_0287A0_RT4_ENABLE(x)                       (((x) >> 4) & 0x1)
+#define   C_0287A0_RT4_ENABLE                          0xFFFFFFEF
+#define   S_0287A0_RT5_ENABLE(x)                       (((x) & 0x1) << 5)
+#define   G_0287A0_RT5_ENABLE(x)                       (((x) >> 5) & 0x1)
+#define   C_0287A0_RT5_ENABLE                          0xFFFFFFDF
+#define   S_0287A0_RT6_ENABLE(x)                       (((x) & 0x1) << 6)
+#define   G_0287A0_RT6_ENABLE(x)                       (((x) >> 6) & 0x1)
+#define   C_0287A0_RT6_ENABLE                          0xFFFFFFBF
+#define   S_0287A0_RT7_ENABLE(x)                       (((x) & 0x1) << 7)
+#define   G_0287A0_RT7_ENABLE(x)                       (((x) >> 7) & 0x1)
+#define   C_0287A0_RT7_ENABLE                          0xFFFFFF7F
+#define R_028894_SQ_PGM_START_FS                     0x028894
+#define   S_028894_PGM_START(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028894_PGM_START(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028894_PGM_START                           0x00000000
+#define R_0288A4_SQ_PGM_RESOURCES_FS                 0x0288A4
+#define   S_0288A4_NUM_GPRS(x)                         (((x) & 0xFF) << 0)
+#define   G_0288A4_NUM_GPRS(x)                         (((x) >> 0) & 0xFF)
+#define   C_0288A4_NUM_GPRS                            0xFFFFFF00
+#define   S_0288A4_STACK_SIZE(x)                       (((x) & 0xFF) << 8)
+#define   G_0288A4_STACK_SIZE(x)                       (((x) >> 8) & 0xFF)
+#define   C_0288A4_STACK_SIZE                          0xFFFF00FF
+#define   S_0288A4_DX10_CLAMP(x)                       (((x) & 0x1) << 21)
+#define   G_0288A4_DX10_CLAMP(x)                       (((x) >> 21) & 0x1)
+#define   C_0288A4_DX10_CLAMP                          0xFFDFFFFF
+#define R_0288A8_SQ_ESGS_RING_ITEMSIZE               0x0288A8
+#define   S_0288A8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288A8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288A8_ITEMSIZE                            0xFFFF8000
+#define R_0288AC_SQ_GSVS_RING_ITEMSIZE               0x0288AC
+#define   S_0288AC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288AC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288AC_ITEMSIZE                            0xFFFF8000
+#define R_0288B0_SQ_ESTMP_RING_ITEMSIZE              0x0288B0
+#define   S_0288B0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B0_ITEMSIZE                            0xFFFF8000
+#define R_0288B4_SQ_GSTMP_RING_ITEMSIZE              0x0288B4
+#define   S_0288B4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B4_ITEMSIZE                            0xFFFF8000
+#define R_0288B8_SQ_VSTMP_RING_ITEMSIZE              0x0288B8
+#define   S_0288B8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288B8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288B8_ITEMSIZE                            0xFFFF8000
+#define R_0288BC_SQ_PSTMP_RING_ITEMSIZE              0x0288BC
+#define   S_0288BC_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288BC_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288BC_ITEMSIZE                            0xFFFF8000
+#define R_0288C0_SQ_FBUF_RING_ITEMSIZE               0x0288C0
+#define   S_0288C0_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C0_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C0_ITEMSIZE                            0xFFFF8000
+#define R_0288C4_SQ_REDUC_RING_ITEMSIZE              0x0288C4
+#define   S_0288C4_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C4_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C4_ITEMSIZE                            0xFFFF8000
+#define R_0288C8_SQ_GS_VERT_ITEMSIZE                 0x0288C8
+#define   S_0288C8_ITEMSIZE(x)                         (((x) & 0x7FFF) << 0)
+#define   G_0288C8_ITEMSIZE(x)                         (((x) >> 0) & 0x7FFF)
+#define   C_0288C8_ITEMSIZE                            0xFFFF8000
+#define R_0288DC_SQ_PGM_CF_OFFSET_FS                 0x0288DC
+#define   S_0288DC_PGM_CF_OFFSET(x)                    (((x) & 0xFFFFF) << 0)
+#define   G_0288DC_PGM_CF_OFFSET(x)                    (((x) >> 0) & 0xFFFFF)
+#define   C_0288DC_PGM_CF_OFFSET                       0xFFF00000
+#define R_028A10_VGT_OUTPUT_PATH_CNTL                0x028A10
+#define   S_028A10_PATH_SELECT(x)                      (((x) & 0x3) << 0)
+#define   G_028A10_PATH_SELECT(x)                      (((x) >> 0) & 0x3)
+#define   C_028A10_PATH_SELECT                         0xFFFFFFFC
+#define R_028A14_VGT_HOS_CNTL                        0x028A14
+#define   S_028A14_TESS_MODE(x)                        (((x) & 0x3) << 0)
+#define   G_028A14_TESS_MODE(x)                        (((x) >> 0) & 0x3)
+#define   C_028A14_TESS_MODE                           0xFFFFFFFC
+#define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x028A18
+#define   S_028A18_MAX_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A18_MAX_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A18_MAX_TESS                            0x00000000
+#define R_028A1C_VGT_HOS_MIN_TESS_LEVEL              0x028A1C
+#define   S_028A1C_MIN_TESS(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_028A1C_MIN_TESS(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028A1C_MIN_TESS                            0x00000000
+#define R_028A20_VGT_HOS_REUSE_DEPTH                 0x028A20
+#define   S_028A20_REUSE_DEPTH(x)                      (((x) & 0xFF) << 0)
+#define   G_028A20_REUSE_DEPTH(x)                      (((x) >> 0) & 0xFF)
+#define   C_028A20_REUSE_DEPTH                         0xFFFFFF00
+#define R_028A24_VGT_GROUP_PRIM_TYPE                 0x028A24
+#define   S_028A24_PRIM_TYPE(x)                        (((x) & 0x1F) << 0)
+#define   G_028A24_PRIM_TYPE(x)                        (((x) >> 0) & 0x1F)
+#define   C_028A24_PRIM_TYPE                           0xFFFFFFE0
+#define   S_028A24_RETAIN_ORDER(x)                     (((x) & 0x1) << 14)
+#define   G_028A24_RETAIN_ORDER(x)                     (((x) >> 14) & 0x1)
+#define   C_028A24_RETAIN_ORDER                        0xFFFFBFFF
+#define   S_028A24_RETAIN_QUADS(x)                     (((x) & 0x1) << 15)
+#define   G_028A24_RETAIN_QUADS(x)                     (((x) >> 15) & 0x1)
+#define   C_028A24_RETAIN_QUADS                        0xFFFF7FFF
+#define   S_028A24_PRIM_ORDER(x)                       (((x) & 0x7) << 16)
+#define   G_028A24_PRIM_ORDER(x)                       (((x) >> 16) & 0x7)
+#define   C_028A24_PRIM_ORDER                          0xFFF8FFFF
+#define R_028A28_VGT_GROUP_FIRST_DECR                0x028A28
+#define   S_028A28_FIRST_DECR(x)                       (((x) & 0xF) << 0)
+#define   G_028A28_FIRST_DECR(x)                       (((x) >> 0) & 0xF)
+#define   C_028A28_FIRST_DECR                          0xFFFFFFF0
+#define R_028A2C_VGT_GROUP_DECR                      0x028A2C
+#define   S_028A2C_DECR(x)                             (((x) & 0xF) << 0)
+#define   G_028A2C_DECR(x)                             (((x) >> 0) & 0xF)
+#define   C_028A2C_DECR                                0xFFFFFFF0
+#define R_028A30_VGT_GROUP_VECT_0_CNTL               0x028A30
+#define   S_028A30_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A30_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A30_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A30_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A30_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A30_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A30_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A30_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A30_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A30_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A30_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A30_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A30_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A30_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A30_STRIDE                              0xFFFF00FF
+#define   S_028A30_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A30_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A30_SHIFT                               0xFF00FFFF
+#define R_028A34_VGT_GROUP_VECT_1_CNTL               0x028A34
+#define   S_028A34_COMP_X_EN(x)                        (((x) & 0x1) << 0)
+#define   G_028A34_COMP_X_EN(x)                        (((x) >> 0) & 0x1)
+#define   C_028A34_COMP_X_EN                           0xFFFFFFFE
+#define   S_028A34_COMP_Y_EN(x)                        (((x) & 0x1) << 1)
+#define   G_028A34_COMP_Y_EN(x)                        (((x) >> 1) & 0x1)
+#define   C_028A34_COMP_Y_EN                           0xFFFFFFFD
+#define   S_028A34_COMP_Z_EN(x)                        (((x) & 0x1) << 2)
+#define   G_028A34_COMP_Z_EN(x)                        (((x) >> 2) & 0x1)
+#define   C_028A34_COMP_Z_EN                           0xFFFFFFFB
+#define   S_028A34_COMP_W_EN(x)                        (((x) & 0x1) << 3)
+#define   G_028A34_COMP_W_EN(x)                        (((x) >> 3) & 0x1)
+#define   C_028A34_COMP_W_EN                           0xFFFFFFF7
+#define   S_028A34_STRIDE(x)                           (((x) & 0xFF) << 8)
+#define   G_028A34_STRIDE(x)                           (((x) >> 8) & 0xFF)
+#define   C_028A34_STRIDE                              0xFFFF00FF
+#define   S_028A34_SHIFT(x)                            (((x) & 0xFF) << 16)
+#define   G_028A34_SHIFT(x)                            (((x) >> 16) & 0xFF)
+#define   C_028A34_SHIFT                               0xFF00FFFF
+#define R_028A38_VGT_GROUP_VECT_0_FMT_CNTL           0x028A38
+#define   S_028A38_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A38_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A38_X_CONV                              0xFFFFFFF0
+#define   S_028A38_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A38_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A38_X_OFFSET                            0xFFFFFF0F
+#define   S_028A38_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A38_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A38_Y_CONV                              0xFFFFF0FF
+#define   S_028A38_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A38_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A38_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A38_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A38_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A38_Z_CONV                              0xFFF0FFFF
+#define   S_028A38_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A38_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A38_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A38_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A38_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A38_W_CONV                              0xF0FFFFFF
+#define   S_028A38_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A38_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A38_W_OFFSET                            0x0FFFFFFF
+#define R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL           0x028A3C
+#define   S_028A3C_X_CONV(x)                           (((x) & 0xF) << 0)
+#define   G_028A3C_X_CONV(x)                           (((x) >> 0) & 0xF)
+#define   C_028A3C_X_CONV                              0xFFFFFFF0
+#define   S_028A3C_X_OFFSET(x)                         (((x) & 0xF) << 4)
+#define   G_028A3C_X_OFFSET(x)                         (((x) >> 4) & 0xF)
+#define   C_028A3C_X_OFFSET                            0xFFFFFF0F
+#define   S_028A3C_Y_CONV(x)                           (((x) & 0xF) << 8)
+#define   G_028A3C_Y_CONV(x)                           (((x) >> 8) & 0xF)
+#define   C_028A3C_Y_CONV                              0xFFFFF0FF
+#define   S_028A3C_Y_OFFSET(x)                         (((x) & 0xF) << 12)
+#define   G_028A3C_Y_OFFSET(x)                         (((x) >> 12) & 0xF)
+#define   C_028A3C_Y_OFFSET                            0xFFFF0FFF
+#define   S_028A3C_Z_CONV(x)                           (((x) & 0xF) << 16)
+#define   G_028A3C_Z_CONV(x)                           (((x) >> 16) & 0xF)
+#define   C_028A3C_Z_CONV                              0xFFF0FFFF
+#define   S_028A3C_Z_OFFSET(x)                         (((x) & 0xF) << 20)
+#define   G_028A3C_Z_OFFSET(x)                         (((x) >> 20) & 0xF)
+#define   C_028A3C_Z_OFFSET                            0xFF0FFFFF
+#define   S_028A3C_W_CONV(x)                           (((x) & 0xF) << 24)
+#define   G_028A3C_W_CONV(x)                           (((x) >> 24) & 0xF)
+#define   C_028A3C_W_CONV                              0xF0FFFFFF
+#define   S_028A3C_W_OFFSET(x)                         (((x) & 0xF) << 28)
+#define   G_028A3C_W_OFFSET(x)                         (((x) >> 28) & 0xF)
+#define   C_028A3C_W_OFFSET                            0x0FFFFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
+#define R_028A4C_PA_SC_MODE_CNTL                     0x028A4C
+#define   S_028A4C_MSAA_ENABLE(x)                      (((x) & 0x1) << 0)
+#define   G_028A4C_MSAA_ENABLE(x)                      (((x) >> 0) & 0x1)
+#define   C_028A4C_MSAA_ENABLE                         0xFFFFFFFE
+#define   S_028A4C_CLIPRECT_ENABLE(x)                  (((x) & 0x1) << 1)
+#define   G_028A4C_CLIPRECT_ENABLE(x)                  (((x) >> 1) & 0x1)
+#define   C_028A4C_CLIPRECT_ENABLE                     0xFFFFFFFD
+#define   S_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) & 0x1) << 2)
+#define   G_028A4C_LINE_STIPPLE_ENABLE(x)              (((x) >> 2) & 0x1)
+#define   C_028A4C_LINE_STIPPLE_ENABLE                 0xFFFFFFFB
+#define   S_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) & 0x1) << 3)
+#define   G_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB(x)     (((x) >> 3) & 0x1)
+#define   C_028A4C_MULTI_CHIP_PRIM_DISCARD_ENAB        0xFFFFFFF7
+#define   S_028A4C_WALK_ORDER_ENABLE(x)                (((x) & 0x1) << 4)
+#define   G_028A4C_WALK_ORDER_ENABLE(x)                (((x) >> 4) & 0x1)
+#define   C_028A4C_WALK_ORDER_ENABLE                   0xFFFFFFEF
+#define   S_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) & 0x1) << 5)
+#define   G_028A4C_HALVE_DETAIL_SAMPLE_PERF(x)         (((x) >> 5) & 0x1)
+#define   C_028A4C_HALVE_DETAIL_SAMPLE_PERF            0xFFFFFFDF
+#define   S_028A4C_WALK_SIZE(x)                        (((x) & 0x1) << 6)
+#define   G_028A4C_WALK_SIZE(x)                        (((x) >> 6) & 0x1)
+#define   C_028A4C_WALK_SIZE                           0xFFFFFFBF
+#define   S_028A4C_WALK_ALIGNMENT(x)                   (((x) & 0x1) << 7)
+#define   G_028A4C_WALK_ALIGNMENT(x)                   (((x) >> 7) & 0x1)
+#define   C_028A4C_WALK_ALIGNMENT                      0xFFFFFF7F
+#define   S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) & 0x1) << 8)
+#define   G_028A4C_WALK_ALIGN8_PRIM_FITS_ST(x)         (((x) >> 8) & 0x1)
+#define   C_028A4C_WALK_ALIGN8_PRIM_FITS_ST            0xFFFFFEFF
+#define   S_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) & 0x1) << 9)
+#define   G_028A4C_TILE_COVER_NO_SCISSOR(x)            (((x) >> 9) & 0x1)
+#define   C_028A4C_TILE_COVER_NO_SCISSOR               0xFFFFFDFF
+#define   S_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) & 0x1) << 10)
+#define   G_028A4C_KILL_PIX_POST_HI_Z(x)               (((x) >> 10) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_HI_Z                  0xFFFFFBFF
+#define   S_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) & 0x1) << 11)
+#define   G_028A4C_KILL_PIX_POST_DETAIL_MASK(x)        (((x) >> 11) & 0x1)
+#define   C_028A4C_KILL_PIX_POST_DETAIL_MASK           0xFFFFF7FF
+#define   S_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) & 0x1) << 12)
+#define   G_028A4C_MULTI_CHIP_SUPERTILE_ENABLE(x)      (((x) >> 12) & 0x1)
+#define   C_028A4C_MULTI_CHIP_SUPERTILE_ENABLE         0xFFFFEFFF
+#define   S_028A4C_TILE_COVER_DISABLE(x)               (((x) & 0x1) << 13)
+#define   G_028A4C_TILE_COVER_DISABLE(x)               (((x) >> 13) & 0x1)
+#define   C_028A4C_TILE_COVER_DISABLE                  0xFFFFDFFF
+#define   S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) & 0x1) << 14)
+#define   G_028A4C_FORCE_EOV_CNTDWN_ENABLE(x)          (((x) >> 14) & 0x1)
+#define   C_028A4C_FORCE_EOV_CNTDWN_ENABLE             0xFFFFBFFF
+#define   S_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) & 0x1) << 15)
+#define   G_028A4C_FORCE_EOV_TILE_ENABLE(x)            (((x) >> 15) & 0x1)
+#define   C_028A4C_FORCE_EOV_TILE_ENABLE               0xFFFF7FFF
+#define   S_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) & 0x1) << 16)
+#define   G_028A4C_FORCE_EOV_REZ_ENABLE(x)             (((x) >> 16) & 0x1)
+#define   C_028A4C_FORCE_EOV_REZ_ENABLE                0xFFFEFFFF
+#define   S_028A4C_PS_ITER_SAMPLE(x)                   (((x) & 0x1) << 17)
+#define   G_028A4C_PS_ITER_SAMPLE(x)                   (((x) >> 17) & 0x1)
+#define   C_028A4C_PS_ITER_SAMPLE                      0xFFFDFFFF
+#define R_028A84_VGT_PRIMITIVEID_EN                  0x028A84
+#define   S_028A84_PRIMITIVEID_EN(x)                   (((x) & 0x1) << 0)
+#define   G_028A84_PRIMITIVEID_EN(x)                   (((x) >> 0) & 0x1)
+#define   C_028A84_PRIMITIVEID_EN                      0xFFFFFFFE
+#define R_028A94_VGT_MULTI_PRIM_IB_RESET_EN          0x028A94
+#define   S_028A94_RESET_EN(x)                         (((x) & 0x1) << 0)
+#define   G_028A94_RESET_EN(x)                         (((x) >> 0) & 0x1)
+#define   C_028A94_RESET_EN                            0xFFFFFFFE
+#define R_028AA0_VGT_INSTANCE_STEP_RATE_0            0x028AA0
+#define   S_028AA0_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA0_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA0_STEP_RATE                           0x00000000
+#define R_028AA4_VGT_INSTANCE_STEP_RATE_1            0x028AA4
+#define   S_028AA4_STEP_RATE(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028AA4_STEP_RATE(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028AA4_STEP_RATE                           0x00000000
+#define R_028AB0_VGT_STRMOUT_EN                      0x028AB0
+#define   S_028AB0_STREAMOUT(x)                        (((x) & 0x1) << 0)
+#define   G_028AB0_STREAMOUT(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB0_STREAMOUT                           0xFFFFFFFE
+#define R_028AB4_VGT_REUSE_OFF                       0x028AB4
+#define   S_028AB4_REUSE_OFF(x)                        (((x) & 0x1) << 0)
+#define   G_028AB4_REUSE_OFF(x)                        (((x) >> 0) & 0x1)
+#define   C_028AB4_REUSE_OFF                           0xFFFFFFFE
+#define R_028AB8_VGT_VTX_CNT_EN                      0x028AB8
+#define   S_028AB8_VTX_CNT_EN(x)                       (((x) & 0x1) << 0)
+#define   G_028AB8_VTX_CNT_EN(x)                       (((x) >> 0) & 0x1)
+#define   C_028AB8_VTX_CNT_EN                          0xFFFFFFFE
+#define R_028B20_VGT_STRMOUT_BUFFER_EN               0x028B20
+#define   S_028B20_BUFFER_0_EN(x)                      (((x) & 0x1) << 0)
+#define   G_028B20_BUFFER_0_EN(x)                      (((x) >> 0) & 0x1)
+#define   C_028B20_BUFFER_0_EN                         0xFFFFFFFE
+#define   S_028B20_BUFFER_1_EN(x)                      (((x) & 0x1) << 1)
+#define   G_028B20_BUFFER_1_EN(x)                      (((x) >> 1) & 0x1)
+#define   C_028B20_BUFFER_1_EN                         0xFFFFFFFD
+#define   S_028B20_BUFFER_2_EN(x)                      (((x) & 0x1) << 2)
+#define   G_028B20_BUFFER_2_EN(x)                      (((x) >> 2) & 0x1)
+#define   C_028B20_BUFFER_2_EN                         0xFFFFFFFB
+#define   S_028B20_BUFFER_3_EN(x)                      (((x) & 0x1) << 3)
+#define   G_028B20_BUFFER_3_EN(x)                      (((x) >> 3) & 0x1)
+#define   C_028B20_BUFFER_3_EN                         0xFFFFFFF7
+#define R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX    0x028C20
+#define   S_028C20_S4_X(x)                             (((x) & 0xF) << 0)
+#define   G_028C20_S4_X(x)                             (((x) >> 0) & 0xF)
+#define   C_028C20_S4_X                                0xFFFFFFF0
+#define   S_028C20_S4_Y(x)                             (((x) & 0xF) << 4)
+#define   G_028C20_S4_Y(x)                             (((x) >> 4) & 0xF)
+#define   C_028C20_S4_Y                                0xFFFFFF0F
+#define   S_028C20_S5_X(x)                             (((x) & 0xF) << 8)
+#define   G_028C20_S5_X(x)                             (((x) >> 8) & 0xF)
+#define   C_028C20_S5_X                                0xFFFFF0FF
+#define   S_028C20_S5_Y(x)                             (((x) & 0xF) << 12)
+#define   G_028C20_S5_Y(x)                             (((x) >> 12) & 0xF)
+#define   C_028C20_S5_Y                                0xFFFF0FFF
+#define   S_028C20_S6_X(x)                             (((x) & 0xF) << 16)
+#define   G_028C20_S6_X(x)                             (((x) >> 16) & 0xF)
+#define   C_028C20_S6_X                                0xFFF0FFFF
+#define   S_028C20_S6_Y(x)                             (((x) & 0xF) << 20)
+#define   G_028C20_S6_Y(x)                             (((x) >> 20) & 0xF)
+#define   C_028C20_S6_Y                                0xFF0FFFFF
+#define   S_028C20_S7_X(x)                             (((x) & 0xF) << 24)
+#define   G_028C20_S7_X(x)                             (((x) >> 24) & 0xF)
+#define   C_028C20_S7_X                                0xF0FFFFFF
+#define   S_028C20_S7_Y(x)                             (((x) & 0xF) << 28)
+#define   G_028C20_S7_Y(x)                             (((x) >> 28) & 0xF)
+#define   C_028C20_S7_Y                                0x0FFFFFFF
+#define R_028C30_CB_CLRCMP_CONTROL                   0x028C30
+#define   S_028C30_CLRCMP_FCN_SRC(x)                   (((x) & 0x7) << 0)
+#define   G_028C30_CLRCMP_FCN_SRC(x)                   (((x) >> 0) & 0x7)
+#define   C_028C30_CLRCMP_FCN_SRC                      0xFFFFFFF8
+#define   S_028C30_CLRCMP_FCN_DST(x)                   (((x) & 0x7) << 8)
+#define   G_028C30_CLRCMP_FCN_DST(x)                   (((x) >> 8) & 0x7)
+#define   C_028C30_CLRCMP_FCN_DST                      0xFFFFF8FF
+#define   S_028C30_CLRCMP_FCN_SEL(x)                   (((x) & 0x3) << 24)
+#define   G_028C30_CLRCMP_FCN_SEL(x)                   (((x) >> 24) & 0x3)
+#define   C_028C30_CLRCMP_FCN_SEL                      0xFCFFFFFF
+#define R_028C34_CB_CLRCMP_SRC                       0x028C34
+#define   S_028C34_CLRCMP_SRC(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C34_CLRCMP_SRC(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C34_CLRCMP_SRC                          0x00000000
+#define R_028C38_CB_CLRCMP_DST                       0x028C38
+#define   S_028C38_CLRCMP_DST(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C38_CLRCMP_DST(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C38_CLRCMP_DST                          0x00000000
+#define R_028C3C_CB_CLRCMP_MSK                       0x028C3C
+#define   S_028C3C_CLRCMP_MSK(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028C3C_CLRCMP_MSK(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028C3C_CLRCMP_MSK                          0x00000000
+#define R_0085F0_CP_COHER_CNTL                       0x0085F0
+#define   S_0085F0_DEST_BASE_0_ENA(x)                  (((x) & 0x1) << 0)
+#define   G_0085F0_DEST_BASE_0_ENA(x)                  (((x) >> 0) & 0x1)
+#define   C_0085F0_DEST_BASE_0_ENA                     0xFFFFFFFE
+#define   S_0085F0_DEST_BASE_1_ENA(x)                  (((x) & 0x1) << 1)
+#define   G_0085F0_DEST_BASE_1_ENA(x)                  (((x) >> 1) & 0x1)
+#define   C_0085F0_DEST_BASE_1_ENA                     0xFFFFFFFD
+#define   S_0085F0_SO0_DEST_BASE_ENA(x)                (((x) & 0x1) << 2)
+#define   G_0085F0_SO0_DEST_BASE_ENA(x)                (((x) >> 2) & 0x1)
+#define   C_0085F0_SO0_DEST_BASE_ENA                   0xFFFFFFFB
+#define   S_0085F0_SO1_DEST_BASE_ENA(x)                (((x) & 0x1) << 3)
+#define   G_0085F0_SO1_DEST_BASE_ENA(x)                (((x) >> 3) & 0x1)
+#define   C_0085F0_SO1_DEST_BASE_ENA                   0xFFFFFFF7
+#define   S_0085F0_SO2_DEST_BASE_ENA(x)                (((x) & 0x1) << 4)
+#define   G_0085F0_SO2_DEST_BASE_ENA(x)                (((x) >> 4) & 0x1)
+#define   C_0085F0_SO2_DEST_BASE_ENA                   0xFFFFFFEF
+#define   S_0085F0_SO3_DEST_BASE_ENA(x)                (((x) & 0x1) << 5)
+#define   G_0085F0_SO3_DEST_BASE_ENA(x)                (((x) >> 5) & 0x1)
+#define   C_0085F0_SO3_DEST_BASE_ENA                   0xFFFFFFDF
+#define   S_0085F0_CB0_DEST_BASE_ENA(x)                (((x) & 0x1) << 6)
+#define   G_0085F0_CB0_DEST_BASE_ENA(x)                (((x) >> 6) & 0x1)
+#define   C_0085F0_CB0_DEST_BASE_ENA                   0xFFFFFFBF
+#define   S_0085F0_CB1_DEST_BASE_ENA(x)                (((x) & 0x1) << 7)
+#define   G_0085F0_CB1_DEST_BASE_ENA(x)                (((x) >> 7) & 0x1)
+#define   C_0085F0_CB1_DEST_BASE_ENA                   0xFFFFFF7F
+#define   S_0085F0_CB2_DEST_BASE_ENA(x)                (((x) & 0x1) << 8)
+#define   G_0085F0_CB2_DEST_BASE_ENA(x)                (((x) >> 8) & 0x1)
+#define   C_0085F0_CB2_DEST_BASE_ENA                   0xFFFFFEFF
+#define   S_0085F0_CB3_DEST_BASE_ENA(x)                (((x) & 0x1) << 9)
+#define   G_0085F0_CB3_DEST_BASE_ENA(x)                (((x) >> 9) & 0x1)
+#define   C_0085F0_CB3_DEST_BASE_ENA                   0xFFFFFDFF
+#define   S_0085F0_CB4_DEST_BASE_ENA(x)                (((x) & 0x1) << 10)
+#define   G_0085F0_CB4_DEST_BASE_ENA(x)                (((x) >> 10) & 0x1)
+#define   C_0085F0_CB4_DEST_BASE_ENA                   0xFFFFFBFF
+#define   S_0085F0_CB5_DEST_BASE_ENA(x)                (((x) & 0x1) << 11)
+#define   G_0085F0_CB5_DEST_BASE_ENA(x)                (((x) >> 11) & 0x1)
+#define   C_0085F0_CB5_DEST_BASE_ENA                   0xFFFFF7FF
+#define   S_0085F0_CB6_DEST_BASE_ENA(x)                (((x) & 0x1) << 12)
+#define   G_0085F0_CB6_DEST_BASE_ENA(x)                (((x) >> 12) & 0x1)
+#define   C_0085F0_CB6_DEST_BASE_ENA                   0xFFFFEFFF
+#define   S_0085F0_CB7_DEST_BASE_ENA(x)                (((x) & 0x1) << 13)
+#define   G_0085F0_CB7_DEST_BASE_ENA(x)                (((x) >> 13) & 0x1)
+#define   C_0085F0_CB7_DEST_BASE_ENA                   0xFFFFDFFF
+#define   S_0085F0_DB_DEST_BASE_ENA(x)                 (((x) & 0x1) << 14)
+#define   G_0085F0_DB_DEST_BASE_ENA(x)                 (((x) >> 14) & 0x1)
+#define   C_0085F0_DB_DEST_BASE_ENA                    0xFFFFBFFF
+#define   S_0085F0_CR_DEST_BASE_ENA(x)                 (((x) & 0x1) << 15)
+#define   G_0085F0_CR_DEST_BASE_ENA(x)                 (((x) >> 15) & 0x1)
+#define   C_0085F0_CR_DEST_BASE_ENA                    0xFFFF7FFF
+#define   S_0085F0_TC_ACTION_ENA(x)                    (((x) & 0x1) << 23)
+#define   G_0085F0_TC_ACTION_ENA(x)                    (((x) >> 23) & 0x1)
+#define   C_0085F0_TC_ACTION_ENA                       0xFF7FFFFF
+#define   S_0085F0_VC_ACTION_ENA(x)                    (((x) & 0x1) << 24)
+#define   G_0085F0_VC_ACTION_ENA(x)                    (((x) >> 24) & 0x1)
+#define   C_0085F0_VC_ACTION_ENA                       0xFEFFFFFF
+#define   S_0085F0_CB_ACTION_ENA(x)                    (((x) & 0x1) << 25)
+#define   G_0085F0_CB_ACTION_ENA(x)                    (((x) >> 25) & 0x1)
+#define   C_0085F0_CB_ACTION_ENA                       0xFDFFFFFF
+#define   S_0085F0_DB_ACTION_ENA(x)                    (((x) & 0x1) << 26)
+#define   G_0085F0_DB_ACTION_ENA(x)                    (((x) >> 26) & 0x1)
+#define   C_0085F0_DB_ACTION_ENA                       0xFBFFFFFF
+#define   S_0085F0_SH_ACTION_ENA(x)                    (((x) & 0x1) << 27)
+#define   G_0085F0_SH_ACTION_ENA(x)                    (((x) >> 27) & 0x1)
+#define   C_0085F0_SH_ACTION_ENA                       0xF7FFFFFF
+#define   S_0085F0_SMX_ACTION_ENA(x)                   (((x) & 0x1) << 28)
+#define   G_0085F0_SMX_ACTION_ENA(x)                   (((x) >> 28) & 0x1)
+#define   C_0085F0_SMX_ACTION_ENA                      0xEFFFFFFF
+#define   S_0085F0_CR0_ACTION_ENA(x)                   (((x) & 0x1) << 29)
+#define   G_0085F0_CR0_ACTION_ENA(x)                   (((x) >> 29) & 0x1)
+#define   C_0085F0_CR0_ACTION_ENA                      0xDFFFFFFF
+#define   S_0085F0_CR1_ACTION_ENA(x)                   (((x) & 0x1) << 30)
+#define   G_0085F0_CR1_ACTION_ENA(x)                   (((x) >> 30) & 0x1)
+#define   C_0085F0_CR1_ACTION_ENA                      0xBFFFFFFF
+#define   S_0085F0_CR2_ACTION_ENA(x)                   (((x) & 0x1) << 31)
+#define   G_0085F0_CR2_ACTION_ENA(x)                   (((x) >> 31) & 0x1)
+#define   C_0085F0_CR2_ACTION_ENA                      0x7FFFFFFF
+
+
+#define R_02812C_CB_CLEAR_ALPHA                      0x02812C
+#define   S_02812C_CLEAR_ALPHA(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_02812C_CLEAR_ALPHA(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02812C_CLEAR_ALPHA                         0x00000000
+#define R_028128_CB_CLEAR_BLUE                       0x028128
+#define   S_028128_CLEAR_BLUE(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_028128_CLEAR_BLUE(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028128_CLEAR_BLUE                          0x00000000
+#define R_028124_CB_CLEAR_GREEN                      0x028124
+#define   S_028124_CLEAR_GREEN(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_028124_CLEAR_GREEN(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028124_CLEAR_GREEN                         0x00000000
+#define R_028120_CB_CLEAR_RED                        0x028120
+#define   S_028120_CLEAR_RED(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028120_CLEAR_RED(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028120_CLEAR_RED                           0x00000000
+#define R_02842C_CB_FOG_BLUE                         0x02842C
+#define   S_02842C_FOG_BLUE(x)                         (((x) & 0xFFFFFFFF) << 0)
+#define   G_02842C_FOG_BLUE(x)                         (((x) >> 0) & 0xFFFFFFFF)
+#define   C_02842C_FOG_BLUE                            0x00000000
+#define R_028428_CB_FOG_GREEN                        0x028428
+#define   S_028428_FOG_GREEN(x)                        (((x) & 0xFFFFFFFF) << 0)
+#define   G_028428_FOG_GREEN(x)                        (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028428_FOG_GREEN                           0x00000000
+#define R_028424_CB_FOG_RED                          0x028424
+#define   S_028424_FOG_RED(x)                          (((x) & 0xFFFFFFFF) << 0)
+#define   G_028424_FOG_RED(x)                          (((x) >> 0) & 0xFFFFFFFF)
+#define   C_028424_FOG_RED                             0x00000000
+#define R_03C000_SQ_TEX_SAMPLER_WORD0_0              0x03C000
+#define   S_03C000_CLAMP_X(x)                          (((x) & 0x7) << 0)
+#define   G_03C000_CLAMP_X(x)                          (((x) >> 0) & 0x7)
+#define   C_03C000_CLAMP_X                             0xFFFFFFF8
+#define   S_03C000_CLAMP_Y(x)                          (((x) & 0x7) << 3)
+#define   G_03C000_CLAMP_Y(x)                          (((x) >> 3) & 0x7)
+#define   C_03C000_CLAMP_Y                             0xFFFFFFC7
+#define   S_03C000_CLAMP_Z(x)                          (((x) & 0x7) << 6)
+#define   G_03C000_CLAMP_Z(x)                          (((x) >> 6) & 0x7)
+#define   C_03C000_CLAMP_Z                             0xFFFFFE3F
+#define   S_03C000_XY_MAG_FILTER(x)                    (((x) & 0x7) << 9)
+#define   G_03C000_XY_MAG_FILTER(x)                    (((x) >> 9) & 0x7)
+#define   C_03C000_XY_MAG_FILTER                       0xFFFFF1FF
+#define   S_03C000_XY_MIN_FILTER(x)                    (((x) & 0x7) << 12)
+#define   G_03C000_XY_MIN_FILTER(x)                    (((x) >> 12) & 0x7)
+#define   C_03C000_XY_MIN_FILTER                       0xFFFF8FFF
+#define   S_03C000_Z_FILTER(x)                         (((x) & 0x3) << 15)
+#define   G_03C000_Z_FILTER(x)                         (((x) >> 15) & 0x3)
+#define   C_03C000_Z_FILTER                            0xFFFE7FFF
+#define   S_03C000_MIP_FILTER(x)                       (((x) & 0x3) << 17)
+#define   G_03C000_MIP_FILTER(x)                       (((x) >> 17) & 0x3)
+#define   C_03C000_MIP_FILTER                          0xFFF9FFFF
+#define   S_03C000_BORDER_COLOR_TYPE(x)                (((x) & 0x3) << 22)
+#define   G_03C000_BORDER_COLOR_TYPE(x)                (((x) >> 22) & 0x3)
+#define   C_03C000_BORDER_COLOR_TYPE                   0xFF3FFFFF
+#define   S_03C000_POINT_SAMPLING_CLAMP(x)             (((x) & 0x1) << 24)
+#define   G_03C000_POINT_SAMPLING_CLAMP(x)             (((x) >> 24) & 0x1)
+#define   C_03C000_POINT_SAMPLING_CLAMP                0xFEFFFFFF
+#define   S_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) & 0x1) << 25)
+#define   G_03C000_TEX_ARRAY_OVERRIDE(x)               (((x) >> 25) & 0x1)
+#define   C_03C000_TEX_ARRAY_OVERRIDE                  0xFDFFFFFF
+#define   S_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) & 0x7) << 26)
+#define   G_03C000_DEPTH_COMPARE_FUNCTION(x)           (((x) >> 26) & 0x7)
+#define   C_03C000_DEPTH_COMPARE_FUNCTION              0xE3FFFFFF
+#define   S_03C000_CHROMA_KEY(x)                       (((x) & 0x3) << 29)
+#define   G_03C000_CHROMA_KEY(x)                       (((x) >> 29) & 0x3)
+#define   C_03C000_CHROMA_KEY                          0x9FFFFFFF
+#define   S_03C000_LOD_USES_MINOR_AXIS(x)              (((x) & 0x1) << 31)
+#define   G_03C000_LOD_USES_MINOR_AXIS(x)              (((x) >> 31) & 0x1)
+#define   C_03C000_LOD_USES_MINOR_AXIS                 0x7FFFFFFF
+#define R_03C004_SQ_TEX_SAMPLER_WORD1_0              0x03C004
+#define   S_03C004_MIN_LOD(x)                          (((x) & 0x3FF) << 0)
+#define   G_03C004_MIN_LOD(x)                          (((x) >> 0) & 0x3FF)
+#define   C_03C004_MIN_LOD                             0xFFFFFC00
+#define   S_03C004_MAX_LOD(x)                          (((x) & 0x3FF) << 10)
+#define   G_03C004_MAX_LOD(x)                          (((x) >> 10) & 0x3FF)
+#define   C_03C004_MAX_LOD                             0xFFF003FF
+#define   S_03C004_LOD_BIAS(x)                         (((x) & 0xFFF) << 20)
+#define   G_03C004_LOD_BIAS(x)                         (((x) >> 20) & 0xFFF)
+#define   C_03C004_LOD_BIAS                            0x000FFFFF
+#define R_03C008_SQ_TEX_SAMPLER_WORD2_0              0x03C008
+#define   S_03C008_LOD_BIAS_SEC(x)                     (((x) & 0xFFF) << 0)
+#define   G_03C008_LOD_BIAS_SEC(x)                     (((x) >> 0) & 0xFFF)
+#define   C_03C008_LOD_BIAS_SEC                        0xFFFFF000
+#define   S_03C008_MC_COORD_TRUNCATE(x)                (((x) & 0x1) << 12)
+#define   G_03C008_MC_COORD_TRUNCATE(x)                (((x) >> 12) & 0x1)
+#define   C_03C008_MC_COORD_TRUNCATE                   0xFFFFEFFF
+#define   S_03C008_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 13)
+#define   G_03C008_FORCE_DEGAMMA(x)                    (((x) >> 13) & 0x1)
+#define   C_03C008_FORCE_DEGAMMA                       0xFFFFDFFF
+#define   S_03C008_HIGH_PRECISION_FILTER(x)            (((x) & 0x1) << 14)
+#define   G_03C008_HIGH_PRECISION_FILTER(x)            (((x) >> 14) & 0x1)
+#define   C_03C008_HIGH_PRECISION_FILTER               0xFFFFBFFF
+#define   S_03C008_PERF_MIP(x)                         (((x) & 0x7) << 15)
+#define   G_03C008_PERF_MIP(x)                         (((x) >> 15) & 0x7)
+#define   C_03C008_PERF_MIP                            0xFFFC7FFF
+#define   S_03C008_PERF_Z(x)                           (((x) & 0x3) << 18)
+#define   G_03C008_PERF_Z(x)                           (((x) >> 18) & 0x3)
+#define   C_03C008_PERF_Z                              0xFFF3FFFF
+#define   S_03C008_FETCH_4(x)                          (((x) & 0x1) << 26)
+#define   G_03C008_FETCH_4(x)                          (((x) >> 26) & 0x1)
+#define   C_03C008_FETCH_4                             0xFBFFFFFF
+#define   S_03C008_SAMPLE_IS_PCF(x)                    (((x) & 0x1) << 27)
+#define   G_03C008_SAMPLE_IS_PCF(x)                    (((x) >> 27) & 0x1)
+#define   C_03C008_SAMPLE_IS_PCF                       0xF7FFFFFF
+#define   S_03C008_TYPE(x)                             (((x) & 0x1) << 31)
+#define   G_03C008_TYPE(x)                             (((x) >> 31) & 0x1)
+#define   C_03C008_TYPE                                0x7FFFFFFF
+#define R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA         0x00A40C
+#define   S_00A40C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A40C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A40C_BORDER_ALPHA                        0x00000000
+#define R_00A408_TD_PS_SAMPLER0_BORDER_BLUE          0x00A408
+#define   S_00A408_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A408_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A408_BORDER_BLUE                         0x00000000
+#define R_00A404_TD_PS_SAMPLER0_BORDER_GREEN         0x00A404
+#define   S_00A404_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A404_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A404_BORDER_GREEN                        0x00000000
+#define R_00A400_TD_PS_SAMPLER0_BORDER_RED           0x00A400
+#define   S_00A400_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A400_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A400_BORDER_RED                          0x00000000
+#define R_00A60C_TD_VS_SAMPLER0_BORDER_ALPHA         0x00A60C
+#define   S_00A60C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A60C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A60C_BORDER_ALPHA                        0x00000000
+#define R_00A608_TD_VS_SAMPLER0_BORDER_BLUE          0x00A608
+#define   S_00A608_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A608_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A608_BORDER_BLUE                         0x00000000
+#define R_00A604_TD_VS_SAMPLER0_BORDER_GREEN         0x00A604
+#define   S_00A604_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A604_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A604_BORDER_GREEN                        0x00000000
+#define R_00A600_TD_VS_SAMPLER0_BORDER_RED           0x00A600
+#define   S_00A600_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A600_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A600_BORDER_RED                          0x00000000
+#define R_00A80C_TD_GS_SAMPLER0_BORDER_ALPHA         0x00A80C
+#define   S_00A80C_BORDER_ALPHA(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A80C_BORDER_ALPHA(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A80C_BORDER_ALPHA                        0x00000000
+#define R_00A808_TD_GS_SAMPLER0_BORDER_BLUE          0x00A808
+#define   S_00A808_BORDER_BLUE(x)                      (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A808_BORDER_BLUE(x)                      (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A808_BORDER_BLUE                         0x00000000
+#define R_00A804_TD_GS_SAMPLER0_BORDER_GREEN         0x00A804
+#define   S_00A804_BORDER_GREEN(x)                     (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A804_BORDER_GREEN(x)                     (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A804_BORDER_GREEN                        0x00000000
+#define R_00A800_TD_GS_SAMPLER0_BORDER_RED           0x00A800
+#define   S_00A800_BORDER_RED(x)                       (((x) & 0xFFFFFFFF) << 0)
+#define   G_00A800_BORDER_RED(x)                       (((x) >> 0) & 0xFFFFFFFF)
+#define   C_00A800_BORDER_RED                          0x00000000
+#define R_030000_SQ_ALU_CONSTANT0_0                  0x030000
+#define   S_030000_X(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030000_X(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030000_X                                   0x00000000
+#define R_030004_SQ_ALU_CONSTANT1_0                  0x030004
+#define   S_030004_Y(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030004_Y(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030004_Y                                   0x00000000
+#define R_030008_SQ_ALU_CONSTANT2_0                  0x030008
+#define   S_030008_Z(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_030008_Z(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_030008_Z                                   0x00000000
+#define R_03000C_SQ_ALU_CONSTANT3_0                  0x03000C
+#define   S_03000C_W(x)                                (((x) & 0xFFFFFFFF) << 0)
+#define   G_03000C_W(x)                                (((x) >> 0) & 0xFFFFFFFF)
+#define   C_03000C_W                                   0x00000000
+
+#endif
diff --git a/src/radeon.c b/src/radeon.c
new file mode 100644
index 0000000..19ed4c8
--- /dev/null
+++ b/src/radeon.c
@@ -0,0 +1,362 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#include "config.h"
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include "xf86drm.h"
+#include "radeon_bo_gem.h"
+#include "radeon_cs_gem.h"
+#include "radeon_priv.h"
+#include "r600d.h"
+
+int radeon_get_device(struct radeon *radeon)
+{
+	struct drm_radeon_info info;
+	int r;
+
+	radeon->device = 0;
+	info.request = RADEON_INFO_DEVICE_ID;
+	info.value = (uintptr_t)&radeon->device;
+	r = drmCommandWriteRead(radeon->fd, DRM_RADEON_INFO, &info,
+			sizeof(struct drm_radeon_info));
+	return r;
+}
+
+int radeon_open_fd(void)
+{
+	return drmOpen("radeon", NULL);
+}
+
+struct radeon *radeon_new(int fd, unsigned device)
+{
+	struct radeon *radeon;
+	int r;
+
+	radeon = calloc(1, sizeof(*radeon));
+	if (radeon == NULL)
+		return NULL;
+	radeon->fd = fd;
+	radeon->device = device;
+	radeon->refcount = 1;
+	if (fd >= 0) {
+		r = radeon_get_device(radeon);
+		if (r) {
+			fprintf(stderr, "Failed to get device id\n");
+			return radeon_decref(radeon);
+		}
+	}
+	radeon->family = radeon_family_from_device(radeon->device);
+	if (radeon->family == CHIP_UNKNOWN) {
+		fprintf(stderr, "Unknown chipset 0x%04X\n", radeon->device);
+		return radeon_decref(radeon);
+	}
+	radeon->csm = radeon_cs_manager_gem_ctor(radeon->fd);
+	if (radeon->csm == NULL) {
+		fprintf(stderr, "Failed to create CS manager\n");
+		return radeon_decref(radeon);
+	}
+	radeon->bom = radeon_bo_manager_gem_ctor(radeon->fd);
+	if (radeon->bom == NULL) {
+		fprintf(stderr, "Failed to create BO manager\n");
+		return radeon_decref(radeon);
+	}
+	switch (radeon->family) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		if (r600_init(radeon)) {
+			return radeon_decref(radeon);
+		}
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+	default:
+		fprintf(stderr, "%s unknown or unsupported chipset 0x%04X\n",
+			__func__, radeon->device);
+		break;
+	}
+	if (radeon->fd >= 0) {
+		/* FIXME compile time enable */
+		r = radeon_mode_configure(radeon);
+		if (r) {
+			return radeon_decref(radeon);
+		}
+	}
+	return radeon;
+}
+
+struct radeon *radeon_incref(struct radeon *radeon)
+{
+	if (radeon == NULL)
+		return NULL;
+	radeon->refcount++;
+	return radeon;
+}
+
+struct radeon *radeon_decref(struct radeon *radeon)
+{
+	if (radeon == NULL)
+		return NULL;
+	if (--radeon->refcount > 0) {
+		return NULL;
+	}
+	radeon_mode_cleanup(radeon);
+	radeon_bo_manager_gem_dtor(radeon->bom);
+	radeon_cs_manager_gem_dtor(radeon->csm);
+	drmClose(radeon->fd);
+	free(radeon);
+	return NULL;
+}
+
+void memset_bo(struct radeon_bo *bo, u32 value)
+{
+	u32 *ptr;
+	int r;
+
+	r = radeon_bo_map(bo, 1);
+	if (r) {
+		fprintf(stderr, "Failed to map buffer\n");
+		perror(NULL);
+		return;
+	}
+	ptr = (u32*)bo->ptr;
+	for (r = 0; r < (bo->size / 4); r++)
+		ptr[r] = value;
+	radeon_bo_unmap(bo);
+}
+
+void memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size)
+{
+	u32 *ptr, tmp;
+	int r;
+
+	r = radeon_bo_map(bo, 1);
+	if (r) {
+		fprintf(stderr, "Failed to map buffer\n");
+		perror(NULL);
+		return;
+	}
+	ptr = (u32*)bo->ptr;
+	for (r = 0; r < size; r++)
+		ptr[r] = src[r];
+	for (r = 0; r < size; r++)
+		ptr[r] = src[r];
+	for (r = 0, tmp = 0; r < size; r++)
+		tmp += ptr[r];
+	radeon_bo_unmap(bo);
+}
+
+void radeon_blit(struct radeon_surface *dst, struct radeon_surface *src,
+		unsigned sx, unsigned sy, unsigned dx, unsigned dy,
+		unsigned w, unsigned h)
+{
+	unsigned y;
+	u8 *dptr, *sptr;
+
+	if (sx >= src->width || sy >= src->height)
+		return;
+	if (dx >= dst->width || dy >= dst->height)
+		return;
+	if ((sx + w) > src->width)
+		w = src->width - sx;
+	if ((dx + w) > dst->width)
+		w = dst->width - dx;
+	if ((sy + h) > src->height)
+		h = src->height - sy;
+	if ((dy + h) > dst->height)
+		h = dst->height - dy;
+	if (!w || !h)
+		return;
+	if (radeon_bo_map(dst->bo, 1))
+		return;
+	if (radeon_bo_map(src->bo, 0))
+		return;
+	sptr = src->bo->ptr;
+	dptr = dst->bo->ptr;
+	sptr = &sptr[(sy * src->pitch + sx) * src->bpe];
+	dptr = &dptr[(dy * dst->pitch + dx) * dst->bpe];
+	for (y = 0; y < h; y++) {
+		memcpy(dptr, sptr, w * src->bpe);
+		dptr += dst->pitch * dst->bpe;
+		sptr += src->pitch * src->bpe;
+	}
+	radeon_bo_unmap(dst->bo);
+	radeon_bo_unmap(src->bo);
+}
+
+int radeon_flush(struct radeon *radeon)
+{
+	struct radeon_ctx *ctx = radeon->ctx;
+	unsigned i;
+	int r;
+
+	free(ctx->pm4);
+	ctx->pm4 = malloc(ctx->cpm4 * 4);
+	if (ctx->pm4 == NULL)
+		return -EINVAL;
+	for (i = 0, ctx->id = 0; i < ctx->ndraw; i++) {
+		r = radeon_ctx_draw_schedule(ctx, i);
+		if (r)
+			return r;
+	}
+	if (ctx->id != ctx->cpm4) {
+		fprintf(stderr, "%s miss predicted pm4 size %d for %d\n",
+			__func__, ctx->cpm4, ctx->id);
+		return -EINVAL;
+	}
+	return radeon_ctx_submit(ctx);
+}
+
+int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id)
+{
+	unsigned i, j;
+
+	for (i = 0; i < radeon->ntype; i++) {
+		if (radeon->type[i].range_start) {
+			if (offset >= radeon->type[i].range_start && offset < radeon->type[i].range_end) {
+				*typeid = i;
+				j = offset - radeon->type[i].range_start;
+				j /= radeon->type[i].stride;
+				*stateid = radeon->type[i].id + j;
+				*id = (offset - radeon->type[i].range_start - radeon->type[i].stride * j) / 4;
+				return 0;
+			}
+		} else {
+			for (j = 0; j < radeon->type[i].nstates; j++) {
+				if (radeon->type[i].regs[j].offset == offset) {
+					*typeid = i;
+					*stateid = radeon->type[i].id;
+					*id = j;
+					return 0;
+				}
+			}
+		}
+	}
+	fprintf(stderr, "%s unknown register 0x%08X\n", __func__, offset);
+	return -EINVAL;
+}
+
+unsigned radeon_type_from_id(struct radeon *radeon, unsigned id)
+{
+	unsigned i;
+
+	for (i = 0; i < radeon->ntype - 1; i++) {
+		if (radeon->type[i].id == id)
+			return i;
+		if (id > radeon->type[i].id && id < radeon->type[i + 1].id)
+			return i;
+	}
+	if (radeon->type[i].id == id)
+		return i;
+	return -1;
+}
+
+int radeon_schedule_draw(struct radeon *radeon, struct radeon_draw *draw)
+{
+	struct radeon_ctx *ctx = radeon->ctx;
+	struct radeon_draw *pdraw = NULL;
+	struct radeon_state *nstate, *ostate;
+	unsigned cpm4, i;
+	int r = 0;
+
+	if (ctx == NULL) {
+		ctx = radeon_ctx(radeon, 0);
+		if (ctx == NULL)
+			return -ENOMEM;
+		radeon->ctx = ctx;
+	}
+	r = radeon_draw_check(draw);
+	if (r)
+		return r;
+	if (draw->cpm4 >= RADEON_CTX_MAX_PM4) {
+		fprintf(stderr, "%s single draw too big %d, max %d\n",
+			__func__, draw->cpm4, RADEON_CTX_MAX_PM4);
+		return -EINVAL;
+	}
+reprocess:
+	pdraw = ctx->cdraw;
+	for (i = 0, cpm4 = 0; i < draw->nstate; i++) {
+		nstate = draw->state[i];
+		if (nstate) {
+			if (pdraw && pdraw->state[i]) {
+				ostate = pdraw->state[i];
+				if (ostate->pm4_crc == nstate->pm4_crc) {
+					cpm4 += nstate->cpm4;
+				} else {
+					cpm4 += nstate->cpm4;
+				}
+			} else {
+				cpm4 += nstate->cpm4;
+			}
+		}
+	}
+	if ((ctx->cpm4 + cpm4) > RADEON_CTX_MAX_PM4) {
+		r = radeon_flush(radeon);
+		if (r)
+			goto out_err;
+		goto reprocess;
+	}
+	r = radeon_ctx_set_draw_new(ctx, draw);
+	if (r)
+		goto out_err;
+	ctx->cpm4 += cpm4;
+out_err:
+	return r;
+}
diff --git a/src/radeon.h b/src/radeon.h
new file mode 100644
index 0000000..f9f392e
--- /dev/null
+++ b/src/radeon.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef RADEON_H
+#define RADEON_H
+
+#include "radeon_bo.h"
+
+#define RADEON_CTX_MAX_PM4	(64 * 1024 / 4)
+
+typedef uint64_t		u64;
+typedef uint32_t		u32;
+typedef uint16_t		u16;
+typedef uint8_t			u8;
+
+enum radeon_family {
+	CHIP_UNKNOWN,
+	CHIP_R100,
+	CHIP_RV100,
+	CHIP_RS100,
+	CHIP_RV200,
+	CHIP_RS200,
+	CHIP_R200,
+	CHIP_RV250,
+	CHIP_RS300,
+	CHIP_RV280,
+	CHIP_R300,
+	CHIP_R350,
+	CHIP_RV350,
+	CHIP_RV380,
+	CHIP_R420,
+	CHIP_R423,
+	CHIP_RV410,
+	CHIP_RS400,
+	CHIP_RS480,
+	CHIP_RS600,
+	CHIP_RS690,
+	CHIP_RS740,
+	CHIP_RV515,
+	CHIP_R520,
+	CHIP_RV530,
+	CHIP_RV560,
+	CHIP_RV570,
+	CHIP_R580,
+	CHIP_R600,
+	CHIP_RV610,
+	CHIP_RV630,
+	CHIP_RV670,
+	CHIP_RV620,
+	CHIP_RV635,
+	CHIP_RS780,
+	CHIP_RS880,
+	CHIP_RV770,
+	CHIP_RV730,
+	CHIP_RV710,
+	CHIP_RV740,
+	CHIP_CEDAR,
+	CHIP_REDWOOD,
+	CHIP_JUNIPER,
+	CHIP_CYPRESS,
+	CHIP_HEMLOCK,
+	CHIP_LAST,
+};
+
+/*
+ * radeon object functions
+ */
+struct radeon_object {
+	unsigned			refcount;
+	unsigned			handle;
+	unsigned			size;
+	unsigned			*data;
+	struct radeon_bo		*bo;
+};
+
+extern struct radeon_object *radeon_object(struct radeon_bo *bo, unsigned handle,
+						unsigned size, void *ptr);
+extern struct radeon_object *radeon_object_incref(struct radeon_object *object);
+extern struct radeon_object *radeon_object_decref(struct radeon_object *object);
+
+/*
+ * states functions
+ */
+struct radeon_state {
+	struct radeon			*radeon;
+	unsigned			refcount;
+	unsigned			type;
+	unsigned			id;
+	unsigned			nstates;
+	u32				*states;
+	unsigned			npm4;
+	unsigned			cpm4;
+	u32				pm4_crc;
+	u32				*pm4;
+	unsigned			nbo;
+	struct radeon_object		*bo[4];
+	unsigned			nreloc;
+	unsigned			reloc_pm4_id[8];
+	unsigned			reloc_bo_id[8];
+	u32				placement[8];
+	unsigned			bo_dirty[4];
+};
+
+extern struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id);
+extern struct radeon_state *radeon_state_incref(struct radeon_state *state);
+extern struct radeon_state *radeon_state_decref(struct radeon_state *state);
+extern int radeon_state_pm4(struct radeon_state *state);
+
+/*
+ * draw functions
+ */
+struct radeon_draw {
+	unsigned			refcount;
+	struct radeon			*radeon;
+	unsigned			nstate;
+	struct radeon_state		**state;
+	unsigned			cpm4;
+};
+
+extern struct radeon_draw *radeon_draw(struct radeon *radeon);
+extern struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw);
+extern struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw);
+extern int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state);
+extern int radeon_draw_check(struct radeon_draw *draw);
+
+int radeon_flush(struct radeon *radeon);
+
+/*
+ * R600/R700
+ */
+
+#define R600_NSTATE				1273
+#define R600_NTYPE				25
+
+#define R600_CONFIG				0
+#define R600_CONFIG_TYPE				0
+#define R600_CB_CNTL				1
+#define R600_CB_CNTL_TYPE				1
+#define R600_RASTERIZER				2
+#define R600_RASTERIZER_TYPE				2
+#define R600_VIEWPORT				3
+#define R600_VIEWPORT_TYPE				3
+#define R600_SCISSOR				4
+#define R600_SCISSOR_TYPE				4
+#define R600_BLEND				5
+#define R600_BLEND_TYPE				5
+#define R600_DSA				6
+#define R600_DSA_TYPE				6
+#define R600_VS_SHADER				7
+#define R600_VS_SHADER_TYPE				7
+#define R600_PS_SHADER				8
+#define R600_PS_SHADER_TYPE				8
+#define R600_PS_CONSTANT				9
+#define R600_PS_CONSTANT_TYPE				9
+#define R600_VS_CONSTANT				265
+#define R600_VS_CONSTANT_TYPE				10
+#define R600_PS_RESOURCE				521
+#define R600_PS_RESOURCE_TYPE				11
+#define R600_VS_RESOURCE				681
+#define R600_VS_RESOURCE_TYPE				12
+#define R600_FS_RESOURCE				841
+#define R600_FS_RESOURCE_TYPE				13
+#define R600_GS_RESOURCE				1001
+#define R600_GS_RESOURCE_TYPE				14
+#define R600_PS_SAMPLER				1161
+#define R600_PS_SAMPLER_TYPE				15
+#define R600_VS_SAMPLER				1179
+#define R600_VS_SAMPLER_TYPE				16
+#define R600_GS_SAMPLER				1197
+#define R600_GS_SAMPLER_TYPE				17
+#define R600_PS_SAMPLER_BORDER				1215
+#define R600_PS_SAMPLER_BORDER_TYPE				18
+#define R600_VS_SAMPLER_BORDER				1233
+#define R600_VS_SAMPLER_BORDER_TYPE				19
+#define R600_GS_SAMPLER_BORDER				1251
+#define R600_GS_SAMPLER_BORDER_TYPE				20
+#define R600_CB0				1269
+#define R600_CB0_TYPE				21
+#define R600_DB				1270
+#define R600_DB_TYPE				22
+#define R600_VGT				1271
+#define R600_VGT_TYPE				23
+#define R600_DRAW				1272
+#define R600_DRAW_TYPE				24
+
+/* R600_CONFIG */
+#define R600_CONFIG__VGT_OUTPUT_PATH_CNTL			0
+#define R600_CONFIG__VGT_HOS_CNTL			1
+#define R600_CONFIG__VGT_HOS_MAX_TESS_LEVEL			2
+#define R600_CONFIG__VGT_HOS_MIN_TESS_LEVEL			3
+#define R600_CONFIG__VGT_HOS_REUSE_DEPTH			4
+#define R600_CONFIG__VGT_GROUP_PRIM_TYPE			5
+#define R600_CONFIG__VGT_GROUP_FIRST_DECR			6
+#define R600_CONFIG__VGT_GROUP_DECR			7
+#define R600_CONFIG__VGT_GROUP_VECT_0_CNTL			8
+#define R600_CONFIG__VGT_GROUP_VECT_1_CNTL			9
+#define R600_CONFIG__VGT_GROUP_VECT_0_FMT_CNTL			10
+#define R600_CONFIG__VGT_GROUP_VECT_1_FMT_CNTL			11
+#define R600_CONFIG__VGT_GS_MODE			12
+#define R600_CONFIG__PA_SC_MODE_CNTL			13
+#define R600_CONFIG__VGT_PRIMITIVEID_EN			14
+#define R600_CONFIG__VGT_MULTI_PRIM_IB_RESET_EN			15
+#define R600_CONFIG__VGT_INSTANCE_STEP_RATE_0			16
+#define R600_CONFIG__VGT_INSTANCE_STEP_RATE_1			17
+#define R600_CONFIG__VGT_STRMOUT_EN			18
+#define R600_CONFIG__VGT_REUSE_OFF			19
+#define R600_CONFIG__VGT_VTX_CNT_EN			20
+#define R600_CONFIG__VGT_STRMOUT_BUFFER_EN			21
+#define R600_CONFIG__SQ_CONFIG			22
+#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_1			23
+#define R600_CONFIG__SQ_GPR_RESOURCE_MGMT_2			24
+#define R600_CONFIG__SQ_THREAD_RESOURCE_MGMT			25
+#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_1			26
+#define R600_CONFIG__SQ_STACK_RESOURCE_MGMT_2			27
+#define R600_CONFIG__SQ_DYN_GPR_CNTL_PS_FLUSH_REQ			28
+#define R600_CONFIG__TA_CNTL_AUX			29
+#define R600_CONFIG__VC_ENHANCE			30
+#define R600_CONFIG__DB_DEBUG			31
+#define R600_CONFIG__DB_WATERMARKS			32
+#define R600_CONFIG__SX_MISC			33
+#define R600_CONFIG__SPI_THREAD_GROUPING			34
+#define R600_CONFIG__CB_SHADER_CONTROL			35
+#define R600_CONFIG__SQ_ESGS_RING_ITEMSIZE			36
+#define R600_CONFIG__SQ_GSVS_RING_ITEMSIZE			37
+#define R600_CONFIG__SQ_ESTMP_RING_ITEMSIZE			38
+#define R600_CONFIG__SQ_GSTMP_RING_ITEMSIZE			39
+#define R600_CONFIG__SQ_VSTMP_RING_ITEMSIZE			40
+#define R600_CONFIG__SQ_PSTMP_RING_ITEMSIZE			41
+#define R600_CONFIG__SQ_FBUF_RING_ITEMSIZE			42
+#define R600_CONFIG__SQ_REDUC_RING_ITEMSIZE			43
+#define R600_CONFIG__SQ_GS_VERT_ITEMSIZE			44
+#define R600_CONFIG_SIZE				45
+#define R600_CONFIG_PM4				128
+/* R600_CB_CNTL */
+#define R600_CB_CNTL__CB_COLOR_CONTROL			0
+#define R600_CB_CNTL__CB_SHADER_MASK			1
+#define R600_CB_CNTL__CB_TARGET_MASK			2
+#define R600_CB_CNTL__PA_SC_AA_CONFIG			3
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_MCTX			4
+#define R600_CB_CNTL__PA_SC_AA_MASK			5
+#define R600_CB_CNTL__PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX			6
+#define R600_CB_CNTL__CB_CLRCMP_CONTROL			7
+#define R600_CB_CNTL__CB_CLRCMP_SRC			8
+#define R600_CB_CNTL__CB_CLRCMP_DST			9
+#define R600_CB_CNTL__CB_CLRCMP_MSK			10
+#define R600_CB_CNTL__CB_CLEAR_ALPHA			11
+#define R600_CB_CNTL__CB_CLEAR_BLUE			12
+#define R600_CB_CNTL__CB_CLEAR_GREEN			13
+#define R600_CB_CNTL__CB_CLEAR_RED			14
+#define R600_CB_CNTL__CB_FOG_BLUE			15
+#define R600_CB_CNTL__CB_FOG_GREEN			16
+#define R600_CB_CNTL__CB_FOG_RED			17
+#define R600_CB_CNTL_SIZE				18
+#define R600_CB_CNTL_PM4				128
+/* R600_RASTERIZER */
+#define R600_RASTERIZER__SPI_INTERP_CONTROL_0			0
+#define R600_RASTERIZER__PA_SC_MPASS_PS_CNTL			1
+#define R600_RASTERIZER__PA_SC_LINE_CNTL			2
+#define R600_RASTERIZER__PA_CL_CLIP_CNTL			3
+#define R600_RASTERIZER__PA_CL_VS_OUT_CNTL			4
+#define R600_RASTERIZER__PA_CL_NANINF_CNTL			5
+#define R600_RASTERIZER__PA_CL_GB_VERT_CLIP_ADJ			6
+#define R600_RASTERIZER__PA_CL_GB_VERT_DISC_ADJ			7
+#define R600_RASTERIZER__PA_CL_GB_HORZ_CLIP_ADJ			8
+#define R600_RASTERIZER__PA_CL_GB_HORZ_DISC_ADJ			9
+#define R600_RASTERIZER__PA_SU_SC_MODE_CNTL			10
+#define R600_RASTERIZER__PA_SU_POINT_SIZE			11
+#define R600_RASTERIZER__PA_SU_POINT_MINMAX			12
+#define R600_RASTERIZER__PA_SU_LINE_CNTL			13
+#define R600_RASTERIZER__PA_SC_LINE_STIPPLE			14
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_DB_FMT_CNTL			15
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_CLAMP			16
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_SCALE			17
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_FRONT_OFFSET			18
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_SCALE			19
+#define R600_RASTERIZER__PA_SU_POLY_OFFSET_BACK_OFFSET			20
+#define R600_RASTERIZER_SIZE				21
+#define R600_RASTERIZER_PM4				128
+/* R600_VIEWPORT */
+#define R600_VIEWPORT__PA_CL_VTE_CNTL			0
+#define R600_VIEWPORT__PA_CL_VPORT_XSCALE_0			1
+#define R600_VIEWPORT__PA_CL_VPORT_YSCALE_0			2
+#define R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0			3
+#define R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0			4
+#define R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0			5
+#define R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0			6
+#define R600_VIEWPORT__PA_SC_VPORT_ZMIN_0			7
+#define R600_VIEWPORT__PA_SC_VPORT_ZMAX_0			8
+#define R600_VIEWPORT_SIZE				9
+#define R600_VIEWPORT_PM4				128
+/* R600_SCISSOR */
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_TL			0
+#define R600_SCISSOR__PA_SC_VPORT_SCISSOR_0_BR			1
+#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_TL			2
+#define R600_SCISSOR__PA_SC_SCREEN_SCISSOR_BR			3
+#define R600_SCISSOR__PA_SC_WINDOW_OFFSET			4
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_TL			5
+#define R600_SCISSOR__PA_SC_WINDOW_SCISSOR_BR			6
+#define R600_SCISSOR__PA_SC_CLIPRECT_RULE			7
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_TL			8
+#define R600_SCISSOR__PA_SC_CLIPRECT_0_BR			9
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_TL			10
+#define R600_SCISSOR__PA_SC_CLIPRECT_1_BR			11
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_TL			12
+#define R600_SCISSOR__PA_SC_CLIPRECT_2_BR			13
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_TL			14
+#define R600_SCISSOR__PA_SC_CLIPRECT_3_BR			15
+#define R600_SCISSOR__PA_SC_EDGERULE			16
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_TL			17
+#define R600_SCISSOR__PA_SC_GENERIC_SCISSOR_BR			18
+#define R600_SCISSOR_SIZE				19
+#define R600_SCISSOR_PM4				128
+/* R600_BLEND */
+#define R600_BLEND__CB_BLEND0_CONTROL			0
+#define R600_BLEND__CB_BLEND1_CONTROL			1
+#define R600_BLEND__CB_BLEND2_CONTROL			2
+#define R600_BLEND__CB_BLEND3_CONTROL			3
+#define R600_BLEND__CB_BLEND4_CONTROL			4
+#define R600_BLEND__CB_BLEND5_CONTROL			5
+#define R600_BLEND__CB_BLEND6_CONTROL			6
+#define R600_BLEND__CB_BLEND7_CONTROL			7
+#define R600_BLEND__CB_BLEND_CONTROL			8
+#define R600_BLEND__CB_BLEND_RED			9
+#define R600_BLEND__CB_BLEND_GREEN			10
+#define R600_BLEND__CB_BLEND_BLUE			11
+#define R600_BLEND__CB_BLEND_ALPHA			12
+#define R600_BLEND_SIZE				13
+#define R600_BLEND_PM4				128
+/* R600_DSA */
+#define R600_DSA__DB_STENCIL_CLEAR			0
+#define R600_DSA__DB_DEPTH_CLEAR			1
+#define R600_DSA__DB_STENCILREFMASK			2
+#define R600_DSA__DB_STENCILREFMASK_BF			3
+#define R600_DSA__DB_DEPTH_CONTROL			4
+#define R600_DSA__DB_SHADER_CONTROL			5
+#define R600_DSA__DB_RENDER_CONTROL			6
+#define R600_DSA__DB_RENDER_OVERRIDE			7
+#define R600_DSA__DB_SRESULTS_COMPARE_STATE1			8
+#define R600_DSA__DB_PRELOAD_CONTROL			9
+#define R600_DSA__DB_ALPHA_TO_MASK			10
+#define R600_DSA__SX_ALPHA_TEST_CONTROL			11
+#define R600_DSA__SX_ALPHA_REF			12
+#define R600_DSA__SPI_FOG_CNTL			13
+#define R600_DSA__SPI_FOG_FUNC_SCALE			14
+#define R600_DSA__SPI_FOG_FUNC_BIAS			15
+#define R600_DSA_SIZE				16
+#define R600_DSA_PM4				128
+/* R600_VS_SHADER */
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_VS			0
+#define R600_VS_SHADER__SPI_VS_OUT_CONFIG			1
+#define R600_VS_SHADER__SQ_PGM_START_VS			2
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_VS			3
+#define R600_VS_SHADER__SQ_PGM_START_FS			4
+#define R600_VS_SHADER__SQ_PGM_CF_OFFSET_FS			5
+#define R600_VS_SHADER__SQ_PGM_RESOURCES_FS			6
+#define R600_VS_SHADER__SPI_VS_OUT_ID_0			7
+#define R600_VS_SHADER__SPI_VS_OUT_ID_1			8
+#define R600_VS_SHADER__SPI_VS_OUT_ID_2			9
+#define R600_VS_SHADER__SPI_VS_OUT_ID_3			10
+#define R600_VS_SHADER__SPI_VS_OUT_ID_4			11
+#define R600_VS_SHADER__SPI_VS_OUT_ID_5			12
+#define R600_VS_SHADER__SPI_VS_OUT_ID_6			13
+#define R600_VS_SHADER__SPI_VS_OUT_ID_7			14
+#define R600_VS_SHADER__SPI_VS_OUT_ID_8			15
+#define R600_VS_SHADER__SPI_VS_OUT_ID_9			16
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_0			17
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_1			18
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_2			19
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_3			20
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_4			21
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_5			22
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_6			23
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_7			24
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_8			25
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_9			26
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_10			27
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_11			28
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_12			29
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_13			30
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_14			31
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_15			32
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_16			33
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_17			34
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_18			35
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_19			36
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_20			37
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_21			38
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_22			39
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_23			40
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_24			41
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_25			42
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_26			43
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_27			44
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_28			45
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_29			46
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_30			47
+#define R600_VS_SHADER__SQ_VTX_SEMANTIC_31			48
+#define R600_VS_SHADER_SIZE				49
+#define R600_VS_SHADER_PM4				128
+/* R600_PS_SHADER */
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_0			0
+#define R600_PS_SHADER__SPI_PS_IN_CONTROL_1			1
+#define R600_PS_SHADER__SQ_PGM_RESOURCES_PS			2
+#define R600_PS_SHADER__SQ_PGM_EXPORTS_PS			3
+#define R600_PS_SHADER__SQ_PGM_START_PS			4
+#define R600_PS_SHADER__SQ_PGM_CF_OFFSET_PS			5
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_0			6
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_1			7
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_2			8
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_3			9
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_4			10
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_5			11
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_6			12
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_7			13
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_8			14
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_9			15
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_10			16
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_11			17
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_12			18
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_13			19
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_14			20
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_15			21
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_16			22
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_17			23
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_18			24
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_19			25
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_20			26
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_21			27
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_22			28
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_23			29
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_24			30
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_25			31
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_26			32
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_27			33
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_28			34
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_29			35
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_30			36
+#define R600_PS_SHADER__SPI_PS_INPUT_CNTL_31			37
+#define R600_PS_SHADER__SPI_INPUT_Z			38
+#define R600_PS_SHADER_SIZE				39
+#define R600_PS_SHADER_PM4				128
+/* R600_PS_CONSTANT */
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT0_0			0
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT1_0			1
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT2_0			2
+#define R600_PS_CONSTANT__SQ_ALU_CONSTANT3_0			3
+#define R600_PS_CONSTANT_SIZE				4
+#define R600_PS_CONSTANT_PM4				128
+/* R600_VS_CONSTANT */
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT0_256			0
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT1_256			1
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT2_256			2
+#define R600_VS_CONSTANT__SQ_ALU_CONSTANT3_256			3
+#define R600_VS_CONSTANT_SIZE				4
+#define R600_VS_CONSTANT_PM4				128
+/* R600_PS_RESOURCE */
+#define R600_PS_RESOURCE__RESOURCE0_WORD0			0
+#define R600_PS_RESOURCE__RESOURCE0_WORD1			1
+#define R600_PS_RESOURCE__RESOURCE0_WORD2			2
+#define R600_PS_RESOURCE__RESOURCE0_WORD3			3
+#define R600_PS_RESOURCE__RESOURCE0_WORD4			4
+#define R600_PS_RESOURCE__RESOURCE0_WORD5			5
+#define R600_PS_RESOURCE__RESOURCE0_WORD6			6
+#define R600_PS_RESOURCE_SIZE				7
+#define R600_PS_RESOURCE_PM4				128
+/* R600_VS_RESOURCE */
+#define R600_VS_RESOURCE__RESOURCE160_WORD0			0
+#define R600_VS_RESOURCE__RESOURCE160_WORD1			1
+#define R600_VS_RESOURCE__RESOURCE160_WORD2			2
+#define R600_VS_RESOURCE__RESOURCE160_WORD3			3
+#define R600_VS_RESOURCE__RESOURCE160_WORD4			4
+#define R600_VS_RESOURCE__RESOURCE160_WORD5			5
+#define R600_VS_RESOURCE__RESOURCE160_WORD6			6
+#define R600_VS_RESOURCE_SIZE				7
+#define R600_VS_RESOURCE_PM4				128
+/* R600_FS_RESOURCE */
+#define R600_FS_RESOURCE__RESOURCE320_WORD0			0
+#define R600_FS_RESOURCE__RESOURCE320_WORD1			1
+#define R600_FS_RESOURCE__RESOURCE320_WORD2			2
+#define R600_FS_RESOURCE__RESOURCE320_WORD3			3
+#define R600_FS_RESOURCE__RESOURCE320_WORD4			4
+#define R600_FS_RESOURCE__RESOURCE320_WORD5			5
+#define R600_FS_RESOURCE__RESOURCE320_WORD6			6
+#define R600_FS_RESOURCE_SIZE				7
+#define R600_FS_RESOURCE_PM4				128
+/* R600_GS_RESOURCE */
+#define R600_GS_RESOURCE__RESOURCE336_WORD0			0
+#define R600_GS_RESOURCE__RESOURCE336_WORD1			1
+#define R600_GS_RESOURCE__RESOURCE336_WORD2			2
+#define R600_GS_RESOURCE__RESOURCE336_WORD3			3
+#define R600_GS_RESOURCE__RESOURCE336_WORD4			4
+#define R600_GS_RESOURCE__RESOURCE336_WORD5			5
+#define R600_GS_RESOURCE__RESOURCE336_WORD6			6
+#define R600_GS_RESOURCE_SIZE				7
+#define R600_GS_RESOURCE_PM4				128
+/* R600_PS_SAMPLER */
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD0_0			0
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD1_0			1
+#define R600_PS_SAMPLER__SQ_TEX_SAMPLER_WORD2_0			2
+#define R600_PS_SAMPLER_SIZE				3
+#define R600_PS_SAMPLER_PM4				128
+/* R600_VS_SAMPLER */
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD0_18			0
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD1_18			1
+#define R600_VS_SAMPLER__SQ_TEX_SAMPLER_WORD2_18			2
+#define R600_VS_SAMPLER_SIZE				3
+#define R600_VS_SAMPLER_PM4				128
+/* R600_GS_SAMPLER */
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD0_36			0
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD1_36			1
+#define R600_GS_SAMPLER__SQ_TEX_SAMPLER_WORD2_36			2
+#define R600_GS_SAMPLER_SIZE				3
+#define R600_GS_SAMPLER_PM4				128
+/* R600_PS_SAMPLER_BORDER */
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_RED			0
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_GREEN			1
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_BLUE			2
+#define R600_PS_SAMPLER_BORDER__TD_PS_SAMPLER0_BORDER_ALPHA			3
+#define R600_PS_SAMPLER_BORDER_SIZE				4
+#define R600_PS_SAMPLER_BORDER_PM4				128
+/* R600_VS_SAMPLER_BORDER */
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_RED			0
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_GREEN			1
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_BLUE			2
+#define R600_VS_SAMPLER_BORDER__TD_VS_SAMPLER0_BORDER_ALPHA			3
+#define R600_VS_SAMPLER_BORDER_SIZE				4
+#define R600_VS_SAMPLER_BORDER_PM4				128
+/* R600_GS_SAMPLER_BORDER */
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_RED			0
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_GREEN			1
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_BLUE			2
+#define R600_GS_SAMPLER_BORDER__TD_GS_SAMPLER0_BORDER_ALPHA			3
+#define R600_GS_SAMPLER_BORDER_SIZE				4
+#define R600_GS_SAMPLER_BORDER_PM4				128
+/* R600_CB0 */
+#define R600_CB0__CB_COLOR0_INFO			0
+#define R600_CB0__CB_COLOR0_SIZE			1
+#define R600_CB0__CB_COLOR0_VIEW			2
+#define R600_CB0__CB_COLOR0_MASK			3
+#define R600_CB0__CB_COLOR0_BASE			4
+#define R600_CB0__CB_COLOR0_FRAG			5
+#define R600_CB0__CB_COLOR0_TILE			6
+#define R600_CB0_SIZE				7
+#define R600_CB0_PM4				128
+/* R600_DB */
+#define R600_DB__DB_DEPTH_BASE			0
+#define R600_DB__DB_DEPTH_SIZE			1
+#define R600_DB__DB_DEPTH_VIEW			2
+#define R600_DB__DB_DEPTH_INFO			3
+#define R600_DB__DB_HTILE_SURFACE			4
+#define R600_DB__DB_PREFETCH_LIMIT			5
+#define R600_DB_SIZE				6
+#define R600_DB_PM4				128
+/* R600_VGT */
+#define R600_VGT__VGT_PRIMITIVE_TYPE			0
+#define R600_VGT__VGT_MAX_VTX_INDX			1
+#define R600_VGT__VGT_MIN_VTX_INDX			2
+#define R600_VGT__VGT_INDX_OFFSET			3
+#define R600_VGT__VGT_DMA_NUM_INSTANCES			4
+#define R600_VGT__VGT_DMA_INDEX_TYPE			5
+#define R600_VGT__VGT_MULTI_PRIM_IB_RESET_INDX			6
+#define R600_VGT_SIZE				7
+#define R600_VGT_PM4				128
+/* R600_DRAW */
+#define R600_DRAW__VGT_NUM_INDICES			0
+#define R600_DRAW__VGT_DRAW_INITIATOR			1
+#define R600_DRAW_SIZE				2
+#define R600_DRAW_PM4				128
+
+#endif
diff --git a/src/radeon_bof.c b/src/radeon_bof.c
new file mode 100644
index 0000000..9f1e7ea
--- /dev/null
+++ b/src/radeon_bof.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <jansson.h>
+#include "radeon_priv.h"
+
+struct radeon_ctx *radeon_ctx_load_bof(const char *filename)
+{
+	struct radeon_ctx *ctx;
+	unsigned i, device, size, handle;
+	struct radeon_object *object;
+	bof_t *tmp, *bo, *array;
+	bof_t *bctx;
+	int r;
+
+	bctx = bof_load_file(filename);
+	if (bctx == NULL) {
+		return NULL;
+	}
+	/* device */
+	tmp = bof_object_get(bctx, "device_id");
+	if (tmp == NULL) {
+		fprintf(stderr, "no device object\n");
+		goto out_err;
+	}
+	device = bof_int32_value(tmp);
+	ctx = radeon_ctx(NULL, device);
+	if (ctx == NULL) {
+		goto out_err;
+	}
+	/* pm4 */
+	tmp = bof_object_get(bctx, "pm4");
+	if (tmp == NULL) {
+		fprintf(stderr, "no pm4 object\n");
+		goto out_err;
+	}
+	ctx->cpm4 = bof_blob_size(tmp) / 4;
+	ctx->pm4 = copy_object(bof_blob_value(tmp), bof_blob_size(tmp));
+	if (ctx->pm4 == NULL) {
+		goto out_err;
+	}
+	/* reloc */
+	tmp = bof_object_get(bctx, "reloc");
+	if (tmp == NULL) {
+		fprintf(stderr, "no reloc object\n");
+		r = -EINVAL;
+		goto out_err;
+	}
+	ctx->reloc_ndw = bof_blob_size(tmp) / 4;
+	ctx->reloc = copy_object(bof_blob_value(tmp), bof_blob_size(tmp));
+	if (ctx->reloc == NULL) {
+		goto out_err;
+	}
+	/* bo */
+	array = bof_object_get(bctx, "bo");
+	if (array == NULL) {
+		fprintf(stderr, "no bo array object\n");
+		r = -EINVAL;
+		goto out_err;
+	}
+	for (i = 0; i < bof_array_size(array); i++) {
+		bo = bof_array_get(array, i);
+		if (bo == NULL) {
+			fprintf(stderr, "can't get %d bo\n", i);
+			goto out_err;
+		}
+		tmp = bof_object_get(bo, "size");
+		if (tmp == NULL) {
+			fprintf(stderr, "can't get %d bo size\n", i);
+			goto out_err;
+		}
+		size = bof_int32_value(tmp);
+		tmp = bof_object_get(bo, "handle");
+		if (tmp == NULL) {
+			fprintf(stderr, "can't get %d bo handle\n", i);
+			goto out_err;
+		}
+		handle = bof_int32_value(tmp);
+		tmp = bof_object_get(bo, "data");
+		if (tmp == NULL) {
+			fprintf(stderr, "can't get %d bo data from %p of %p\n", i, bo, array);
+			goto out_err;
+		}
+		object = radeon_object(NULL, handle, size,
+					bof_blob_value(tmp));
+		if (object == NULL)
+			goto out_err;
+		if (radeon_ctx_set_object_new(ctx, object, -1))
+			goto out_err;
+	}
+	bof_decref(bctx);
+	return ctx;
+out_err:
+	bof_decref(bctx);
+	radeon_ctx_destroy(ctx);
+	return NULL;
+}
diff --git a/src/radeon_ctx.c b/src/radeon_ctx.c
new file mode 100644
index 0000000..b3074db
--- /dev/null
+++ b/src/radeon_ctx.c
@@ -0,0 +1,409 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include "radeon_priv.h"
+
+#pragma pack(1)
+struct cs_reloc_gem {
+	uint32_t	handle;
+	uint32_t	read_domain;
+	uint32_t	write_domain;
+	uint32_t	flags;
+};
+#pragma pack()
+
+int radeon_ctx_set_object_new(struct radeon_ctx *ctx,
+				struct radeon_object *bo,
+				int id)
+{
+	void *ptr;
+
+	ptr = realloc(ctx->bo, sizeof(struct radeon_ctx_bo) * (ctx->nbo + 1));
+	if (ptr == NULL) {
+		return -ENOMEM;
+	}
+	ctx->bo = ptr;
+	ctx->bo[ctx->nbo].bo = bo;
+	ctx->bo[ctx->nbo].id = id;
+	ctx->nbo++;
+	return 0;
+}
+
+struct radeon_object *radeon_ctx_get_object(struct radeon_ctx *ctx, unsigned handle)
+{
+	unsigned i;
+
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i].bo->handle == handle) {
+			return radeon_object_incref(ctx->bo[i].bo);
+		}
+	}
+	return NULL;
+}
+
+struct radeon_object *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc)
+{
+	struct cs_reloc_gem *greloc;
+	unsigned i;
+
+	greloc = (struct cs_reloc_gem *)&ctx->reloc[reloc];
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i].bo->handle == greloc->handle) {
+			ctx->bo[i].id = reloc;
+			return radeon_object_incref(ctx->bo[i].bo);
+		}
+	}
+	fprintf(stderr, "%s no bo for reloc[%d 0x%08X] %d\n", __func__, reloc, greloc->handle, ctx->nbo);
+	return NULL;
+}
+
+void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement)
+{
+	struct cs_reloc_gem *greloc;
+	unsigned i;
+
+	placement[0] = 0;
+	placement[1] = 0;
+	greloc = (struct cs_reloc_gem *)&ctx->reloc[reloc];
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i].bo->handle == greloc->handle) {
+			placement[0] = greloc->read_domain | greloc->write_domain;
+			placement[1] = placement[0];
+			return;
+		}
+	}
+}
+
+struct radeon_ctx *radeon_ctx(struct radeon *radeon, unsigned device)
+{
+	struct radeon_ctx *ctx;
+
+	ctx = calloc(1, sizeof(*ctx));
+	if (ctx == NULL)
+		return NULL;
+	ctx->radeon = radeon_incref(radeon);
+	if (radeon == NULL) {
+		ctx->radeon = radeon_new(-1, device);
+		if (ctx->radeon == NULL) {
+			free(ctx);
+			return NULL;
+		}
+	}
+	return ctx;
+}
+
+void radeon_ctx_destroy(struct radeon_ctx *ctx)
+{
+	unsigned i;
+
+	for (i = 0; i < ctx->ndraw; i++) {
+		ctx->draw[i] = radeon_draw_decref(ctx->draw[i]);
+	}
+	for (i = 0; i < ctx->nbo; i++) {
+		ctx->bo[i].bo = radeon_object_decref(ctx->bo[i].bo);
+	}
+	radeon_decref(ctx->radeon);
+	free(ctx->draw);
+	free(ctx->bo);
+	free(ctx->pm4);
+	free(ctx->reloc);
+	memset(ctx, 0, sizeof(*ctx));
+	free(ctx);
+}
+
+static int radeon_ctx_state_bo(struct radeon_ctx *ctx,
+				struct radeon_state *state)
+{
+	unsigned i, j;
+	int r;
+
+	if (state == NULL)
+		return 0;
+	for (i = 0; i < state->nbo; i++) {
+		for (j = 0; j < ctx->nbo; j++) {
+			if (state->bo[i] == ctx->bo[j].bo)
+				break;
+		}
+		if (j == ctx->nbo) {
+			radeon_object_incref(state->bo[i]);
+			r = radeon_ctx_set_object_new(ctx, state->bo[i], -1);
+			if (r)
+				return r;
+		}
+	}
+	return 0;
+}
+
+int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
+{
+	struct radeon_draw **ndraw;
+	unsigned i;
+	int r;
+
+	ndraw = realloc(ctx->draw, sizeof(void*) * (ctx->ndraw + 1));
+	if (ndraw == NULL)
+		return -ENOMEM;
+	ctx->draw = ndraw;
+	for (i = 0; i < draw->nstate; i++) {
+		r = radeon_ctx_state_bo(ctx, draw->state[i]);
+		if (r)
+			return r;
+	}
+	ctx->draw[ctx->ndraw++] = draw;
+	ctx->cdraw = draw;
+	return 0;
+}
+
+struct radeon_object *radeon_object(struct radeon_bo *bo, unsigned handle,
+						unsigned size, void *ptr)
+{
+	struct radeon_object *object;
+
+	object = calloc(1, sizeof(*object));
+	if (object == NULL)
+		return NULL;
+	object->data = calloc(1, size);
+	if (object->data == NULL) {
+		return NULL;
+	}
+	object->size = size;
+	object->handle = handle;
+	object->bo = bo;
+	object->refcount = 1;
+	if (ptr)
+		memcpy(object->data, ptr, size);
+	return object;
+}
+
+struct radeon_object *radeon_object_incref(struct radeon_object *object)
+{
+	object->refcount++;
+	return object;
+}
+
+struct radeon_object *radeon_object_decref(struct radeon_object *object)
+{
+	if (object == NULL)
+		return NULL;
+	if (--object->refcount > 0) {
+		return NULL;
+	}
+	free(object->data);
+	object->data = NULL;
+	object->bo = radeon_bo_unref(object->bo);
+	free(object);
+	return NULL;
+}
+
+int radeon_ctx_allocate_bo(struct radeon_ctx *ctx)
+{
+	struct radeon *radeon = ctx->radeon;
+	struct radeon_object *bo;
+	struct cs_reloc_gem *greloc;
+	unsigned i;
+
+	for (i = 0; i < ctx->nbo; i++) {
+		bo = ctx->bo[i].bo;
+		bo->bo = radeon_bo_open(radeon->bom, 0, bo->size, 0,
+				RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
+		if (bo->bo == NULL) {
+			return -ENOMEM;
+		}
+		radeon_bo_map(bo->bo, 1);
+		memcpy(bo->bo->ptr, bo->data, bo->size);
+		radeon_bo_unmap(bo->bo);
+	}
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i].id >= 0) {
+			greloc = (struct cs_reloc_gem *)&ctx->reloc[ctx->bo[i].id];
+			greloc->handle = ctx->bo[i].bo->bo->handle;
+		}
+	}
+	for (i = 0; i < ctx->nbo; i++) {
+		ctx->bo[i].bo->handle = ctx->bo[i].bo->bo->handle;
+	}
+	return 0;
+}
+
+int radeon_ctx_submit(struct radeon_ctx *ctx)
+{
+	struct drm_radeon_cs drmib;
+	struct drm_radeon_cs_chunk chunks[2];
+	uint64_t chunk_array[2];
+	int r = 0;
+
+#if 0
+	printf("reloc %d %d %d pm4 %d\n", ctx->reloc_ndw, ctx->reloc_ndw / 4, ctx->nbo, ctx->cpm4);
+	for (r = 0; r < ctx->cpm4; r++) {
+		fprintf(stderr, "0x%08X\n", ctx->pm4[r]);
+	}
+#endif
+	drmib.num_chunks = 2;
+	drmib.chunks = (uint64_t)(uintptr_t)chunk_array;
+	chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
+	chunks[0].length_dw = ctx->cpm4;
+	chunks[0].chunk_data = (uint64_t)(uintptr_t)ctx->pm4;
+	chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS;
+	chunks[1].length_dw = ctx->reloc_ndw;
+	chunks[1].chunk_data = (uint64_t)(uintptr_t)ctx->reloc;
+	chunk_array[0] = (uint64_t)(uintptr_t)&chunks[0];
+	chunk_array[1] = (uint64_t)(uintptr_t)&chunks[1];
+	r = drmCommandWriteRead(ctx->radeon->fd, DRM_RADEON_CS, &drmib,
+				sizeof(struct drm_radeon_cs));
+	return r;
+}
+
+int radeon_ctx_draw(struct radeon_ctx *ctx)
+{
+	return ctx->radeon->asic->ctx_draw(ctx);
+}
+
+int radeon_ctx_reloc(struct radeon_ctx *ctx, struct radeon_object *bo,
+			unsigned id, unsigned *placement)
+{
+	unsigned i;
+	void *ptr;
+	struct cs_reloc_gem *greloc;
+
+	for (i = 0; i < ctx->nbo; i++) {
+		if (ctx->bo[i].bo == bo) {
+			if (ctx->bo[i].id >= 0) {
+				ctx->pm4[id] = ctx->bo[i].id;
+				return 0;
+			}
+			break;
+		}
+	}
+	if (i == ctx->nbo) {
+		fprintf(stderr, "%s bo %p 0x%08X unknown to context\n",
+			__func__, bo, bo->handle);
+		return -EINVAL;
+	}
+	ptr = realloc(ctx->reloc, sizeof(struct cs_reloc_gem) + ctx->reloc_ndw *4);
+	if (ptr == NULL)
+		return -ENOMEM;
+	ctx->reloc = ptr;
+	greloc = (struct cs_reloc_gem *)&ctx->reloc[ctx->reloc_ndw];
+	greloc->handle = bo->bo->handle;
+	greloc->read_domain = placement[0] | placement [1];
+	greloc->write_domain = placement[0] | placement [1];
+	greloc->flags = 0;
+	ctx->bo[i].id = ctx->reloc_ndw;
+	ctx->reloc_ndw += sizeof(struct cs_reloc_gem) / 4;
+	return 0;
+}
+
+int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state *state)
+{
+	unsigned i, rid, bid;
+	int r;
+
+	if (state == NULL)
+		return 0;
+	memcpy(&ctx->pm4[ctx->id], state->pm4, state->cpm4 * 4);
+	for (i = 0; i < state->nreloc; i++) {
+		rid = state->reloc_pm4_id[i];
+		bid = state->reloc_bo_id[i];
+		r = radeon_ctx_reloc(ctx, state->bo[bid], ctx->id + rid,
+					&state->placement[bid * 2]);
+		if (r) {
+			fprintf(stderr, "%s state %d failed to reloc\n", __func__, state->type);
+			return r;
+		}
+	}
+	ctx->id += state->cpm4;
+	return 0;
+}
+
+int radeon_ctx_draw_schedule(struct radeon_ctx *ctx, unsigned id)
+{
+	struct radeon_draw *draw;
+	unsigned i;
+	int r;
+
+	draw = ctx->draw[id];
+	for (i = 0; i < draw->nstate; i++) {
+		r = radeon_ctx_state_schedule(ctx, draw->state[i]);
+		if (r)
+			return r;
+	}
+	return 0;
+}
+
+int radeon_ctx_draw_set_reg(struct radeon_ctx *ctx, unsigned offset, u32 value)
+{
+	struct radeon_draw *draw;
+	struct radeon *radeon = ctx->radeon;
+	struct radeon_object *bo;
+	unsigned id, stateid, typeid, boid, reloc;
+	int r;
+
+	draw = ctx->cdraw;
+	if (draw == NULL) {
+		draw = radeon_draw(ctx->radeon);
+		if (draw == NULL)
+			return -ENOMEM;
+		r = radeon_ctx_set_draw_new(ctx, draw);
+		if (r) {
+			radeon_draw_decref(draw);
+			return r;
+		}
+	}
+	r = radeon_reg_id(radeon, offset, &typeid, &stateid, &id);
+	if (r) {
+		return r;
+	}
+	if (draw->state[stateid] == NULL) {
+		draw->state[stateid] = radeon_state(radeon, typeid, stateid);
+		if (draw->state[stateid] == NULL)
+			return -ENOMEM;
+	};
+	draw->state[stateid]->states[id] = value;
+	if (radeon->type[typeid].regs[id].need_reloc) {
+		r = radeon_ctx_next_reloc(ctx, &reloc);
+		if (r)
+			return r;
+		bo = radeon_ctx_get_bo(ctx, reloc);
+		if (bo == NULL)
+			return -ENOMEM;
+		boid = radeon->type[typeid].regs[id].bo_id;
+		radeon_object_decref(draw->state[stateid]->bo[boid]);
+		draw->state[stateid]->bo[boid] = bo;
+		radeon_ctx_get_placement(ctx, reloc, &draw->state[stateid]->placement[boid * 2]);
+	}
+	return 0;
+}
+
+void *copy_object(void *ptr, unsigned size)
+{
+	void *copy;
+
+	copy = calloc(1, size);
+	if (copy == NULL)
+		return NULL;
+	memcpy(copy, ptr, size);
+	return copy;
+}
diff --git a/src/radeon_draw.c b/src/radeon_draw.c
new file mode 100644
index 0000000..660b77c
--- /dev/null
+++ b/src/radeon_draw.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "radeon_priv.h"
+
+/*
+ * draw functions
+ */
+struct radeon_draw *radeon_draw(struct radeon *radeon)
+{
+	struct radeon_draw *draw;
+
+	draw = calloc(1, sizeof(*draw));
+	if (draw == NULL)
+		return NULL;
+	draw->nstate = radeon->nstate;
+	draw->radeon = radeon;
+	draw->refcount = 1;
+	draw->state = calloc(1, sizeof(void*) * draw->nstate);
+	if (draw->state == NULL) {
+		free(draw);
+		return NULL;
+	}
+	return draw;
+}
+
+struct radeon_draw *radeon_draw_incref(struct radeon_draw *draw)
+{
+	draw->refcount++;
+	return draw;
+}
+
+struct radeon_draw *radeon_draw_decref(struct radeon_draw *draw)
+{
+	unsigned i;
+
+	if (draw == NULL)
+		return NULL;
+	if (--draw->refcount > 0)
+		return NULL;
+	for (i = 0; i < draw->nstate; i++) {
+		draw->state[i] = radeon_state_decref(draw->state[i]);
+	}
+	free(draw->state);
+	memset(draw, 0, sizeof(*draw));
+	free(draw);
+	return NULL;
+}
+
+int radeon_draw_set(struct radeon_draw *draw, struct radeon_state *state)
+{
+	struct radeon_state *nstate;
+
+	if (state == NULL)
+		return 0;
+	if (state->type >= draw->radeon->ntype)
+		return -EINVAL;
+	nstate = radeon_state_duplicate(state);
+	if (nstate == NULL)
+		return -ENOMEM;
+	draw->state[state->id] = radeon_state_decref(draw->state[state->id]);
+	draw->state[state->id] = nstate;
+	return 0;
+}
+
+int radeon_draw_check(struct radeon_draw *draw)
+{
+	unsigned i;
+
+	for (i = 0, draw->cpm4 = 0; i < draw->nstate; i++) {
+		if (draw->state[i]) {
+			draw->cpm4 += draw->state[i]->cpm4;
+		}
+	}
+	return 0;
+}
+
+struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw)
+{
+	struct radeon_draw *ndraw;
+	unsigned i;
+
+	if (draw == NULL)
+		return NULL;
+	ndraw = radeon_draw(draw->radeon);
+	if (ndraw == NULL) {
+		return NULL;
+	}
+	for (i = 0; i < draw->nstate; i++) {
+		if (radeon_draw_set(ndraw, draw->state[i])) {
+			radeon_draw_decref(ndraw);
+			return NULL;
+		}
+	}
+	return ndraw;
+}
+
+int radeon_draw_pm4(struct radeon_draw *draw)
+{
+	unsigned i;
+	int r;
+
+	for (i = 0; i < draw->nstate; i++) {
+		r = radeon_state_pm4(draw->state[i]);
+		if (r)
+			return r;
+	}
+	return 0;
+}
diff --git a/src/radeon_json.c b/src/radeon_json.c
new file mode 100644
index 0000000..b29e632
--- /dev/null
+++ b/src/radeon_json.c
@@ -0,0 +1,359 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <jansson.h>
+#include "radeon_priv.h"
+
+int radeon_ctx_dump_json(struct radeon_ctx *ctx, const char *filename)
+{
+	struct radeon_ctx_json jctx;
+	json_t *jboffile, *jdevice, *jarray, *jdraw;
+	unsigned i;
+	int r = 0;
+
+	jctx.jctx = json_object();
+	if (jctx.jctx == NULL) {
+		return -ENOMEM;
+	}
+	jctx.ctx = ctx;
+	/* device id */
+	jdevice = json_integer(ctx->radeon->device);
+	if (jdevice == NULL) {
+		fprintf(stderr, "%s failed to create json device_id object\n", __func__);
+		r = -EINVAL;
+		goto out_err;
+	}
+	json_object_set_new(jctx.jctx, "device_id", jdevice);
+	/* bof filename */
+	jboffile = json_string(filename);
+	if (jboffile == NULL) {
+		fprintf(stderr, "%s failed to create json bof_file object\n", __func__);
+		r = -EINVAL;
+		goto out_err;
+	}
+	json_object_set_new(jctx.jctx, "bof_file", jboffile);
+	/* draw array */
+	jarray = json_array();
+	if (jarray == NULL) {
+		fprintf(stderr, "%s failed to create json array\n", __func__);
+		r = -EINVAL;
+		goto out_err;
+	}
+	json_object_set_new(jctx.jctx, "draw", jarray);
+	jctx.jdraw_array = jarray;
+	for (i = 0; i < ctx->ndraw; i++) {
+		jdraw = radeon_json_load_draw(ctx->draw[i]);
+		if (jdraw == NULL) {
+			r = -EINVAL;
+			goto out_err;
+		}
+		if (json_array_append_new(jarray, jdraw)) {
+			json_decref(jdraw);
+			r = -EINVAL;
+			goto out_err;
+		}
+	}
+	r = json_dump_file(jctx.jctx, filename, JSON_INDENT(2));
+out_err:
+	json_decref(jctx.jctx);
+	return r;
+}
+
+json_t *radeon_json_load_state(struct radeon_state *state)
+{
+	json_t *jstate, *value, *bo, *array, *placement;
+	const char *name;
+	unsigned i, type;
+	char tmp[16];
+
+	jstate = json_object();
+	if (jstate == NULL) {
+		return NULL;
+	}
+	for (i = 0, type = state->type; i < state->nstates; i++) {
+		name = state->radeon->type[type].regs[i].name;
+		sprintf(tmp, "0x%08X", state->states[i]);
+		value = json_string(tmp);
+		if (value == NULL) {
+			goto out_err;
+		}
+		if (json_object_set_new(jstate, name, value)) {
+			goto out_err;
+		}
+	}
+	array = json_array();
+	if (array == NULL) {
+		goto out_err;
+	}
+	if (json_object_set_new(jstate, "bo", array)) {
+		goto out_err;
+	}
+	for (i = 0; i < state->nbo; i++) {
+		bo = json_object();
+		if (bo == NULL) {
+			goto out_err;
+		}
+		if (json_array_append_new(array, bo)) {
+			goto out_err;
+		}
+		value = json_integer(state->bo[i]->size);
+		if (value == NULL) {
+			goto out_err;
+		}
+		if (json_object_set_new(bo, "size", value)) {
+			goto out_err;
+		}
+		sprintf(tmp, "0x%08X", state->bo[i]->handle);
+		value = json_string(tmp);
+		if (value == NULL) {
+			goto out_err;
+		}
+		if (json_object_set_new(bo, "handle", value)) {
+			goto out_err;
+		}
+		placement = json_array();
+		if (placement == NULL) {
+			goto out_err;
+		}
+		if (json_object_set_new(bo, "placement", placement)) {
+			goto out_err;
+		}
+		sprintf(tmp, "0x%08X", state->placement[i * 2 + 0]);
+		value = json_string(tmp);
+		if (value == NULL) {
+			goto out_err;
+		}
+		if (json_array_append_new(placement, value)) {
+			goto out_err;
+		}
+		sprintf(tmp, "0x%08X", state->placement[i * 2 + 1]);
+		value = json_string(tmp);
+		if (value == NULL) {
+			goto out_err;
+		}
+		if (json_array_append_new(placement, value)) {
+			goto out_err;
+		}
+	}
+	return jstate;
+out_err:
+	json_decref(jstate);
+	return NULL;
+}
+
+json_t *radeon_json_load_draw(struct radeon_draw *draw)
+{
+	json_t *jdraw, *jstate;
+	struct radeon_state *state;
+	char name[256];
+	unsigned i;
+
+	jdraw = json_object();
+	if (jdraw == NULL)
+		return NULL;
+	for (i = 0; i < draw->nstate; i++) {
+		state = draw->state[i];
+		if (state) {
+			sprintf(name, "%s_%04d",
+				draw->radeon->type[state->type].name, i);
+			jstate = radeon_json_load_state(draw->state[i]);
+			if (jstate == NULL) {
+				json_decref(jdraw);
+				return NULL;
+			}
+			if (json_object_set_new(jdraw, name, jstate)) {
+				json_decref(jdraw);
+				return NULL;
+			}
+		}
+	}
+	return jdraw;
+}
+
+struct radeon_state *radeon_state_load_json(struct radeon_ctx *ctx,
+						unsigned type, unsigned id,
+						json_t *jstate)
+{
+	struct radeon_state *state;
+	json_t *value, *bo, *array, *placement;
+	unsigned i, size, handle;
+	const char *name;
+
+	state = radeon_state(ctx->radeon, type, id);
+	if (state == NULL)
+		return NULL;
+	for (i = 0; i < state->nstates; i++) {
+		name = ctx->radeon->type[type].regs[i].name;
+		value = json_object_get(jstate, name);
+		if (value == NULL || !json_is_string(value)) {
+			fprintf(stderr, "missing %s for state %d\n", name, type);
+			return radeon_state_decref(state);
+		}
+		state->states[i] = strtoul(json_string_value(value), NULL, 0);
+	}
+	array = json_object_get(jstate, "bo");
+	if (array == NULL || !json_is_array(array)) {
+		fprintf(stderr, "missing bo array for state %d\n", state->type);
+		return radeon_state_decref(state);
+	}
+	state->nbo = json_array_size(array);
+	for (i = 0; i < state->nbo; i++) {
+		bo = json_array_get(array, i);
+		if (bo == NULL || !json_is_object(bo)) {
+			fprintf(stderr, "missing bo %d array for state %d\n", i, state->type);
+			return radeon_state_decref(state);
+		}
+		value = json_object_get(bo, "size");
+		if (value == NULL) {
+			fprintf(stderr, "missing size for bo %d of state %d\n",
+				i, state->type);
+			return radeon_state_decref(state);
+		}
+		size = json_integer_value(value);
+		value = json_object_get(bo, "handle");
+		if (value == NULL) {
+			fprintf(stderr, "missing handle for bo %d of state %d\n",
+				i, state->type);
+			return radeon_state_decref(state);
+		}
+		handle = strtoul(json_string_value(value), NULL, 0);
+		placement = json_object_get(bo, "placement");
+		if (placement == NULL || !json_is_array(placement) || json_array_size(placement) != 2) {
+			fprintf(stderr, "missing placement for bo %d of state %d\n",
+				i, state->type);
+			return radeon_state_decref(state);
+		}
+		value = json_array_get(placement, 0);
+		state->placement[i * 2 + 0] = strtoul(json_string_value(value), NULL, 0);
+		value = json_array_get(placement, 1);
+		state->placement[i * 2 + 1] = strtoul(json_string_value(value), NULL, 0);
+		state->bo[i] = radeon_ctx_get_object(ctx, handle);
+		if (state->bo[i] == NULL) {
+			return radeon_state_decref(state);
+		}
+	}
+	return state;
+}
+
+struct radeon_draw *radeon_draw_load_json(struct radeon_ctx *ctx,
+						json_t *jdraw)
+{
+	struct radeon_draw *draw;
+	struct radeon_state *state;
+	json_t *jstate;
+	char name[256];
+	unsigned i, type;
+
+	draw = radeon_draw(ctx->radeon);
+	if (draw == NULL)
+		return NULL;
+	for (i = 0; i < draw->nstate; i++) {
+		type = radeon_type_from_id(ctx->radeon, i);
+		sprintf(name, "%s_%04d", draw->radeon->type[type].name, i);
+		jstate = json_object_get(jdraw, name);
+		if (jstate == NULL || !json_is_object(jstate)) {
+			return radeon_draw_decref(draw);
+		}
+		state = radeon_state_load_json(ctx, type, i, jstate);
+		if (state == NULL) {
+			return radeon_draw_decref(draw);
+		}
+		if (radeon_draw_set(draw, state)) {
+			return radeon_draw_decref(draw);
+		}
+	}
+	return 0;
+}
+
+struct radeon_ctx *radeon_ctx_load_json(const char *filename)
+{
+	struct radeon_ctx_json jctx;
+	unsigned device;
+	struct radeon_draw *draw;
+	json_t *tmp, *array, *jdraw;
+	json_error_t error;
+	unsigned i;
+	int r;
+
+	memset(&jctx, 0, sizeof(struct radeon_ctx_json));
+	jctx.jctx = json_load_file(filename, &error);
+	if (jctx.jctx == NULL) {
+		return NULL;
+	}
+	/* device */
+	tmp = json_object_get(jctx.jctx, "device_id");
+	if (tmp == NULL) {
+		fprintf(stderr, "no device id object\n");
+		goto out_err;
+	}
+	device = json_integer_value(tmp);
+	jctx.ctx = radeon_ctx(NULL, device);
+	if (jctx.ctx == NULL) {
+		goto out_err;
+	}
+	tmp = json_object_get(jctx.jctx, "bof_file");
+	if (tmp == NULL || !json_is_string(tmp)) {
+		fprintf(stderr, "no bof_file\n");
+		goto out_err;
+	}
+	jctx.bof_ctx = radeon_ctx_load_bof(json_string_value(tmp));
+	if (jctx.bof_ctx == NULL) {
+		goto out_err;
+	}
+	jctx.ctx->bo = calloc(1, sizeof(struct radeon_ctx_bo) * jctx.bof_ctx->nbo);
+	if (jctx.ctx->bo == NULL) {
+		goto out_err;
+	}
+	jctx.ctx->nbo = jctx.bof_ctx->nbo;
+	memcpy(jctx.ctx->bo, jctx.bof_ctx->bo, sizeof(struct radeon_ctx_bo*) * jctx.ctx->nbo);
+	for (i = 0; i < jctx.ctx->nbo; i++) {
+		radeon_object_incref(jctx.ctx->bo[i].bo);
+		jctx.ctx->bo[i].id = -1;
+	}
+	radeon_ctx_destroy(jctx.bof_ctx);
+	array = json_object_get(jctx.jctx, "draw");
+	if (array == NULL || !json_is_array(array)) {
+		goto out_err;
+	}
+	for (i = 0; i < json_array_size(array); i++) {
+		jdraw = json_array_get(array, i);
+		if (jdraw == NULL || !json_is_object(jdraw))
+			goto out_err;
+		draw = radeon_draw_load_json(jctx.ctx, jdraw);
+		r = radeon_ctx_set_draw_new(jctx.ctx, draw);
+		if (r) {
+			radeon_draw_decref(draw);
+			goto out_err;
+		}
+	}
+	json_decref(jctx.jctx);
+	return jctx.ctx;
+out_err:
+	radeon_ctx_destroy(jctx.bof_ctx);
+	radeon_ctx_destroy(jctx.ctx);
+	json_decref(jctx.jctx);
+	return NULL;
+}
diff --git a/src/radeon_pciid.c b/src/radeon_pciid.c
new file mode 100644
index 0000000..33d3c7f
--- /dev/null
+++ b/src/radeon_pciid.c
@@ -0,0 +1,528 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include "radeon.h"
+
+struct pci_id {
+	unsigned	vendor;
+	unsigned	device;
+	unsigned	family;
+};
+
+struct pci_id radeon_pci_id[] = {
+	{0x1002, 0x3150, CHIP_RV380},
+	{0x1002, 0x3152, CHIP_RV380},
+	{0x1002, 0x3154, CHIP_RV380},
+	{0x1002, 0x3E50, CHIP_RV380},
+	{0x1002, 0x3E54, CHIP_RV380},
+	{0x1002, 0x4136, CHIP_RS100},
+	{0x1002, 0x4137, CHIP_RS200},
+	{0x1002, 0x4144, CHIP_R300}, 
+	{0x1002, 0x4145, CHIP_R300}, 
+	{0x1002, 0x4146, CHIP_R300}, 
+	{0x1002, 0x4147, CHIP_R300}, 
+	{0x1002, 0x4148, CHIP_R350}, 
+	{0x1002, 0x4149, CHIP_R350}, 
+	{0x1002, 0x414A, CHIP_R350}, 
+	{0x1002, 0x414B, CHIP_R350}, 
+	{0x1002, 0x4150, CHIP_RV350}, 
+	{0x1002, 0x4151, CHIP_RV350}, 
+	{0x1002, 0x4152, CHIP_RV350}, 
+	{0x1002, 0x4153, CHIP_RV350}, 
+	{0x1002, 0x4154, CHIP_RV350}, 
+	{0x1002, 0x4155, CHIP_RV350}, 
+	{0x1002, 0x4156, CHIP_RV350}, 
+	{0x1002, 0x4237, CHIP_RS200},
+	{0x1002, 0x4242, CHIP_R200}, 
+	{0x1002, 0x4243, CHIP_R200}, 
+	{0x1002, 0x4336, CHIP_RS100},
+	{0x1002, 0x4337, CHIP_RS200},
+	{0x1002, 0x4437, CHIP_RS200},
+	{0x1002, 0x4966, CHIP_RV250}, 
+	{0x1002, 0x4967, CHIP_RV250}, 
+	{0x1002, 0x4A48, CHIP_R420},
+	{0x1002, 0x4A49, CHIP_R420},
+	{0x1002, 0x4A4A, CHIP_R420},
+	{0x1002, 0x4A4B, CHIP_R420},
+	{0x1002, 0x4A4C, CHIP_R420},
+	{0x1002, 0x4A4D, CHIP_R420},
+	{0x1002, 0x4A4E, CHIP_R420},
+	{0x1002, 0x4A4F, CHIP_R420},
+	{0x1002, 0x4A50, CHIP_R420},
+	{0x1002, 0x4A54, CHIP_R420},
+	{0x1002, 0x4B48, CHIP_R420},
+	{0x1002, 0x4B49, CHIP_R420},
+	{0x1002, 0x4B4A, CHIP_R420},
+	{0x1002, 0x4B4B, CHIP_R420},
+	{0x1002, 0x4B4C, CHIP_R420},
+	{0x1002, 0x4C57, CHIP_RV200},
+	{0x1002, 0x4C58, CHIP_RV200},
+	{0x1002, 0x4C59, CHIP_RV100},
+	{0x1002, 0x4C5A, CHIP_RV100},
+	{0x1002, 0x4C64, CHIP_RV250},
+	{0x1002, 0x4C66, CHIP_RV250},
+	{0x1002, 0x4C67, CHIP_RV250},
+	{0x1002, 0x4E44, CHIP_R300}, 
+	{0x1002, 0x4E45, CHIP_R300}, 
+	{0x1002, 0x4E46, CHIP_R300}, 
+	{0x1002, 0x4E47, CHIP_R300}, 
+	{0x1002, 0x4E48, CHIP_R350}, 
+	{0x1002, 0x4E49, CHIP_R350}, 
+	{0x1002, 0x4E4A, CHIP_R350}, 
+	{0x1002, 0x4E4B, CHIP_R350}, 
+	{0x1002, 0x4E50, CHIP_RV350},
+	{0x1002, 0x4E51, CHIP_RV350},
+	{0x1002, 0x4E52, CHIP_RV350},
+	{0x1002, 0x4E53, CHIP_RV350},
+	{0x1002, 0x4E54, CHIP_RV350},
+	{0x1002, 0x4E56, CHIP_RV350},
+	{0x1002, 0x5144, CHIP_R100},
+	{0x1002, 0x5145, CHIP_R100},
+	{0x1002, 0x5146, CHIP_R100},
+	{0x1002, 0x5147, CHIP_R100},
+	{0x1002, 0x5148, CHIP_R200}, 
+	{0x1002, 0x514C, CHIP_R200}, 
+	{0x1002, 0x514D, CHIP_R200}, 
+	{0x1002, 0x5157, CHIP_RV200}, 
+	{0x1002, 0x5158, CHIP_RV200}, 
+	{0x1002, 0x5159, CHIP_RV100}, 
+	{0x1002, 0x515A, CHIP_RV100}, 
+	{0x1002, 0x515E, CHIP_RV100},
+	{0x1002, 0x5460, CHIP_RV380},
+	{0x1002, 0x5462, CHIP_RV380},
+	{0x1002, 0x5464, CHIP_RV380},
+	{0x1002, 0x5657, CHIP_RV380},
+	{0x1002, 0x5548, CHIP_R423},
+	{0x1002, 0x5549, CHIP_R423},
+	{0x1002, 0x554A, CHIP_R423},
+	{0x1002, 0x554B, CHIP_R423},
+	{0x1002, 0x554C, CHIP_R423},
+	{0x1002, 0x554D, CHIP_R423},
+	{0x1002, 0x554E, CHIP_R423},
+	{0x1002, 0x554F, CHIP_R423},
+	{0x1002, 0x5550, CHIP_R423},
+	{0x1002, 0x5551, CHIP_R423},
+	{0x1002, 0x5552, CHIP_R423},
+	{0x1002, 0x5554, CHIP_R423},
+	{0x1002, 0x564A, CHIP_RV410},
+	{0x1002, 0x564B, CHIP_RV410},
+	{0x1002, 0x564F, CHIP_RV410},
+	{0x1002, 0x5652, CHIP_RV410},
+	{0x1002, 0x5653, CHIP_RV410},
+	{0x1002, 0x5834, CHIP_RS300},
+	{0x1002, 0x5835, CHIP_RS300},
+	{0x1002, 0x5954, CHIP_RS480},
+	{0x1002, 0x5955, CHIP_RS480},
+	{0x1002, 0x5974, CHIP_RS480},
+	{0x1002, 0x5975, CHIP_RS480},
+	{0x1002, 0x5960, CHIP_RV280}, 
+	{0x1002, 0x5961, CHIP_RV280}, 
+	{0x1002, 0x5962, CHIP_RV280}, 
+	{0x1002, 0x5964, CHIP_RV280}, 
+	{0x1002, 0x5965, CHIP_RV280},
+	{0x1002, 0x5969, CHIP_RV100},
+	{0x1002, 0x5a41, CHIP_RS400},
+	{0x1002, 0x5a42, CHIP_RS400},
+	{0x1002, 0x5a61, CHIP_RS400},
+	{0x1002, 0x5a62, CHIP_RS400},
+	{0x1002, 0x5b60, CHIP_RV380},
+	{0x1002, 0x5b62, CHIP_RV380},
+	{0x1002, 0x5b63, CHIP_RV380},
+	{0x1002, 0x5b64, CHIP_RV380},
+	{0x1002, 0x5b65, CHIP_RV380},
+	{0x1002, 0x5c61, CHIP_RV280},
+	{0x1002, 0x5c63, CHIP_RV280},
+	{0x1002, 0x5d48, CHIP_R423},
+	{0x1002, 0x5d49, CHIP_R423},
+	{0x1002, 0x5d4a, CHIP_R423},
+	{0x1002, 0x5d4c, CHIP_R423},
+	{0x1002, 0x5d4d, CHIP_R423},
+	{0x1002, 0x5d4e, CHIP_R423},
+	{0x1002, 0x5d4f, CHIP_R423},
+	{0x1002, 0x5d50, CHIP_R423},
+	{0x1002, 0x5d52, CHIP_R423},
+	{0x1002, 0x5d57, CHIP_R423},
+	{0x1002, 0x5e48, CHIP_RV410},
+	{0x1002, 0x5e4a, CHIP_RV410},
+	{0x1002, 0x5e4b, CHIP_RV410},
+	{0x1002, 0x5e4c, CHIP_RV410},
+	{0x1002, 0x5e4d, CHIP_RV410},
+	{0x1002, 0x5e4f, CHIP_RV410},
+	{0x1002, 0x6880, CHIP_CYPRESS},
+	{0x1002, 0x6888, CHIP_CYPRESS},
+	{0x1002, 0x6889, CHIP_CYPRESS},
+	{0x1002, 0x688A, CHIP_CYPRESS},
+	{0x1002, 0x6898, CHIP_CYPRESS},
+	{0x1002, 0x6899, CHIP_CYPRESS},
+	{0x1002, 0x689c, CHIP_HEMLOCK},
+	{0x1002, 0x689d, CHIP_HEMLOCK},
+	{0x1002, 0x689e, CHIP_CYPRESS},
+	{0x1002, 0x68a0, CHIP_JUNIPER},
+	{0x1002, 0x68a1, CHIP_JUNIPER},
+	{0x1002, 0x68a8, CHIP_JUNIPER},
+	{0x1002, 0x68a9, CHIP_JUNIPER},
+	{0x1002, 0x68b0, CHIP_JUNIPER},
+	{0x1002, 0x68b8, CHIP_JUNIPER},
+	{0x1002, 0x68b9, CHIP_JUNIPER},
+	{0x1002, 0x68be, CHIP_JUNIPER},
+	{0x1002, 0x68c0, CHIP_REDWOOD},
+	{0x1002, 0x68c1, CHIP_REDWOOD},
+	{0x1002, 0x68c8, CHIP_REDWOOD},
+	{0x1002, 0x68c9, CHIP_REDWOOD},
+	{0x1002, 0x68d8, CHIP_REDWOOD},
+	{0x1002, 0x68d9, CHIP_REDWOOD},
+	{0x1002, 0x68da, CHIP_REDWOOD},
+	{0x1002, 0x68de, CHIP_REDWOOD},
+	{0x1002, 0x68e0, CHIP_CEDAR},
+	{0x1002, 0x68e1, CHIP_CEDAR},
+	{0x1002, 0x68e4, CHIP_CEDAR},
+	{0x1002, 0x68e5, CHIP_CEDAR},
+	{0x1002, 0x68e8, CHIP_CEDAR},
+	{0x1002, 0x68e9, CHIP_CEDAR},
+	{0x1002, 0x68f1, CHIP_CEDAR},
+	{0x1002, 0x68f8, CHIP_CEDAR},
+	{0x1002, 0x68f9, CHIP_CEDAR},
+	{0x1002, 0x68fe, CHIP_CEDAR},
+	{0x1002, 0x7100, CHIP_R520},
+	{0x1002, 0x7101, CHIP_R520},
+	{0x1002, 0x7102, CHIP_R520},
+	{0x1002, 0x7103, CHIP_R520},
+	{0x1002, 0x7104, CHIP_R520},
+	{0x1002, 0x7105, CHIP_R520},
+	{0x1002, 0x7106, CHIP_R520},
+	{0x1002, 0x7108, CHIP_R520},
+	{0x1002, 0x7109, CHIP_R520},
+	{0x1002, 0x710A, CHIP_R520},
+	{0x1002, 0x710B, CHIP_R520},
+	{0x1002, 0x710C, CHIP_R520},
+	{0x1002, 0x710E, CHIP_R520},
+	{0x1002, 0x710F, CHIP_R520},
+	{0x1002, 0x7140, CHIP_RV515},
+	{0x1002, 0x7141, CHIP_RV515},
+	{0x1002, 0x7142, CHIP_RV515},
+	{0x1002, 0x7143, CHIP_RV515},
+	{0x1002, 0x7144, CHIP_RV515},
+	{0x1002, 0x7145, CHIP_RV515},
+	{0x1002, 0x7146, CHIP_RV515},
+	{0x1002, 0x7147, CHIP_RV515},
+	{0x1002, 0x7149, CHIP_RV515},
+	{0x1002, 0x714A, CHIP_RV515},
+	{0x1002, 0x714B, CHIP_RV515},
+	{0x1002, 0x714C, CHIP_RV515},
+	{0x1002, 0x714D, CHIP_RV515},
+	{0x1002, 0x714E, CHIP_RV515},
+	{0x1002, 0x714F, CHIP_RV515},
+	{0x1002, 0x7151, CHIP_RV515},
+	{0x1002, 0x7152, CHIP_RV515},
+	{0x1002, 0x7153, CHIP_RV515},
+	{0x1002, 0x715E, CHIP_RV515},
+	{0x1002, 0x715F, CHIP_RV515},
+	{0x1002, 0x7180, CHIP_RV515},
+	{0x1002, 0x7181, CHIP_RV515},
+	{0x1002, 0x7183, CHIP_RV515},
+	{0x1002, 0x7186, CHIP_RV515},
+	{0x1002, 0x7187, CHIP_RV515},
+	{0x1002, 0x7188, CHIP_RV515},
+	{0x1002, 0x718A, CHIP_RV515},
+	{0x1002, 0x718B, CHIP_RV515},
+	{0x1002, 0x718C, CHIP_RV515},
+	{0x1002, 0x718D, CHIP_RV515},
+	{0x1002, 0x718F, CHIP_RV515},
+	{0x1002, 0x7193, CHIP_RV515},
+	{0x1002, 0x7196, CHIP_RV515},
+	{0x1002, 0x719B, CHIP_RV515},
+	{0x1002, 0x719F, CHIP_RV515},
+	{0x1002, 0x71C0, CHIP_RV530},
+	{0x1002, 0x71C1, CHIP_RV530},
+	{0x1002, 0x71C2, CHIP_RV530},
+	{0x1002, 0x71C3, CHIP_RV530},
+	{0x1002, 0x71C4, CHIP_RV530},
+	{0x1002, 0x71C5, CHIP_RV530},
+	{0x1002, 0x71C6, CHIP_RV530},
+	{0x1002, 0x71C7, CHIP_RV530},
+	{0x1002, 0x71CD, CHIP_RV530},
+	{0x1002, 0x71CE, CHIP_RV530},
+	{0x1002, 0x71D2, CHIP_RV530},
+	{0x1002, 0x71D4, CHIP_RV530},
+	{0x1002, 0x71D5, CHIP_RV530},
+	{0x1002, 0x71D6, CHIP_RV530},
+	{0x1002, 0x71DA, CHIP_RV530},
+	{0x1002, 0x71DE, CHIP_RV530},
+	{0x1002, 0x7200, CHIP_RV515},
+	{0x1002, 0x7210, CHIP_RV515},
+	{0x1002, 0x7211, CHIP_RV515},
+	{0x1002, 0x7240, CHIP_R580},
+	{0x1002, 0x7243, CHIP_R580},
+	{0x1002, 0x7244, CHIP_R580},
+	{0x1002, 0x7245, CHIP_R580},
+	{0x1002, 0x7246, CHIP_R580},
+	{0x1002, 0x7247, CHIP_R580},
+	{0x1002, 0x7248, CHIP_R580},
+	{0x1002, 0x7249, CHIP_R580},
+	{0x1002, 0x724A, CHIP_R580},
+	{0x1002, 0x724B, CHIP_R580},
+	{0x1002, 0x724C, CHIP_R580},
+	{0x1002, 0x724D, CHIP_R580},
+	{0x1002, 0x724E, CHIP_R580},
+	{0x1002, 0x724F, CHIP_R580},
+	{0x1002, 0x7280, CHIP_RV570},
+	{0x1002, 0x7281, CHIP_RV560},
+	{0x1002, 0x7283, CHIP_RV560},
+	{0x1002, 0x7284, CHIP_R580},
+	{0x1002, 0x7287, CHIP_RV560},
+	{0x1002, 0x7288, CHIP_RV570},
+	{0x1002, 0x7289, CHIP_RV570},
+	{0x1002, 0x728B, CHIP_RV570},
+	{0x1002, 0x728C, CHIP_RV570},
+	{0x1002, 0x7290, CHIP_RV560},
+	{0x1002, 0x7291, CHIP_RV560},
+	{0x1002, 0x7293, CHIP_RV560},
+	{0x1002, 0x7297, CHIP_RV560},
+	{0x1002, 0x7834, CHIP_RS300},
+	{0x1002, 0x7835, CHIP_RS300},
+	{0x1002, 0x791e, CHIP_RS690},
+	{0x1002, 0x791f, CHIP_RS690},
+	{0x1002, 0x793f, CHIP_RS600},
+	{0x1002, 0x7941, CHIP_RS600},
+	{0x1002, 0x7942, CHIP_RS600},
+	{0x1002, 0x796c, CHIP_RS740},
+	{0x1002, 0x796d, CHIP_RS740},
+	{0x1002, 0x796e, CHIP_RS740},
+	{0x1002, 0x796f, CHIP_RS740},
+	{0x1002, 0x9400, CHIP_R600},
+	{0x1002, 0x9401, CHIP_R600},
+	{0x1002, 0x9402, CHIP_R600},
+	{0x1002, 0x9403, CHIP_R600},
+	{0x1002, 0x9405, CHIP_R600},
+	{0x1002, 0x940A, CHIP_R600},
+	{0x1002, 0x940B, CHIP_R600},
+	{0x1002, 0x940F, CHIP_R600},
+	{0x1002, 0x94A0, CHIP_RV740},
+	{0x1002, 0x94A1, CHIP_RV740},
+	{0x1002, 0x94A3, CHIP_RV740},
+	{0x1002, 0x94B1, CHIP_RV740},
+	{0x1002, 0x94B3, CHIP_RV740},
+	{0x1002, 0x94B4, CHIP_RV740},
+	{0x1002, 0x94B5, CHIP_RV740},
+	{0x1002, 0x94B9, CHIP_RV740},
+	{0x1002, 0x9440, CHIP_RV770},
+	{0x1002, 0x9441, CHIP_RV770},
+	{0x1002, 0x9442, CHIP_RV770},
+	{0x1002, 0x9443, CHIP_RV770},
+	{0x1002, 0x9444, CHIP_RV770},
+	{0x1002, 0x9446, CHIP_RV770},
+	{0x1002, 0x944A, CHIP_RV770},
+	{0x1002, 0x944B, CHIP_RV770},
+	{0x1002, 0x944C, CHIP_RV770},
+	{0x1002, 0x944E, CHIP_RV770},
+	{0x1002, 0x9450, CHIP_RV770},
+	{0x1002, 0x9452, CHIP_RV770},
+	{0x1002, 0x9456, CHIP_RV770},
+	{0x1002, 0x945A, CHIP_RV770},
+	{0x1002, 0x945B, CHIP_RV770},
+	{0x1002, 0x9460, CHIP_RV770},
+	{0x1002, 0x9462, CHIP_RV770},
+	{0x1002, 0x946A, CHIP_RV770},
+	{0x1002, 0x946B, CHIP_RV770},
+	{0x1002, 0x947A, CHIP_RV770},
+	{0x1002, 0x947B, CHIP_RV770},
+	{0x1002, 0x9480, CHIP_RV730},
+	{0x1002, 0x9487, CHIP_RV730},
+	{0x1002, 0x9488, CHIP_RV730},
+	{0x1002, 0x9489, CHIP_RV730},
+	{0x1002, 0x948F, CHIP_RV730},
+	{0x1002, 0x9490, CHIP_RV730},
+	{0x1002, 0x9491, CHIP_RV730},
+	{0x1002, 0x9495, CHIP_RV730},
+	{0x1002, 0x9498, CHIP_RV730},
+	{0x1002, 0x949C, CHIP_RV730},
+	{0x1002, 0x949E, CHIP_RV730},
+	{0x1002, 0x949F, CHIP_RV730},
+	{0x1002, 0x94C0, CHIP_RV610},
+	{0x1002, 0x94C1, CHIP_RV610},
+	{0x1002, 0x94C3, CHIP_RV610},
+	{0x1002, 0x94C4, CHIP_RV610},
+	{0x1002, 0x94C5, CHIP_RV610},
+	{0x1002, 0x94C6, CHIP_RV610},
+	{0x1002, 0x94C7, CHIP_RV610},
+	{0x1002, 0x94C8, CHIP_RV610},
+	{0x1002, 0x94C9, CHIP_RV610},
+	{0x1002, 0x94CB, CHIP_RV610},
+	{0x1002, 0x94CC, CHIP_RV610},
+	{0x1002, 0x94CD, CHIP_RV610},
+	{0x1002, 0x9500, CHIP_RV670},
+	{0x1002, 0x9501, CHIP_RV670},
+	{0x1002, 0x9504, CHIP_RV670},
+	{0x1002, 0x9505, CHIP_RV670},
+	{0x1002, 0x9506, CHIP_RV670},
+	{0x1002, 0x9507, CHIP_RV670},
+	{0x1002, 0x9508, CHIP_RV670},
+	{0x1002, 0x9509, CHIP_RV670},
+	{0x1002, 0x950F, CHIP_RV670},
+	{0x1002, 0x9511, CHIP_RV670},
+	{0x1002, 0x9515, CHIP_RV670},
+	{0x1002, 0x9517, CHIP_RV670},
+	{0x1002, 0x9519, CHIP_RV670},
+	{0x1002, 0x9540, CHIP_RV710},
+	{0x1002, 0x9541, CHIP_RV710},
+	{0x1002, 0x9542, CHIP_RV710},
+	{0x1002, 0x954E, CHIP_RV710},
+	{0x1002, 0x954F, CHIP_RV710},
+	{0x1002, 0x9552, CHIP_RV710},
+	{0x1002, 0x9553, CHIP_RV710},
+	{0x1002, 0x9555, CHIP_RV710},
+	{0x1002, 0x9557, CHIP_RV710},
+	{0x1002, 0x9580, CHIP_RV630},
+	{0x1002, 0x9581, CHIP_RV630},
+	{0x1002, 0x9583, CHIP_RV630},
+	{0x1002, 0x9586, CHIP_RV630},
+	{0x1002, 0x9587, CHIP_RV630},
+	{0x1002, 0x9588, CHIP_RV630},
+	{0x1002, 0x9589, CHIP_RV630},
+	{0x1002, 0x958A, CHIP_RV630},
+	{0x1002, 0x958B, CHIP_RV630},
+	{0x1002, 0x958C, CHIP_RV630},
+	{0x1002, 0x958D, CHIP_RV630},
+	{0x1002, 0x958E, CHIP_RV630},
+	{0x1002, 0x958F, CHIP_RV630},
+	{0x1002, 0x9590, CHIP_RV635},
+	{0x1002, 0x9591, CHIP_RV635},
+	{0x1002, 0x9593, CHIP_RV635},
+	{0x1002, 0x9595, CHIP_RV635},
+	{0x1002, 0x9596, CHIP_RV635},
+	{0x1002, 0x9597, CHIP_RV635},
+	{0x1002, 0x9598, CHIP_RV635},
+	{0x1002, 0x9599, CHIP_RV635},
+	{0x1002, 0x959B, CHIP_RV635},
+	{0x1002, 0x95C0, CHIP_RV620},
+	{0x1002, 0x95C2, CHIP_RV620},
+	{0x1002, 0x95C4, CHIP_RV620},
+	{0x1002, 0x95C5, CHIP_RV620},
+	{0x1002, 0x95C6, CHIP_RV620},
+	{0x1002, 0x95C7, CHIP_RV620},
+	{0x1002, 0x95C9, CHIP_RV620},
+	{0x1002, 0x95CC, CHIP_RV620},
+	{0x1002, 0x95CD, CHIP_RV620},
+	{0x1002, 0x95CE, CHIP_RV620},
+	{0x1002, 0x95CF, CHIP_RV620},
+	{0x1002, 0x9610, CHIP_RS780},
+	{0x1002, 0x9611, CHIP_RS780},
+	{0x1002, 0x9612, CHIP_RS780},
+	{0x1002, 0x9613, CHIP_RS780},
+	{0x1002, 0x9614, CHIP_RS780},
+	{0x1002, 0x9615, CHIP_RS780},
+	{0x1002, 0x9616, CHIP_RS780},
+	{0x1002, 0x9710, CHIP_RS880},
+	{0x1002, 0x9711, CHIP_RS880},
+	{0x1002, 0x9712, CHIP_RS880},
+	{0x1002, 0x9713, CHIP_RS880},
+	{0x1002, 0x9714, CHIP_RS880},
+	{0x1002, 0x9715, CHIP_RS880},
+	{0, 0},
+};
+
+unsigned radeon_family_from_device(unsigned device)
+{
+	unsigned i;
+
+	for (i = 0; ; i++) {
+		if (!radeon_pci_id[i].vendor)
+			return CHIP_UNKNOWN;
+		if (radeon_pci_id[i].device == device)
+			return radeon_pci_id[i].family;
+	}
+	return CHIP_UNKNOWN;
+}
+
+int radeon_is_family_compatible(unsigned family1, unsigned family2)
+{
+	switch (family1) {
+	case CHIP_R600:
+	case CHIP_RV610:
+	case CHIP_RV630:
+	case CHIP_RV670:
+	case CHIP_RV620:
+	case CHIP_RV635:
+	case CHIP_RS780:
+	case CHIP_RS880:
+	case CHIP_RV770:
+	case CHIP_RV730:
+	case CHIP_RV710:
+	case CHIP_RV740:
+		switch (family2) {
+		case CHIP_R600:
+		case CHIP_RV610:
+		case CHIP_RV630:
+		case CHIP_RV670:
+		case CHIP_RV620:
+		case CHIP_RV635:
+		case CHIP_RS780:
+		case CHIP_RS880:
+		case CHIP_RV770:
+		case CHIP_RV730:
+		case CHIP_RV710:
+		case CHIP_RV740:
+			return 1;
+		default:
+			return 0;
+		}
+		break;
+	case CHIP_R100:
+	case CHIP_RV100:
+	case CHIP_RS100:
+	case CHIP_RV200:
+	case CHIP_RS200:
+	case CHIP_R200:
+	case CHIP_RV250:
+	case CHIP_RS300:
+	case CHIP_RV280:
+	case CHIP_R300:
+	case CHIP_R350:
+	case CHIP_RV350:
+	case CHIP_RV380:
+	case CHIP_R420:
+	case CHIP_R423:
+	case CHIP_RV410:
+	case CHIP_RS400:
+	case CHIP_RS480:
+	case CHIP_RS600:
+	case CHIP_RS690:
+	case CHIP_RS740:
+	case CHIP_RV515:
+	case CHIP_R520:
+	case CHIP_RV530:
+	case CHIP_RV560:
+	case CHIP_RV570:
+	case CHIP_R580:
+	case CHIP_CEDAR:
+	case CHIP_REDWOOD:
+	case CHIP_JUNIPER:
+	case CHIP_CYPRESS:
+	case CHIP_HEMLOCK:
+	default:
+		return 0;
+	}
+}
diff --git a/src/radeon_priv.h b/src/radeon_priv.h
new file mode 100644
index 0000000..758c6c6
--- /dev/null
+++ b/src/radeon_priv.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright © 2009 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#ifndef RADEON_PRIV_H
+#define RADEON_PRIV_H
+
+#include <stdint.h>
+#include "xf86drm.h"
+#include "xf86drmMode.h"
+#include "radeon_bo.h"
+#include "radeon_cs.h"
+#include <errno.h>
+#include <jansson.h>
+#include "bof.h"
+#include "radeon.h"
+
+struct radeon;
+struct radeon_ctx;
+struct radeon_surface;
+
+#define slist_init(e) do { (e)->next = e; (e)->prev = e; } while(0)
+#define slist_add(e, h) do { (e)->next = (h)->next; (e)->prev = h;  (h)->next = e; (e)->next->prev = e; } while(0)
+#define slist_add_tail(e, h) do { (e)->next = h; (e)->prev = (h)->prev;  (h)->prev = e; (e)->prev->next = e; } while(0)
+#define slist_del_init(e) do { (e)->next->prev = (e)->prev; (e)->prev->next = (e)->next; slist_init(e); } while(0)
+#define slist_empty(h) ((h)->next == (h))
+#define slist_for_each(p, h) for (p = (h)->next; p != (h); p = p->next)
+#define slist_for_each_from(p, s, h) for (p = s; p != (h); p = p->next)
+#define slist_for_each_safe(p, n, h) for (p = (h)->next, n = p->next; p != (h); p = n, n = p->next)
+
+/*
+ * asic backend
+ */
+struct radeon_asic {
+	int (*ctx_draw)(struct radeon_ctx *ctx);
+	int (*ctx_get_dst_surface)(struct radeon_ctx *ctx, struct radeon_surface *dst);
+	int (*ctx_next_reloc)(struct radeon_ctx *ctx, unsigned *reloc);
+};
+
+/*
+ * mode functions
+ */
+struct radeon_mode {
+	drmModeModeInfo		info;
+	u32			pitch;
+	u32			height;
+	u32			bpp;
+	u32			size;
+	u32			encoder_id;
+	u32			connector_id;
+	u32			crtc_id;
+	u32			fb_id;
+	struct radeon_bo	*bo;
+};
+extern int radeon_mode_configure(struct radeon *radeon);
+extern void radeon_mode_cleanup(struct radeon *radeon);
+
+/*
+ * blit functions
+ */
+struct radeon_surface {
+	struct radeon_bo		*bo;
+	unsigned			bpe;
+	unsigned			pitch;
+	unsigned			width;
+	unsigned			height;
+};
+void radeon_blit(struct radeon_surface *dst, struct radeon_surface *src,
+		unsigned sx, unsigned sy, unsigned dx, unsigned dy,
+		unsigned w, unsigned h);
+
+/*
+ * radeon functions
+ */
+typedef int (*radeon_state_pm4_t)(struct radeon_state *state);
+struct radeon_register {
+	unsigned			offset;
+	unsigned			need_reloc;
+	unsigned			bo_id;
+	char				name[64];
+};
+
+struct radeon_type {
+	unsigned			npm4;
+	unsigned			id;
+	unsigned			range_start;
+	unsigned			range_end;
+	unsigned			stride;
+	unsigned			immediate;
+	char				name[64];
+	unsigned			nstates;
+	radeon_state_pm4_t		pm4;
+	const struct radeon_register	*regs;
+};
+
+struct radeon {
+	int				fd;
+	int				refcount;
+	struct radeon_mode		mode;
+	struct radeon_bo_manager	*bom;
+	struct radeon_cs_manager	*csm;
+	unsigned			device;
+	unsigned			family;
+	unsigned			nstate;
+	unsigned			ntype;
+	const struct radeon_type	*type;
+	const struct radeon_asic	*asic;
+	struct radeon_ctx		*ctx;
+};
+
+extern int radeon_open_fd(void);
+extern struct radeon *radeon_new(int fd, unsigned device);
+extern struct radeon *radeon_incref(struct radeon *radeon);
+extern struct radeon *radeon_decref(struct radeon *radeon);
+extern unsigned radeon_family_from_device(unsigned device);
+extern int radeon_is_family_compatible(unsigned family1, unsigned family2);
+extern int radeon_reg_id(struct radeon *radeon, unsigned offset, unsigned *typeid, unsigned *stateid, unsigned *id);
+extern unsigned radeon_type_from_id(struct radeon *radeon, unsigned id);
+extern int radeon_schedule_draw(struct radeon *radeon, struct radeon_draw *draw);
+
+/*
+ * radeon context functions
+ */
+struct radeon_ctx_bo {
+	int			id;
+	struct radeon_object	*bo;
+};
+
+struct radeon_ctx {
+	struct radeon			*radeon;
+	u32				*pm4;
+	u32				cpm4;
+	unsigned			id;
+	unsigned			next_id;
+	u32				*reloc;
+	u32				reloc_ndw;
+	unsigned			nbo;
+	struct radeon_ctx_bo		*bo;
+	unsigned			ndraw;
+	struct radeon_draw		*cdraw;
+	struct radeon_draw		**draw;
+};
+
+extern struct radeon_ctx *radeon_ctx(struct radeon *radeon, unsigned device);
+extern void radeon_ctx_destroy(struct radeon_ctx *ctx);
+extern int radeon_ctx_set_object_new(struct radeon_ctx *ctx,
+					struct radeon_object *bo,
+					int id);
+extern struct radeon_object *radeon_ctx_get_object(struct radeon_ctx *ctx, unsigned handle);
+extern struct radeon_object *radeon_ctx_get_bo(struct radeon_ctx *ctx, unsigned reloc);
+extern void radeon_ctx_get_placement(struct radeon_ctx *ctx, unsigned reloc, u32 *placement);
+extern int radeon_ctx_allocate_bo(struct radeon_ctx *ctx);
+extern int radeon_ctx_submit(struct radeon_ctx *ctx);
+extern int radeon_ctx_draw(struct radeon_ctx *ctx);
+extern int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
+extern int radeon_ctx_draw_schedule(struct radeon_ctx *ctx, unsigned id);
+extern int radeon_ctx_draw_set_reg(struct radeon_ctx *ctx, unsigned offset, u32 value);
+
+/*
+ * r600/r700 context functions
+ */
+extern int r600_init(struct radeon *radeon);
+extern int r600_ctx_draw(struct radeon_ctx *ctx);
+extern int r600_ctx_get_dst_surface(struct radeon_ctx *ctx, struct radeon_surface *dst);
+extern int r600_ctx_next_reloc(struct radeon_ctx *ctx, unsigned *reloc);
+
+/*
+ * radeon state functions
+ */
+extern u32 radeon_state_register_get(struct radeon_state *state, unsigned offset);
+extern int radeon_state_register_set(struct radeon_state *state, unsigned offset, u32 value);
+extern struct radeon_state *radeon_state_duplicate(struct radeon_state *state);
+extern int radeon_state_replace_always(struct radeon_state *ostate, struct radeon_state *nstate);
+extern int radeon_state_pm4_generic(struct radeon_state *state);
+extern int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id);
+
+/*
+ * radeon draw functions
+ */
+extern struct radeon_draw *radeon_draw_duplicate(struct radeon_draw *draw);
+extern int radeon_draw_pm4(struct radeon_draw *draw);
+
+/*
+ * bof functions
+ */
+extern struct radeon_ctx *radeon_ctx_load_bof(const char *filename);
+
+/*
+ * json functions
+ */
+struct radeon_ctx_json {
+	struct radeon_ctx	*ctx;
+	struct radeon_ctx	*bof_ctx;
+	json_t			*jdraw_array;
+	json_t			*jctx;
+};
+extern int radeon_ctx_dump_json(struct radeon_ctx *ctx, const char *filename);
+extern struct radeon_ctx *radeon_ctx_load_json(const char *filename);
+extern json_t *radeon_json_load_draw(struct radeon_draw *draw);
+
+/*
+ * helpers
+ */
+extern void *copy_object(void *ptr, unsigned size);
+extern void memset_bo(struct radeon_bo *bo, u32 value);
+extern void memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size);
+
+#define radeon_ctx_get_dst_surface(ctx, dst) (ctx)->radeon->asic->ctx_get_dst_surface((ctx), (dst))
+#define radeon_ctx_next_reloc(ctx, reloc) (ctx)->radeon->asic->ctx_next_reloc(ctx, reloc)
+
+#endif
diff --git a/src/radeon_state.c b/src/radeon_state.c
new file mode 100644
index 0000000..2a568a9
--- /dev/null
+++ b/src/radeon_state.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include "radeon_priv.h"
+
+/*
+ * state core functions
+ */
+struct radeon_state *radeon_state(struct radeon *radeon, u32 type, u32 id)
+{
+	struct radeon_state *state;
+
+	if (type > radeon->ntype) {
+		fprintf(stderr, "%s invalid type %d\n", __func__, type);
+		return NULL;
+	}
+	if (id > radeon->nstate) {
+		fprintf(stderr, "%s invalid state id %d\n", __func__, id);
+		return NULL;
+	}
+	state = calloc(1, sizeof(*state));
+	if (state == NULL)
+		return NULL;
+	state->radeon = radeon;
+	state->type = type;
+	state->id = id;
+	state->refcount = 1;
+	state->npm4 = radeon->type[type].npm4;
+	state->nstates = radeon->type[type].nstates;
+	state->states = calloc(1, state->nstates * 4);
+	state->pm4 = calloc(1, radeon->type[type].npm4 * 4);
+	if (state->states == NULL || state->pm4 == NULL) {
+		radeon_state_decref(state);
+		return NULL;
+	}
+	return state;
+}
+
+struct radeon_state *radeon_state_duplicate(struct radeon_state *state)
+{
+	struct radeon_state *nstate = radeon_state(state->radeon, state->type, state->id);
+	unsigned i;
+
+	if (state == NULL)
+		return NULL;
+	nstate->cpm4 = state->cpm4;
+	nstate->nbo = state->nbo;
+	nstate->nreloc = state->nreloc;
+	memcpy(nstate->states, state->states, state->nstates * 4);
+	memcpy(nstate->pm4, state->pm4, state->npm4 * 4);
+	memcpy(nstate->placement, state->placement, 8 * 4);
+	memcpy(nstate->reloc_pm4_id, state->reloc_pm4_id, 8 * 4);
+	memcpy(nstate->reloc_bo_id, state->reloc_bo_id, 8 * 4);
+	memcpy(nstate->bo_dirty, state->bo_dirty, 4 * 4);
+	for (i = 0; i < state->nbo; i++) {
+		nstate->bo[i] = radeon_object_incref(state->bo[i]);
+	}
+	return nstate;
+}
+
+struct radeon_state *radeon_state_incref(struct radeon_state *state)
+{
+	state->refcount++;
+	return state;
+}
+
+struct radeon_state *radeon_state_decref(struct radeon_state *state)
+{
+	unsigned i;
+
+	if (state == NULL)
+		return NULL;
+	if (--state->refcount > 0) {
+		return NULL;
+	}
+	for (i = 0; i < state->nbo; i++) {
+		state->bo[i] = radeon_object_decref(state->bo[i]);
+	}
+	free(state->states);
+	free(state->pm4);
+	memset(state, 0, sizeof(*state));
+	free(state);
+	return NULL;
+}
+
+int radeon_state_replace_always(struct radeon_state *ostate,
+				struct radeon_state *nstate)
+{
+	return 1;
+}
+
+int radeon_state_pm4_generic(struct radeon_state *state)
+{
+	return -EINVAL;
+}
+
+u32 crc32(void *d, size_t len)
+{
+	u16 *data = (uint16_t*)d;
+	u32 sum1 = 0xffff, sum2 = 0xffff;
+
+	len = len >> 1;
+	while (len) {
+		unsigned tlen = len > 360 ? 360 : len;
+		len -= tlen;
+		do {
+			sum1 += *data++;
+			sum2 += sum1;
+		} while (--tlen);
+		sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+		sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+	}
+	/* Second reduction step to reduce sums to 16 bits */
+	sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+	sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+	return sum2 << 16 | sum1;
+}
+
+int radeon_state_pm4(struct radeon_state *state)
+{
+	int r;
+
+	if (state == NULL)
+		return 0;
+	state->cpm4 = 0;
+	r = state->radeon->type[state->type].pm4(state);
+	if (r) {
+		return r;
+	}
+	state->pm4_crc = crc32(state->pm4, state->cpm4);
+	return 0;
+}
+
+int radeon_state_reloc(struct radeon_state *state, unsigned id, unsigned bo_id)
+{
+	state->reloc_pm4_id[state->nreloc] = id;
+	state->reloc_bo_id[state->nreloc] = bo_id;
+	state->nreloc++;
+	return 0;
+}
diff --git a/src/radeondb.c b/src/radeondb.c
new file mode 100644
index 0000000..5fb5711
--- /dev/null
+++ b/src/radeondb.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#include "config.h"
+#include <stdlib.h>
+#include <errno.h>
+#include <getopt.h>
+#include <jansson.h>
+#include "radeon_priv.h"
+
+void usage(void)
+{
+	printf("usage: radeondb [arguments] [file ..]\n\n");
+	printf("arguments:\n");
+	printf(" -p      replay command stream\n");
+	printf(" -d      dump command stream in raw hex\n");
+}
+
+static int play(const char *file);
+static int dump(const char *file);
+
+int main(int argc, char *argv[])
+{
+	static struct option options[] = {
+		{"play",    required_argument, 0, 'p'},
+		{"dump",    required_argument, 0, 'd'},
+		{0, 0, 0, 0}
+	};
+	int option_id;
+	int c;
+
+	while (1) {
+		c = getopt_long(argc, argv, "p:d:", options, &option_id);
+		if (c == -1)
+			break;
+		switch (c) {
+		case 'd':
+			return dump(optarg);
+		case 'p':
+			return play(optarg);
+		case '?':
+			/* getopt_long already printed an error message. */
+			break;
+		default:
+			abort ();
+		}
+	}
+}
+
+static int play(const char *file)
+{
+	struct radeon *radeon;
+	struct radeon_ctx *ctx = NULL;
+	struct radeon_surface dst;
+	struct radeon_surface src;
+	int r, fd;
+
+	fd = radeon_open_fd();
+	if (fd < 0) {
+		fprintf(stderr, "failed to open radeon drm device\n");
+		return -1;
+	}
+	radeon = radeon_new(fd, 0);
+	if (radeon == NULL) {
+		fprintf(stderr, "failed to initialize radeon\n");
+		return -1;
+	}
+	/* setup framebuffer surface */
+	memset_bo(radeon->mode.bo, 0x000000FF);
+	dst.bo = radeon->mode.bo;
+	dst.width = radeon->mode.pitch / 4;
+	dst.pitch = radeon->mode.pitch / 4;
+	dst.bpe = 4;
+	dst.height = radeon->mode.height;
+	/* load bof */
+	ctx = radeon_ctx_load_bof(file);
+	if (ctx == NULL) {
+		fprintf(stderr, "failed to read bof file %s\n", file);
+		r = -EINVAL;
+		goto out;
+	}
+	if (!radeon_is_family_compatible(radeon->family, ctx->radeon->family)) {
+		fprintf(stderr, "Incompatible hardware\n");
+		r = -EINVAL;
+		goto out;
+	}
+	radeon_decref(ctx->radeon);
+	ctx->radeon = radeon_incref(radeon);
+	r = radeon_ctx_draw(ctx);
+	if (r) {
+		fprintf(stderr, "failed to reconstruct draw sequences from %s\n", file);
+		goto out;
+	}
+	if (radeon_ctx_allocate_bo(ctx)) {
+		ctx->radeon = NULL;
+		r = -EINVAL;
+		goto out;
+	}
+	if (radeon_ctx_get_dst_surface(ctx, &src)) {
+		ctx->radeon = NULL;
+		r = -EINVAL;
+		goto out;
+	}
+	radeon_blit(&dst, &src, 0, 0, 0, 0, src.width, src.height);
+	getchar();
+	r = radeon_ctx_submit(ctx);
+	radeon_bo_wait(src.bo);
+	radeon_blit(&dst, &src, 0, 0, 0, 0, src.width, src.height);
+	getchar();
+	ctx->radeon = NULL;
+out:
+	radeon_ctx_destroy(ctx);
+	radeon_decref(radeon);
+	return r;
+}
+
+static int dump(const char *file)
+{
+	struct radeon_ctx *ctx;
+	unsigned i;
+
+	ctx = radeon_ctx_load_bof(file);
+	if (ctx == NULL) {
+		fprintf(stderr, "failed to read bof file %s\n", file);
+		return -1;
+	}
+	for (i = 0; i < ctx->cpm4; i++) {
+		printf("0x%08X\n", ctx->pm4[i]);
+	}
+	return 0;
+}