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/*
 * Copyright © 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 */
#ifndef R600_WINSYS_H
#define R600_WINSYS_H

#include "r600_atom.h"

/* opaque structure */
struct radeon_device *rdev;
struct radeon_atom *atom;



struct drm_r600_vs_buffer {
	u32			handle;
	u32			resource_id;
	u32			sq_vtx_constant_word0;
	u32			sq_vtx_constant_word2;
	u32			sq_vtx_constant_word3;
};

struct drm_r600_vs_element {
	u32			buffer_id;
	u32			semantic;
	u32			sq_vtx_word0;
	u32			sq_vtx_word1;
	u32			sq_vtx_word2;
};
struct drm_r600_vs_input {
	u32				nelements;
	u32				nbuffers;
	struct drm_r600_vs_element	elements[32];
	struct drm_r600_vs_buffer	buffers[32];
};
struct r600_vs_input {
	struct drm_r600_vs_input	drm;
	struct radeon_bo		*bo[32];
	u32				nbo;
};

struct r600_vs_buffer {
	struct drm_r600_vs_buffer	drm;
	struct radeon_bo		*bo;
};

struct drm_r600_batch {
	struct radeon_atom		*vs_constants;
	struct radeon_atom		*ps_constants;
	struct radeon_atom		*blend;
	struct radeon_atom		*cb;
	struct radeon_atom		*cb_cntl;
	struct radeon_atom		*pa;
	struct radeon_atom		*vport;
	struct radeon_atom		*db;
	struct radeon_atom		*db_cntl;
	struct radeon_atom		*vs_shader;
	struct radeon_atom		*ps_shader;
	struct r600_vs_input		inputs;
};
/* vs_shader - vertex shader */
struct drm_r600_vs_shader {
	u32			sq_pgm_resources_vs;
	u8			input_semantic[32];
	u8			input_gpr[32];
	u8			ninputs;
	u8			output_semantic[32];
	u8			fog_output_id;
	u8			noutputs;
	u32			ndwords;
	u32			opcodes[512];
};

/* atom */
extern int radeon_batches_queue(struct radeon_device *rdev, void *batch);
extern int radeon_batches_flush(struct radeon_device *rdev);

/* core functions */
extern int radeon_device_init(struct radeon_device **rdev, struct radeon_bo_manager *bom, int fd);
extern void radeon_device_release(struct radeon_device *rdev);

#endif