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/*
* Copyright © 2010 Jerome Glisse <glisse@freedesktop.org>
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef R600_ATOM_KERNEL_H
#define R600_ATOM_KERNEL_H
#define R600_ATOM_CB 1
#define R600_ATOM_PA 2
#define R600_ATOM_CB_CNTL 3
#define R600_ATOM_VPORT 4
#define R600_ATOM_BLEND 5
#define R600_ATOM_CONSTANTS 6
#define R600_ATOM_DB 7
#define R600_ATOM_DB_CNTL 8
#define R600_ATOM_VS_SHADER 9
#define R600_ATOM_PS_SHADER 10
#define R600_BATCH_NATOMS 11
struct drm_r600_cb {
u32 pitch;
u32 height;
u32 color_info;
u32 nsamples;
u32 placements[2];
u32 handle;
};
struct drm_r600_cb_cntl {
u32 cb_target_mask;
u32 cb_shader_mask;
u32 cb_clrcmp_control;
u32 cb_clrcmp_src;
u32 cb_clrcmp_dst;
u32 cb_clrcmp_msk;
u32 cb_color_control;
u32 cb_blend_alpha;
u32 cb_blend_blue;
u32 cb_blend_green;
u32 cb_blend_red;
u32 cb_clear_alpha;
u32 cb_clear_blue;
u32 cb_clear_green;
u32 cb_clear_red;
u32 cb_fog_blue;
u32 cb_fog_green;
u32 cb_fog_red;
};
/* pa - primitive assembly */
struct drm_r600_pa {
u32 pa_sc_mpass_ps_cntl;
u32 pa_sc_mode_cntl;
u32 pa_sc_line_cntl;
u32 pa_sc_aa_config;
u32 pa_sc_aa_sample_locs_mctx;
u32 pa_sc_aa_mask;
u32 pa_cl_clip_cntl;
u32 pa_cl_vte_cntl;
u32 pa_cl_vs_out_cntl;
u32 pa_cl_naninf_cntl;
u32 pa_cl_gb_vert_clip_adj;
u32 pa_cl_gb_vert_disc_adj;
u32 pa_cl_gb_horz_clip_adj;
u32 pa_cl_gb_horz_disc_adj;
u32 pa_su_sc_mode_cntl;
u32 pa_su_point_size;
u32 pa_su_point_minmax;
u32 pa_su_line_cntl;
u32 pa_sc_line_stipple;
u32 pa_su_poly_offset_db_fmt_cntl;
u32 pa_su_poly_offset_clamp;
u32 pa_su_poly_offset_front_scale;
u32 pa_su_poly_offset_front_offset;
u32 pa_su_poly_offset_back_scale;
u32 pa_su_poly_offset_back_offset;
};
/* vport - viewport */
struct drm_r600_vport {
u32 pa_sc_vport_zmin_0;
u32 pa_sc_vport_zmax_0;
u32 pa_cl_vport_xscale_0;
u32 pa_cl_vport_xoffset_0;
u32 pa_cl_vport_yscale_0;
u32 pa_cl_vport_yoffset_0;
u32 pa_cl_vport_zscale_0;
u32 pa_cl_vport_zoffset_0;
u32 pa_sc_screen_scissor_tl;
u32 pa_sc_screen_scissor_br;
u32 pa_sc_window_offset;
u32 pa_sc_window_scissor_tl;
u32 pa_sc_window_scissor_br;
u32 pa_sc_cliprect_rule;
u32 pa_sc_cliprect_0_tl;
u32 pa_sc_cliprect_0_br;
u32 pa_sc_cliprect_1_tl;
u32 pa_sc_cliprect_1_br;
u32 pa_sc_cliprect_2_tl;
u32 pa_sc_cliprect_2_br;
u32 pa_sc_cliprect_3_tl;
u32 pa_sc_cliprect_3_br;
u32 pa_sc_generic_scissor_tl;
u32 pa_sc_generic_scissor_br;
};
/* blend - blending */
struct drm_r600_blend {
u32 cb_blend0_control;
u32 cb_blend1_control;
u32 cb_blend2_control;
u32 cb_blend3_control;
u32 cb_blend4_control;
u32 cb_blend5_control;
u32 cb_blend6_control;
u32 cb_blend7_control;
u32 cb_blend_control;
};
/* constant */
struct drm_r600_constants {
u32 offset;
u32 nconstants;
u32 constants[512];
};
/* db - depth buffer */
struct drm_r600_db {
u32 db_depth_size;
u32 db_depth_view;
u32 db_depth_info;
u32 db_htile_surface;
u32 db_prefetch_limit;
u32 db_placements[2];
u32 hz_placements[2];
u32 db_handle;
u32 hz_handle;
};
/* db_cntl - depth buffer control */
struct drm_r600_db_cntl {
u32 db_stencil_clear;
u32 db_depth_clear;
u32 db_stencilrefmask;
u32 db_stencilrefmask_bf;
u32 db_depth_control;
u32 db_shader_control;
u32 db_render_control;
u32 db_render_override;
u32 db_sresults_compare_state1;
u32 db_preload_control;
u32 db_alpha_to_mask;
};
/* vs_shader - vertex shader */
struct drm_r600_vs_shader {
u32 sq_pgm_resources_vs;
u8 input_semantic[32];
u8 input_gpr[32];
u8 ninputs;
u8 output_semantic[32];
u8 fog_output_id;
u8 noutputs;
u32 ndwords;
u32 handle;
u32 offset;
};
/* ps_shader - pixel shader */
struct drm_r600_ps_shader {
u32 spi_ps_in_control_0;
u32 spi_ps_in_control_1;
u32 spi_ps_input_cntl[32];
u32 sq_pgm_resources_ps;
u32 sq_pgm_exports_ps;
u32 ndwords;
u32 handle;
u32 offset;
};
struct drm_r600_vs_buffer {
u32 handle;
u32 resource_id;
u32 sq_vtx_constant_word0;
u32 sq_vtx_constant_word2;
u32 sq_vtx_constant_word3;
};
struct drm_r600_vs_element {
u32 buffer_id;
u32 semantic;
u32 sq_vtx_word0;
u32 sq_vtx_word1;
u32 sq_vtx_word2;
};
struct drm_r600_vs_input {
u32 nelements;
u32 nbuffers;
struct drm_r600_vs_element elements[32];
struct drm_r600_vs_buffer buffers[32];
};
struct drm_r600_batch {
struct radeon_atom *vs_constants;
struct radeon_atom *ps_constants;
struct radeon_atom *blend;
struct radeon_atom *cb;
struct radeon_atom *cb_cntl;
struct radeon_atom *pa;
struct radeon_atom *vport;
struct radeon_atom *db;
struct radeon_atom *db_cntl;
struct radeon_atom *vs_shader;
struct radeon_atom *ps_shader;
struct drm_r600_vs_input inputs;
};
#endif
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