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/*
 * Copyright © 2010 Jerome Glisse <glisse@freedesktop.org>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
 */
#ifndef R600_ATOM_H
#define R600_ATOM_H

#include "r600_atom_kernel.h"


struct radeon_device;

/* public API */
struct drm_radeon_atom {
	u32			type;
	u32			id;
	void			*data;
};

struct r600_state_container {
	void			*data;
	u32			nbo;
	struct radeon_bo	*bo[32];
};

struct r600_vs_buffer {
	struct drm_r600_vs_buffer	drm;
	struct radeon_bo		*bo;
};

struct r600_vs_input {
	struct drm_r600_vs_input	drm;
	struct radeon_bo		*bo[32];
	u32				nbo;
};

struct drm_r600_batch {
	struct radeon_atom		*vs_constants;
	struct radeon_atom		*ps_constants;
	struct radeon_atom		*blend;
	struct radeon_atom		*cb;
	struct radeon_atom		*cb_cntl;
	struct radeon_atom		*pa;
	struct radeon_atom		*vport;
	struct radeon_atom		*db;
	struct radeon_atom		*db_cntl;
	struct radeon_atom		*vs_shader;
	struct radeon_atom		*ps_shader;
	struct r600_vs_input		inputs;
};

/* R600 */
#define R600_BATCH_NATOMS	11
struct r600_batch {
	struct list_head		list;
	struct list_head		pre_flushes;
	struct list_head		post_flushes;
	struct radeon_atom		*atoms[R600_BATCH_NATOMS];
	struct radeon_atom		*emit_atoms[R600_BATCH_NATOMS];
	u32				nemit_atoms;
	u32				nflushes;
	u32				npkts;
	struct radeon_bo		*shaders;
	u32				shaders_idx;
	struct r600_vs_input		inputs;
	u32				nfs_resources;
};

struct r600_batches {
	struct radeon_ib		*ib;
	u32				npkts;
	struct list_head		batches;
	u32				nfs_resources;
	struct r600_vs_buffer		fs_resource[160];
	u32				last_id[R600_BATCH_NATOMS];
};

/* R600 */
extern void r600_shader_disassemble(u32 *bytecode, u32 ndwords);
extern int r600_shader_build_fs(struct radeon_device *rdev,
				u32 *bytecode, u32 *ndwords,
				struct drm_r600_vs_input *inputs,
				struct drm_r600_vs_shader *vs);
extern int r600_atoms_init(struct radeon_device *rdev);
extern void r600_atoms_release(struct radeon_device *rdev);
extern int r600_atom_create(struct radeon_device *rdev,
				struct drm_radeon_atom *patom,
				struct radeon_atom **atomptr);
extern int r600_batches_queue(struct radeon_device *rdev,
				struct drm_r600_batch *batch);
extern int r600_batches_flush(struct radeon_device *rdev);
/* R700 */
extern void r700_batches_states_default(struct radeon_device *rdev, struct r600_batches *batches);

#endif