remove spi

6 files changed, 159 insertions, 279 deletions

diff --git a/r600_atom.c b/r600_atom.c
index 0b353f7..a91ee26 100644
--- a/r600_atom.c
+++ b/r600_atom.c
@@ -1238,118 +1238,11 @@ out_err:
 }
 
 /*
- * r600_spi
- */
-struct r600_spi {
-	struct radeon_atom	atom;
-	u32			pkts[64];
-	struct r600_atoms	*atoms;
-};
-
-static void r600_spi_release(struct kref *kref)
-{
-	struct radeon_atom *atom = container_of(kref, struct radeon_atom, kref);
-	struct r600_spi *spi = container_of(atom, struct r600_spi, atom);
-
-	mutex_lock(&spi->atoms->mutex);
-	list_del_init(&spi->atom.list);
-	mutex_unlock(&spi->atoms->mutex);
-	kfree(spi);
-}
-
-static int r600_spi_create(struct radeon_device *rdev,
-				struct r600_atoms *atoms,
-				struct drm_radeon_atom *patom,
-				struct radeon_atom **atom)
-{
-	struct drm_r600_spi pspi;
-	struct r600_spi *spi;
-	int r;
-
-	spi = kmalloc(sizeof(*spi), GFP_KERNEL);
-	if (spi == NULL)
-		return -ENOMEM;
-	/* make sure structure properly initialized */
-	memset(spi, 0, sizeof(*spi));
-	r = radeon_atom_init(&spi->atom, &atoms->idr, &r600_spi_release,
-			&radeon_atom_emit_default, &r600_atom_process_default,
-			spi->pkts);
-	if (r)
-		goto out_err;
-	/* KERNEL use get user data */
-	memcpy(&pspi, (void*)(unsigned long)patom->data, sizeof(struct drm_r600_spi));
-	/* SPI_VS_OUT_ID_0 */
-	spi->pkts[spi->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 10);
-	spi->pkts[spi->atom.npkts++] = 0x00000185;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_0;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_1;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_2;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_3;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_4;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_5;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_6;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_7;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_8;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_id_9;
-	/* SPI_PS_INPUT_CNTL_0 */
-	spi->pkts[spi->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 41);
-	spi->pkts[spi->atom.npkts++] = 0x00000191;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_0;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_1;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_2;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_3;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_4;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_5;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_6;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_7;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_8;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_9;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_10;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_11;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_12;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_13;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_14;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_15;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_16;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_17;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_18;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_19;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_20;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_21;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_22;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_23;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_24;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_25;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_26;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_27;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_28;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_29;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_30;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_input_cntl_31;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_vs_out_config;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_thread_grouping;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_in_control_0;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_ps_in_control_1;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_interp_control_0;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_input_z;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_fog_cntl;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_fog_func_scale;
-	spi->pkts[spi->atom.npkts++] = pspi.spi_fog_func_bias;
-	*atom = &spi->atom;
-fprintf(stderr, "%s %d pkts\n", __func__, (*atom)->npkts);
-	return 0;
-out_err:
-	radeon_atom_put(&spi->atom);
-	*atom = NULL;
-	return r;
-}
-
-/*
  * r600_vs_shader
  */
 struct r600_vs_shader {
 	struct radeon_atom		atom;
-	u32				pkts[64];
+	u32				pkts[128];
 	struct drm_r600_vs_shader	vs;
 	struct r600_atoms		*atoms;
 };
@@ -1398,7 +1291,8 @@ static int r600_vs_shader_create(struct radeon_device *rdev,
 {
 	struct drm_r600_vs_shader pvs_shader;
 	struct r600_vs_shader *vs_shader;
-	int r, i;
+	int r, i, j;
+	u32 tmp;
 
 	vs_shader = kmalloc(sizeof(*vs_shader), GFP_KERNEL);
 	if (vs_shader == NULL)
@@ -1449,11 +1343,34 @@ static int r600_vs_shader_create(struct radeon_device *rdev,
 	/* SQ_PGM_RESOURCES_VS */
 	vs_shader->pkts[vs_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
 	vs_shader->pkts[vs_shader->atom.npkts++] = 0x0000021A;
-	vs_shader->pkts[vs_shader->atom.npkts++] = pvs_shader.sq_pgm_resources_vs;
+	vs_shader->pkts[vs_shader->atom.npkts++] = vs_shader->vs.sq_pgm_resources_vs;
 	/* SQ_PGM_CF_OFFSET_VS */
 	vs_shader->pkts[vs_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
 	vs_shader->pkts[vs_shader->atom.npkts++] = 0x00000234;
 	vs_shader->pkts[vs_shader->atom.npkts++] = 0;
+	/* SPI_VS_OUT_CONFIG */
+	tmp = S_0286C4_VS_EXPORT_COUNT(vs_shader->vs.noutputs - 1);
+	if (vs_shader->vs.fog_output_id < 32) {
+		tmp |= S_0286C4_VS_OUT_FOG_VEC_ADDR(vs_shader->vs.fog_output_id);
+		tmp |= S_0286C4_VS_EXPORTS_FOG(1);
+	}
+	vs_shader->pkts[vs_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vs_shader->pkts[vs_shader->atom.npkts++] = 0x000001B1;
+	vs_shader->pkts[vs_shader->atom.npkts++] = tmp;
+	/* SPI_VS_OUT_ID_* */
+	tmp = (vs_shader->vs.noutputs + 3) >> 2;
+	vs_shader->pkts[vs_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, tmp);
+	vs_shader->pkts[vs_shader->atom.npkts++] = 0x00000185;
+	vs_shader->pkts[vs_shader->atom.npkts] = 0;
+	for (i = 0, j = 0; i < vs_shader->vs.noutputs; i++, j++) {
+		if (j & 4) {
+			vs_shader->atom.npkts++;
+			vs_shader->pkts[vs_shader->atom.npkts] = 0;
+		}
+		j &= 3;
+		vs_shader->pkts[vs_shader->atom.npkts] |= vs_shader->vs.output_semantic[i] << (j * 8);
+	}
+	vs_shader->atom.npkts++;
 	*atom = &vs_shader->atom;
 fprintf(stderr, "%s %d pkts\n", __func__, (*atom)->npkts);
 	return 0;
@@ -1467,17 +1384,10 @@ out_err:
  * r600_ps_shader
  */
 struct r600_ps_shader {
-	struct radeon_atom	atom;
-	u32			pkts[16];
-	u8			input_semantic[32];
-	u8			input_gpr[32];
-	u8			ninputs;
-	u8			output_semantic[32];
-	u8			output_gpr[32];
-	u8			noutputs;
-	u32			ndwords;
-	u32			*opcodes;
-	struct r600_atoms	*atoms;
+	struct radeon_atom		atom;
+	u32				pkts[64];
+	struct drm_r600_ps_shader	ps;
+	struct r600_atoms		*atoms;
 };
 
 static void r600_ps_shader_release(struct kref *kref)
@@ -1488,7 +1398,7 @@ static void r600_ps_shader_release(struct kref *kref)
 	mutex_lock(&ps_shader->atoms->mutex);
 	list_del_init(&ps_shader->atom.list);
 	mutex_unlock(&ps_shader->atoms->mutex);
-	kfree(ps_shader->opcodes);
+	kfree(ps_shader->ps.opcodes);
 	kfree(ps_shader);
 }
 
@@ -1502,10 +1412,10 @@ static int r600_ps_shader_emit(struct radeon_device *rdev,
 	u32 *opcodes = batch->shaders->ptr;
 	int r;
 
-	memcpy(&opcodes[batch->shaders_idx], ps_shader->opcodes, ps_shader->ndwords * 4);
+	memcpy(&opcodes[batch->shaders_idx], ps_shader->ps.opcodes, ps_shader->ps.ndwords * 4);
 	ps_shader->pkts[2] = batch->shaders_idx >> 6;
 	ps_shader->pkts[4] = radeon_ib_reloc(ib, batch->shaders, RADEON_GEM_DOMAIN_GTT);
-	batch->shaders_idx += (ps_shader->ndwords + 63) & 0xFFFFFFC0;
+	batch->shaders_idx += (ps_shader->ps.ndwords + 63) & 0xFFFFFFC0;
 	r = radeon_ib_copy(ib, ps_shader->pkts, atom->npkts);
 	return r;
 }
@@ -1517,6 +1427,7 @@ static int r600_ps_shader_create(struct radeon_device *rdev,
 {
 	struct drm_r600_ps_shader pps_shader;
 	struct r600_ps_shader *ps_shader;
+	u32 ninputs;
 	int r, i;
 
 	ps_shader = kmalloc(sizeof(*ps_shader), GFP_KERNEL);
@@ -1536,22 +1447,14 @@ static int r600_ps_shader_create(struct radeon_device *rdev,
 		r = -EINVAL;
 		goto out_err;
 	}
-	ps_shader->opcodes = kmalloc(4 * pps_shader.ndwords, GFP_KERNEL);
-	if (ps_shader->opcodes == NULL) {
+	memcpy(&ps_shader->ps, &pps_shader, sizeof(struct drm_r600_ps_shader));
+	ps_shader->ps.opcodes = kmalloc(4 * pps_shader.ndwords, GFP_KERNEL);
+	if (ps_shader->ps.opcodes == NULL) {
 		dev_err(rdev->dev, "shader too big\n");
 		r = -ENOMEM;
 		goto out_err;
 	}
-	memcpy(ps_shader->opcodes, pps_shader.opcodes, 4 * pps_shader.ndwords);
-	ps_shader->ndwords = pps_shader.ndwords;
-	ps_shader->ninputs = pps_shader.ninputs;
-	ps_shader->noutputs = pps_shader.noutputs;
-	for (i = 0; i < 32; i++) {
-		ps_shader->input_semantic[i] = pps_shader.input_semantic[i];
-		ps_shader->input_gpr[i] = pps_shader.input_gpr[i];
-		ps_shader->output_semantic[i] = pps_shader.output_semantic[i];
-		ps_shader->output_gpr[i] = pps_shader.output_gpr[i];
-	}
+	memcpy(ps_shader->ps.opcodes, pps_shader.opcodes, 4 * pps_shader.ndwords);
 	ps_shader->atom.npkts = 0;
 	/* SQ_PGM_START_PS */
 	ps_shader->pkts[ps_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
@@ -1568,6 +1471,17 @@ static int r600_ps_shader_create(struct radeon_device *rdev,
 	ps_shader->pkts[ps_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
 	ps_shader->pkts[ps_shader->atom.npkts++] = 0x00000233;
 	ps_shader->pkts[ps_shader->atom.npkts++] = 0;
+	/* setup pixel shader input */
+	ninputs = G_0286CC_NUM_INTERP(ps_shader->ps.spi_ps_in_control_0) + 1;
+	ps_shader->pkts[ps_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, ninputs);
+	ps_shader->pkts[ps_shader->atom.npkts++] = 0x00000191;
+	for (i = 0; i < ninputs; i++) {
+		ps_shader->pkts[ps_shader->atom.npkts++] = ps_shader->ps.spi_ps_input_cntl[i];
+	}
+	ps_shader->pkts[ps_shader->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	ps_shader->pkts[ps_shader->atom.npkts++] = 0x000001B3;
+	ps_shader->pkts[ps_shader->atom.npkts++] = ps_shader->ps.spi_ps_in_control_0;
+	ps_shader->pkts[ps_shader->atom.npkts++] = ps_shader->ps.spi_ps_in_control_1;
 	*atom = &ps_shader->atom;
 fprintf(stderr, "%s %d pkts\n", __func__, (*atom)->npkts);
 	return 0;
@@ -1661,13 +1575,6 @@ int r600_atom_create(struct radeon_device *rdev,
 		atom->type = patom->type;
 		list_add_tail(&atom->list, &atoms->vgt_atoms);
 		break;
-	case R600_ATOM_SPI:
-		r = r600_spi_create(rdev, atoms, patom, &atom);
-		if (r)
-			return r;
-		atom->type = patom->type;
-		list_add_tail(&atom->list, &atoms->spi_atoms);
-		break;
 	case R600_ATOM_VS_SHADER:
 		r = r600_vs_shader_create(rdev, atoms, patom, &atom);
 		if (r)
@@ -1841,8 +1748,7 @@ int r600_batches_queue(struct radeon_device *rdev,
 		batch->pa == NULL || batch->vport == NULL ||
 		batch->tp == NULL || batch->cb == NULL ||
 		batch->db_cntl == NULL || batch->vgt == NULL ||
-		batch->spi == NULL || batch->vs_shader == NULL ||
-		batch->ps_shader == NULL) {
+		batch->vs_shader == NULL || batch->ps_shader == NULL) {
 		mutex_unlock(&atoms->mutex);
 		kfree(rbatch);
 		dev_err(rdev->dev, "invalid batch\n");
@@ -1880,7 +1786,6 @@ int r600_batches_queue(struct radeon_device *rdev,
 	if (batch->db)
 		kref_get(&batch->db->kref);
 	rbatch->atoms[i++] = batch->vgt; kref_get(&batch->vgt->kref);
-	rbatch->atoms[i++] = batch->spi; kref_get(&batch->spi->kref);
 	rbatch->atoms[i++] = batch->cb; kref_get(&batch->cb->kref);
 	db_cntl = container_of(batch->db_cntl, struct r600_db_cntl, atom);
 	if (db_cntl->need_z || db_cntl->need_h || db_cntl->need_s) {
@@ -2020,7 +1925,6 @@ int r600_atoms_init(struct radeon_device *rdev, struct r600_atoms *atoms)
 	INIT_LIST_HEAD(&atoms->db_atoms);
 	INIT_LIST_HEAD(&atoms->db_cntl_atoms);
 	INIT_LIST_HEAD(&atoms->pa_atoms);
-	INIT_LIST_HEAD(&atoms->spi_atoms);
 	INIT_LIST_HEAD(&atoms->sq_atoms);
 	INIT_LIST_HEAD(&atoms->tp_atoms);
 	INIT_LIST_HEAD(&atoms->vgt_atoms);
diff --git a/r600_atom_api.h b/r600_atom_api.h
index 5ba1cee..86737e1 100644
--- a/r600_atom_api.h
+++ b/r600_atom_api.h
@@ -37,9 +37,8 @@ struct drm_radeon_atom {
 #define R600_ATOM_DB		8
 #define R600_ATOM_DB_CNTL	9
 #define R600_ATOM_VGT		10
-#define R600_ATOM_SPI		11
-#define R600_ATOM_VS_SHADER	12
-#define R600_ATOM_PS_SHADER	13
+#define R600_ATOM_VS_SHADER	11
+#define R600_ATOM_PS_SHADER	12
 
 struct drm_r600_cb {
 	u32			pitch;
@@ -209,87 +208,28 @@ struct drm_r600_vgt {
 	u32			vgt_vtx_vect_eject_reg;
 };
 
-/* spi */
-struct drm_r600_spi {
-	u32			spi_fog_cntl;
-	u32			spi_fog_func_bias;
-	u32			spi_fog_func_scale;
-	u32			spi_input_z;
-	u32			spi_interp_control_0;
-	u32			spi_ps_input_cntl_0;
-	u32			spi_ps_input_cntl_1;
-	u32			spi_ps_input_cntl_2;
-	u32			spi_ps_input_cntl_3;
-	u32			spi_ps_input_cntl_4;
-	u32			spi_ps_input_cntl_5;
-	u32			spi_ps_input_cntl_6;
-	u32			spi_ps_input_cntl_7;
-	u32			spi_ps_input_cntl_8;
-	u32			spi_ps_input_cntl_9;
-	u32			spi_ps_input_cntl_10;
-	u32			spi_ps_input_cntl_11;
-	u32			spi_ps_input_cntl_12;
-	u32			spi_ps_input_cntl_13;
-	u32			spi_ps_input_cntl_14;
-	u32			spi_ps_input_cntl_15;
-	u32			spi_ps_input_cntl_16;
-	u32			spi_ps_input_cntl_17;
-	u32			spi_ps_input_cntl_18;
-	u32			spi_ps_input_cntl_19;
-	u32			spi_ps_input_cntl_20;
-	u32			spi_ps_input_cntl_21;
-	u32			spi_ps_input_cntl_22;
-	u32			spi_ps_input_cntl_23;
-	u32			spi_ps_input_cntl_24;
-	u32			spi_ps_input_cntl_25;
-	u32			spi_ps_input_cntl_26;
-	u32			spi_ps_input_cntl_27;
-	u32			spi_ps_input_cntl_28;
-	u32			spi_ps_input_cntl_29;
-	u32			spi_ps_input_cntl_30;
-	u32			spi_ps_input_cntl_31;
-	u32			spi_vs_out_config;
-	u32			spi_thread_grouping;
-	u32			spi_ps_in_control_0;
-	u32			spi_ps_in_control_1;
-	u32			spi_vs_out_id_0;
-	u32			spi_vs_out_id_1;
-	u32			spi_vs_out_id_2;
-	u32			spi_vs_out_id_3;
-	u32			spi_vs_out_id_4;
-	u32			spi_vs_out_id_5;
-	u32			spi_vs_out_id_6;
-	u32			spi_vs_out_id_7;
-	u32			spi_vs_out_id_8;
-	u32			spi_vs_out_id_9;
-};
-
 /* vs_shader - vertex shader */
 struct drm_r600_vs_shader {
+	u32			sq_pgm_resources_vs;
 	u8			input_semantic[32];
-	u8			input_resource_id[32];
 	u8			input_gpr[32];
 	u8			ninputs;
 	u8			output_semantic[32];
-	u8			output_gpr[32];
+	u8			fog_output_id;
 	u8			noutputs;
-	u32			*opcodes;
 	u32			ndwords;
-	u32			sq_pgm_resources_vs;
+	u32			*opcodes;
 };
 
 /* ps_shader - pixel shader */
 struct drm_r600_ps_shader {
-	u8			input_semantic[32];
-	u8			input_gpr[32];
-	u8			ninputs;
-	u8			output_semantic[32];
-	u8			output_gpr[32];
-	u8			noutputs;
-	u32			*opcodes;
-	u32			ndwords;
+	u32			spi_ps_in_control_0;
+	u32			spi_ps_in_control_1;
+	u32			spi_ps_input_cntl[32];
 	u32			sq_pgm_resources_ps;
 	u32			sq_pgm_exports_ps;
+	u32			ndwords;
+	u32			*opcodes;
 };
 
 struct drm_r600_vs_buffer {
@@ -327,7 +267,6 @@ struct drm_r600_batch {
 	struct radeon_atom		*db;
 	struct radeon_atom		*db_cntl;
 	struct radeon_atom		*vgt;
-	struct radeon_atom		*spi;
 	struct radeon_atom		*vs_shader;
 	struct radeon_atom		*ps_shader;
 	struct drm_r600_vs_input	inputs;
diff --git a/r600d.h b/r600d.h
index 0f805a7..5404c58 100644
--- a/r600d.h
+++ b/r600d.h
@@ -599,5 +599,80 @@
 #define   S_008040_CMDFIFO_ENTRIES(x)                  (((x) & 0x1F) << 20)
 #define   G_008040_CMDFIFO_ENTRIES(x)                  (((x) >> 20) & 0x1F)
 #define   C_008040_CMDFIFO_ENTRIES                     0xFE0FFFFF
+#define R_0286CC_SPI_PS_IN_CONTROL_0                 0x0286CC
+#define   S_0286CC_NUM_INTERP(x)                       (((x) & 0x3F) << 0)
+#define   G_0286CC_NUM_INTERP(x)                       (((x) >> 0) & 0x3F)
+#define   C_0286CC_NUM_INTERP                          0xFFFFFFC0
+#define   S_0286CC_POSITION_ENA(x)                     (((x) & 0x1) << 8)
+#define   G_0286CC_POSITION_ENA(x)                     (((x) >> 8) & 0x1)
+#define   C_0286CC_POSITION_ENA                        0xFFFFFEFF
+#define   S_0286CC_POSITION_CENTROID(x)                (((x) & 0x1) << 9)
+#define   G_0286CC_POSITION_CENTROID(x)                (((x) >> 9) & 0x1)
+#define   C_0286CC_POSITION_CENTROID                   0xFFFFFDFF
+#define   S_0286CC_POSITION_ADDR(x)                    (((x) & 0x1F) << 10)
+#define   G_0286CC_POSITION_ADDR(x)                    (((x) >> 10) & 0x1F)
+#define   C_0286CC_POSITION_ADDR                       0xFFFF83FF
+#define   S_0286CC_PARAM_GEN(x)                        (((x) & 0xF) << 15)
+#define   G_0286CC_PARAM_GEN(x)                        (((x) >> 15) & 0xF)
+#define   C_0286CC_PARAM_GEN                           0xFFF87FFF
+#define   S_0286CC_PARAM_GEN_ADDR(x)                   (((x) & 0x7F) << 19)
+#define   G_0286CC_PARAM_GEN_ADDR(x)                   (((x) >> 19) & 0x7F)
+#define   C_0286CC_PARAM_GEN_ADDR                      0xFC07FFFF
+#define   S_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) & 0x3) << 26)
+#define   G_0286CC_BARYC_SAMPLE_CNTL(x)                (((x) >> 26) & 0x3)
+#define   C_0286CC_BARYC_SAMPLE_CNTL                   0xF3FFFFFF
+#define   S_0286CC_PERSP_GRADIENT_ENA(x)               (((x) & 0x1) << 28)
+#define   G_0286CC_PERSP_GRADIENT_ENA(x)               (((x) >> 28) & 0x1)
+#define   C_0286CC_PERSP_GRADIENT_ENA                  0xEFFFFFFF
+#define   S_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) & 0x1) << 29)
+#define   G_0286CC_LINEAR_GRADIENT_ENA(x)              (((x) >> 29) & 0x1)
+#define   C_0286CC_LINEAR_GRADIENT_ENA                 0xDFFFFFFF
+#define   S_0286CC_POSITION_SAMPLE(x)                  (((x) & 0x1) << 30)
+#define   G_0286CC_POSITION_SAMPLE(x)                  (((x) >> 30) & 0x1)
+#define   C_0286CC_POSITION_SAMPLE                     0xBFFFFFFF
+#define   S_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) & 0x1) << 31)
+#define   G_0286CC_BARYC_AT_SAMPLE_ENA(x)              (((x) >> 31) & 0x1)
+#define   C_0286CC_BARYC_AT_SAMPLE_ENA                 0x7FFFFFFF
+#define R_0286D0_SPI_PS_IN_CONTROL_1                 0x0286D0
+#define   S_0286D0_GEN_INDEX_PIX(x)                    (((x) & 0x1) << 0)
+#define   G_0286D0_GEN_INDEX_PIX(x)                    (((x) >> 0) & 0x1)
+#define   C_0286D0_GEN_INDEX_PIX                       0xFFFFFFFE
+#define   S_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) & 0x7F) << 1)
+#define   G_0286D0_GEN_INDEX_PIX_ADDR(x)               (((x) >> 1) & 0x7F)
+#define   C_0286D0_GEN_INDEX_PIX_ADDR                  0xFFFFFF01
+#define   S_0286D0_FRONT_FACE_ENA(x)                   (((x) & 0x1) << 8)
+#define   G_0286D0_FRONT_FACE_ENA(x)                   (((x) >> 8) & 0x1)
+#define   C_0286D0_FRONT_FACE_ENA                      0xFFFFFEFF
+#define   S_0286D0_FRONT_FACE_CHAN(x)                  (((x) & 0x3) << 9)
+#define   G_0286D0_FRONT_FACE_CHAN(x)                  (((x) >> 9) & 0x3)
+#define   C_0286D0_FRONT_FACE_CHAN                     0xFFFFF9FF
+#define   S_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) & 0x1) << 11)
+#define   G_0286D0_FRONT_FACE_ALL_BITS(x)              (((x) >> 11) & 0x1)
+#define   C_0286D0_FRONT_FACE_ALL_BITS                 0xFFFFF7FF
+#define   S_0286D0_FRONT_FACE_ADDR(x)                  (((x) & 0x1F) << 12)
+#define   G_0286D0_FRONT_FACE_ADDR(x)                  (((x) >> 12) & 0x1F)
+#define   C_0286D0_FRONT_FACE_ADDR                     0xFFFE0FFF
+#define   S_0286D0_FOG_ADDR(x)                         (((x) & 0x7F) << 17)
+#define   G_0286D0_FOG_ADDR(x)                         (((x) >> 17) & 0x7F)
+#define   C_0286D0_FOG_ADDR                            0xFF01FFFF
+#define   S_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) & 0x1) << 24)
+#define   G_0286D0_FIXED_PT_POSITION_ENA(x)            (((x) >> 24) & 0x1)
+#define   C_0286D0_FIXED_PT_POSITION_ENA               0xFEFFFFFF
+#define   S_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) & 0x1F) << 25)
+#define   G_0286D0_FIXED_PT_POSITION_ADDR(x)           (((x) >> 25) & 0x1F)
+#define   C_0286D0_FIXED_PT_POSITION_ADDR              0xC1FFFFFF
+#define R_0286C4_SPI_VS_OUT_CONFIG                   0x0286C4
+#define   S_0286C4_VS_PER_COMPONENT(x)                 (((x) & 0x1) << 0)
+#define   G_0286C4_VS_PER_COMPONENT(x)                 (((x) >> 0) & 0x1)
+#define   C_0286C4_VS_PER_COMPONENT                    0xFFFFFFFE
+#define   S_0286C4_VS_EXPORT_COUNT(x)                  (((x) & 0x1F) << 1)
+#define   G_0286C4_VS_EXPORT_COUNT(x)                  (((x) >> 1) & 0x1F)
+#define   C_0286C4_VS_EXPORT_COUNT                     0xFFFFFFC1
+#define   S_0286C4_VS_EXPORTS_FOG(x)                   (((x) & 0x1) << 8)
+#define   G_0286C4_VS_EXPORTS_FOG(x)                   (((x) >> 8) & 0x1)
+#define   C_0286C4_VS_EXPORTS_FOG                      0xFFFFFEFF
+#define   S_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) & 0x1F) << 9)
+#define   G_0286C4_VS_OUT_FOG_VEC_ADDR(x)              (((x) >> 9) & 0x1F)
+#define   C_0286C4_VS_OUT_FOG_VEC_ADDR                 0xFFFFC1FF
 
 #endif
diff --git a/r700_atom.c b/r700_atom.c
index 868656e..abfd2a6 100644
--- a/r700_atom.c
+++ b/r700_atom.c
@@ -88,4 +88,17 @@ void r700_batches_states_default(struct radeon_device *rdev, struct r600_batches
 	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
 	ib->ptr[ib->cpkts++] = 0x0000010E;
 	ib->ptr[ib->cpkts++] = 0x00000000;
+	/* SPI_THREAD_GROUPING */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	ib->ptr[ib->cpkts++] = 0x000001B2;
+	ib->ptr[ib->cpkts++] = 0x00000001;
+	/* SPI_INTERP_CONTROL_0
+	 * SPI_INPUT_Z
+	 * SPI_FOG_CNTL
+	 */
+	ib->ptr[ib->cpkts++] = PKT3(PKT3_SET_CONTEXT_REG, 3);
+	ib->ptr[ib->cpkts++] = 0x000001B5;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
+	ib->ptr[ib->cpkts++] = 0x00000000;
 }
diff --git a/radeon_atom.h b/radeon_atom.h
index d58e7db..37b045d 100644
--- a/radeon_atom.h
+++ b/radeon_atom.h
@@ -53,7 +53,7 @@ struct radeon_atom {
 };
 
 /* R600 */
-#define R600_BATCH_NATOMS	14
+#define R600_BATCH_NATOMS	13
 struct r600_batch {
 	struct list_head		list;
 	struct list_head		pre_flushes;
@@ -88,7 +88,6 @@ struct r600_atoms {
 	struct list_head	db_atoms;
 	struct list_head	db_cntl_atoms;
 	struct list_head	pa_atoms;
-	struct list_head	spi_atoms;
 	struct list_head	sq_atoms;
 	struct list_head	tp_atoms;
 	struct list_head	vgt_atoms;
@@ -123,6 +122,7 @@ static inline void radeon_atom_put(struct radeon_atom *atom)
 }
 
 /* R600 */
+extern void r600_shader_disassemble(u32 *bytecode, u32 ndwords);
 extern int r600_shader_build_fs(struct radeon_device *rdev,
 				u32 *bytecode, u32 *ndwords,
 				struct drm_r600_vs_input *inputs,
diff --git a/test.c b/test.c
index 4b3b744..b4aec38 100644
--- a/test.c
+++ b/test.c
@@ -22,6 +22,7 @@
 #include <string.h>
 #include <errno.h>
 #include "radeon.h"
+#include "radeon_atom.h"
 #include "r600_winsys.h"
 
 int r600_tri_flat(struct radeon *radeon);
@@ -101,7 +102,6 @@ int r600_tri_flat(struct radeon *radeon)
 	struct drm_r600_vport vport;
 	struct drm_r600_constants vs_constants;
 	struct drm_r600_vgt vgt;
-	struct drm_r600_spi spi;
 	struct drm_r600_vs_shader vs_shader;
 	struct drm_r600_ps_shader ps_shader;
 	struct drm_r600_batch batch;
@@ -109,6 +109,7 @@ int r600_tri_flat(struct radeon *radeon)
 	struct radeon_bo *vbo1;
 	int r;
 
+//	r600_shader_disassemble(vsshaders, 64);
 	vbo1 = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	if (vbo1 == NULL) {
 		fprintf(stderr, "Failed to create vbo1 bo\n");
@@ -310,70 +311,14 @@ int r600_tri_flat(struct radeon *radeon)
 	r = radeon_atom_create(rdev, &atom, &batch.vgt);
 	if (r)
 		return r;
-	/* spi */
-	spi.spi_fog_cntl = 0x00000000;
-	spi.spi_fog_func_bias = 0x00000000;
-	spi.spi_fog_func_scale = 0x00000000;
-	spi.spi_input_z = 0x00000000;
-	spi.spi_interp_control_0 = 0x00000000;
-	spi.spi_ps_input_cntl_0 = 0x00000800;
-	spi.spi_ps_input_cntl_1 = 0x00000000;
-	spi.spi_ps_input_cntl_2 = 0x00000000;
-	spi.spi_ps_input_cntl_3 = 0x00000000;
-	spi.spi_ps_input_cntl_4 = 0x00000000;
-	spi.spi_ps_input_cntl_5 = 0x00000000;
-	spi.spi_ps_input_cntl_6 = 0x00000000;
-	spi.spi_ps_input_cntl_7 = 0x00000000;
-	spi.spi_ps_input_cntl_8 = 0x00000000;
-	spi.spi_ps_input_cntl_9 = 0x00000000;
-	spi.spi_ps_input_cntl_10 = 0x00000000;
-	spi.spi_ps_input_cntl_11 = 0x00000000;
-	spi.spi_ps_input_cntl_12 = 0x00000000;
-	spi.spi_ps_input_cntl_13 = 0x00000000;
-	spi.spi_ps_input_cntl_14 = 0x00000000;
-	spi.spi_ps_input_cntl_15 = 0x00000000;
-	spi.spi_ps_input_cntl_16 = 0x00000000;
-	spi.spi_ps_input_cntl_17 = 0x00000000;
-	spi.spi_ps_input_cntl_18 = 0x00000000;
-	spi.spi_ps_input_cntl_19 = 0x00000000;
-	spi.spi_ps_input_cntl_20 = 0x00000000;
-	spi.spi_ps_input_cntl_21 = 0x00000000;
-	spi.spi_ps_input_cntl_22 = 0x00000000;
-	spi.spi_ps_input_cntl_23 = 0x00000000;
-	spi.spi_ps_input_cntl_24 = 0x00000000;
-	spi.spi_ps_input_cntl_25 = 0x00000000;
-	spi.spi_ps_input_cntl_26 = 0x00000000;
-	spi.spi_ps_input_cntl_27 = 0x00000000;
-	spi.spi_ps_input_cntl_28 = 0x00000000;
-	spi.spi_ps_input_cntl_29 = 0x00000000;
-	spi.spi_ps_input_cntl_30 = 0x00000000;
-	spi.spi_ps_input_cntl_31 = 0x00000000;
-	spi.spi_ps_in_control_0 = 0x10000001;
-	spi.spi_ps_in_control_1 = 0x00000000;
-	spi.spi_vs_out_config = 0x00000000;
-	spi.spi_thread_grouping = 0x00000001;
-	spi.spi_vs_out_id_0 = 0x03020100;
-	spi.spi_vs_out_id_1 = 0x07060504;
-	spi.spi_vs_out_id_2 = 0x0B0A0908;
-	spi.spi_vs_out_id_3 = 0x0F0E0D0C;
-	spi.spi_vs_out_id_4 = 0x00000000;
-	spi.spi_vs_out_id_5 = 0x00000000;
-	spi.spi_vs_out_id_6 = 0x00000000;
-	spi.spi_vs_out_id_7 = 0x00000000;
-	spi.spi_vs_out_id_8 = 0x00000000;
-	spi.spi_vs_out_id_9 = 0x00000000;
-	atom.type = R600_ATOM_SPI;
-	atom.id = 0;
-	atom.data = (uint64_t)(uintptr_t)&spi;
-	r = radeon_atom_create(rdev, &atom, &batch.spi);
-	if (r)
-		return r;
 	/* vs_shader */
 	vs_shader.ninputs = 2;
 	vs_shader.input_semantic[0] = 1;
 	vs_shader.input_gpr[0] = 1;
 	vs_shader.input_semantic[1] = 2;
 	vs_shader.input_gpr[1] = 2;
+	vs_shader.noutputs = 1;
+	vs_shader.output_semantic[0] = 4;
 	vs_shader.sq_pgm_resources_vs = 0x00000106;
 	vs_shader.ndwords = 64;
 	vs_shader.opcodes = vsshaders;
@@ -384,6 +329,10 @@ int r600_tri_flat(struct radeon *radeon)
 	if (r)
 		return r;
 	/* ps_shader */
+	ps_shader.spi_ps_input_cntl[0] = 0x00000804;
+	ps_shader.spi_ps_input_cntl[1] = 0x00000000;
+	ps_shader.spi_ps_in_control_0 = 0x10000001;
+	ps_shader.spi_ps_in_control_1 = 0x00000000;
 	ps_shader.sq_pgm_resources_ps = 0x00000003;
 	ps_shader.sq_pgm_exports_ps = 0x00000002;
 	ps_shader.ndwords = 20;