cleanup triflat

2 files changed, 37 insertions, 33 deletions

diff --git a/radeon.c b/radeon.c
index 7e39778..cf77af7 100644
--- a/radeon.c
+++ b/radeon.c
@@ -81,7 +81,7 @@ void memset_bo(struct radeon_bo *bo, u32 value)
 
 void memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size)
 {
-    u32 *ptr;
+    u32 *ptr, tmp;
     int r;
 
     r = radeon_bo_map(bo, 1);
@@ -93,6 +93,10 @@ void memcpy_bo(struct radeon_bo *bo, u32 *src, u32 size)
     ptr = (u32*)bo->ptr;
     for (r = 0; r < size; r++)
         ptr[r] = src[r];
+    for (r = 0; r < size; r++)
+        ptr[r] = src[r];
+    for (r = 0, tmp = 0; r < size; r++)
+        tmp += ptr[r];
     radeon_bo_unmap(bo);
 }
 
diff --git a/test.c b/test.c
index 2b9c937..c12ed03 100644
--- a/test.c
+++ b/test.c
@@ -24,11 +24,14 @@
 #include "r600_winsys.h"
 #include "radeon.h"
 
-int r600_tri_flat(struct radeon *radeon);
+int r600_winsys_init(struct r600_winsys **rdev, struct radeon_bo_manager *bom, int fd);
+void r600_winsys_release(struct r600_winsys *rdev);
+int r600_tri_flat(struct r600_winsys *rw, struct radeon_bo_manager *bom, int w, int h, struct radeon_bo *fbbo);
 
 int main(void)
 {
 	struct radeon radeon;
+	struct r600_winsys *rw;
 	int r;
 	int i;
 
@@ -38,7 +41,11 @@ int main(void)
 		return r;
 	}
 	memset_bo(radeon.mode.bo, 0x000000FF);
-	r600_tri_flat(&radeon);
+	r = r600_winsys_init(&rw, radeon.bom, radeon.fd);
+	if (r)
+		return r;
+	r600_tri_flat(rw, radeon.bom, radeon.mode.pitch / 4, radeon.mode.height, radeon.mode.bo);
+	r600_winsys_release(rw);
 	getchar();
 	radeon_fini(&radeon);
 	return 0;
@@ -88,12 +95,9 @@ static float rvbo1[32] = {
     0.500000, 0.500000, 0.500000, 0.000000,
     0.000000, 0.000000, 0.000000, 0.000000,
 };
-int r600_winsys_init(struct r600_winsys **rdev, struct radeon_bo_manager *bom, int fd);
-void r600_winsys_release(struct r600_winsys *rdev);
 
-int r600_tri_flat(struct radeon *radeon)
+int r600_tri_flat(struct r600_winsys *rw, struct radeon_bo_manager *bom, int w, int h, struct radeon_bo *fbbo)
 {
-	struct r600_winsys *rdev;
 	struct r600_request rq;
 	struct drm_r600_blend blend;
 	struct drm_r600_framebuffer fb;
@@ -112,21 +116,21 @@ int r600_tri_flat(struct radeon *radeon)
 	struct radeon_bo *ps;
 	int r;
 
-	vbo1 = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	vbo1 = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	if (vbo1 == NULL) {
 		fprintf(stderr, "Failed to create vbo1 bo\n");
 		return -ENOMEM;
 	}
 	memset_bo(vbo1, 0);
 	memcpy_bo(vbo1, (u32*)rvbo1, 32 * 4);
-	vs = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	vs = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	if (vs == NULL) {
 		fprintf(stderr, "Failed to create vs bo\n");
 		return -ENOMEM;
 	}
 	memset_bo(vs, 0);
 	memcpy_bo(vs, (u32*)vsshaders, 20 * 4);
-	ps = radeon_bo_open(radeon->bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
+	ps = radeon_bo_open(bom, 0, 4096, 0, RADEON_GEM_DOMAIN_GTT, 0);
 	if (ps == NULL) {
 		fprintf(stderr, "Failed to create ps bo\n");
 		return -ENOMEM;
@@ -134,22 +138,19 @@ int r600_tri_flat(struct radeon *radeon)
 	memset_bo(ps, 0);
 	memcpy_bo(ps, (u32*)psshaders, 64 * 4);
 
-	r = r600_winsys_init(&rdev, radeon->bom, radeon->fd);
-	if (r)
-		return r;
 	/* build cb */
-	fb.width = radeon->mode.pitch / 4;
-	fb.height = radeon->mode.height;
+	fb.width = w;
+	fb.height = h;
 	fb.ncb = 1;
-	fb.cb[0].width = radeon->mode.pitch / 4;
-	fb.cb[0].height = radeon->mode.height;
+	fb.cb[0].width = w;
+	fb.cb[0].height = h;
 	fb.cb[0].nsamples = 1;
 	fb.cb[0].cb_target_mask = 0xF;
 	fb.cb[0].cb_shader_mask = 0xF;
 	fb.cb[0].color_info = 0x08110068;
 	fb.cb[0].placements[0] = RADEON_GEM_DOMAIN_VRAM;
 	fb.cb[0].placements[1] = 0;
-	fb.cb[0].handle = radeon->mode.bo->handle;
+	fb.cb[0].handle = fbbo->handle;
 	fb.db_handle = 0;
 	fb.db_depth_size = 0;
 	fb.db_depth_view = 0;
@@ -157,10 +158,10 @@ int r600_tri_flat(struct radeon *radeon)
 	fb.db_htile_surface = 0;
 	fb.db_prefetch_limit = 0;
 	rq.type = R600_ATOM_FRAMEBUFFER;
-	rq.bo[0] = radeon->mode.bo;
+	rq.bo[0] = fbbo;
 	rq.nbo = 1;
 	rq.data = &fb;
-	batch.framebuffer = r600_atom_create(rdev, &rq);
+	batch.framebuffer = r600_atom_create(rw, &rq);
 	/* build pa */
 	rasterizer.pa_sc_mpass_ps_cntl = 0x00000000;
 	rasterizer.pa_sc_line_cntl = 0x00000400;
@@ -187,7 +188,7 @@ int r600_tri_flat(struct radeon *radeon)
 	rasterizer.pa_su_poly_offset_back_offset = 0x00000000;
 	rq.type = R600_ATOM_RASTERIZER;
 	rq.data = &rasterizer;
-	batch.rasterizer = r600_atom_create(rdev, &rq);
+	batch.rasterizer = r600_atom_create(rw, &rq);
 	/* cb rqrol */
 	cb_cntl.cb_clrcmp_control = 0x01000000;
 	cb_cntl.cb_clrcmp_src = 0x00000000;
@@ -207,7 +208,7 @@ int r600_tri_flat(struct radeon *radeon)
 	cb_cntl.cb_fog_red = 0x00000000;
 	rq.type = R600_ATOM_CB_CNTL;
 	rq.data = &cb_cntl;
-	batch.cb_cntl = r600_atom_create(rdev, &rq);
+	batch.cb_cntl = r600_atom_create(rw, &rq);
 	/* viewport */
 	vport.pa_cl_vte_cntl = 0x0000043f;
 //	vport.pa_sc_vport_zmin_0 = 0x00000000;
@@ -220,13 +221,13 @@ int r600_tri_flat(struct radeon *radeon)
 	vport.pa_cl_vport_zoffset_0 = 0x3f000000;
 	rq.type = R600_ATOM_VIEWPORT;
 	rq.data = &vport;
-	batch.viewport = r600_atom_create(rdev, &rq);
+	batch.viewport = r600_atom_create(rw, &rq);
 	/* scissor */
 	scissor.pa_sc_vport_scissor_0_tl = 0x80000000;
 	scissor.pa_sc_vport_scissor_0_br = 0x00fa00fa;
 	rq.type = R600_ATOM_SCISSOR;
 	rq.data = &scissor;
-	batch.scissor = r600_atom_create(rdev, &rq);
+	batch.scissor = r600_atom_create(rw, &rq);
 	/* blend */
 	blend.cb_blend0_control = 0x00010001;
 	blend.cb_blend1_control = 0x00000000;
@@ -239,7 +240,7 @@ int r600_tri_flat(struct radeon *radeon)
 	blend.cb_blend_control = 0x00010001;
 	rq.type = R600_ATOM_BLEND;
 	rq.data = &blend;
-	batch.blend = r600_atom_create(rdev, &rq);
+	batch.blend = r600_atom_create(rw, &rq);
 	/* ps constant */
 	batch.ps_constants = NULL;
 	/* vs constant */
@@ -249,7 +250,7 @@ int r600_tri_flat(struct radeon *radeon)
 	batch.vs_constants = NULL;
 	rq.type = R600_ATOM_CONSTANTS;
 	rq.data = &vs_constants;
-	batch.vs_constants = r600_atom_create(rdev, &rq);
+	batch.vs_constants = r600_atom_create(rw, &rq);
 	/* db rqrol */
 	dsa.db_stencil_clear = 0x00000000;
 	dsa.db_depth_clear = 0x3F800000;
@@ -264,7 +265,7 @@ int r600_tri_flat(struct radeon *radeon)
 	dsa.db_preload_control = 0x00000000;
 	rq.type = R600_ATOM_DSA;
 	rq.data = &dsa;
-	batch.dsa = r600_atom_create(rdev, &rq);
+	batch.dsa = r600_atom_create(rw, &rq);
 	/* vs_shader */
 	vs_shader.ninputs = 2;
 	vs_shader.input_semantic[0] = 1;
@@ -281,7 +282,7 @@ int r600_tri_flat(struct radeon *radeon)
 	rq.nbo = 1;
 	rq.type = R600_ATOM_VS_SHADER;
 	rq.data = &vs_shader;
-	batch.vs_shader = r600_atom_create(rdev, &rq);
+	batch.vs_shader = r600_atom_create(rw, &rq);
 	/* ps_shader */
 	ps_shader.spi_ps_input_cntl[0] = 0x00000804;
 	ps_shader.spi_ps_input_cntl[1] = 0x00000000;
@@ -296,7 +297,7 @@ int r600_tri_flat(struct radeon *radeon)
 	rq.nbo = 1;
 	rq.type = R600_ATOM_FS_SHADER;
 	rq.data = &ps_shader;
-	batch.fs_shader = r600_atom_create(rdev, &rq);
+	batch.fs_shader = r600_atom_create(rw, &rq);
 	/* inputs */
 	vs_resource.nresource = 2;
 	vs_resource.resource[0].handle = vbo1->handle;
@@ -322,7 +323,7 @@ int r600_tri_flat(struct radeon *radeon)
 	rq.nbo = 2;
 	rq.type = R600_ATOM_SHADER_RESOURCE;
 	rq.data = &vs_resource;
-	batch.vs_resource = r600_atom_create(rdev, &rq);
+	batch.vs_resource = r600_atom_create(rw, &rq);
 
 
 	batch.vgt_primitive_type = 5;
@@ -336,11 +337,10 @@ int r600_tri_flat(struct radeon *radeon)
 	rq.nbo = 1;
 
 	/* batch */
-	r =  r600_batches_queue(rdev, &rq);
+	r =  r600_batches_queue(rw, &rq);
 	if (r)
 		return r;
-	r = r600_batches_flush(rdev);
-	r600_winsys_release(rdev);
+	r = r600_batches_flush(rw);
 	radeon_bo_unref(vbo1);
 	return r;
 }