add vgt atom

5 files changed, 290 insertions, 148 deletions

diff --git a/r600_atom.c b/r600_atom.c
index bcb29fd..5ff936d 100644
--- a/r600_atom.c
+++ b/r600_atom.c
@@ -99,16 +99,16 @@ static int r600_cb_emit(struct radeon_device *rdev,
 	cb->pkts[16] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
 	cb->pkts[21] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
 	cb->pkts[26] = radeon_ib_reloc(ib, cb->bo, cb->placements[0] | cb->placements[1]);
-	cb->pkts[229] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[234] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[247] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[252] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[268] = radeon_ib_reloc(ib, cb->psshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[273] = radeon_ib_reloc(ib, cb->psshader1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[298] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[309] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[316] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
-	cb->pkts[327] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[93] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[98] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[111] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[116] = radeon_ib_reloc(ib, cb->vsshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[132] = radeon_ib_reloc(ib, cb->psshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[137] = radeon_ib_reloc(ib, cb->psshader1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[162] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[173] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[180] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
+	cb->pkts[191] = radeon_ib_reloc(ib, cb->vbo1, RADEON_GEM_DOMAIN_GTT);
 	r = radeon_ib_copy(ib, cb->pkts, atom->npkts);
 	return r;
 }
@@ -1091,6 +1091,135 @@ out_err:
 }
 
 /*
+ * r600_vgt
+ */
+struct r600_vgt {
+	struct radeon_atom	atom;
+	u32			pkts[64];
+	struct r600_atoms	*atoms;
+	int			need_gs;
+};
+
+static void r600_vgt_release(struct kref *kref)
+{
+	struct radeon_atom *atom = container_of(kref, struct radeon_atom, kref);
+	struct r600_vgt *vgt = container_of(atom, struct r600_vgt, atom);
+
+	mutex_lock(&vgt->atoms->mutex);
+	list_del_init(&vgt->atom.list);
+	mutex_unlock(&vgt->atoms->mutex);
+	kfree(vgt);
+}
+
+static int r600_vgt_create(struct radeon_device *rdev,
+				struct r600_atoms *atoms,
+				struct drm_radeon_atom *patom,
+				struct radeon_atom **atom)
+{
+	struct drm_r600_vgt pvgt;
+	struct r600_vgt *vgt;
+	int r;
+
+	vgt = kmalloc(sizeof(*vgt), GFP_KERNEL);
+	if (vgt == NULL)
+		return -ENOMEM;
+	/* make sure structure properly initialized */
+	memset(vgt, 0, sizeof(*vgt));
+	r = radeon_atom_init(&vgt->atom, &atoms->idr, &r600_vgt_release,
+			&radeon_atom_emit_default, &r600_atom_process_default,
+			vgt->pkts);
+	if (r)
+		goto out_err;
+	/* KERNEL use get user data */
+	memcpy(&pvgt, (void*)(unsigned long)patom->data, sizeof(struct drm_r600_vgt));
+	vgt->need_gs = 0;
+	if (G_028A40_MODE(pvgt.vgt_gs_mode))
+		vgt->need_gs = 1;
+	/* VGT_VTX_VECT_EJECT_REG */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x0000022C;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_vtx_vect_eject_reg;
+	/* VGT_GS_PER_ES */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000232;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_gs_per_es;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_es_per_gs;
+	/* VGT_GS_VERTEX_REUSE */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000235;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_gs_vertex_reuse;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_mc_lat_cntl;
+	/* VGT_GS_PER_VS */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x0000023A;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_gs_per_vs;
+	/* VGT_PRIMITIVE_TYPE */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000256;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_primitive_type;
+	/* VGT_NUM_INDICES */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONFIG_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x0000025C;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_num_indices;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_num_instances;
+	/* VGT_MAX_VTX_INDX */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000100;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_max_vtx_indx;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_min_vtx_indx;
+	/* VGT_MULTI_PRIM_IB_RESET_INDX */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000103;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_multi_prim_ib_reset_indx;
+	/* VGT_OUTPUT_PATH_CNTL */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000284;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_output_path_cntl;
+	/* VGT_GS_MODE */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000290;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_gs_mode;
+	/* VGT_ENHANCE */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000294;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_enhance;
+	/* VGT_GS_OUT_PRIM_TYPE */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x0000029B;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_gs_out_prim_type;
+	/* VGT_PRIMITIVEID_EN */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x000002A1;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_primitiveid_en;
+	/* VGT_MULTI_PRIM_IB_RESET_EN */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 1);
+	vgt->pkts[vgt->atom.npkts++] = 0x000002A5;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_multi_prim_ib_reset_en;
+	/* VGT_INSTANCE_STEP_RATE_0 */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x000002A8;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_instance_step_rate_0;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_instance_step_rate_1;
+	/* VGT_REUSE_OFF */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x000002AD;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_reuse_off;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_vtx_cnt_en;
+	/* VGT_VERTEX_REUSE_BLOCK_CNTL */
+	vgt->pkts[vgt->atom.npkts++] = PKT3(PKT3_SET_CONTEXT_REG, 2);
+	vgt->pkts[vgt->atom.npkts++] = 0x00000316;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_vertex_reuse_block_cntl;
+	vgt->pkts[vgt->atom.npkts++] = pvgt.vgt_out_dealloc_cntl;
+	*atom = &vgt->atom;
+fprintf(stderr, "%s %d pkts\n", __func__, (*atom)->npkts);
+	return 0;
+out_err:
+	radeon_atom_put(&vgt->atom);
+	*atom = NULL;
+	return r;
+}
+
+/*
  * r600 atom core functions
  */
 int r600_atom_create(struct radeon_device *rdev,
@@ -1167,6 +1296,13 @@ int r600_atom_create(struct radeon_device *rdev,
 		atom->type = patom->type;
 		list_add_tail(&atom->list, &atoms->db_cntl_atoms);
 		break;
+	case R600_ATOM_VGT:
+		r = r600_vgt_create(rdev, atoms, patom, &atom);
+		if (r)
+			return r;
+		atom->type = patom->type;
+		list_add_tail(&atom->list, &atoms->vgt_atoms);
+		break;
 	default:
 		dev_err(rdev->dev, "unknown R600 atom type 0x%08X\n", patom->type);
 		return -EINVAL;
@@ -1276,6 +1412,7 @@ int r600_batches_queue(struct radeon_device *rdev,
 	struct r600_batch *rbatch;
 	struct r600_batches *batches =  &atoms->batches;
 	struct r600_db_cntl *db_cntl;
+	struct r600_vgt *vgt;
 	int r, i;
 
 	r = r600_batch_alloc(&rbatch);
@@ -1297,7 +1434,7 @@ int r600_batches_queue(struct radeon_device *rdev,
 	if (batch->blend == NULL || batch->cb_cntl == NULL ||
 		batch->pa == NULL || batch->vport == NULL ||
 		batch->tp == NULL || batch->cb == NULL ||
-		batch->db_cntl == NULL) {
+		batch->db_cntl == NULL || batch->vgt == NULL) {
 		kfree(rbatch);
 		dev_err(rdev->dev, "invalid batch\n");
 		return -EINVAL;
@@ -1323,6 +1460,8 @@ int r600_batches_queue(struct radeon_device *rdev,
 	rbatch->atoms[i++] = batch->db;
 	if (batch->db)
 		kref_get(&batch->db->kref);
+	rbatch->atoms[i++] = batch->vgt;
+	kref_get(&batch->vgt->kref);
 	rbatch->atoms[i++] = batch->cb;
 	kref_get(&batch->cb->kref);
 	db_cntl = container_of(batch->db_cntl, struct r600_db_cntl, atom);
@@ -1345,6 +1484,12 @@ int r600_batches_queue(struct radeon_device *rdev,
 			goto out_err;
 		}
 	}
+	vgt = container_of(batch->vgt, struct r600_vgt, atom);
+	if (vgt->need_gs) {
+		dev_err(rdev->dev, "we don't support GS shader\n");
+		r = -EINVAL;
+		goto out_err;
+	}
 reprocess:
 	radeon_atom_flush_cleanup(&rbatch->pre_flushes);
 	radeon_atom_flush_cleanup(&rbatch->post_flushes);
@@ -1534,142 +1679,6 @@ void r600_tflat(struct radeon_atom *atom)
     WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
     WPKT(0x0000010E);
     WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 4));
-    WPKT(0x00000100);
-    WPKT(0x00FFFFFF);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 13));
-    WPKT(0x00000284);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000002A1);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000002A5);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000002A8);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000002A9);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 3));
-    WPKT(0x000002AC);
-    WPKT(0x00000000);
-    WPKT(0x00000001);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 1));
-    WPKT(0x000002C8);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 32));
-    WPKT(0x000000E0);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 10));
-    WPKT(0x00000185);
-    WPKT(0x03020100);
-    WPKT(0x07060504);
-    WPKT(0x0B0A0908);
-    WPKT(0x0F0E0D0C);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 9));
-    WPKT(0x000001B1);
-    WPKT(0x00000000);
-    WPKT(0x00000001);
-    WPKT(0x10000001);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 32));
-    WPKT(0x00000191);
-    WPKT(0x00000800);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(0x00000000);
-    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 2));
-    WPKT(0x00000094);
-    WPKT(0x80000000);
-    WPKT(0x00FA00FA);
     WPKT(PKT3(PKT3_SURFACE_SYNC, 3));
     WPKT(0x08000000);
     WPKT(0x00000001);
@@ -1765,6 +1774,67 @@ void r600_tflat(struct radeon_atom *atom)
     WPKT(0x00000000);
     WPKT(0xC0000000);
     WPKT_RELOC("vbo1");
+    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 10));
+    WPKT(0x00000185);
+    WPKT(0x03020100);
+    WPKT(0x07060504);
+    WPKT(0x0B0A0908);
+    WPKT(0x0F0E0D0C);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 9));
+    WPKT(0x000001B1);
+    WPKT(0x00000000);
+    WPKT(0x00000001);
+    WPKT(0x10000001);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 32));
+    WPKT(0x00000191);
+    WPKT(0x00000800);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(0x00000000);
+    WPKT(PKT3(PKT3_SET_CONTEXT_REG, 2));
+    WPKT(0x00000094);
+    WPKT(0x80000000);
+    WPKT(0x00FA00FA);
     WPKT(PKT3(PKT3_SET_CONFIG_REG, 1));
     WPKT(0x00000256);
     WPKT(0x00000005);
diff --git a/r600_atom_api.h b/r600_atom_api.h
index 33f83cd..2d8db21 100644
--- a/r600_atom_api.h
+++ b/r600_atom_api.h
@@ -36,6 +36,7 @@ struct drm_radeon_atom {
 #define R600_ATOM_CONSTANTS	7
 #define R600_ATOM_DB		8
 #define R600_ATOM_DB_CNTL	9
+#define R600_ATOM_VGT		10
 
 struct drm_r600_cb {
 	u32			pitch;
@@ -166,6 +167,34 @@ struct drm_r600_db_cntl {
 	u32			db_alpha_to_mask;
 };
 
+/* vgt */
+struct drm_r600_vgt {
+	u32			vgt_enhance;
+	u32			vgt_es_per_gs;
+	u32			vgt_gs_mode;
+	u32			vgt_gs_out_prim_type;
+	u32			vgt_gs_per_es;
+	u32			vgt_gs_per_vs;
+	u32			vgt_gs_vertex_reuse;
+	u32			vgt_instance_step_rate_0;
+	u32			vgt_instance_step_rate_1;
+	u32			vgt_max_vtx_indx;
+	u32			vgt_mc_lat_cntl;
+	u32			vgt_min_vtx_indx;
+	u32			vgt_multi_prim_ib_reset_en;
+	u32			vgt_multi_prim_ib_reset_indx;
+	u32			vgt_num_indices;
+	u32			vgt_num_instances;
+	u32			vgt_output_path_cntl;
+	u32			vgt_out_dealloc_cntl;
+	u32			vgt_primitiveid_en;
+	u32			vgt_primitive_type;
+	u32			vgt_reuse_off;
+	u32			vgt_vertex_reuse_block_cntl;
+	u32			vgt_vtx_cnt_en;
+	u32			vgt_vtx_vect_eject_reg;
+};
+
 struct drm_r600_batch {
 	u32			cb_blend_alpha;
 	u32			cb_blend_blue;
@@ -188,6 +217,7 @@ struct drm_r600_batch {
 	struct radeon_atom	*vport;
 	struct radeon_atom	*db;
 	struct radeon_atom	*db_cntl;
+	struct radeon_atom	*vgt;
 };
 
 
diff --git a/r600d.h b/r600d.h
index 012af1e..cd0c9bf 100644
--- a/r600d.h
+++ b/r600d.h
@@ -316,5 +316,15 @@
 #define   S_028D10_IGNORE_SC_ZRANGE(x)                 (((x) & 0x1) << 17)
 #define   G_028D10_IGNORE_SC_ZRANGE(x)                 (((x) >> 17) & 0x1)
 #define   C_028D10_IGNORE_SC_ZRANGE                    0xFFFDFFFF
+#define R_028A40_VGT_GS_MODE                         0x028A40
+#define   S_028A40_MODE(x)                             (((x) & 0x3) << 0)
+#define   G_028A40_MODE(x)                             (((x) >> 0) & 0x3)
+#define   C_028A40_MODE                                0xFFFFFFFC
+#define   S_028A40_ES_PASSTHRU(x)                      (((x) & 0x1) << 2)
+#define   G_028A40_ES_PASSTHRU(x)                      (((x) >> 2) & 0x1)
+#define   C_028A40_ES_PASSTHRU                         0xFFFFFFFB
+#define   S_028A40_CUT_MODE(x)                         (((x) & 0x3) << 3)
+#define   G_028A40_CUT_MODE(x)                         (((x) >> 3) & 0x3)
+#define   C_028A40_CUT_MODE                            0xFFFFFFE7
 
 #endif
diff --git a/radeon_atom.h b/radeon_atom.h
index 7872328..059fd85 100644
--- a/radeon_atom.h
+++ b/radeon_atom.h
@@ -53,7 +53,7 @@ struct radeon_atom {
 };
 
 /* R600 */
-#define R600_BATCH_NATOMS	10
+#define R600_BATCH_NATOMS	11
 struct r600_batch {
 	struct list_head	list;
 	struct list_head	pre_flushes;
diff --git a/test.c b/test.c
index 8ef57af..d8aa42e 100644
--- a/test.c
+++ b/test.c
@@ -62,6 +62,7 @@ int r600_tri_flat(struct radeon *radeon)
 	struct drm_r600_tp tp;
 	struct drm_r600_vport vport;
 	struct drm_r600_constants vs_constants;
+	struct drm_r600_vgt vgt;
 	struct drm_r600_batch batch;
 	struct drm_radeon_atom atom;
 	int r;
@@ -217,6 +218,37 @@ int r600_tri_flat(struct radeon *radeon)
 	r = radeon_atom_create(rdev, &atom, &batch.db_cntl);
 	if (r)
 		return r;
+	/* vgt */
+	vgt.vgt_enhance = 0x00000000;
+	vgt.vgt_es_per_gs = 0x00000000;
+	vgt.vgt_gs_mode = 0x00000000;
+	vgt.vgt_gs_out_prim_type = 0x00000000;
+	vgt.vgt_gs_per_es = 0x00000000;
+	vgt.vgt_gs_per_vs = 0x00000000;
+	vgt.vgt_gs_vertex_reuse = 0x00000000;
+	vgt.vgt_instance_step_rate_0 = 0x00000000;
+	vgt.vgt_instance_step_rate_1 = 0x00000000;
+	vgt.vgt_max_vtx_indx = 0x00FFFFFF;
+	vgt.vgt_mc_lat_cntl = 0x00000000;
+	vgt.vgt_min_vtx_indx = 0x00000000;
+	vgt.vgt_multi_prim_ib_reset_en = 0x00000000;
+	vgt.vgt_multi_prim_ib_reset_indx = 0x00000000;
+	vgt.vgt_num_indices = 0x00000000;
+	vgt.vgt_num_instances = 0x00000000;
+	vgt.vgt_output_path_cntl = 0x00000000;
+	vgt.vgt_out_dealloc_cntl = 0x00000000;
+	vgt.vgt_primitiveid_en = 0x00000000;
+	vgt.vgt_primitive_type = 0x00000005;
+	vgt.vgt_reuse_off = 0x00000001;
+	vgt.vgt_vertex_reuse_block_cntl = 0x00000000;
+	vgt.vgt_vtx_cnt_en = 0x00000000;
+	vgt.vgt_vtx_vect_eject_reg = 0x00000000;
+	atom.type = R600_ATOM_VGT;
+	atom.id = 0;
+	atom.data = (uint64_t)(uintptr_t)&vgt;
+	r = radeon_atom_create(rdev, &atom, &batch.vgt);
+	if (r)
+		return r;
 
 	/* batch */
 	batch.cb_clear_alpha = 0x00000000;