diff options
| author | Jerome Glisse <jglisse@redhat.com> | 2012-05-16 17:09:13 -0400 |
|---|---|---|
| committer | Jerome Glisse <jglisse@redhat.com> | 2012-05-16 17:09:13 -0400 |
| commit | 98a26545fd041bff49186fb8439a7282d7df3ca3 (patch) | |
| tree | 9a65b46b03bacb77ecda27a2cffbce23830781e9 | |
| parent | 80799c0fa8e82822b223f0cd82cc554752d75add (diff) | |
replay/tati: X command stream replayer, tati tools
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
| -rw-r--r-- | Makefile | 16 | ||||
| -rw-r--r-- | replayx.c | 377 | ||||
| -rw-r--r-- | replayx.h | 189 | ||||
| -rw-r--r-- | replayx_drv.c | 306 | ||||
| -rw-r--r-- | replayx_r6xxd.h | 2997 | ||||
| -rw-r--r-- | tati.c | 64 |
6 files changed, 3947 insertions, 2 deletions
@@ -1,5 +1,5 @@ CC = gcc -CFLAGS = -I . -O2 -Wall -I/usr/include/libdrm/ +CFLAGS = -I . -g -O0 -Wall -I/usr/include/libdrm/ JOUJOU_SOURCES = joujou.c radeon.c radeon_pciid.c radeon_bo.c JOUJOU_OBJECTS = $(JOUJOU_SOURCES:.c=.o) @@ -7,6 +7,12 @@ JOUJOU_OBJECTS = $(JOUJOU_SOURCES:.c=.o) RDUMP_SOURCES = rdump.c radeon_pci.c reg.c RDUMP_OBJECTS = $(RDUMP_SOURCES:.c=.o) +TATI_SOURCES = tati.c +TATI_OBJECTS = $(TATI_SOURCES:.c=.o) + +REPLAYX_SOURCES = replayx.c replayx_drv.c replayx_r6xx.c +REPLAYX_OBJECTS = $(REPLAYX_SOURCES:.c=.o) + CDUMP_SOURCES = cdump.c radeon_pci.c reg.c CDUMP_OBJECTS = $(CDUMP_SOURCES:.c=.o) @@ -22,7 +28,7 @@ JSONCS_OBJECTS = $(JSONCS_SOURCES:.c=.o) TESTGTTVRAM_SOURCES = testgttvram.c TESTGTTVRAM_OBJECTS = $(TESTGTTVRAM_SOURCES:.c=.o) -TARGETS = joujou rdump cdump wdump bofjson jsoncs testgttvram +TARGETS = joujou rdump cdump wdump testgttvram replayx tati ##### RULES ##### .SUFFIXES: @@ -41,6 +47,12 @@ joujou: $(JOUJOU_OBJECTS) rdump: $(RDUMP_OBJECTS) $(CC) -o $@ $(RDUMP_OBJECTS) -lpciaccess +tati: $(TATI_OBJECTS) + $(CC) -o $@ $(TATI_OBJECTS) -ldrm -ldrm_radeon + +replayx: $(REPLAYX_OBJECTS) + $(CC) -o $@ $(REPLAYX_OBJECTS) -lxcb -lxcb-util -lxcb-dri2 -lxcb-render -lxcb-xfixes -ldrm -ldrm_radeon + cdump: $(CDUMP_OBJECTS) $(CC) -o $@ $(CDUMP_OBJECTS) -lpciaccess diff --git a/replayx.c b/replayx.c new file mode 100644 index 0000000..0ba6003 --- /dev/null +++ b/replayx.c @@ -0,0 +1,377 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include "replayx.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +static int ctx_start_visual(struct ctx *ctx) +{ + xcb_screen_iterator_t s; + xcb_depth_iterator_t d; + xcb_visualtype_t *visuals; + unsigned i; + + s = xcb_setup_roots_iterator(xcb_get_setup(ctx->con)); + d = xcb_screen_allowed_depths_iterator(s.data); + ctx->root = s.data->root; + + while (d.rem > 0) { + if (d.data->depth == ctx->depth) { + visuals = xcb_depth_visuals(d.data); + for (i = 0; i < xcb_depth_visuals_length(d.data); i++) { + if (visuals[i].red_mask == 0xff0000 && + visuals[i].green_mask == 0xff00 && + visuals[i].blue_mask == 0xff) { + ctx->visual_id = visuals[i].visual_id; + return 0; + } + } + } + xcb_depth_next(&d); + } + return -EINVAL; +} + +static int ctx_dri2_bo(struct ctx *ctx) +{ + struct drm_gem_open open_arg; + int r; + + memset(&open_arg, 0, sizeof(open_arg)); + open_arg.name = ctx->front.name; + r = drmIoctl(ctx->fd, DRM_IOCTL_GEM_OPEN, &open_arg); + if (r) { + fprintf(stderr, "%s failed to open front bo (%d)\n", __func__, r); + return -EINVAL; + } + ctx->front.handle = open_arg.handle; + if (!ctx_bo_map(ctx, &ctx->front)) { + memset(ctx->front.data, 0, ctx->front.size); + } + return 0; +} + +static int ctx_dri2_buffer(struct ctx *ctx) +{ + xcb_dri2_get_buffers_reply_t *reply; + xcb_dri2_get_buffers_cookie_t cookie; + xcb_dri2_dri2_buffer_t *buffers; + uint32_t attachments[2]; + unsigned count = 2; + + attachments[0] = XCB_DRI2_ATTACHMENT_BUFFER_BACK_LEFT; + attachments[1] = XCB_DRI2_ATTACHMENT_BUFFER_FAKE_FRONT_LEFT; + cookie = xcb_dri2_get_buffers_unchecked(ctx->con, ctx->window, + count, count, + attachments); + reply = xcb_dri2_get_buffers_reply(ctx->con, cookie, NULL); + if (reply == NULL) { + fprintf(stderr, "%s failed to get dri2 buffer\n", __func__); + return -EINVAL; + } + buffers = xcb_dri2_get_buffers_buffers(reply); + if (buffers == NULL) { + free(reply); + return -EINVAL; + } + if (reply->width != ctx->win_w || reply->height != ctx->win_h) { + fprintf(stderr, "%s window & dri2 drawable missmatch (%d x %d) vs (%d x %d)\n", + __func__, ctx->win_w, ctx->win_h, reply->width, reply->height); + free(reply); + return -EINVAL; + } + if (reply->count != count) { + fprintf(stderr, "%s expect %d dri2 drawable got %d\n", + __func__, count, reply->count); + free(reply); + return -EINVAL; + } + if (buffers[0].attachment != XCB_DRI2_ATTACHMENT_BUFFER_BACK_LEFT) { + fprintf(stderr, "%s expect fake front left dri2 got %d\n", + __func__, buffers[1].attachment); + free(reply); + return -EINVAL; + } + if (buffers[0].name == ctx->front.name) { + /* still same bo */ + return 0; + } + /* close previous bo */ + ctx_bo_free(ctx, &ctx->front); + ctx->front.w = reply->width; + ctx->front.h = reply->height; + ctx->front.pitch = buffers[0].pitch / 4; + ctx->front.flags = buffers[0].flags; + ctx->front.name = buffers[0].name; + ctx->front.cpp = buffers[0].cpp; + ctx->front.size = ctx->front.pitch * ctx->front.h * ctx->front.cpp; + free(reply); + + return ctx_dri2_bo(ctx); +} + +static int ctx_dri2_swap(struct ctx *ctx) +{ + xcb_dri2_swap_buffers_cookie_t cookie; + xcb_dri2_swap_buffers_reply_t *reply; + + cookie = xcb_dri2_swap_buffers(ctx->con, ctx->window, + 0, 0, 0, 0, 0, 0); + reply = xcb_dri2_swap_buffers_reply(ctx->con, cookie, NULL); + if (reply == NULL) { + fprintf(stderr, "%s failed to swap buffer\n", __func__); + return -EINVAL; + } + free(reply); + return ctx_dri2_buffer(ctx); +} + +static int ctx_x11_authenticate(struct ctx *ctx, uint32_t id) +{ + xcb_dri2_authenticate_reply_t *authenticate; + xcb_dri2_authenticate_cookie_t authenticate_cookie; + xcb_screen_iterator_t s; + + s = xcb_setup_roots_iterator(xcb_get_setup(ctx->con)); + authenticate_cookie = xcb_dri2_authenticate_unchecked(ctx->con, s.data->root, id); + authenticate = xcb_dri2_authenticate_reply(ctx->con, authenticate_cookie, NULL); + + if (authenticate == NULL || !authenticate->authenticated) { + free(authenticate); + return -EINVAL; + } + free(authenticate); + return 0; +} + +static int ctx_dri2_authenticate(struct ctx *ctx) +{ + drm_magic_t magic; + + if (drmGetMagic(ctx->fd, &magic)) { + return -EINVAL; + } + return ctx_x11_authenticate(ctx, magic); +} + +static int ctx_start_dri2(struct ctx *ctx) +{ + xcb_prefetch_extension_data(ctx->con, &xcb_xfixes_id); + xcb_prefetch_extension_data(ctx->con, &xcb_dri2_id); + const xcb_query_extension_reply_t *extension; + xcb_dri2_connect_cookie_t connect_cookie; + xcb_dri2_connect_reply_t *con; + const char *device_name; + int r; + + extension = xcb_get_extension_data(ctx->con, &xcb_xfixes_id); + if (!(extension && extension->present)) { + fprintf(stderr, "%s xfixes extension needed for dri2\n", __func__); + return -EINVAL; + } + + extension = xcb_get_extension_data(ctx->con, &xcb_dri2_id); + if (!(extension && extension->present)) { + fprintf(stderr, "%s dri2 extension missing\n", __func__); + return -EINVAL; + } + + connect_cookie = xcb_dri2_connect_unchecked(ctx->con, ctx->root, + XCB_DRI2_DRIVER_TYPE_DRI); + con = xcb_dri2_connect_reply(ctx->con, connect_cookie, NULL); + if (con == NULL || con->driver_name_length + con->device_name_length == 0) { + fprintf(stderr, "%s dri2 failed to authenticate\n", __func__); + free(con); + return -EINVAL; + } + + device_name = xcb_dri2_connect_device_name(con); + ctx->device_name = strdup(device_name); + if (ctx->device_name == NULL) { + free(con); + return -ENOMEM; + } + free(con); + + ctx->fd = open(ctx->device_name, O_RDWR | O_CLOEXEC); + if (ctx->fd == -1) { + fprintf(stderr, "%s dri2 could not open %s\n", __func__, + ctx->device_name); + return -EINVAL; + } + + r = ctx_dri2_authenticate(ctx); + if (r) { + fprintf(stderr, "%s dri2 authentification failed\n", __func__); + return r; + } + + xcb_dri2_create_drawable(ctx->con, ctx->window); + + r = ctx_dri2_buffer(ctx); + if (r) { + return r; + } + return ctx_dri2_swap(ctx); +} + +static int ctx_start(struct ctx *ctx, unsigned win_w, unsigned win_h) +{ + uint32_t value_mask, value_list[1]; + int r; + + /* connect and get visual */ + ctx->depth = 24; + ctx->win_w = win_w; + ctx->win_h = win_h; + ctx->con = xcb_connect(0, &ctx->screen_num); + r = ctx_start_visual(ctx); + if (r) { + return r; + } + + /* create window */ + value_mask = XCB_CW_EVENT_MASK; + value_list[0] = XCB_EVENT_MASK_KEY_PRESS | XCB_EVENT_MASK_RESIZE_REDIRECT; + ctx->window = xcb_generate_id(ctx->con); + xcb_create_window(ctx->con, ctx->depth, ctx->window, ctx->root, + 64, 64, ctx->win_w, ctx->win_h, 0, + XCB_WINDOW_CLASS_INPUT_OUTPUT, + ctx->visual_id, value_mask, value_list); + xcb_map_window(ctx->con, ctx->window); + xcb_flush(ctx->con); + + return ctx_start_dri2(ctx); +} + +static void ctx_end(struct ctx *ctx) +{ + xcb_disconnect(ctx->con); + free(ctx->device_name); + if (ctx->fd) { + close(ctx->fd); + } +} + +static int ctx_do_blit(struct ctx *ctx) +{ + int r; + + r = ctx->drv.blit(ctx, ctx->target[ctx->ctarget++]); + if (r) { + /* finish execution */ + fprintf(stderr, "%s blit failed\n", __func__); + return r; + } + if (ctx->ctarget >= ctx->ntarget) { + ctx->ctarget = 0; + } + return r; +} + +static void ctx_main(struct ctx *ctx) +{ + xcb_generic_event_t *e; + xcb_resize_request_event_t *er; + int r; + + while ((e = xcb_wait_for_event (ctx->con))) { + switch (e->response_type) { + case XCB_RESIZE_REQUEST: + er = (void*)e; + if (ctx->win_w != er->width || ctx->win_h != er->height) { + /* resize */ + ctx->win_w = er->width; + ctx->win_h = er->height; + printf("resize %d %d\n", ctx->win_w, ctx->win_h); + } + r = ctx_dri2_buffer(ctx); + if (r) { + /* finish execution */ + return; + } + break; + case XCB_KEY_PRESS: + r = ctx_do_blit(ctx); + if (r) { + return; + } + r = ctx_dri2_swap(ctx); + if (r) { + /* finish execution */ + return; + } + break; + default: + break; + } + free(e); + } +} + +static void usage(const char *exename) +{ + printf("%s <filename>\n", exename); + exit(0); +} + +int main(int argc, char *argv[]) +{ + struct ctx ctx = {0}; + + if (argc != 2) { + usage(argv[0]); + } + + if (ctx_start(&ctx, 800, 600)) { + return -1; + } + if (ctx_rati_load(&ctx, argv[1])) { + return -1; + } + if (ctx_drv_init(&ctx)) { + return -1; + } + if (ctx_cs_rati(&ctx)) { + fprintf(stderr, "cs submission failed\n"); + return -1; + } + if (ctx_do_blit(&ctx)) { + return -1; + } + ctx_main(&ctx); + ctx_drv_fini(&ctx); + ctx_end(&ctx); + return 0; +} diff --git a/replayx.h b/replayx.h new file mode 100644 index 0000000..20347da --- /dev/null +++ b/replayx.h @@ -0,0 +1,189 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#ifndef REPLAYX_H +#define REPLAYX_H + +#include <xcb/xcb.h> +#include <xcb/xcb_aux.h> +#include <xcb/dri2.h> +#include <xcb/xfixes.h> +#include <stdint.h> +#include <libdrm/rati_file.h> + +struct ctx; + +struct ctx_bo { + unsigned w; + unsigned h; + unsigned flags; + unsigned pitch; + unsigned name; + unsigned cpp; + unsigned handle; + unsigned size; + unsigned alignment; + unsigned mapcount; + void *data; + unsigned format; + unsigned hw_format; + unsigned hw_tile; +}; + +#pragma pack(1) +struct radeon_cs_reloc { + uint32_t handle; + uint32_t read_domain; + uint32_t write_domain; + uint32_t flags; +}; +#pragma pack() + +struct r6xx_sq_conf { + unsigned ps_prio; + unsigned vs_prio; + unsigned gs_prio; + unsigned es_prio; + unsigned num_ps_gprs; + unsigned num_vs_gprs; + unsigned num_gs_gprs; + unsigned num_es_gprs; + unsigned num_temp_gprs; + unsigned num_ps_threads; + unsigned num_vs_threads; + unsigned num_gs_threads; + unsigned num_es_threads; + unsigned num_ps_stack_entries; + unsigned num_vs_stack_entries; + unsigned num_gs_stack_entries; + unsigned num_es_stack_entries; + unsigned sq_config; +}; + +struct r6xx_vbo { + unsigned offset; + unsigned ndw; + unsigned stride; + unsigned data_format; + unsigned num_format_all; + unsigned format_comp_all; + unsigned srf_mode_all; + unsigned endian_swap; + unsigned mem_request_size; + struct ctx_bo *bo; +}; + +struct r6xx_draw { + unsigned primitive_type; + unsigned num_instances; + unsigned index_type; + unsigned num_indices; + unsigned vgt_draw_initiator; +}; + +struct r6xx_blit { + uint32_t *cs; + unsigned cdw; + struct ctx *ctx; + struct ctx_bo shader_bo; + struct radeon_cs_reloc relocs[3]; + struct r6xx_sq_conf sq_conf; + unsigned vs_offset; + unsigned ps_offset; + unsigned vbo_offset; + unsigned ps_size; + unsigned vs_size; +}; + +union ctx_blit { + struct r6xx_blit r6xx; +}; + + +typedef int (*drv_compatible_t)(struct ctx *ctx); +typedef int (*drv_blit_init_t)(struct ctx *ctx); +typedef void (*drv_blit_fini_t)(struct ctx *ctx); +typedef int (*drv_blit_t)(struct ctx *ctx, struct ctx_bo *bo); + +struct ctx_drv { + drv_compatible_t compatible; + drv_blit_init_t blit_init; + drv_blit_fini_t blit_fini; + drv_blit_t blit; +}; + +struct ctx { + xcb_connection_t *con; + xcb_window_t root; + xcb_window_t window; + int screen_num; + xcb_visualid_t visual_id; + unsigned depth; + unsigned win_w; + unsigned win_h; + char *device_name; + int fd; + struct ctx_bo front; + struct rati_file rfile; + struct radeon_cs_reloc *relocs; + struct ctx_bo *bos; + unsigned nbos; + unsigned family; + struct ctx_drv drv; + uint32_t pciid; + union ctx_blit blit; + struct ctx_bo **target; + unsigned ntarget; + unsigned ctarget; +}; + +int ctx_bo(struct ctx *ctx, struct ctx_bo *bo, void *data); +int ctx_bo_map(struct ctx *ctx, struct ctx_bo *bo); +void ctx_bo_unmap(struct ctx_bo *bo); +void ctx_bo_free(struct ctx *ctx, struct ctx_bo *bo); +int ctx_bo_wait(struct ctx *ctx, struct ctx_bo *bo); + +int ctx_rati_load(struct ctx *ctx, const char *filename); +int ctx_cs_rati(struct ctx *ctx); + +int ctx_cs(struct ctx *ctx, void *cs, unsigned ndw, void *relocs, unsigned nrelocs); +int ctx_drv_init(struct ctx *ctx); +void ctx_drv_fini(struct ctx *ctx); + +extern const struct ctx_drv _r6xx_drv; + + +static inline unsigned fui(float f) +{ + union { + float f; + unsigned u; + } c; + + c.f = f; + return c.u; +} + +#endif diff --git a/replayx_drv.c b/replayx_drv.c new file mode 100644 index 0000000..73a5061 --- /dev/null +++ b/replayx_drv.c @@ -0,0 +1,306 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#define _FILE_OFFSET_BITS 64 +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <sys/mman.h> +#include "replayx.h" +#include "xf86drm.h" +#include "radeon_drm.h" + +int ctx_bo(struct ctx *ctx, struct ctx_bo *bo, void *data) +{ + struct drm_radeon_gem_create args; + int r; + + args.size = bo->size; + args.alignment = bo->alignment; + args.initial_domain = RADEON_GEM_DOMAIN_CPU; + args.flags = bo->flags; + args.handle = 0; + r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_CREATE, &args, sizeof(args)); + bo->handle = args.handle; + if (r) { + fprintf(stderr, "Failed to allocate :\n"); + fprintf(stderr, " size : %d bytes\n", bo->size); + fprintf(stderr, " alignment : %d bytes\n", bo->alignment); + } + if (data) { + r = ctx_bo_map(ctx, bo); + if (r) { + return r; + } + memcpy(bo->data, data, bo->size); + } + return r; +} + +int ctx_bo_map(struct ctx *ctx, struct ctx_bo *bo) +{ + struct drm_radeon_gem_mmap args; + void *ptr; + int r; + + if (bo->mapcount++ != 0) { + return 0; + } + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + args.offset = 0; + args.size = (uint64_t)bo->size; + r = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_MMAP, &args, sizeof(args)); + if (r) { + fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n", + bo, bo->handle, r); + return r; + } + ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, ctx->fd, args.addr_ptr); + if (ptr == MAP_FAILED) { + fprintf(stderr, "%s failed to map bo\n", __func__); + return -errno; + } + bo->data = ptr; + return 0; +} + +void ctx_bo_unmap(struct ctx_bo *bo) +{ + if (--bo->mapcount > 0) { + return; + } + munmap(bo->data, bo->size); + bo->data = NULL; +} + +void ctx_bo_free(struct ctx *ctx, struct ctx_bo *bo) +{ + struct drm_gem_close args; + + if (bo == NULL) { + return; + } + + if (bo->data) { + munmap(bo->data, bo->size); + } + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + drmIoctl(ctx->fd, DRM_IOCTL_GEM_CLOSE, &args); + memset(bo, 0, sizeof(struct ctx_bo)); +} + +int ctx_bo_wait(struct ctx *ctx, struct ctx_bo *bo) +{ + struct drm_radeon_gem_wait_idle args; + int ret; + + /* Zero out args to make valgrind happy */ + memset(&args, 0, sizeof(args)); + args.handle = bo->handle; + do { + ret = drmCommandWriteRead(ctx->fd, DRM_RADEON_GEM_WAIT_IDLE, + &args, sizeof(args)); + } while (ret == -EBUSY); + return ret; +} + +int ctx_rati_load(struct ctx *ctx, const char *filename) +{ + unsigned i; + int r; + + r = rati_file_read(&ctx->rfile, filename); + if (r) { + fprintf(stderr, "failed reading %s\n", filename); + return r; + } + + ctx->ntarget = 0; + ctx->nbos = ctx->rfile.header.v001.ndata_buffers; + ctx->bos = calloc(1, sizeof(*ctx->bos) * ctx->nbos); + ctx->relocs = calloc(1, sizeof(*ctx->relocs) * ctx->nbos); + ctx->target = calloc(1, sizeof(void*) * ctx->nbos); + if (ctx->bos == NULL || ctx->relocs == NULL || ctx->target == NULL) { + free(ctx->bos); + free(ctx->relocs); + return -ENOMEM; + } + + for (i = 0; i < ctx->nbos; ++i) { + ctx->bos[i].size = ctx->rfile.data_buffer[i].v001.size; + ctx->bos[i].alignment = ctx->rfile.data_buffer[i].v001.alignment; + r = ctx_bo(ctx, &ctx->bos[i], ctx->rfile.data_buffer_ptr[i]); + if (r) { + return r; + } + ctx->relocs[i].handle = ctx->bos[i].handle; + ctx->relocs[i].read_domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; + ctx->relocs[i].write_domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT; + ctx->relocs[i].flags = 0; + } + + return 0; +} + +int ctx_cs(struct ctx *ctx, void *cs, unsigned ndw, void *relocs, unsigned nrelocs) +{ + struct drm_radeon_cs drmib; + struct drm_radeon_cs_chunk chunks[2]; + uint64_t chunk_array[2]; + int r; + + drmib.num_chunks = 2; + drmib.chunks = (uint64_t)(uintptr_t)chunk_array; + chunks[0].chunk_id = RADEON_CHUNK_ID_IB; + chunks[0].length_dw = ndw; + chunks[0].chunk_data = (uintptr_t)cs; + chunks[1].chunk_id = RADEON_CHUNK_ID_RELOCS; + chunks[1].length_dw = nrelocs * 4; + chunks[1].chunk_data = (uintptr_t)relocs; + chunk_array[0] = (uintptr_t)&chunks[0]; + chunk_array[1] = (uintptr_t)&chunks[1]; +#if 1 + r = drmCommandWriteRead(ctx->fd, DRM_RADEON_CS, &drmib, sizeof(struct drm_radeon_cs)); +#endif + return r; +} + +int ctx_cs_rati(struct ctx *ctx) +{ + return ctx_cs(ctx, ctx->rfile.cmd_buffer_ptr[0], + ctx->rfile.cmd_buffer[0].v001.ndw, + ctx->relocs, ctx->nbos); +} + +static int ctx_get_drm_value(struct ctx *ctx, unsigned request, uint32_t *out) +{ + struct drm_radeon_info info; + + memset(&info, 0, sizeof(info)); + info.value = (unsigned long)out; + info.request = request; + return drmCommandWriteRead(ctx->fd, DRM_RADEON_INFO, &info, sizeof(info)); +} + +int ctx_drv_init(struct ctx *ctx) +{ + const struct radeon_chipinfo *chipinfo; + int r; + + r = ctx_get_drm_value(ctx, RADEON_INFO_DEVICE_ID, &ctx->pciid); + if (r) { + return r; + } + ctx->pciid |= 0x10020000; + chipinfo = radeon_chipinfo_from_pciid(ctx->pciid); + if (chipinfo == NULL) { + fprintf(stderr, "%s unknown gpu 0x%08x\n", __func__, ctx->pciid); + return -EINVAL; + } + ctx->family = chipinfo->family; + + switch (ctx->family) { + case CHIP_R600: + case CHIP_RV610: + case CHIP_RV630: + case CHIP_RV670: + case CHIP_RV620: + case CHIP_RV635: + case CHIP_RS780: + case CHIP_RS880: + ctx->drv = _r6xx_drv; + break; + case CHIP_RV770: + case CHIP_RV730: + case CHIP_RV710: + case CHIP_RV740: + case CHIP_R100: + case CHIP_RV100: + case CHIP_RS100: + case CHIP_RV200: + case CHIP_RS200: + case CHIP_R200: + case CHIP_RV250: + case CHIP_RS300: + case CHIP_RV280: + case CHIP_R300: + case CHIP_R350: + case CHIP_RV350: + case CHIP_RV380: + case CHIP_R420: + case CHIP_R423: + case CHIP_RV410: + case CHIP_RS400: + case CHIP_RS480: + case CHIP_RS600: + case CHIP_RS690: + case CHIP_RS740: + case CHIP_RV515: + case CHIP_R520: + case CHIP_RV530: + case CHIP_RV560: + case CHIP_RV570: + case CHIP_R580: + case CHIP_CEDAR: + case CHIP_REDWOOD: + case CHIP_JUNIPER: + case CHIP_CYPRESS: + case CHIP_HEMLOCK: + case CHIP_PALM: + case CHIP_SUMO: + case CHIP_SUMO2: + case CHIP_BARTS: + case CHIP_TURKS: + case CHIP_CAICOS: + case CHIP_CAYMAN: + case CHIP_ARUBA: + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + default: + fprintf(stderr, "%s unsupported gpu %s 0x%08x\n", __func__, chipinfo->name, ctx->pciid); + return -EINVAL; + } + + r = ctx->drv.compatible(ctx); + if (r) { + return r; + } + + return ctx->drv.blit_init(ctx); +} + +void ctx_drv_fini(struct ctx *ctx) +{ + ctx->drv.blit_fini(ctx); +} diff --git a/replayx_r6xxd.h b/replayx_r6xxd.h new file mode 100644 index 0000000..4284503 --- /dev/null +++ b/replayx_r6xxd.h @@ -0,0 +1,2997 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Alex Deucher <alexander.deucher@amd.com> + * Jerome Glisse + */ +#ifndef REPLAYX_R6XXD_H +#define REPLAYX_R6XXD_H + +/***************************************************************************** + * PM4 + */ + +#define PKT3(it, n) ((3 << 30) | ((((n) - 1) & 0x3fff) << 16) | (((it) & 0xff) << 8)) +#define PKT0(reg, n) ((0 << 30) | ((((n) - 1) & 0x3fff) << 16) | (((reg) >> 2) & 0xffff)) + +/* packet3 commands */ +#define IT_NOP 0x10 +#define IT_INDIRECT_BUFFER_END 0x17 +#define IT_SET_PREDICATION 0x20 +#define IT_REG_RMW 0x21 +#define IT_COND_EXEC 0x22 +#define IT_PRED_EXEC 0x23 +#define IT_START_3D_CMDBUF 0x24 +#define IT_DRAW_INDEX_2 0x27 +#define IT_CONTEXT_CONTROL 0x28 +#define IT_DRAW_INDEX_IMMD_BE 0x29 +#define IT_INDEX_TYPE 0x2a +#define IT_DRAW_INDEX 0x2b +#define IT_DRAW_INDEX_AUTO 0x2d +#define IT_DRAW_INDEX_IMMD 0x2e +#define IT_NUM_INSTANCES 0x2f +#define IT_STRMOUT_BUFFER_UPDATE 0x34 +#define IT_INDIRECT_BUFFER_MP 0x38 +#define IT_MEM_SEMAPHORE 0x39 +#define IT_MPEG_INDEX 0x3a +#define IT_WAIT_REG_MEM 0x3c +#define IT_MEM_WRITE 0x3d +#define IT_INDIRECT_BUFFER 0x32 +#define IT_CP_INTERRUPT 0x40 +#define IT_SURFACE_SYNC 0x43 +#define IT_ME_INITIALIZE 0x44 +#define IT_COND_WRITE 0x45 +#define IT_EVENT_WRITE 0x46 +#define IT_EVENT_WRITE_EOP 0x47 +#define IT_ONE_REG_WRITE 0x57 +#define IT_SET_CONFIG_REG 0x68 +#define IT_SET_CONTEXT_REG 0x69 +#define IT_SET_ALU_CONST 0x6a +#define IT_SET_BOOL_CONST 0x6b +#define IT_SET_LOOP_CONST 0x6c +#define IT_SET_RESOURCE 0x6d +#define IT_SET_SAMPLER 0x6e +#define IT_SET_CTL_CONST 0x6f +#define IT_SURFACE_BASE_UPDATE 0x73 + + +/***************************************************************************** + * REG RANGE + */ +#define SET_CONFIG_REG__OFFSET 0x00008000 +#define SET_CONFIG_REG__END 0x0000ac00 +#define SET_CONTEXT_REG__OFFSET 0x00028000 +#define SET_CONTEXT_REG__END 0x00029000 +#define SET_ALU_CONST__OFFSET 0x00030000 +#define SET_ALU_CONST__END 0x00032000 +#define SET_RESOURCE__OFFSET 0x00038000 +#define SET_RESOURCE__END 0x0003c000 +#define SET_SAMPLER__OFFSET 0x0003c000 +#define SET_SAMPLER__END 0x0003cff0 +#define SET_CTL_CONST__OFFSET 0x0003cff0 +#define SET_CTL_CONST__END 0x0003e200 +#define SET_LOOP_CONST__OFFSET 0x0003e200 +#define SET_LOOP_CONST__END 0x0003e380 +#define SET_BOOL_CONST__OFFSET 0x0003e380 +#define SET_BOOL_CONST__END 0x0003e38c + + +/***************************************************************************** + * GENERAL [0x00000000 0x00008000] + */ +#define CP_RB_BASE 0x0000c100 +#define CP_RB_CNTL 0x0000c104 +#define CP_RB_CNTL__RB_BUFSZ(x) (((x) & 0x0000003f) << 0) +#define CP_RB_WPTR 0x0000c114 +#define CP_RB_WPTR__RB_WPTR(x) (((x) & 0x000fffff) << 0) +#define CP_RB_RPTR_WR 0x0000c108 +#define CP_RB_RPTR_WR__RB_RPTR_WR(x) (((x) & 0x000fffff) << 0) +#define CP_INT_STATUS 0x0000c128 +#define CP_INT_STATUS__DISABLE_CNTX_SWITCH_INT_STAT(x) (((x) & 0x00000001) << 0) +#define CP_INT_STATUS__ENABLE_CNTX_SWITCH_INT_STAT(x) (((x) & 0x00000001) << 1) +#define CP_INT_STATUS__SEM_SIGNAL_INT_STAT(x) (((x) & 0x00000001) << 18) +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT(x) (((x) & 0x00000001) << 19) +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT(x) (((x) & 0x00000001) << 20) +#define CP_INT_STATUS__WAITMEM_SEM_INT_STAT(x) (((x) & 0x00000001) << 21) +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT(x) (((x) & 0x00000001) << 22) +#define CP_INT_STATUS__PRIV_REG_INT_STAT(x) (((x) & 0x00000001) << 23) +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT(x) (((x) & 0x00000001) << 24) +#define CP_INT_STATUS__SCRATCH_INT_STAT(x) (((x) & 0x00000001) << 25) +#define CP_INT_STATUS__TIME_STAMP_INT_STAT(x) (((x) & 0x00000001) << 26) +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT(x) (((x) & 0x00000001) << 27) +#define CP_INT_STATUS__DMA_INT_STAT(x) (((x) & 0x00000001) << 28) +#define CP_INT_STATUS__IB2_INT_STAT(x) (((x) & 0x00000001) << 29) +#define CP_INT_STATUS__IB1_INT_STAT(x) (((x) & 0x00000001) << 30) +#define CP_INT_STATUS__RB_INT_STAT(x) (((x) & 0x00000001) << 31) +#define SRBM_STATUS 0x00000e50 +#define SRBM_STATUS__RLC_RQ_PENDING(x) (((x) & 0x00000001) << 3) +#define SRBM_STATUS__RCU_RQ_PENDING(x) (((x) & 0x00000001) << 4) +#define SRBM_STATUS__GRBM_RQ_PENDING(x) (((x) & 0x00000001) << 5) +#define SRBM_STATUS__HI_RQ_PENDING(x) (((x) & 0x00000001) << 6) +#define SRBM_STATUS__IO_EXTERN_SIGNAL(x) (((x) & 0x00000001) << 7) +#define SRBM_STATUS__VMC_BUSY(x) (((x) & 0x00000001) << 8) +#define SRBM_STATUS__MCB_BUSY(x) (((x) & 0x00000001) << 9) +#define SRBM_STATUS__MCDZ_BUSY(x) (((x) & 0x00000001) << 10) +#define SRBM_STATUS__MCDY_BUSY(x) (((x) & 0x00000001) << 11) +#define SRBM_STATUS__MCDX_BUSY(x) (((x) & 0x00000001) << 12) +#define SRBM_STATUS__MCDW_BUSY(x) (((x) & 0x00000001) << 13) +#define SRBM_STATUS__SEM_BUSY(x) (((x) & 0x00000001) << 14) +#define SRBM_STATUS__SRBM_STATUS__RLC_BUSY(x) (((x) & 0x00000001) << 15) +#define SRBM_STATUS__PDMA_BUSY(x) (((x) & 0x00000001) << 16) +#define SRBM_STATUS__IH_BUSY(x) (((x) & 0x00000001) << 17) +#define SRBM_STATUS__CSC_BUSY(x) (((x) & 0x00000001) << 20) +#define SRBM_STATUS__CMC7_BUSY(x) (((x) & 0x00000001) << 21) +#define SRBM_STATUS__CMC6_BUSY(x) (((x) & 0x00000001) << 22) +#define SRBM_STATUS__CMC5_BUSY(x) (((x) & 0x00000001) << 23) +#define SRBM_STATUS__CMC4_BUSY(x) (((x) & 0x00000001) << 24) +#define SRBM_STATUS__CMC3_BUSY(x) (((x) & 0x00000001) << 25) +#define SRBM_STATUS__CMC2_BUSY(x) (((x) & 0x00000001) << 26) +#define SRBM_STATUS__CMC1_BUSY(x) (((x) & 0x00000001) << 27) +#define SRBM_STATUS__CMC0_BUSY(x) (((x) & 0x00000001) << 28) +#define SRBM_STATUS__BIF_BUSY(x) (((x) & 0x00000001) << 29) +#define SRBM_STATUS__IDCT_BUSY(x) (((x) & 0x00000001) << 30) +#define SRBM_READ_ERROR 0x00000e98 +#define SRBM_READ_ERROR__READ_ADDRESS(x) (((x) & 0x0000ffff) << 2) +#define SRBM_READ_ERROR__READ_REQUESTER_HI(x) (((x) & 0x00000001) << 24) +#define SRBM_READ_ERROR__READ_REQUESTER_GRBM(x) (((x) & 0x00000001) << 25) +#define SRBM_READ_ERROR__READ_REQUESTER_RCU(x) (((x) & 0x00000001) << 26) +#define SRBM_READ_ERROR__READ_REQUESTER_RLC(x) (((x) & 0x00000001) << 27) +#define SRBM_READ_ERROR__READ_ERROR(x) (((x) & 0x00000001) << 31) +#define SRBM_INT_STATUS 0x00000ea4 +#define SRBM_INT_STATUS__RDERR_INT_STAT(x) (((x) & 0x00000001) << 0) +#define SRBM_INT_STATUS__GFX_CNTX_SWITCH_INT_STAT(x) (((x) & 0x00000001) << 1) +#define SRBM_INT_ACK 0x00000ea8 +#define SRBM_INT_ACK__RDERR_INT_ACK(x) (((x) & 0x00000001) << 0) +#define SRBM_INT_ACK__GFX_CNTX_SWITCH_INT_ACK(x) (((x) & 0x00000001) << 1) +#define R6XX_MC_VM_FB_LOCATION 0x00002180 +#define VENDOR_DEVICE_ID 0x00004000 +#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x00005480 +#define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00006110 +#define D1GRPH_PITCH 0x00006120 +#define D1GRPH_Y_END 0x00006138 + + +/***************************************************************************** + * CONFIG REG [0x00008000 0x0000ac00] + */ +#define GRBM_STATUS 0x00008010 +#define GRBM_STATUS__CMDFIFO_AVAIL(x) (((x) & 0x0000001f) << 0) +#define GRBM_STATUS__SRBM_RQ_PENDING(x) (((x) & 0x00000001) << 5) +#define GRBM_STATUS__CP_RQ_PENDING(x) (((x) & 0x00000001) << 6) +#define GRBM_STATUS__CF_RQ_PENDING(x) (((x) & 0x00000001) << 7) +#define GRBM_STATUS__PF_RQ_PENDING(x) (((x) & 0x00000001) << 8) +#define GRBM_STATUS__GRBM_EE_BUSY(x) (((x) & 0x00000001) << 10) +#define GRBM_STATUS__GRBM_STATUS__VC_BUSY(x) (((x) & 0x00000001) << 11) +#define GRBM_STATUS__DB03_CLEAN(x) (((x) & 0x00000001) << 12) +#define GRBM_STATUS__CB03_CLEAN(x) (((x) & 0x00000001) << 13) +#define GRBM_STATUS__VGT_BUSY_NO_DMA(x) (((x) & 0x00000001) << 16) +#define GRBM_STATUS__GRBM_STATUS__VGT_BUSY(x) (((x) & 0x00000001) << 17) +#define GRBM_STATUS__TA03_BUSY(x) (((x) & 0x00000001) << 18) +#define GRBM_STATUS__GRBM_STATUS__TC_BUSY(x) (((x) & 0x00000001) << 19) +#define GRBM_STATUS__SX_BUSY(x) (((x) & 0x00000001) << 20) +#define GRBM_STATUS__SH_BUSY(x) (((x) & 0x00000001) << 21) +#define GRBM_STATUS__SPI03_BUSY(x) (((x) & 0x00000001) << 22) +#define GRBM_STATUS__SMX_BUSY(x) (((x) & 0x00000001) << 23) +#define GRBM_STATUS__SC_BUSY(x) (((x) & 0x00000001) << 24) +#define GRBM_STATUS__PA_BUSY(x) (((x) & 0x00000001) << 25) +#define GRBM_STATUS__DB03_BUSY(x) (((x) & 0x00000001) << 26) +#define GRBM_STATUS__CR_BUSY(x) (((x) & 0x00000001) << 27) +#define GRBM_STATUS__CP_COHERENCY_BUSY(x) (((x) & 0x00000001) << 28) +#define GRBM_STATUS__GRBM_STATUS__CP_BUSY(x) (((x) & 0x00000001) << 29) +#define GRBM_STATUS__CB03_BUSY(x) (((x) & 0x00000001) << 30) +#define GRBM_STATUS__GUI_ACTIVE(x) (((x) & 0x00000001) << 31) +#define GRBM_STATUS2 0x00008014 +#define GRBM_STATUS2__CR_CLEAN(x) (((x) & 0x00000001) << 0) +#define GRBM_STATUS2__SMX_CLEAN(x) (((x) & 0x00000001) << 1) +#define GRBM_STATUS2__SPI0_BUSY(x) (((x) & 0x00000001) << 8) +#define GRBM_STATUS2__SPI1_BUSY(x) (((x) & 0x00000001) << 9) +#define GRBM_STATUS2__SPI2_BUSY(x) (((x) & 0x00000001) << 10) +#define GRBM_STATUS2__SPI3_BUSY(x) (((x) & 0x00000001) << 11) +#define GRBM_STATUS2__TA0_BUSY(x) (((x) & 0x00000001) << 12) +#define GRBM_STATUS2__TA1_BUSY(x) (((x) & 0x00000001) << 13) +#define GRBM_STATUS2__TA2_BUSY(x) (((x) & 0x00000001) << 14) +#define GRBM_STATUS2__TA3_BUSY(x) (((x) & 0x00000001) << 15) +#define GRBM_STATUS2__DB0_BUSY(x) (((x) & 0x00000001) << 16) +#define GRBM_STATUS2__DB1_BUSY(x) (((x) & 0x00000001) << 17) +#define GRBM_STATUS2__DB2_BUSY(x) (((x) & 0x00000001) << 18) +#define GRBM_STATUS2__DB3_BUSY(x) (((x) & 0x00000001) << 19) +#define GRBM_STATUS2__CB0_BUSY(x) (((x) & 0x00000001) << 20) +#define GRBM_STATUS2__CB1_BUSY(x) (((x) & 0x00000001) << 21) +#define GRBM_STATUS2__CB2_BUSY(x) (((x) & 0x00000001) << 22) +#define GRBM_STATUS2__CB3_BUSY(x) (((x) & 0x00000001) << 23) +#define GRBM_SOFT_RESET 0x00008020 +#define GRBM_SOFT_RESET__SOFT_RESET_CP(x) (((x) & 0x00000001) << 0) +#define GRBM_SOFT_RESET__SOFT_RESET_CB(x) (((x) & 0x00000001) << 1) +#define GRBM_SOFT_RESET__SOFT_RESET_CR(x) (((x) & 0x00000001) << 2) +#define GRBM_SOFT_RESET__SOFT_RESET_DB(x) (((x) & 0x00000001) << 3) +#define GRBM_SOFT_RESET__SOFT_RESET_PA(x) (((x) & 0x00000001) << 5) +#define GRBM_SOFT_RESET__SOFT_RESET_SC(x) (((x) & 0x00000001) << 6) +#define GRBM_SOFT_RESET__SOFT_RESET_SMX(x) (((x) & 0x00000001) << 7) +#define GRBM_SOFT_RESET__SOFT_RESET_SPI(x) (((x) & 0x00000001) << 8) +#define GRBM_SOFT_RESET__SOFT_RESET_SH(x) (((x) & 0x00000001) << 9) +#define GRBM_SOFT_RESET__SOFT_RESET_SX(x) (((x) & 0x00000001) << 10) +#define GRBM_SOFT_RESET__SOFT_RESET_TC(x) (((x) & 0x00000001) << 11) +#define GRBM_SOFT_RESET__SOFT_RESET_TA(x) (((x) & 0x00000001) << 12) +#define GRBM_SOFT_RESET__SOFT_RESET_VC(x) (((x) & 0x00000001) << 13) +#define GRBM_SOFT_RESET__SOFT_RESET_VGT(x) (((x) & 0x00000001) << 14) +#define GRBM_SOFT_RESET__SOFT_RESET_GRBM_GCA(x) (((x) & 0x00000001) << 15) +#define WAIT_UNTIL 0x00008040 +#define WAIT_UNTIL__WAIT_CP_DMA_IDLE(x) (((x) & 0x00000001) << 8) +#define WAIT_UNTIL__WAIT_CMDFIFO(x) (((x) & 0x00000001) << 10) +#define WAIT_UNTIL__WAIT_2D_IDLE(x) (((x) & 0x00000001) << 14) +#define WAIT_UNTIL__WAIT_3D_IDLE(x) (((x) & 0x00000001) << 15) +#define WAIT_UNTIL__WAIT_2D_IDLECLEAN(x) (((x) & 0x00000001) << 16) +#define WAIT_UNTIL__WAIT_3D_IDLECLEAN(x) (((x) & 0x00000001) << 17) +#define WAIT_UNTIL__WAIT_EXTERN_SIG(x) (((x) & 0x00000001) << 19) +#define WAIT_UNTIL__CMDFIFO_ENTRIES(x) (((x) & 0x0000001f) << 20) +#define GRBM_READ_ERROR 0x00008058 +#define GRBM_READ_ERROR__READ_ADDRESS(x) (((x) & 0x0000ffff) << 2) +#define GRBM_READ_ERROR__READ_REQUESTER_SRBM(x) (((x) & 0x00000001) << 28) +#define GRBM_READ_ERROR__READ_REQUESTER_CP(x) (((x) & 0x00000001) << 29) +#define GRBM_READ_ERROR__READ_REQUESTER_WU_POLL(x) (((x) & 0x00000001) << 30) +#define GRBM_READ_ERROR__READ_ERROR(x) (((x) & 0x00000001) << 31) +#define SCRATCH_REG0 0x00008500 +#define SCRATCH_REG1 0x00008504 +#define SCRATCH_REG2 0x00008508 +#define SCRATCH_REG3 0x0000850c +#define SCRATCH_REG4 0x00008510 +#define SCRATCH_REG5 0x00008514 +#define SCRATCH_REG6 0x00008518 +#define SCRATCH_REG7 0x0000851c +#define SCRATCH_UMSK 0x00008540 +#define SCRATCH_ADDR 0x00008544 +#define CP_COHER_CNTL 0x000085f0 +#define CP_COHER_CNTL__DEST_BASE_0_ENA(x) (((x) & 0x00000001) << 0) +#define CP_COHER_CNTL__DEST_BASE_1_ENA(x) (((x) & 0x00000001) << 1) +#define CP_COHER_CNTL__SO0_DEST_BASE_ENA(x) (((x) & 0x00000001) << 2) +#define CP_COHER_CNTL__SO1_DEST_BASE_ENA(x) (((x) & 0x00000001) << 3) +#define CP_COHER_CNTL__SO2_DEST_BASE_ENA(x) (((x) & 0x00000001) << 4) +#define CP_COHER_CNTL__SO3_DEST_BASE_ENA(x) (((x) & 0x00000001) << 5) +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA(x) (((x) & 0x00000001) << 6) +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA(x) (((x) & 0x00000001) << 7) +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA(x) (((x) & 0x00000001) << 8) +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA(x) (((x) & 0x00000001) << 9) +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA(x) (((x) & 0x00000001) << 10) +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA(x) (((x) & 0x00000001) << 11) +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA(x) (((x) & 0x00000001) << 12) +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA(x) (((x) & 0x00000001) << 13) +#define CP_COHER_CNTL__DB_DEST_BASE_ENA(x) (((x) & 0x00000001) << 14) +#define CP_COHER_CNTL__CR_DEST_BASE_ENA(x) (((x) & 0x00000001) << 15) +#define CP_COHER_CNTL__TC_ACTION_ENA(x) (((x) & 0x00000001) << 23) +#define CP_COHER_CNTL__VC_ACTION_ENA(x) (((x) & 0x00000001) << 24) +#define CP_COHER_CNTL__CB_ACTION_ENA(x) (((x) & 0x00000001) << 25) +#define CP_COHER_CNTL__DB_ACTION_ENA(x) (((x) & 0x00000001) << 26) +#define CP_COHER_CNTL__SH_ACTION_ENA(x) (((x) & 0x00000001) << 27) +#define CP_COHER_CNTL__SMX_ACTION_ENA(x) (((x) & 0x00000001) << 28) +#define CP_COHER_CNTL__CR0_ACTION_ENA(x) (((x) & 0x00000001) << 29) +#define CP_COHER_CNTL__CR1_ACTION_ENA(x) (((x) & 0x00000001) << 30) +#define CP_COHER_CNTL__CR2_ACTION_ENA(x) (((x) & 0x00000001) << 31) +#define CP_STALLED_STAT1 0x00008674 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 0) +#define CP_STALLED_STAT1__RBIU_TO_IBS_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 1) +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 2) +#define CP_STALLED_STAT1__RBIU_TO_2DREGS_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 3) +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 4) +#define CP_STALLED_STAT1__RBIU_TO_MEMRD_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 5) +#define CP_STALLED_STAT1__RBIU_TO_EOPD_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 6) +#define CP_STALLED_STAT1__RBIU_TO_RECT_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 7) +#define CP_STALLED_STAT1__RBIU_TO_STRMO_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 8) +#define CP_STALLED_STAT1__RBIU_TO_PSTAT_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 9) +#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE(x) (((x) & 0x00000001) << 16) +#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE(x) (((x) & 0x00000001) << 17) +#define CP_STALLED_STAT1__MIU_NEEDS_AVAIL_WRREQ_PHASE(x) (((x) & 0x00000001) << 18) +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE(x) (((x) & 0x00000001) << 24) +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE(x) (((x) & 0x00000001) << 25) +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ(x) (((x) & 0x00000001) << 26) +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ(x) (((x) & 0x00000001) << 27) +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION(x) (((x) & 0x00000001) << 28) +#define CP_STALLED_STAT2 0x00008678 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 0) +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 1) +#define CP_STALLED_STAT2__PFP_TO_VGT_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 2) +#define CP_STALLED_STAT2__PFP_HALTED_BY_INSTR_VIOLATION(x) (((x) & 0x00000001) << 3) +#define CP_STALLED_STAT2__MULTIPASS_IB_PENDING_IN_PFP(x) (((x) & 0x00000001) << 4) +#define CP_STALLED_STAT2__ME_BRUSH_WC_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 8) +#define CP_STALLED_STAT2__ME_STALLED_ON_BRUSH_LOGIC(x) (((x) & 0x00000001) << 9) +#define CP_STALLED_STAT2__CR_CNTX_NOT_AVAIL_TO_ME(x) (((x) & 0x00000001) << 10) +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME(x) (((x) & 0x00000001) << 11) +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 12) +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV(x) (((x) & 0x00000001) << 13) +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP(x) (((x) & 0x00000001) << 14) +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH(x) (((x) & 0x00000001) << 15) +#define CP_STALLED_STAT2__RECT_FIFO_NEEDS_CR_RECT_DONE(x) (((x) & 0x00000001) << 16) +#define CP_STALLED_STAT2__RECT_FIFO_NEEDS_WR_CONFIRM(x) (((x) & 0x00000001) << 17) +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE(x) (((x) & 0x00000001) << 18) +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SMX_EOP_DONE(x) (((x) & 0x00000001) << 19) +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM(x) (((x) & 0x00000001) << 20) +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SIGNAL_SEM(x) (((x) & 0x00000001) << 21) +#define CP_STALLED_STAT2__SO_NUMPRIM_FIFO_NEEDS_SOADDR(x) (((x) & 0x00000001) << 22) +#define CP_STALLED_STAT2__SO_NUMPRIM_FIFO_NEEDS_NUMPRIM(x) (((x) & 0x00000001) << 23) +#define CP_STALLED_STAT2__PIPE_STATS_FIFO_NEEDS_SAMPLE(x) (((x) & 0x00000001) << 24) +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS(x) (((x) & 0x00000001) << 30) +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN(x) (((x) & 0x00000001) << 31) +#define CP_BUSY_STAT 0x0000867c +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY(x) (((x) & 0x00000001) << 0) +#define CP_BUSY_STAT__RING_FETCHING_DATA(x) (((x) & 0x00000001) << 1) +#define CP_BUSY_STAT__INDR1_FETCHING_DATA(x) (((x) & 0x00000001) << 2) +#define CP_BUSY_STAT__INDR2_FETCHING_DATA(x) (((x) & 0x00000001) << 3) +#define CP_BUSY_STAT__STATE_FETCHING_DATA(x) (((x) & 0x00000001) << 4) +#define CP_BUSY_STAT__PRED_FETCHING_DATA(x) (((x) & 0x00000001) << 5) +#define CP_BUSY_STAT__COHER_CNTR_NEQ_ZERO(x) (((x) & 0x00000001) << 6) +#define CP_BUSY_STAT__PFP_PARSING_PACKETS(x) (((x) & 0x00000001) << 7) +#define CP_BUSY_STAT__ME_PARSING_PACKETS(x) (((x) & 0x00000001) << 8) +#define CP_BUSY_STAT__RCIU_PFP_BUSY(x) (((x) & 0x00000001) << 9) +#define CP_BUSY_STAT__RCIU_ME_BUSY(x) (((x) & 0x00000001) << 10) +#define CP_BUSY_STAT__OUTSTANDING_READ_TAGS(x) (((x) & 0x00000001) << 11) +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY(x) (((x) & 0x00000001) << 12) +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING(x) (((x) & 0x00000001) << 13) +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS(x) (((x) & 0x00000001) << 14) +#define CP_BUSY_STAT__X_3D_BUSY(x) (((x) & 0x00000001) << 15) +#define CP_BUSY_STAT__X_2D_BUSY(x) (((x) & 0x00000001) << 16) +#define CP_STAT 0x00008680 +#define CP_STAT__CSF_RING_BUSY(x) (((x) & 0x00000001) << 0) +#define CP_STAT__CSF_WPTR_POLL_BUSY(x) (((x) & 0x00000001) << 1) +#define CP_STAT__CSF_INDIRECT1_BUSY(x) (((x) & 0x00000001) << 2) +#define CP_STAT__CSF_INDIRECT2_BUSY(x) (((x) & 0x00000001) << 3) +#define CP_STAT__CSF_STATE_BUSY(x) (((x) & 0x00000001) << 4) +#define CP_STAT__CSF_PREDICATE_BUSY(x) (((x) & 0x00000001) << 5) +#define CP_STAT__CSF_BUSY(x) (((x) & 0x00000001) << 6) +#define CP_STAT__MIU_RDREQ_BUSY(x) (((x) & 0x00000001) << 7) +#define CP_STAT__MIU_WRREQ_BUSY(x) (((x) & 0x00000001) << 8) +#define CP_STAT__ROQ_RING_BUSY(x) (((x) & 0x00000001) << 9) +#define CP_STAT__ROQ_INDIRECT1_BUSY(x) (((x) & 0x00000001) << 10) +#define CP_STAT__ROQ_INDIRECT2_BUSY(x) (((x) & 0x00000001) << 11) +#define CP_STAT__ROQ_STATE_BUSY(x) (((x) & 0x00000001) << 12) +#define CP_STAT__ROQ_PREDICATE_BUSY(x) (((x) & 0x00000001) << 13) +#define CP_STAT__ROQ_ALIGN_BUSY(x) (((x) & 0x00000001) << 14) +#define CP_STAT__PFP_BUSY(x) (((x) & 0x00000001) << 15) +#define CP_STAT__MEQ_BUSY(x) (((x) & 0x00000001) << 16) +#define CP_STAT__ME_BUSY(x) (((x) & 0x00000001) << 17) +#define CP_STAT__QUERY_BUSY(x) (((x) & 0x00000001) << 18) +#define CP_STAT__SEMAPHORE_BUSY(x) (((x) & 0x00000001) << 19) +#define CP_STAT__INTERRUPT_BUSY(x) (((x) & 0x00000001) << 20) +#define CP_STAT__SURFACE_SYNC_BUSY(x) (((x) & 0x00000001) << 21) +#define CP_STAT__DMA_BUSY(x) (((x) & 0x00000001) << 22) +#define CP_STAT__RCIU_BUSY(x) (((x) & 0x00000001) << 23) +#define CP_STAT__CP_STAT__CP_BUSY(x) (((x) & 0x00000001) << 31) +#define CP_ME_CNTL 0x000086d8 +#define CP_ME_CNTL__ME_STATMUX(x) (((x) & 0x000000ff) << 0) +#define CP_ME_CNTL__ME_HALT(x) (((x) & 0x00000001) << 28) +#define CP_ME_STATUS 0x000086dc +#define CP_RB_RPTR 0x00008700 +#define CP_RB_RPTR__RB_RPTR(x) (((x) & 0x000fffff) << 0) +#define CP_RB_WPTR_DELAY 0x00008704 +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER(x) (((x) & 0x0fffffff) << 0) +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT(x) (((x) & 0x0000000f) << 28) +#define CP_ROQ_RB_STAT 0x00008780 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY(x) (((x) & 0x000003ff) << 0) +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY(x) (((x) & 0x000003ff) << 16) +#define CP_ROQ_IB1_STAT 0x00008784 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1(x) (((x) & 0x000003ff) << 0) +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1(x) (((x) & 0x000003ff) << 16) +#define CP_ROQ_IB2_STAT 0x00008788 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2(x) (((x) & 0x000003ff) << 0) +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2(x) (((x) & 0x000003ff) << 16) +#define CP_MEQ_STAT 0x00008794 +#define CP_MEQ_STAT__MEQ_RPTR(x) (((x) & 0x000003ff) << 0) +#define CP_MEQ_STAT__MEQ_WPTR(x) (((x) & 0x000003ff) << 16) +#define CP_COHER_SIZE 0x000085f4 +#define CP_COHER_BASE 0x000085f8 +#define CP_COHER_STATUS 0x000085fc +#define CP_COHER_STATUS__MATCHING_GFX_CNTX(x) (((x) & 0x000000ff) << 0) +#define CP_COHER_STATUS__MATCHING_CR_CNTX(x) (((x) & 0x0000ffff) << 8) +#define CP_COHER_STATUS__STATUS(x) (((x) & 0x00000001) << 31) +#define VGT_VTX_VECT_EJECT_REG 0x000088b0 +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT(x) (((x) & 0x000003ff) << 0) +#define VGT_LAST_COPY_STATE 0x000088c0 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID(x) (((x) & 0x00000007) << 0) +#define VGT_LAST_COPY_STATE__DST_STATE_ID(x) (((x) & 0x00000007) << 16) +#define VGT_CACHE_INVALIDATION 0x000088c4 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION(x) (((x) & 0x00000003) << 0) +#define VC_ONLY 0 +#define TC_ONLY 1 +#define VC_AND_TC 2 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER(x) (((x) & 0x00000001) << 5) +#define VGT_GS_PER_ES 0x000088c8 +#define VGT_ES_PER_GS 0x000088cc +#define VGT_GS_VERTEX_REUSE 0x000088d4 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE(x) (((x) & 0x0000001f) << 0) +#define VGT_MC_LAT_CNTL 0x000088d8 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES(x) (((x) & 0x00000003) << 0) +#define X_0_992_MAX_LATENCY 0 +#define X_0_496_MAX_LATENCY 1 +#define X_0_248_MAX_LATENCY 2 +#define X_0_124_MAX_LATENCY 3 +#define VGT_GS_PER_VS 0x000088e8 +#define VGT_GS_PER_VS__GS_PER_VS(x) (((x) & 0x0000000f) << 0) +#define VGT_CNTL_STATUS 0x000088f0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY(x) (((x) & 0x00000001) << 0) +#define VGT_CNTL_STATUS__VGT_OUT_BUSY(x) (((x) & 0x00000001) << 1) +#define VGT_CNTL_STATUS__VGT_PT_BUSY(x) (((x) & 0x00000001) << 2) +#define VGT_CNTL_STATUS__VGT_TE_BUSY(x) (((x) & 0x00000001) << 3) +#define VGT_CNTL_STATUS__VGT_VR_BUSY(x) (((x) & 0x00000001) << 4) +#define VGT_CNTL_STATUS__VGT_GRP_BUSY(x) (((x) & 0x00000001) << 5) +#define VGT_CNTL_STATUS__VGT_DMA_REQ_BUSY(x) (((x) & 0x00000001) << 6) +#define VGT_CNTL_STATUS__VGT_DMA_BUSY(x) (((x) & 0x00000001) << 7) +#define VGT_CNTL_STATUS__VGT_GS_BUSY(x) (((x) & 0x00000001) << 8) +#define VGT_CNTL_STATUS__VGT_BUSY(x) (((x) & 0x00000001) << 9) +#define CC_GC_SHADER_PIPE_CONFIG 0x00008950 +#define CC_GC_SHADER_PIPE_CONFIG__INACTIVE_QD_PIPES(x) (((x) & 0x000000ff) << 8) +#define R6XX_MAX_QD_PIPES 8 +#define CC_GC_SHADER_PIPE_CONFIG__INACTIVE_SIMDS(x) (((x) & 0x000000ff) << 16) +#define R6XX_MAX_SIMDS 8 +#define GC_USER_SHADER_PIPE_CONFIG 0x00008954 +#define VGT_PRIMITIVE_TYPE 0x00008958 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE(x) (((x) & 0x0000003f) << 0) +#define DI_PT_NONE 0 +#define DI_PT_POINTLIST 1 +#define DI_PT_LINELIST 2 +#define DI_PT_LINESTRIP 3 +#define DI_PT_TRILIST 4 +#define DI_PT_TRIFAN 5 +#define DI_PT_TRISTRIP 6 +#define DI_PT_UNUSED_0 7 +#define DI_PT_UNUSED_1 8 +#define DI_PT_UNUSED_2 9 +#define DI_PT_LINELIST_ADJ 10 +#define DI_PT_LINESTRIP_ADJ 11 +#define DI_PT_TRILIST_ADJ 12 +#define DI_PT_TRISTRIP_ADJ 13 +#define DI_PT_UNUSED_3 14 +#define DI_PT_UNUSED_4 15 +#define DI_PT_TRI_WITH_WFLAGS 16 +#define DI_PT_RECTLIST 17 +#define DI_PT_LINELOOP 18 +#define DI_PT_QUADLIST 19 +#define DI_PT_QUADSTRIP 20 +#define DI_PT_POLYGON 21 +#define DI_PT_2D_COPY_RECT_LIST_V0 22 +#define DI_PT_2D_COPY_RECT_LIST_V1 23 +#define DI_PT_2D_COPY_RECT_LIST_V2 24 +#define DI_PT_2D_COPY_RECT_LIST_V3 25 +#define DI_PT_2D_FILL_RECT_LIST 26 +#define DI_PT_2D_LINE_STRIP 27 +#define DI_PT_2D_TRI_STRIP 28 +#define VGT_INDEX_TYPE 0x0000895c +#define VGT_INDEX_TYPE__INDEX_TYPE(x) (((x) & 0x00000003) << 0) +#define DI_INDEX_SIZE_16_BIT 0 +#define DI_INDEX_SIZE_32_BIT 1 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x00008960 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x00008964 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x00008968 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3 0x0000896c +#define VGT_NUM_INDICES 0x00008970 +#define VGT_NUM_INSTANCES 0x00008974 +#define PA_CL_CNTL_STATUS 0x00008a10 +#define PA_CL_CNTL_STATUS__CL_BUSY(x) (((x) & 0x00000001) << 31) +#define PA_CL_ENHANCE 0x00008a14 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA(x) (((x) & 0x00000001) << 0) +#define PA_CL_ENHANCE__NUM_CLIP_SEQ(x) (((x) & 0x00000003) << 1) +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL(x) (((x) & 0x00000001) << 3) +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE(x) (((x) & 0x00000001) << 4) +#define PA_SU_CNTL_STATUS 0x00008a50 +#define PA_SU_CNTL_STATUS__SU_BUSY(x) (((x) & 0x00000001) << 31) +#define PA_SC_LINE_STIPPLE_STATE 0x00008b10 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR(x) (((x) & 0x0000000f) << 0) +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT(x) (((x) & 0x000000ff) << 8) +#define PA_SC_MULTI_CHIP_CNTL 0x00008b20 +#define PA_SC_MULTI_CHIP_CNTL__LOG2_NUM_CHIPS(x) (((x) & 0x00000007) << 0) +#define PA_SC_MULTI_CHIP_CNTL__MULTI_CHIP_TILE_SIZE(x) (((x) & 0x00000003) << 3) +#define X_16_X_16_PIXEL_TILE_PER_CHIP 0 +#define X_32_X_32_PIXEL_TILE_PER_CHIP 1 +#define X_64_X_64_PIXEL_TILE_PER_CHIP 2 +#define X_128X128_PIXEL_TILE_PER_CHIP 3 +#define PA_SC_MULTI_CHIP_CNTL__CHIP_TILE_X_LOC(x) (((x) & 0x00000007) << 5) +#define PA_SC_MULTI_CHIP_CNTL__CHIP_TILE_Y_LOC(x) (((x) & 0x00000007) << 8) +#define PA_SC_MULTI_CHIP_CNTL__CHIP_SUPER_TILE_B(x) (((x) & 0x00000001) << 11) +#define PA_SC_AA_SAMPLE_LOCS_2S 0x00008b40 +#define PA_SC_AA_SAMPLE_LOCS_2S__S0_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_2S__S0_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_2S__S1_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_2S__S1_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_4S 0x00008b44 +#define PA_SC_AA_SAMPLE_LOCS_4S__S0_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_4S__S0_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_4S__S1_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_4S__S1_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_4S__S2_X(x) (((x) & 0x0000000f) << 16) +#define PA_SC_AA_SAMPLE_LOCS_4S__S2_Y(x) (((x) & 0x0000000f) << 20) +#define PA_SC_AA_SAMPLE_LOCS_4S__S3_X(x) (((x) & 0x0000000f) << 24) +#define PA_SC_AA_SAMPLE_LOCS_4S__S3_Y(x) (((x) & 0x0000000f) << 28) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x00008b48 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S0_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S0_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S1_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S1_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S2_X(x) (((x) & 0x0000000f) << 16) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S2_Y(x) (((x) & 0x0000000f) << 20) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S3_X(x) (((x) & 0x0000000f) << 24) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD0__S3_Y(x) (((x) & 0x0000000f) << 28) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x00008b4c +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S4_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S4_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S5_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S5_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S6_X(x) (((x) & 0x0000000f) << 16) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S6_Y(x) (((x) & 0x0000000f) << 20) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S7_X(x) (((x) & 0x0000000f) << 24) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1__S7_Y(x) (((x) & 0x0000000f) << 28) +#define PA_SC_CNTL_STATUS 0x00008be0 +#define PA_SC_CNTL_STATUS__MPASS_OVERFLOW(x) (((x) & 0x00000001) << 30) +#define PA_SC_ENHANCE 0x00008bf0 +#define PA_SC_ENHANCE__FORCE_EOV_MAX_CLK_CNT(x) (((x) & 0x00000fff) << 0) +#define PA_SC_ENHANCE__FORCE_EOV_MAX_TILE_CNT(x) (((x) & 0x00000fff) << 12) +#define SQ_CONFIG 0x00008c00 +#define SQ_CONFIG__VC_ENABLE(x) (((x) & 0x00000001) << 0) +#define SQ_CONFIG__EXPORT_SRC_C(x) (((x) & 0x00000001) << 1) +#define SQ_CONFIG__DX9_CONSTS(x) (((x) & 0x00000001) << 2) +#define SQ_CONFIG__ALU_INST_PREFER_VECTOR(x) (((x) & 0x00000001) << 3) +#define SQ_CONFIG__DX10_CLAMP(x) (((x) & 0x00000001) << 4) +#define SQ_CONFIG__ALU_PREFER_ONE_WATERFALL(x) (((x) & 0x00000001) << 5) +#define SQ_CONFIG__ALU_MAX_ONE_WATERFALL(x) (((x) & 0x00000001) << 6) +#define SQ_CONFIG__CLAUSE_SEQ_PRIO(x) (((x) & 0x00000003) << 8) +#define SQ_CL_PRIO_RND_ROBIN 0 +#define SQ_CL_PRIO_MACRO_SEQ 1 +#define SQ_CL_PRIO_NONE 2 +#define SQ_CONFIG__PS_PRIO(x) (((x) & 0x00000003) << 24) +#define SQ_CONFIG__VS_PRIO(x) (((x) & 0x00000003) << 26) +#define SQ_CONFIG__GS_PRIO(x) (((x) & 0x00000003) << 28) +#define SQ_CONFIG__ES_PRIO(x) (((x) & 0x00000003) << 30) +#define SQ_GPR_RESOURCE_MGMT_1 0x00008c04 +#define SQ_GPR_RESOURCE_MGMT_1__NUM_PS_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_GPR_RESOURCE_MGMT_1__NUM_VS_GPRS(x) (((x) & 0x000000ff) << 16) +#define SQ_GPR_RESOURCE_MGMT_1__NUM_CLAUSE_TEMP_GPRS(x) (((x) & 0x0000000f) << 28) +#define SQ_GPR_RESOURCE_MGMT_2 0x00008c08 +#define SQ_GPR_RESOURCE_MGMT_2__NUM_GS_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_GPR_RESOURCE_MGMT_2__NUM_ES_GPRS(x) (((x) & 0x000000ff) << 16) +#define SQ_THREAD_RESOURCE_MGMT 0x00008c0c +#define SQ_THREAD_RESOURCE_MGMT__NUM_PS_THREADS(x) (((x) & 0x000000ff) << 0) +#define SQ_THREAD_RESOURCE_MGMT__NUM_VS_THREADS(x) (((x) & 0x000000ff) << 8) +#define SQ_THREAD_RESOURCE_MGMT__NUM_GS_THREADS(x) (((x) & 0x000000ff) << 16) +#define SQ_THREAD_RESOURCE_MGMT__NUM_ES_THREADS(x) (((x) & 0x000000ff) << 24) +#define SQ_STACK_RESOURCE_MGMT_1 0x00008c10 +#define SQ_STACK_RESOURCE_MGMT_1__NUM_PS_STACK_ENTRIES(x) (((x) & 0x00000fff) << 0) +#define SQ_STACK_RESOURCE_MGMT_1__NUM_VS_STACK_ENTRIES(x) (((x) & 0x00000fff) << 16) +#define SQ_STACK_RESOURCE_MGMT_2 0x00008c14 +#define SQ_STACK_RESOURCE_MGMT_2__NUM_GS_STACK_ENTRIES(x) (((x) & 0x00000fff) << 0) +#define SQ_STACK_RESOURCE_MGMT_2__NUM_ES_STACK_ENTRIES(x) (((x) & 0x00000fff) << 16) +#define SQ_ESGS_RING_BASE 0x00008c40 +#define SQ_ESGS_RING_SIZE 0x00008c44 +#define SQ_GSVS_RING_BASE 0x00008c48 +#define SQ_GSVS_RING_SIZE 0x00008c4c +#define SQ_ESTMP_RING_BASE 0x00008c50 +#define SQ_ESTMP_RING_SIZE 0x00008c54 +#define SQ_GSTMP_RING_BASE 0x00008c58 +#define SQ_GSTMP_RING_SIZE 0x00008c5c +#define SQ_VSTMP_RING_BASE 0x00008c60 +#define SQ_VSTMP_RING_SIZE 0x00008c64 +#define SQ_PSTMP_RING_BASE 0x00008c68 +#define SQ_PSTMP_RING_SIZE 0x00008c6c +#define SQ_FBUF_RING_BASE 0x00008c70 +#define SQ_FBUF_RING_SIZE 0x00008c74 +#define SQ_REDUC_RING_BASE 0x00008c78 +#define SQ_REDUC_RING_SIZE 0x00008c7c +#define SX_EXPORT_BUFFER_SIZES 0x0000900c +#define SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE(x) (((x) & 0x000000ff) << 0) +#define SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE(x) (((x) & 0x000000ff) << 8) +#define SX_EXPORT_BUFFER_SIZES__SMX_BUFFER_SIZE(x) (((x) & 0x000000ff) << 16) +#define SX_MEMORY_EXPORT_BASE 0x00009010 +#define SX_MEMORY_EXPORT_SIZE 0x00009014 +#define SPI_CONFIG_CNTL 0x00009100 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY(x) (((x) & 0x0000001f) << 0) +#define X_PRIORITY_ORDER 0 +#define X_PRIORITY_ORDER_VS 1 +#define SPI_CONFIG_CNTL__DISABLE_INTERP_1(x) (((x) & 0x00000001) << 5) +#define SPI_CONFIG_CNTL__DEBUG_THREAD_TYPE_SEL(x) (((x) & 0x00000003) << 6) +#define SPI_CONFIG_CNTL__DEBUG_GROUP_SEL(x) (((x) & 0x0000001f) << 8) +#define SPI_CONFIG_CNTL__DEBUG_GRBM_OVERRIDE(x) (((x) & 0x00000001) << 13) +#define SPI_CONFIG_CNTL_1 0x0000913c +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY(x) (((x) & 0x0000000f) << 0) +#define X_DELAY_10_CLKS 0 +#define X_DELAY_11_CLKS 1 +#define X_DELAY_12_CLKS 2 +#define X_DELAY_13_CLKS 3 +#define X_DELAY_14_CLKS 4 +#define X_DELAY_15_CLKS 5 +#define X_DELAY_16_CLKS 6 +#define X_DELAY_17_CLKS 7 +#define X_DELAY_2_CLKS 8 +#define X_DELAY_3_CLKS 9 +#define X_DELAY_4_CLKS 10 +#define X_DELAY_5_CLKS 11 +#define X_DELAY_6_CLKS 12 +#define X_DELAY_7_CLKS 13 +#define X_DELAY_8_CLKS 14 +#define X_DELAY_9_CLKS 15 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW(x) (((x) & 0x00000001) << 4) +#define TD_FILTER4 0x00009400 +#define TD_FILTER4__WEIGHT_1(x) (((x) & 0x000007ff) << 0) +#define TD_FILTER4__WEIGHT_0(x) (((x) & 0x000007ff) << 11) +#define TD_FILTER4__WEIGHT_PAIR(x) (((x) & 0x00000001) << 22) +#define TD_FILTER4__PHASE(x) (((x) & 0x0000000f) << 23) +#define TD_FILTER4__DIRECTION(x) (((x) & 0x00000001) << 27) +#define TD_FILTER4_1 0x00009404 +#define TD_FILTER4_1__WEIGHT_1(x) (((x) & 0x000007ff) << 0) +#define TD_FILTER4_1__WEIGHT_0(x) (((x) & 0x000007ff) << 11) +#define TD_CNTL 0x00009490 +#define TD_CNTL__SYNC_PHASE_SH(x) (((x) & 0x00000003) << 0) +#define TD_CNTL__SYNC_PHASE_VC_SMX(x) (((x) & 0x00000003) << 4) +#define TD0_CNTL 0x00009494 +#define TD0_CNTL__ID_OVERRIDE(x) (((x) & 0x00000003) << 28) +#define TD0_STATUS 0x000094a4 +#define TD0_STATUS__BUSY(x) (((x) & 0x00000001) << 31) +#define TA_CNTL 0x00009504 +#define TA_CNTL__GRADIENT_CREDIT(x) (((x) & 0x0000001f) << 0) +#define TA_CNTL__WALKER_CREDIT(x) (((x) & 0x0000001f) << 8) +#define TA_CNTL__ALIGNER_CREDIT(x) (((x) & 0x0000001f) << 16) +#define TA_CNTL__TD_FIFO_CREDIT(x) (((x) & 0x000003ff) << 22) +#define TA_CNTL_AUX 0x00009508 +#define TA_CNTL_AUX__DISABLE_CUBE_WRAP(x) (((x) & 0x00000001) << 0) +#define TA_CNTL_AUX__SYNC_GRADIENT(x) (((x) & 0x00000001) << 24) +#define TA_CNTL_AUX__SYNC_WALKER(x) (((x) & 0x00000001) << 25) +#define TA_CNTL_AUX__SYNC_ALIGNER(x) (((x) & 0x00000001) << 26) +#define TA_CNTL_AUX__BILINEAR_PRECISION(x) (((x) & 0x00000001) << 31) +#define TA0_CNTL 0x00009510 +#define TA0_CNTL__ID_OVERRIDE(x) (((x) & 0x00000003) << 28) +#define TA1_CNTL 0x00009514 +#define TA1_CNTL__ID_OVERRIDE(x) (((x) & 0x00000003) << 28) +#define TA2_CNTL 0x00009518 +#define TA2_CNTL__ID_OVERRIDE(x) (((x) & 0x00000003) << 28) +#define TA3_CNTL 0x0000951c +#define TA3_CNTL__ID_OVERRIDE(x) (((x) & 0x00000003) << 28) +#define TA0_STATUS 0x00009520 +#define TA0_STATUS__FG_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 12) +#define TA0_STATUS__FG_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 13) +#define TA0_STATUS__FG_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 14) +#define TA0_STATUS__FL_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 16) +#define TA0_STATUS__FL_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 17) +#define TA0_STATUS__FL_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 18) +#define TA0_STATUS__FA_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 20) +#define TA0_STATUS__FA_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 21) +#define TA0_STATUS__FA_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 22) +#define TA0_STATUS__IN_BUSY(x) (((x) & 0x00000001) << 24) +#define TA0_STATUS__FG_BUSY(x) (((x) & 0x00000001) << 25) +#define TA0_STATUS__FL_BUSY(x) (((x) & 0x00000001) << 27) +#define TA0_STATUS__TA_BUSY(x) (((x) & 0x00000001) << 28) +#define TA0_STATUS__FA_BUSY(x) (((x) & 0x00000001) << 29) +#define TA0_STATUS__AL_BUSY(x) (((x) & 0x00000001) << 30) +#define TA0_STATUS__BUSY(x) (((x) & 0x00000001) << 31) +#define TA1_STATUS 0x00009524 +#define TA1_STATUS__FG_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 12) +#define TA1_STATUS__FG_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 13) +#define TA1_STATUS__FG_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 14) +#define TA1_STATUS__FL_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 16) +#define TA1_STATUS__FL_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 17) +#define TA1_STATUS__FL_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 18) +#define TA1_STATUS__FA_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 20) +#define TA1_STATUS__FA_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 21) +#define TA1_STATUS__FA_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 22) +#define TA1_STATUS__IN_BUSY(x) (((x) & 0x00000001) << 24) +#define TA1_STATUS__FG_BUSY(x) (((x) & 0x00000001) << 25) +#define TA1_STATUS__FL_BUSY(x) (((x) & 0x00000001) << 27) +#define TA1_STATUS__TA_BUSY(x) (((x) & 0x00000001) << 28) +#define TA1_STATUS__FA_BUSY(x) (((x) & 0x00000001) << 29) +#define TA1_STATUS__AL_BUSY(x) (((x) & 0x00000001) << 30) +#define TA1_STATUS__BUSY(x) (((x) & 0x00000001) << 31) +#define TA2_STATUS 0x00009528 +#define TA2_STATUS__FG_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 12) +#define TA2_STATUS__FG_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 13) +#define TA2_STATUS__FG_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 14) +#define TA2_STATUS__FL_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 16) +#define TA2_STATUS__FL_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 17) +#define TA2_STATUS__FL_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 18) +#define TA2_STATUS__FA_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 20) +#define TA2_STATUS__FA_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 21) +#define TA2_STATUS__FA_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 22) +#define TA2_STATUS__IN_BUSY(x) (((x) & 0x00000001) << 24) +#define TA2_STATUS__FG_BUSY(x) (((x) & 0x00000001) << 25) +#define TA2_STATUS__FL_BUSY(x) (((x) & 0x00000001) << 27) +#define TA2_STATUS__TA_BUSY(x) (((x) & 0x00000001) << 28) +#define TA2_STATUS__FA_BUSY(x) (((x) & 0x00000001) << 29) +#define TA2_STATUS__AL_BUSY(x) (((x) & 0x00000001) << 30) +#define TA2_STATUS__BUSY(x) (((x) & 0x00000001) << 31) +#define TA3_STATUS 0x0000952c +#define TA3_STATUS__FG_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 12) +#define TA3_STATUS__FG_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 13) +#define TA3_STATUS__FG_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 14) +#define TA3_STATUS__FL_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 16) +#define TA3_STATUS__FL_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 17) +#define TA3_STATUS__FL_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 18) +#define TA3_STATUS__FA_PFIFO_EMPTYB(x) (((x) & 0x00000001) << 20) +#define TA3_STATUS__FA_LFIFO_EMPTYB(x) (((x) & 0x00000001) << 21) +#define TA3_STATUS__FA_SFIFO_EMPTYB(x) (((x) & 0x00000001) << 22) +#define TA3_STATUS__IN_BUSY(x) (((x) & 0x00000001) << 24) +#define TA3_STATUS__FG_BUSY(x) (((x) & 0x00000001) << 25) +#define TA3_STATUS__FL_BUSY(x) (((x) & 0x00000001) << 27) +#define TA3_STATUS__TA_BUSY(x) (((x) & 0x00000001) << 28) +#define TA3_STATUS__FA_BUSY(x) (((x) & 0x00000001) << 29) +#define TA3_STATUS__AL_BUSY(x) (((x) & 0x00000001) << 30) +#define TA3_STATUS__BUSY(x) (((x) & 0x00000001) << 31) +#define TC_STATUS 0x00009600 +#define TC_STATUS__TC_BUSY(x) (((x) & 0x00000001) << 0) +#define TC_INVALIDATE 0x00009604 +#define TC_INVALIDATE__START(x) (((x) & 0x00000001) << 0) +#define TC_CNTL 0x00009608 +#define TC_CNTL__FORCE_HIT(x) (((x) & 0x00000001) << 0) +#define TC_CNTL__FORCE_MISS(x) (((x) & 0x00000001) << 1) +#define TC_CNTL__L2_SIZE(x) (((x) & 0x0000000f) << 5) +#define L2_256K 0 +#define L2_224K 1 +#define L2_192K 2 +#define L2_160K 3 +#define L2_128K 4 +#define L2_96K 5 +#define L2_64K 6 +#define L2_32K 7 +#define TC_CNTL__L2_DISABLE_LATE_HIT(x) (((x) & 0x00000001) << 9) +#define TC_CNTL__DISABLE_VERT_PERF(x) (((x) & 0x00000001) << 10) +#define TC_CNTL__DISABLE_INVAL_BUSY(x) (((x) & 0x00000001) << 11) +#define TC_CNTL__DISABLE_INVAL_SAME_SURFACE(x) (((x) & 0x00000001) << 12) +#define TC_CNTL__PARTITION_MODE(x) (((x) & 0x00000003) << 13) +#define X_VERTEX 0 +#define TC_CNTL__MISS_ARB_MODE(x) (((x) & 0x00000001) << 15) +#define TC_CNTL__HIT_ARB_MODE(x) (((x) & 0x00000001) << 16) +#define TC_CNTL__DISABLE_WRITE_DELAY(x) (((x) & 0x00000001) << 17) +#define TC_CNTL__HIT_FIFO_DEPTH(x) (((x) & 0x00000001) << 18) +#define VC_CNTL 0x00009700 +#define VC_CNTL__L2_INVALIDATE(x) (((x) & 0x00000001) << 0) +#define VC_CNTL__RESERVED(x) (((x) & 0x00000001) << 1) +#define VC_CNTL__CC_FORCE_MISS(x) (((x) & 0x00000001) << 2) +#define VC_CNTL__MI_CHAN_SEL(x) (((x) & 0x00000003) << 3) +#define X_MC0_USES_CH_0_1 0 +#define X_MC0_USES_CH_0_3 1 +#define X_VC_MC0_IS_ACTIVE 2 +#define X_VC_MC1_IS_DISABLED 3 +#define VC_CNTL__MI_STEER_DISABLE(x) (((x) & 0x00000001) << 5) +#define VC_CNTL__MI_CREDIT_CTR(x) (((x) & 0x0000000f) << 6) +#define VC_CNTL__MI_CREDIT_WE(x) (((x) & 0x00000001) << 10) +#define VC_CNTL__MI_REQ_STALL_THLD(x) (((x) & 0x00000007) << 11) +#define X_LATENCY_EXCEEDS_399_CLOCKS 0 +#define X_LATENCY_EXCEEDS_415_CLOCKS 1 +#define X_LATENCY_EXCEEDS_431_CLOCKS 2 +#define X_LATENCY_EXCEEDS_447_CLOCKS 3 +#define X_LATENCY_EXCEEDS_463_CLOCKS 4 +#define X_LATENCY_EXCEEDS_479_CLOCKS 5 +#define X_LATENCY_EXCEEDS_495_CLOCKS 6 +#define X_LATENCY_EXCEEDS_511_CLOCKS 7 +#define VC_CNTL__MI_TIMESTAMP_RES(x) (((x) & 0x0000001f) << 14) +#define X_1X_SYSTEM_CLOCK 0 +#define X_2X_SYSTEM_CLOCK 1 +#define X_4X_SYSTEM_CLOCK 2 +#define X_8X_SYSTEM_CLOCK 3 +#define X_16X_SYSTEM_CLOCK 4 +#define X_32X_SYSTEM_CLOCK 5 +#define X_64X_SYSTEM_CLOCK 6 +#define X_128X_SYSTEM_CLOCK 7 +#define X_256X_SYSTEM_CLOCK 8 +#define X_512X_SYSTEM_CLOCK 9 +#define X_1024X_SYSTEM_CLOCK 10 +#define X_2048X_SYSTEM_CLOCK 11 +#define X_4092X_SYSTEM_CLOCK 12 +#define X_8192X_SYSTEM_CLOCK 13 +#define X_16384X_SYSTEM_CLOCK 14 +#define X_32768X_SYSTEM_CLOCK 15 +#define VC_CNTL_STATUS 0x00009704 +#define VC_CNTL_STATUS__RP_BUSY(x) (((x) & 0x00000001) << 0) +#define VC_CNTL_STATUS__RG_BUSY(x) (((x) & 0x00000001) << 1) +#define VC_CNTL_STATUS__VC_BUSY(x) (((x) & 0x00000001) << 2) +#define VC_CNTL_STATUS__CLAMP_DETECT(x) (((x) & 0x00000001) << 3) +#define VC_ENHANCE 0x00009714 +#define VC_CONFIG 0x00009718 +#define VC_CONFIG__WRITE_DIS(x) (((x) & 0x00000001) << 0) +#define VC_CONFIG__GPR_DATA_PHASE_ADJ(x) (((x) & 0x00000007) << 1) +#define X_LATENCY_BASE_0_CYCLES 0 +#define X_LATENCY_BASE_1_CYCLES 1 +#define X_LATENCY_BASE_2_CYCLES 2 +#define X_LATENCY_BASE_3_CYCLES 3 +#define VC_CONFIG__TD_SIMD_SYNC_ADJ(x) (((x) & 0x00000007) << 4) +#define X_0_CYCLES_DELAY 0 +#define X_1_CYCLES_DELAY 1 +#define X_2_CYCLES_DELAY 2 +#define X_3_CYCLES_DELAY 3 +#define X_4_CYCLES_DELAY 4 +#define X_5_CYCLES_DELAY 5 +#define X_6_CYCLES_DELAY 6 +#define X_7_CYCLES_DELAY 7 +#define DB_DEBUG 0x00009830 +#define DB_WATERMARKS 0x00009838 +#define DB_WATERMARKS__DEPTH_FREE(x) (((x) & 0x0000001f) << 0) +#define DB_WATERMARKS__DEPTH_FLUSH(x) (((x) & 0x0000003f) << 5) +#define DB_WATERMARKS__FORCE_SUMMARIZE(x) (((x) & 0x0000000f) << 11) +#define DB_WATERMARKS__DEPTH_PENDING_FREE(x) (((x) & 0x0000001f) << 15) +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE(x) (((x) & 0x0000001f) << 20) +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE(x) (((x) & 0x00000001) << 25) +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE(x) (((x) & 0x00000001) << 26) +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE(x) (((x) & 0x00000001) << 27) +#define DB_WATERMARKS__DB_EXTRA_DEBUG(x) (((x) & 0x0000000f) << 28) +#define SMX_DC_CTL0 0x0000a020 +#define SMX_DC_CTL0__WR_GATHER_STREAM0(x) (((x) & 0x00000001) << 0) +#define SMX_DC_CTL0__WR_GATHER_STREAM1(x) (((x) & 0x00000001) << 1) +#define SMX_DC_CTL0__WR_GATHER_STREAM2(x) (((x) & 0x00000001) << 2) +#define SMX_DC_CTL0__WR_GATHER_STREAM3(x) (((x) & 0x00000001) << 3) +#define SMX_DC_CTL0__WR_GATHER_SCRATCH(x) (((x) & 0x00000001) << 4) +#define SMX_DC_CTL0__WR_GATHER_REDUC_BUF(x) (((x) & 0x00000001) << 5) +#define SMX_DC_CTL0__WR_GATHER_RING_BUF(x) (((x) & 0x00000001) << 6) +#define SMX_DC_CTL0__WR_GATHER_F_BUF(x) (((x) & 0x00000001) << 7) +#define SMX_DC_CTL0__DISABLE_CACHES(x) (((x) & 0x00000001) << 8) +#define SMX_DC_CTL0__AUTO_FLUSH_INVAL_EN(x) (((x) & 0x00000001) << 10) +#define SMX_DC_CTL0__AUTO_FLUSH_EN(x) (((x) & 0x00000001) << 11) +#define SMX_DC_CTL0__AUTO_FLUSH_CNT(x) (((x) & 0x0000ffff) << 12) +#define SMX_DC_CTL0__MC_RD_STALL_FACTOR(x) (((x) & 0x00000003) << 28) +#define SMX_DC_CTL0__MC_WR_STALL_FACTOR(x) (((x) & 0x00000003) << 30) +#define SMX_DC_CTL1 0x0000a024 +#define SMX_DC_CTL1__OP_FIFO_SKID(x) (((x) & 0x0000007f) << 0) +#define SMX_DC_CTL1__CACHE_LINE_SIZE(x) (((x) & 0x00000001) << 8) +#define SMX_DC_CTL1__MULTI_FLUSH_MODE(x) (((x) & 0x00000001) << 9) +#define SMX_DC_CTL1__MULTI_FLUSH_REQ_ABORT_IDX_FIFO_SKID(x) (((x) & 0x0000000f) << 10) +#define SMX_DC_CTL1__DISABLE_WR_GATHER_RD_HIT_FORCE_EVICT(x)(((x) & 0x00000001) << 16) +#define SMX_DC_CTL1__DISABLE_WR_GATHER_RD_HIT_COMP_VLDS_CHECK(x) (((x) & 0x00000001) << 17) +#define SMX_DC_CTL1__DISABLE_FLUSH_ES_ALSO_INVALS(x) (((x) & 0x00000001) << 18) +#define SMX_DC_CTL1__DISABLE_FLUSH_GS_ALSO_INVALS(x) (((x) & 0x00000001) << 19) +#define SMX_DC_CTL2 0x0000a028 +#define SMX_DC_CTL2__INVALIDATE_CACHES(x) (((x) & 0x00000001) << 0) +#define SMX_DC_CTL2__CACHES_INVALID(x) (((x) & 0x00000001) << 1) +#define SMX_DC_CTL2__CACHES_DIRTY(x) (((x) & 0x00000001) << 2) +#define SMX_DC_CTL2__FLUSH_ALL(x) (((x) & 0x00000001) << 4) +#define SMX_DC_CTL2__FLUSH_GS_THREADS(x) (((x) & 0x00000001) << 8) +#define SMX_DC_CTL2__FLUSH_ES_THREADS(x) (((x) & 0x00000001) << 9) +#define SMX_DC_MC_INTF_CTL 0x0000a02c +#define SMX_DC_MC_INTF_CTL__MC_RD_REQ_CRED(x) (((x) & 0x000000ff) << 0) +#define SMX_DC_MC_INTF_CTL__MC_WR_REQ_CRED(x) (((x) & 0x000000ff) << 16) +#define TD_PS_SAMPLER0_BORDER_RED 0x0000a400 +#define TD_PS_SAMPLER0_BORDER_GREEN 0x0000a404 +#define TD_PS_SAMPLER0_BORDER_BLUE 0x0000a408 +#define TD_PS_SAMPLER0_BORDER_ALPHA 0x0000a40c +#define TD_VS_SAMPLER0_BORDER_RED 0x0000a600 +#define TD_VS_SAMPLER0_BORDER_GREEN 0x0000a604 +#define TD_VS_SAMPLER0_BORDER_BLUE 0x0000a608 +#define TD_VS_SAMPLER0_BORDER_ALPHA 0x0000a60c +#define TD_GS_SAMPLER0_BORDER_RED 0x0000a800 +#define TD_GS_SAMPLER0_BORDER_GREEN 0x0000a804 +#define TD_GS_SAMPLER0_BORDER_BLUE 0x0000a808 +#define TD_GS_SAMPLER0_BORDER_ALPHA 0x0000a80c +#define TD_PS_SAMPLER0_CLEARTYPE_KERNEL 0x0000aa00 +#define TD_PS_SAMPLER0_CLEARTYPE_KERNEL__WIDTH(x) (((x) & 0x00000007) << 0) +#define TD_PS_SAMPLER0_CLEARTYPE_KERNEL__HEIGHT(x) (((x) & 0x00000007) << 3) + + +/***************************************************************************** + * CONTEXT REG [0x00028000 0x00029000] + */ +#define DB_DEPTH_SIZE 0x00028000 +#define DB_DEPTH_SIZE__PITCH_TILE_MAX(x) (((x) & 0x000003ff) << 0) +#define DB_DEPTH_SIZE__SLICE_TILE_MAX(x) (((x) & 0x000fffff) << 10) +#define DB_DEPTH_VIEW 0x00028004 +#define DB_DEPTH_VIEW__SLICE_START(x) (((x) & 0x000007ff) << 0) +#define DB_DEPTH_VIEW__SLICE_MAX(x) (((x) & 0x000007ff) << 13) +#define DB_DEPTH_BASE 0x0002800c +#define DB_DEPTH_INFO 0x00028010 +#define DB_DEPTH_INFO__FORMAT(x) (((x) & 0x00000007) << 0) +#define DEPTH_INVALID 0 +#define DEPTH_16 1 +#define DEPTH_X8_24 2 +#define DEPTH_8_24 3 +#define DEPTH_X8_24_FLOAT 4 +#define DEPTH_8_24_FLOAT 5 +#define DEPTH_32_FLOAT 6 +#define DEPTH_X24_8_32_FLOAT 7 +#define DB_DEPTH_INFO__READ_SIZE(x) (((x) & 0x00000001) << 3) +#define DB_DEPTH_INFO__ARRAY_MODE(x) (((x) & 0x0000000f) << 15) +#define ARRAY_1D_TILED_THIN1 2 +#define ARRAY_2D_TILED_THIN1 4 +#define DB_DEPTH_INFO__TILE_SURFACE_ENABLE(x) (((x) & 0x00000001) << 25) +#define DB_DEPTH_INFO__TILE_COMPACT(x) (((x) & 0x00000001) << 26) +#define DB_DEPTH_INFO__ZRANGE_PRECISION(x) (((x) & 0x00000001) << 31) +#define DB_HTILE_DATA_BASE 0x00028014 +#define DB_STENCIL_CLEAR 0x00028028 +#define DB_STENCIL_CLEAR__CLEAR(x) (((x) & 0x000000ff) << 0) +#define DB_STENCIL_CLEAR__MIN(x) (((x) & 0x000000ff) << 16) +#define DB_DEPTH_CLEAR 0x0002802c +#define PA_SC_SCREEN_SCISSOR_TL 0x00028030 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X(x) (((x) & 0x00007fff) << 0) +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y(x) (((x) & 0x00007fff) << 16) +#define PA_SC_SCREEN_SCISSOR_BR 0x00028034 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X(x) (((x) & 0x00007fff) << 0) +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y(x) (((x) & 0x00007fff) << 16) +#define CB_COLOR0_BASE 0x00028040 +#define CB_COLOR0_SIZE 0x00028060 +#define CB_COLOR0_SIZE__PITCH_TILE_MAX(x) (((x) & 0x000003ff) << 0) +#define CB_COLOR0_SIZE__SLICE_TILE_MAX(x) (((x) & 0x000fffff) << 10) +#define CB_COLOR0_VIEW 0x00028080 +#define CB_COLOR0_VIEW__SLICE_START(x) (((x) & 0x000007ff) << 0) +#define CB_COLOR0_VIEW__SLICE_MAX(x) (((x) & 0x000007ff) << 13) +#define CB_COLOR0_INFO 0x000280a0 +#define CB_COLOR0_INFO__ENDIAN(x) (((x) & 0x00000003) << 0) +#define ENDIAN_NONE 0 +#define ENDIAN_8IN16 1 +#define ENDIAN_8IN32 2 +#define ENDIAN_8IN64 3 +#define CB_COLOR0_INFO__FORMAT(x) (((x) & 0x0000003f) << 2) +#define COLOR_INVALID 0 +#define COLOR_8 1 +#define COLOR_4_4 2 +#define COLOR_3_3_2 3 +#define COLOR_16 5 +#define COLOR_16_FLOAT 6 +#define COLOR_8_8 7 +#define COLOR_5_6_5 8 +#define COLOR_6_5_5 9 +#define COLOR_1_5_5_5 10 +#define COLOR_4_4_4_4 11 +#define COLOR_5_5_5_1 12 +#define COLOR_32 13 +#define COLOR_32_FLOAT 14 +#define COLOR_16_16 15 +#define COLOR_16_16_FLOAT 16 +#define COLOR_8_24 17 +#define COLOR_8_24_FLOAT 18 +#define COLOR_24_8 19 +#define COLOR_24_8_FLOAT 20 +#define COLOR_10_11_11 21 +#define COLOR_10_11_11_FLOAT 22 +#define COLOR_11_11_10 23 +#define COLOR_11_11_10_FLOAT 24 +#define COLOR_2_10_10_10 25 +#define COLOR_8_8_8_8 26 +#define COLOR_10_10_10_2 27 +#define COLOR_X24_8_32_FLOAT 28 +#define COLOR_32_32 29 +#define COLOR_32_32_FLOAT 30 +#define COLOR_16_16_16_16 31 +#define COLOR_16_16_16_16_FLOAT 32 +#define COLOR_32_32_32_32 34 +#define COLOR_32_32_32_32_FLOAT 35 +#define CB_COLOR0_INFO__ARRAY_MODE(x) (((x) & 0x0000000f) << 8) +#define ARRAY_LINEAR_GENERAL 0 +#define ARRAY_LINEAR_ALIGNED 1 +#define ARRAY_2D_TILED_THIN1 4 +#define CB_COLOR0_INFO__NUMBER_TYPE(x) (((x) & 0x00000007) << 12) +#define NUMBER_UNORM 0 +#define NUMBER_SNORM 1 +#define NUMBER_USCALED 2 +#define NUMBER_SSCALED 3 +#define NUMBER_UINT 4 +#define NUMBER_SINT 5 +#define NUMBER_SRGB 6 +#define NUMBER_FLOAT 7 +#define CB_COLOR0_INFO__READ_SIZE(x) (((x) & 0x00000001) << 15) +#define CB_COLOR0_INFO__COMP_SWAP(x) (((x) & 0x00000003) << 16) +#define SWAP_STD 0 +#define SWAP_ALT 1 +#define SWAP_STD_REV 2 +#define SWAP_ALT_REV 3 +#define CB_COLOR0_INFO__TILE_MODE(x) (((x) & 0x00000003) << 18) +#define TILE_DISABLE 0 +#define TILE_CLEAR_ENABLE 1 +#define TILE_FRAG_ENABLE 2 +#define CB_COLOR0_INFO__BLEND_CLAMP(x) (((x) & 0x00000001) << 20) +#define CB_COLOR0_INFO__CLEAR_COLOR(x) (((x) & 0x00000001) << 21) +#define CB_COLOR0_INFO__BLEND_BYPASS(x) (((x) & 0x00000001) << 22) +#define CB_COLOR0_INFO__BLEND_FLOAT32(x) (((x) & 0x00000001) << 23) +#define CB_COLOR0_INFO__SIMPLE_FLOAT(x) (((x) & 0x00000001) << 24) +#define CB_COLOR0_INFO__ROUND_MODE(x) (((x) & 0x00000001) << 25) +#define CB_COLOR0_INFO__TILE_COMPACT(x) (((x) & 0x00000001) << 26) +#define CB_COLOR0_INFO__SOURCE_FORMAT(x) (((x) & 0x00000001) << 27) +#define CB_COLOR0_TILE 0x000280c0 +#define CB_COLOR0_FRAG 0x000280e0 +#define CB_COLOR0_MASK 0x00028100 +#define CB_COLOR0_MASK__CMASK_BLOCK_MAX(x) (((x) & 0x00000fff) << 0) +#define CB_COLOR0_MASK__FMASK_TILE_MAX(x) (((x) & 0x000fffff) << 12) +#define CB_CLEAR_RED 0x00028120 +#define CB_CLEAR_GREEN 0x00028124 +#define CB_CLEAR_BLUE 0x00028128 +#define CB_CLEAR_ALPHA 0x0002812c +#define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 +#define SQ_ALU_CONST_BUFFER_SIZE_PS_0__DATA(x) (((x) & 0x000001ff) << 0) +#define SQ_ALU_CONST_BUFFER_SIZE_VS_0 0x00028180 +#define SQ_ALU_CONST_BUFFER_SIZE_VS_0__DATA(x) (((x) & 0x000001ff) << 0) +#define SQ_ALU_CONST_BUFFER_SIZE_GS_0 0x000281c0 +#define SQ_ALU_CONST_BUFFER_SIZE_GS_0__DATA(x) (((x) & 0x000001ff) << 0) +#define PA_SC_WINDOW_OFFSET 0x00028200 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET(x) (((x) & 0x00007fff) << 0) +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET(x) (((x) & 0x00007fff) << 16) +#define PA_SC_WINDOW_SCISSOR_TL 0x00028204 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE(x) (((x) & 0x00000001) << 31) +#define PA_SC_WINDOW_SCISSOR_BR 0x00028208 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_CLIPRECT_RULE 0x0002820c +#define PA_SC_CLIPRECT_RULE__CLIP_RULE(x) (((x) & 0x0000ffff) << 0) +#define PA_SC_CLIPRECT_0_TL 0x00028210 +#define PA_SC_CLIPRECT_0_TL__NUM 4 +#define PA_SC_CLIPRECT_0_TL__STRIDE 8 +#define PA_SC_CLIPRECT_0_TL__TL_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_CLIPRECT_0_TL__TL_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_CLIPRECT_0_BR 0x00028214 +#define PA_SC_CLIPRECT_0_BR__BR_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_CLIPRECT_0_BR__BR_Y(x) (((x) & 0x00003fff) << 16) +#define CB_TARGET_MASK 0x00028238 +#define CB_TARGET_MASK__TARGET0_ENABLE(x) (((x) & 0x0000000f) << 0) +#define CB_TARGET_MASK__TARGET1_ENABLE(x) (((x) & 0x0000000f) << 4) +#define CB_TARGET_MASK__TARGET2_ENABLE(x) (((x) & 0x0000000f) << 8) +#define CB_TARGET_MASK__TARGET3_ENABLE(x) (((x) & 0x0000000f) << 12) +#define CB_TARGET_MASK__TARGET4_ENABLE(x) (((x) & 0x0000000f) << 16) +#define CB_TARGET_MASK__TARGET5_ENABLE(x) (((x) & 0x0000000f) << 20) +#define CB_TARGET_MASK__TARGET6_ENABLE(x) (((x) & 0x0000000f) << 24) +#define CB_TARGET_MASK__TARGET7_ENABLE(x) (((x) & 0x0000000f) << 28) +#define CB_SHADER_MASK 0x0002823c +#define CB_SHADER_MASK__OUTPUT0_ENABLE(x) (((x) & 0x0000000f) << 0) +#define CB_SHADER_MASK__OUTPUT1_ENABLE(x) (((x) & 0x0000000f) << 4) +#define CB_SHADER_MASK__OUTPUT2_ENABLE(x) (((x) & 0x0000000f) << 8) +#define CB_SHADER_MASK__OUTPUT3_ENABLE(x) (((x) & 0x0000000f) << 12) +#define CB_SHADER_MASK__OUTPUT4_ENABLE(x) (((x) & 0x0000000f) << 16) +#define CB_SHADER_MASK__OUTPUT5_ENABLE(x) (((x) & 0x0000000f) << 20) +#define CB_SHADER_MASK__OUTPUT6_ENABLE(x) (((x) & 0x0000000f) << 24) +#define CB_SHADER_MASK__OUTPUT7_ENABLE(x) (((x) & 0x0000000f) << 28) +#define PA_SC_GENERIC_SCISSOR_TL 0x00028240 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE(x) (((x) & 0x00000001) << 31) +#define PA_SC_GENERIC_SCISSOR_BR 0x00028244 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_VPORT_SCISSOR_0_TL 0x00028250 +#define PA_SC_VPORT_SCISSOR_0_TL__NUM 16 +#define PA_SC_VPORT_SCISSOR_0_TL__STRIDE 8 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE(x) (((x) & 0x00000001) << 31) +#define PA_SC_VPORT_SCISSOR_0_BR 0x00028254 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X(x) (((x) & 0x00003fff) << 0) +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y(x) (((x) & 0x00003fff) << 16) +#define PA_SC_VPORT_ZMIN_0 0x000282d0 +#define PA_SC_VPORT_ZMAX_0 0x000282d4 +#define SX_MISC 0x00028350 +#define SX_MISC__MULTIPASS(x) (((x) & 0x00000001) << 0) +#define SQ_VTX_SEMANTIC_0 0x00028380 +#define SQ_VTX_SEMANTIC_0__SEMANTIC_ID(x) (((x) & 0x000000ff) << 0) +#define VGT_MAX_VTX_INDX 0x00028400 +#define VGT_MIN_VTX_INDX 0x00028404 +#define VGT_INDX_OFFSET 0x00028408 +#define VGT_MULTI_PRIM_IB_RESET_INDX 0x0002840c +#define SX_ALPHA_TEST_CONTROL 0x00028410 +#define SX_ALPHA_TEST_CONTROL__ALPHA_FUNC(x) (((x) & 0x00000007) << 0) +#define REF_NEVER 0 +#define REF_LESS 1 +#define REF_EQUAL 2 +#define REF_LEQUAL 3 +#define REF_GREATER 4 +#define REF_NOTEQUAL 5 +#define REF_GEQUAL 6 +#define REF_ALWAYS 7 +#define SX_ALPHA_TEST_CONTROL__ALPHA_TEST_ENABLE(x) (((x) & 0x00000001) << 3) +#define SX_ALPHA_TEST_CONTROL__ALPHA_TEST_BYPASS(x) (((x) & 0x00000001) << 8) +#define CB_BLEND_RED 0x00028414 +#define CB_BLEND_GREEN 0x00028418 +#define CB_BLEND_BLUE 0x0002841c +#define CB_BLEND_ALPHA 0x00028420 +#define CB_FOG_RED 0x00028424 +#define CB_FOG_GREEN 0x00028428 +#define CB_FOG_BLUE 0x0002842c +#define DB_STENCILREFMASK 0x00028430 +#define DB_STENCILREFMASK__STENCILREF(x) (((x) & 0x000000ff) << 0) +#define DB_STENCILREFMASK__STENCILMASK(x) (((x) & 0x000000ff) << 8) +#define DB_STENCILREFMASK__STENCILWRITEMASK(x) (((x) & 0x000000ff) << 16) +#define DB_STENCILREFMASK_BF 0x00028434 +#define DB_STENCILREFMASK_BF__STENCILREF_BF(x) (((x) & 0x000000ff) << 0) +#define DB_STENCILREFMASK_BF__STENCILMASK_BF(x) (((x) & 0x000000ff) << 8) +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF(x) (((x) & 0x000000ff) << 16) +#define SX_ALPHA_REF 0x00028438 +#define PA_CL_VPORT_XSCALE_0 0x0002843c +#define PA_CL_VPORT_XOFFSET_0 0x00028440 +#define PA_CL_VPORT_YSCALE_0 0x00028444 +#define PA_CL_VPORT_YOFFSET_0 0x00028448 +#define PA_CL_VPORT_ZSCALE_0 0x0002844c +#define PA_CL_VPORT_ZOFFSET_0 0x00028450 +#define SPI_VS_OUT_ID_0 0x00028614 +#define SPI_VS_OUT_ID_0__SEMANTIC_0(x) (((x) & 0x000000ff) << 0) +#define SPI_VS_OUT_ID_0__SEMANTIC_1(x) (((x) & 0x000000ff) << 8) +#define SPI_VS_OUT_ID_0__SEMANTIC_2(x) (((x) & 0x000000ff) << 16) +#define SPI_VS_OUT_ID_0__SEMANTIC_3(x) (((x) & 0x000000ff) << 24) +#define SPI_PS_INPUT_CNTL_0 0x00028644 +#define SPI_PS_INPUT_CNTL_0__SEMANTIC(x) (((x) & 0x000000ff) << 0) +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL(x) (((x) & 0x00000003) << 8) +#define X_0_0F 0 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE(x) (((x) & 0x00000001) << 10) +#define SPI_PS_INPUT_CNTL_0__SEL_CENTROID(x) (((x) & 0x00000001) << 11) +#define SPI_PS_INPUT_CNTL_0__SEL_LINEAR(x) (((x) & 0x00000001) << 12) +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP(x) (((x) & 0x0000000f) << 13) +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX(x) (((x) & 0x00000001) << 17) +#define SPI_PS_INPUT_CNTL_0__SEL_SAMPLE(x) (((x) & 0x00000001) << 18) +#define SPI_VS_OUT_CONFIG 0x000286c4 +#define SPI_VS_OUT_CONFIG__VS_PER_COMPONENT(x) (((x) & 0x00000001) << 0) +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT(x) (((x) & 0x0000001f) << 1) +#define SPI_VS_OUT_CONFIG__VS_EXPORTS_FOG(x) (((x) & 0x00000001) << 8) +#define SPI_VS_OUT_CONFIG__VS_OUT_FOG_VEC_ADDR(x) (((x) & 0x0000001f) << 9) +#define SPI_PS_IN_CONTROL_0 0x000286cc +#define SPI_PS_IN_CONTROL_0__NUM_INTERP(x) (((x) & 0x0000003f) << 0) +#define SPI_PS_IN_CONTROL_0__POSITION_ENA(x) (((x) & 0x00000001) << 8) +#define SPI_PS_IN_CONTROL_0__POSITION_CENTROID(x) (((x) & 0x00000001) << 9) +#define SPI_PS_IN_CONTROL_0__POSITION_ADDR(x) (((x) & 0x0000001f) << 10) +#define SPI_PS_IN_CONTROL_0__PARAM_GEN(x) (((x) & 0x0000000f) << 15) +#define SPI_PS_IN_CONTROL_0__PARAM_GEN_ADDR(x) (((x) & 0x0000007f) << 19) +#define SPI_PS_IN_CONTROL_0__BARYC_SAMPLE_CNTL(x) (((x) & 0x00000003) << 26) +#define CENTROIDS_ONLY 0 +#define CENTERS_ONLY 1 +#define CENTROIDS_AND_CENTERS 2 +#define UNDEF 3 +#define SPI_PS_IN_CONTROL_0__PERSP_GRADIENT_ENA(x) (((x) & 0x00000001) << 28) +#define SPI_PS_IN_CONTROL_0__LINEAR_GRADIENT_ENA(x) (((x) & 0x00000001) << 29) +#define SPI_PS_IN_CONTROL_0__POSITION_SAMPLE(x) (((x) & 0x00000001) << 30) +#define SPI_PS_IN_CONTROL_0__BARYC_AT_SAMPLE_ENA(x) (((x) & 0x00000001) << 31) +#define SPI_PS_IN_CONTROL_1 0x000286d0 +#define SPI_PS_IN_CONTROL_1__GEN_INDEX_PIX(x) (((x) & 0x00000001) << 0) +#define SPI_PS_IN_CONTROL_1__GEN_INDEX_PIX_ADDR(x) (((x) & 0x0000007f) << 1) +#define SPI_PS_IN_CONTROL_1__FRONT_FACE_ENA(x) (((x) & 0x00000001) << 8) +#define SPI_PS_IN_CONTROL_1__FRONT_FACE_CHAN(x) (((x) & 0x00000003) << 9) +#define SPI_PS_IN_CONTROL_1__FRONT_FACE_ALL_BITS(x) (((x) & 0x00000001) << 11) +#define SPI_PS_IN_CONTROL_1__FRONT_FACE_ADDR(x) (((x) & 0x0000001f) << 12) +#define SPI_PS_IN_CONTROL_1__FOG_ADDR(x) (((x) & 0x0000007f) << 17) +#define SPI_PS_IN_CONTROL_1__FIXED_PT_POSITION_ENA(x) (((x) & 0x00000001) << 24) +#define SPI_PS_IN_CONTROL_1__FIXED_PT_POSITION_ADDR(x) (((x) & 0x0000001f) << 25) +#define SPI_INTERP_CONTROL_0 0x000286d4 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA(x) (((x) & 0x00000001) << 0) +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA(x) (((x) & 0x00000001) << 1) +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X(x) (((x) & 0x00000007) << 2) +#define SPI_PNT_SPRITE_SEL_0 0 +#define SPI_PNT_SPRITE_SEL_1 1 +#define SPI_PNT_SPRITE_SEL_S 2 +#define SPI_PNT_SPRITE_SEL_T 3 +#define SPI_PNT_SPRITE_SEL_NONE 4 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y(x) (((x) & 0x00000007) << 5) +#define SPI_PNT_SPRITE_SEL_0 0 +#define SPI_PNT_SPRITE_SEL_1 1 +#define SPI_PNT_SPRITE_SEL_S 2 +#define SPI_PNT_SPRITE_SEL_T 3 +#define SPI_PNT_SPRITE_SEL_NONE 4 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z(x) (((x) & 0x00000007) << 8) +#define SPI_PNT_SPRITE_SEL_0 0 +#define SPI_PNT_SPRITE_SEL_1 1 +#define SPI_PNT_SPRITE_SEL_S 2 +#define SPI_PNT_SPRITE_SEL_T 3 +#define SPI_PNT_SPRITE_SEL_NONE 4 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W(x) (((x) & 0x00000007) << 11) +#define SPI_PNT_SPRITE_SEL_0 0 +#define SPI_PNT_SPRITE_SEL_1 1 +#define SPI_PNT_SPRITE_SEL_S 2 +#define SPI_PNT_SPRITE_SEL_T 3 +#define SPI_PNT_SPRITE_SEL_NONE 4 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1(x) (((x) & 0x00000001) << 14) +#define SPI_INPUT_Z 0x000286d8 +#define SPI_INPUT_Z__PROVIDE_Z_TO_SPI(x) (((x) & 0x00000001) << 0) +#define SPI_FOG_CNTL 0x000286dc +#define SPI_FOG_CNTL__PASS_FOG_THROUGH_PS(x) (((x) & 0x00000001) << 0) +#define SPI_FOG_CNTL__PIXEL_FOG_FUNC(x) (((x) & 0x00000003) << 1) +#define SPI_FOG_NONE 0 +#define SPI_FOG_EXP 1 +#define SPI_FOG_EXP2 2 +#define SPI_FOG_LINEAR 3 +#define SPI_FOG_CNTL__PIXEL_FOG_SRC_SEL(x) (((x) & 0x00000001) << 3) +#define SPI_FOG_CNTL__VS_FOG_CLAMP_DISABLE(x) (((x) & 0x00000001) << 4) +#define SPI_FOG_FUNC_SCALE 0x000286e0 +#define SPI_FOG_FUNC_BIAS 0x000286e4 +#define CB_BLEND0_CONTROL 0x00028780 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND(x) (((x) & 0x0000001f) << 0) +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN(x) (((x) & 0x00000007) << 5) +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND(x) (((x) & 0x0000001f) << 8) +#define CB_BLEND0_CONTROL__OPACITY_WEIGHT(x) (((x) & 0x00000001) << 13) +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND(x) (((x) & 0x0000001f) << 16) +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN(x) (((x) & 0x00000007) << 21) +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND(x) (((x) & 0x0000001f) << 24) +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND(x) (((x) & 0x00000001) << 29) +#define VGT_DMA_BASE_HI 0x000287e4 +#define VGT_DMA_BASE_HI__BASE_ADDR(x) (((x) & 0x000000ff) << 0) +#define VGT_DMA_BASE 0x000287e8 +#define VGT_DRAW_INITIATOR 0x000287f0 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT(x) (((x) & 0x00000003) << 0) +#define DI_SRC_SEL_DMA 0 +#define DI_SRC_SEL_IMMEDIATE 1 +#define DI_SRC_SEL_AUTO_INDEX 2 +#define DI_SRC_SEL_RESERVED 3 +#define VGT_DRAW_INITIATOR__MAJOR_MODE(x) (((x) & 0x00000003) << 2) +#define DI_MAJOR_MODE_0 0 +#define DI_MAJOR_MODE_1 1 +#define VGT_DRAW_INITIATOR__SPRITE_EN(x) (((x) & 0x00000001) << 4) +#define VGT_DRAW_INITIATOR__NOT_EOP(x) (((x) & 0x00000001) << 5) +#define VGT_DRAW_INITIATOR__USE_OPAQUE(x) (((x) & 0x00000001) << 6) +#define VGT_IMMED_DATA 0x000287f4 +#define VGT_EVENT_ADDRESS_REG 0x000287f8 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW(x) (((x) & 0x0fffffff) << 0) +#define DB_DEPTH_CONTROL 0x00028800 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE(x) (((x) & 0x00000001) << 0) +#define DB_DEPTH_CONTROL__Z_ENABLE(x) (((x) & 0x00000001) << 1) +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE(x) (((x) & 0x00000001) << 2) +#define DB_DEPTH_CONTROL__ZFUNC(x) (((x) & 0x00000007) << 4) +#define FRAG_NEVER 0 +#define FRAG_LESS 1 +#define FRAG_EQUAL 2 +#define FRAG_LEQUAL 3 +#define FRAG_GREATER 4 +#define FRAG_NOTEQUAL 5 +#define FRAG_GEQUAL 6 +#define FRAG_ALWAYS 7 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE(x) (((x) & 0x00000001) << 7) +#define DB_DEPTH_CONTROL__STENCILFUNC(x) (((x) & 0x00000007) << 8) +#define REF_NEVER 0 +#define REF_LESS 1 +#define REF_EQUAL 2 +#define REF_LEQUAL 3 +#define REF_GREATER 4 +#define REF_NOTEQUAL 5 +#define REF_GEQUAL 6 +#define REF_ALWAYS 7 +#define DB_DEPTH_CONTROL__STENCILFAIL(x) (((x) & 0x00000007) << 11) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define DB_DEPTH_CONTROL__STENCILZPASS(x) (((x) & 0x00000007) << 14) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define DB_DEPTH_CONTROL__STENCILZFAIL(x) (((x) & 0x00000007) << 17) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF(x) (((x) & 0x00000007) << 20) +#define REF_NEVER 0 +#define REF_LESS 1 +#define REF_EQUAL 2 +#define REF_LEQUAL 3 +#define REF_GREATER 4 +#define REF_NOTEQUAL 5 +#define REF_GEQUAL 6 +#define REF_ALWAYS 7 +#define DB_DEPTH_CONTROL__STENCILFAIL_BF(x) (((x) & 0x00000007) << 23) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define DB_DEPTH_CONTROL__STENCILZPASS_BF(x) (((x) & 0x00000007) << 26) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define DB_DEPTH_CONTROL__STENCILZFAIL_BF(x) (((x) & 0x00000007) << 29) +#define STENCIL_KEEP 0 +#define STENCIL_ZERO 1 +#define STENCIL_REPLACE 2 +#define STENCIL_INCR_CLAMP 3 +#define STENCIL_DECR_CLAMP 4 +#define STENCIL_INVERT 5 +#define STENCIL_INCR_WRAP 6 +#define STENCIL_DECR_WRAP 7 +#define CB_BLEND_CONTROL 0x00028804 +#define CB_BLEND_CONTROL__COLOR_SRCBLEND(x) (((x) & 0x0000001f) << 0) +#define BLEND_ZERO 0 +#define BLEND_ONE 1 +#define BLEND_SRC_COLOR 2 +#define BLEND_ONE_MINUS_SRC_COLOR 3 +#define BLEND_SRC_ALPHA 4 +#define BLEND_ONE_MINUS_SRC_ALPHA 5 +#define BLEND_DST_ALPHA 6 +#define BLEND_ONE_MINUS_DST_ALPHA 7 +#define BLEND_DST_COLOR 8 +#define BLEND_ONE_MINUS_DST_COLOR 9 +#define BLEND_SRC_ALPHA_SATURATE 10 +#define BLEND_BOTH_SRC_ALPHA 11 +#define BLEND_BOTH_INV_SRC_ALPHA 12 +#define BLEND_CONSTANT_COLOR 13 +#define BLEND_ONE_MINUS_CONSTANT_COLOR 14 +#define BLEND_SRC1_COLOR 15 +#define BLEND_INV_SRC1_COLOR 16 +#define BLEND_SRC1_ALPHA 17 +#define BLEND_INV_SRC1_ALPHA 18 +#define BLEND_CONSTANT_ALPHA 19 +#define BLEND_ONE_MINUS_CONSTANT_ALPHA 20 +#define CB_BLEND_CONTROL__COLOR_COMB_FCN(x) (((x) & 0x00000007) << 5) +#define COMB_DST_PLUS_SRC 0 +#define COMB_SRC_MINUS_DST 1 +#define COMB_MIN_DST_SRC 2 +#define COMB_MAX_DST_SRC 3 +#define COMB_DST_MINUS_SRC 4 +#define CB_BLEND_CONTROL__COLOR_DESTBLEND(x) (((x) & 0x0000001f) << 8) +#define BLEND_ZERO 0 +#define BLEND_ONE 1 +#define BLEND_SRC_COLOR 2 +#define BLEND_ONE_MINUS_SRC_COLOR 3 +#define BLEND_SRC_ALPHA 4 +#define BLEND_ONE_MINUS_SRC_ALPHA 5 +#define BLEND_DST_ALPHA 6 +#define BLEND_ONE_MINUS_DST_ALPHA 7 +#define BLEND_DST_COLOR 8 +#define BLEND_ONE_MINUS_DST_COLOR 9 +#define BLEND_SRC_ALPHA_SATURATE 10 +#define BLEND_BOTH_SRC_ALPHA 11 +#define BLEND_BOTH_INV_SRC_ALPHA 12 +#define BLEND_CONSTANT_COLOR 13 +#define BLEND_ONE_MINUS_CONSTANT_COLOR 14 +#define BLEND_SRC1_COLOR 15 +#define BLEND_INV_SRC1_COLOR 16 +#define BLEND_SRC1_ALPHA 17 +#define BLEND_INV_SRC1_ALPHA 18 +#define BLEND_CONSTANT_ALPHA 19 +#define BLEND_ONE_MINUS_CONSTANT_ALPHA 20 +#define CB_BLEND_CONTROL__OPACITY_WEIGHT(x) (((x) & 0x00000001) << 13) +#define CB_BLEND_CONTROL__ALPHA_SRCBLEND(x) (((x) & 0x0000001f) << 16) +#define BLEND_ZERO 0 +#define BLEND_ONE 1 +#define BLEND_SRC_COLOR 2 +#define BLEND_ONE_MINUS_SRC_COLOR 3 +#define BLEND_SRC_ALPHA 4 +#define BLEND_ONE_MINUS_SRC_ALPHA 5 +#define BLEND_DST_ALPHA 6 +#define BLEND_ONE_MINUS_DST_ALPHA 7 +#define BLEND_DST_COLOR 8 +#define BLEND_ONE_MINUS_DST_COLOR 9 +#define BLEND_SRC_ALPHA_SATURATE 10 +#define BLEND_BOTH_SRC_ALPHA 11 +#define BLEND_BOTH_INV_SRC_ALPHA 12 +#define BLEND_CONSTANT_COLOR 13 +#define BLEND_ONE_MINUS_CONSTANT_COLOR 14 +#define BLEND_SRC1_COLOR 15 +#define BLEND_INV_SRC1_COLOR 16 +#define BLEND_SRC1_ALPHA 17 +#define BLEND_INV_SRC1_ALPHA 18 +#define BLEND_CONSTANT_ALPHA 19 +#define BLEND_ONE_MINUS_CONSTANT_ALPHA 20 +#define CB_BLEND_CONTROL__ALPHA_COMB_FCN(x) (((x) & 0x00000007) << 21) +#define COMB_DST_PLUS_SRC 0 +#define COMB_SRC_MINUS_DST 1 +#define COMB_MIN_DST_SRC 2 +#define COMB_MAX_DST_SRC 3 +#define COMB_DST_MINUS_SRC 4 +#define CB_BLEND_CONTROL__ALPHA_DESTBLEND(x) (((x) & 0x0000001f) << 24) +#define BLEND_ZERO 0 +#define BLEND_ONE 1 +#define BLEND_SRC_COLOR 2 +#define BLEND_ONE_MINUS_SRC_COLOR 3 +#define BLEND_SRC_ALPHA 4 +#define BLEND_ONE_MINUS_SRC_ALPHA 5 +#define BLEND_DST_ALPHA 6 +#define BLEND_ONE_MINUS_DST_ALPHA 7 +#define BLEND_DST_COLOR 8 +#define BLEND_ONE_MINUS_DST_COLOR 9 +#define BLEND_SRC_ALPHA_SATURATE 10 +#define BLEND_BOTH_SRC_ALPHA 11 +#define BLEND_BOTH_INV_SRC_ALPHA 12 +#define BLEND_CONSTANT_COLOR 13 +#define BLEND_ONE_MINUS_CONSTANT_COLOR 14 +#define BLEND_SRC1_COLOR 15 +#define BLEND_INV_SRC1_COLOR 16 +#define BLEND_SRC1_ALPHA 17 +#define BLEND_INV_SRC1_ALPHA 18 +#define BLEND_CONSTANT_ALPHA 19 +#define BLEND_ONE_MINUS_CONSTANT_ALPHA 20 +#define CB_BLEND_CONTROL__SEPARATE_ALPHA_BLEND(x) (((x) & 0x00000001) << 29) +#define CB_COLOR_CONTROL 0x00028808 +#define CB_COLOR_CONTROL__FOG_ENABLE(x) (((x) & 0x00000001) << 0) +#define CB_COLOR_CONTROL__MULTIWRITE_ENABLE(x) (((x) & 0x00000001) << 1) +#define CB_COLOR_CONTROL__DITHER_ENABLE(x) (((x) & 0x00000001) << 2) +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE(x) (((x) & 0x00000001) << 3) +#define CB_COLOR_CONTROL__SPECIAL_OP(x) (((x) & 0x00000007) << 4) +#define SPECIAL_NORMAL 0 +#define SPECIAL_DISABLE 1 +#define SPECIAL_FAST_CLEAR 2 +#define SPECIAL_FORCE_CLEAR 3 +#define SPECIAL_EXPAND_COLOR 4 +#define SPECIAL_EXPAND_TEXTURE 5 +#define SPECIAL_EXPAND_SAMPLES 6 +#define SPECIAL_RESOLVE_BOX 7 +#define CB_COLOR_CONTROL__PER_MRT_BLEND(x) (((x) & 0x00000001) << 7) +#define CB_COLOR_CONTROL__TARGET_BLEND_ENABLE(x) (((x) & 0x000000ff) << 8) +#define CB_COLOR_CONTROL__ROP3(x) (((x) & 0x000000ff) << 16) +#define ROP3_ZERO 0 +#define ROP3_NOR 17 +#define ROP3_AND_INVERTED 37 +#define ROP3_COPY_INVERTED 51 +#define ROP3_AND_REVERSE 68 +#define ROP3_INVERT 85 +#define ROP3_XOR 102 +#define ROP3_NAND 119 +#define ROP3_AND 136 +#define ROP3_EQUIV 153 +#define ROP3_NOOP 170 +#define ROP3_OR_INVERTED 187 +#define ROP3_COPY 204 +#define ROP3_OR_REVERSE 221 +#define ROP3_OR 238 +#define ROP3_ONE 255 +#define DB_SHADER_CONTROL 0x0002880c +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE(x) (((x) & 0x00000001) << 0) +#define DB_SHADER_CONTROL__STENCIL_REF_EXPORT_ENABLE(x) (((x) & 0x00000001) << 1) +#define DB_SHADER_CONTROL__Z_ORDER(x) (((x) & 0x00000003) << 4) +#define LATE_Z 0 +#define EARLY_Z_THEN_LATE_Z 1 +#define RE_Z 2 +#define EARLY_Z_THEN_RE_Z 3 +#define DB_SHADER_CONTROL__KILL_ENABLE(x) (((x) & 0x00000001) << 6) +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE(x) (((x) & 0x00000001) << 7) +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE(x) (((x) & 0x00000001) << 8) +#define DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE(x) (((x) & 0x00000001) << 9) +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL(x) (((x) & 0x00000001) << 10) +#define DB_SHADER_CONTROL__EXEC_ON_NOOP(x) (((x) & 0x00000001) << 11) +#define PA_CL_CLIP_CNTL 0x00028810 +#define PA_CL_CLIP_CNTL__UCP_ENA_0(x) (((x) & 0x00000001) << 0) +#define PA_CL_CLIP_CNTL__UCP_ENA_1(x) (((x) & 0x00000001) << 1) +#define PA_CL_CLIP_CNTL__UCP_ENA_2(x) (((x) & 0x00000001) << 2) +#define PA_CL_CLIP_CNTL__UCP_ENA_3(x) (((x) & 0x00000001) << 3) +#define PA_CL_CLIP_CNTL__UCP_ENA_4(x) (((x) & 0x00000001) << 4) +#define PA_CL_CLIP_CNTL__UCP_ENA_5(x) (((x) & 0x00000001) << 5) +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG(x) (((x) & 0x00000001) << 13) +#define PA_CL_CLIP_CNTL__PS_UCP_MODE(x) (((x) & 0x00000003) << 14) +#define PA_CL_CLIP_CNTL__CLIP_DISABLE(x) (((x) & 0x00000001) << 16) +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA(x) (((x) & 0x00000001) << 17) +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA(x) (((x) & 0x00000001) << 18) +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF(x) (((x) & 0x00000001) << 19) +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT(x) (((x) & 0x00000001) << 20) +#define PA_CL_CLIP_CNTL__VTX_KILL_OR(x) (((x) & 0x00000001) << 21) +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA(x) (((x) & 0x00000001) << 24) +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE(x) (((x) & 0x00000001) << 25) +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE(x) (((x) & 0x00000001) << 26) +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE(x) (((x) & 0x00000001) << 27) +#define PA_SU_SC_MODE_CNTL 0x00028814 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT(x) (((x) & 0x00000001) << 0) +#define PA_SU_SC_MODE_CNTL__CULL_BACK(x) (((x) & 0x00000001) << 1) +#define PA_SU_SC_MODE_CNTL__FACE(x) (((x) & 0x00000001) << 2) +#define PA_SU_SC_MODE_CNTL__POLY_MODE(x) (((x) & 0x00000003) << 3) +#define X_DISABLE_POLY_MODE 0 +#define X_DUAL_MODE 1 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE(x) (((x) & 0x00000007) << 5) +#define X_DRAW_POINTS 0 +#define X_DRAW_LINES 1 +#define X_DRAW_TRIANGLES 2 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE(x) (((x) & 0x00000007) << 8) +#define X_DRAW_POINTS 0 +#define X_DRAW_LINES 1 +#define X_DRAW_TRIANGLES 2 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE(x) (((x) & 0x00000001) << 11) +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE(x) (((x) & 0x00000001) << 12) +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE(x) (((x) & 0x00000001) << 13) +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE(x) (((x) & 0x00000001) << 16) +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST(x) (((x) & 0x00000001) << 19) +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS(x) (((x) & 0x00000001) << 20) +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA(x) (((x) & 0x00000001) << 21) +#define PA_CL_VTE_CNTL 0x00028818 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA(x) (((x) & 0x00000001) << 0) +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA(x) (((x) & 0x00000001) << 1) +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA(x) (((x) & 0x00000001) << 2) +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA(x) (((x) & 0x00000001) << 3) +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA(x) (((x) & 0x00000001) << 4) +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA(x) (((x) & 0x00000001) << 5) +#define PA_CL_VTE_CNTL__VTX_XY_FMT(x) (((x) & 0x00000001) << 8) +#define PA_CL_VTE_CNTL__VTX_Z_FMT(x) (((x) & 0x00000001) << 9) +#define PA_CL_VTE_CNTL__VTX_W0_FMT(x) (((x) & 0x00000001) << 10) +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF(x) (((x) & 0x00000001) << 11) +#define PA_CL_VS_OUT_CNTL 0x0002881c +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0(x) (((x) & 0x00000001) << 0) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1(x) (((x) & 0x00000001) << 1) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2(x) (((x) & 0x00000001) << 2) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3(x) (((x) & 0x00000001) << 3) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4(x) (((x) & 0x00000001) << 4) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5(x) (((x) & 0x00000001) << 5) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6(x) (((x) & 0x00000001) << 6) +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7(x) (((x) & 0x00000001) << 7) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0(x) (((x) & 0x00000001) << 8) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1(x) (((x) & 0x00000001) << 9) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2(x) (((x) & 0x00000001) << 10) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3(x) (((x) & 0x00000001) << 11) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4(x) (((x) & 0x00000001) << 12) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5(x) (((x) & 0x00000001) << 13) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6(x) (((x) & 0x00000001) << 14) +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7(x) (((x) & 0x00000001) << 15) +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE(x) (((x) & 0x00000001) << 16) +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG(x) (((x) & 0x00000001) << 17) +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX(x) (((x) & 0x00000001) << 18) +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX(x) (((x) & 0x00000001) << 19) +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG(x) (((x) & 0x00000001) << 20) +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA(x) (((x) & 0x00000001) << 21) +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA(x) (((x) & 0x00000001) << 22) +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA(x) (((x) & 0x00000001) << 23) +#define PA_CL_NANINF_CNTL 0x00028820 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD(x) (((x) & 0x00000001) << 0) +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD(x) (((x) & 0x00000001) << 1) +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD(x) (((x) & 0x00000001) << 2) +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0(x) (((x) & 0x00000001) << 3) +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN(x) (((x) & 0x00000001) << 4) +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN(x) (((x) & 0x00000001) << 5) +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN(x) (((x) & 0x00000001) << 6) +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0(x) (((x) & 0x00000001) << 7) +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF(x) (((x) & 0x00000001) << 8) +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN(x) (((x) & 0x00000001) << 9) +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF(x) (((x) & 0x00000001) << 10) +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN(x) (((x) & 0x00000001) << 11) +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF(x) (((x) & 0x00000001) << 12) +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN(x) (((x) & 0x00000001) << 13) +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD(x) (((x) & 0x00000001) << 14) +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0(x) (((x) & 0x00000001) << 20) +#define SQ_PGM_START_PS 0x00028840 +#define SQ_PGM_RESOURCES_PS 0x00028850 +#define SQ_PGM_RESOURCES_PS__NUM_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_PGM_RESOURCES_PS__STACK_SIZE(x) (((x) & 0x000000ff) << 8) +#define SQ_PGM_RESOURCES_PS__DX10_CLAMP(x) (((x) & 0x00000001) << 21) +#define SQ_PGM_RESOURCES_PS__FETCH_CACHE_LINES(x) (((x) & 0x00000007) << 24) +#define SQ_PGM_RESOURCES_PS__UNCACHED_FIRST_INST(x) (((x) & 0x00000001) << 28) +#define SQ_PGM_RESOURCES_PS__CLAMP_CONSTS(x) (((x) & 0x00000001) << 31) +#define SQ_PGM_EXPORTS_PS 0x00028854 +#define SQ_PGM_EXPORTS_PS__EXPORT_MODE(x) (((x) & 0x0000001f) << 0) +#define SQ_PGM_START_VS 0x00028858 +#define SQ_PGM_RESOURCES_VS 0x00028868 +#define SQ_PGM_RESOURCES_VS__NUM_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_PGM_RESOURCES_VS__STACK_SIZE(x) (((x) & 0x000000ff) << 8) +#define SQ_PGM_RESOURCES_VS__DX10_CLAMP(x) (((x) & 0x00000001) << 21) +#define SQ_PGM_RESOURCES_VS__FETCH_CACHE_LINES(x) (((x) & 0x00000007) << 24) +#define SQ_PGM_RESOURCES_VS__UNCACHED_FIRST_INST(x) (((x) & 0x00000001) << 28) +#define SQ_PGM_START_GS 0x0002886c +#define SQ_PGM_RESOURCES_GS 0x0002887c +#define SQ_PGM_RESOURCES_GS__NUM_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_PGM_RESOURCES_GS__STACK_SIZE(x) (((x) & 0x000000ff) << 8) +#define SQ_PGM_RESOURCES_GS__DX10_CLAMP(x) (((x) & 0x00000001) << 21) +#define SQ_PGM_RESOURCES_GS__FETCH_CACHE_LINES(x) (((x) & 0x00000007) << 24) +#define SQ_PGM_RESOURCES_GS__UNCACHED_FIRST_INST(x) (((x) & 0x00000001) << 28) +#define SQ_PGM_START_ES 0x00028880 +#define SQ_PGM_RESOURCES_ES 0x00028890 +#define SQ_PGM_RESOURCES_ES__NUM_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_PGM_RESOURCES_ES__STACK_SIZE(x) (((x) & 0x000000ff) << 8) +#define SQ_PGM_RESOURCES_ES__DX10_CLAMP(x) (((x) & 0x00000001) << 21) +#define SQ_PGM_RESOURCES_ES__FETCH_CACHE_LINES(x) (((x) & 0x00000007) << 24) +#define SQ_PGM_RESOURCES_ES__UNCACHED_FIRST_INST(x) (((x) & 0x00000001) << 28) +#define SQ_PGM_START_FS 0x00028894 +#define SQ_PGM_RESOURCES_FS 0x000288a4 +#define SQ_PGM_RESOURCES_FS__NUM_GPRS(x) (((x) & 0x000000ff) << 0) +#define SQ_PGM_RESOURCES_FS__STACK_SIZE(x) (((x) & 0x000000ff) << 8) +#define SQ_PGM_RESOURCES_FS__DX10_CLAMP(x) (((x) & 0x00000001) << 21) +#define SQ_ESGS_RING_ITEMSIZE 0x000288a8 +#define SQ_ESGS_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_GSVS_RING_ITEMSIZE 0x000288ac +#define SQ_GSVS_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_ESTMP_RING_ITEMSIZE 0x000288b0 +#define SQ_ESTMP_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_GSTMP_RING_ITEMSIZE 0x000288b4 +#define SQ_GSTMP_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_VSTMP_RING_ITEMSIZE 0x000288b8 +#define SQ_VSTMP_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_PSTMP_RING_ITEMSIZE 0x000288bc +#define SQ_PSTMP_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_FBUF_RING_ITEMSIZE 0x000288c0 +#define SQ_FBUF_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_REDUC_RING_ITEMSIZE 0x000288c4 +#define SQ_REDUC_RING_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_GS_VERT_ITEMSIZE 0x000288c8 +#define SQ_GS_VERT_ITEMSIZE__ITEMSIZE(x) (((x) & 0x00007fff) << 0) +#define SQ_PGM_CF_OFFSET_PS 0x000288cc +#define SQ_PGM_CF_OFFSET_PS__PGM_CF_OFFSET(x) (((x) & 0x000fffff) << 0) +#define SQ_PGM_CF_OFFSET_VS 0x000288d0 +#define SQ_PGM_CF_OFFSET_VS__PGM_CF_OFFSET(x) (((x) & 0x000fffff) << 0) +#define SQ_PGM_CF_OFFSET_GS 0x000288d4 +#define SQ_PGM_CF_OFFSET_GS__PGM_CF_OFFSET(x) (((x) & 0x000fffff) << 0) +#define SQ_PGM_CF_OFFSET_ES 0x000288d8 +#define SQ_PGM_CF_OFFSET_ES__PGM_CF_OFFSET(x) (((x) & 0x000fffff) << 0) +#define SQ_PGM_CF_OFFSET_FS 0x000288dc +#define SQ_PGM_CF_OFFSET_FS__PGM_CF_OFFSET(x) (((x) & 0x000fffff) << 0) +#define SQ_VTX_SEMANTIC_CLEAR 0x000288e0 +#define SQ_ALU_CONST_CACHE_PS_0 0x00028940 +#define SQ_ALU_CONST_CACHE_VS_0 0x00028980 +#define SQ_ALU_CONST_CACHE_GS_0 0x000289c0 +#define PA_SU_POINT_SIZE 0x00028a00 +#define PA_SU_POINT_SIZE__HEIGHT(x) (((x) & 0x0000ffff) << 0) +#define PA_SU_POINT_SIZE__WIDTH(x) (((x) & 0x0000ffff) << 16) +#define PA_SU_POINT_MINMAX 0x00028a04 +#define PA_SU_POINT_MINMAX__MIN_SIZE(x) (((x) & 0x0000ffff) << 0) +#define PA_SU_POINT_MINMAX__MAX_SIZE(x) (((x) & 0x0000ffff) << 16) +#define PA_SU_LINE_CNTL 0x00028a08 +#define PA_SU_LINE_CNTL__WIDTH(x) (((x) & 0x0000ffff) << 0) +#define PA_SC_LINE_STIPPLE 0x00028a0c +#define PA_SC_LINE_STIPPLE__LINE_PATTERN(x) (((x) & 0x0000ffff) << 0) +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT(x) (((x) & 0x000000ff) << 16) +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER(x) (((x) & 0x00000001) << 28) +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL(x) (((x) & 0x00000003) << 29) +#define VGT_OUTPUT_PATH_CNTL 0x00028a10 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT(x) (((x) & 0x00000003) << 0) +#define VGT_OUTPATH_VTX_REUSE 0 +#define VGT_OUTPATH_TESS_EN 1 +#define VGT_OUTPATH_PASSTHRU 2 +#define VGT_OUTPATH_GS_BLOCK 3 +#define VGT_HOS_CNTL 0x00028a14 +#define VGT_HOS_CNTL__TESS_MODE(x) (((x) & 0x00000003) << 0) +#define VGT_HOS_MAX_TESS_LEVEL 0x00028a18 +#define VGT_HOS_MIN_TESS_LEVEL 0x00028a1c +#define VGT_HOS_REUSE_DEPTH 0x00028a20 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH(x) (((x) & 0x000000ff) << 0) +#define VGT_GROUP_PRIM_TYPE 0x00028a24 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE(x) (((x) & 0x0000001f) << 0) +#define VGT_GRP_3D_POINT 0 +#define VGT_GRP_3D_LINE 1 +#define VGT_GRP_3D_TRI 2 +#define VGT_GRP_3D_RECT 3 +#define VGT_GRP_3D_QUAD 4 +#define VGT_GRP_2D_COPY_RECT_V0 5 +#define VGT_GRP_2D_COPY_RECT_V1 6 +#define VGT_GRP_2D_COPY_RECT_V2 7 +#define VGT_GRP_2D_COPY_RECT_V3 8 +#define VGT_GRP_2D_FILL_RECT 9 +#define VGT_GRP_2D_LINE 10 +#define VGT_GRP_2D_TRI 11 +#define VGT_GRP_PRIM_INDEX_LINE 12 +#define VGT_GRP_PRIM_INDEX_TRI 13 +#define VGT_GRP_PRIM_INDEX_QUAD 14 +#define VGT_GRP_3D_LINE_ADJ 15 +#define VGT_GRP_3D_TRI_ADJ 16 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER(x) (((x) & 0x00000001) << 14) +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS(x) (((x) & 0x00000001) << 15) +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER(x) (((x) & 0x00000007) << 16) +#define VGT_GRP_LIST 0 +#define VGT_GRP_STRIP 1 +#define VGT_GRP_FAN 2 +#define VGT_GRP_LOOP 3 +#define VGT_GRP_POLYGON 4 +#define VGT_GROUP_FIRST_DECR 0x00028a28 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR(x) (((x) & 0x0000000f) << 0) +#define VGT_GROUP_DECR 0x00028a2c +#define VGT_GROUP_DECR__DECR(x) (((x) & 0x0000000f) << 0) +#define VGT_GROUP_VECT_0_CNTL 0x00028a30 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN(x) (((x) & 0x00000001) << 0) +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN(x) (((x) & 0x00000001) << 1) +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN(x) (((x) & 0x00000001) << 2) +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN(x) (((x) & 0x00000001) << 3) +#define VGT_GROUP_VECT_0_CNTL__STRIDE(x) (((x) & 0x000000ff) << 8) +#define VGT_GROUP_VECT_0_CNTL__SHIFT(x) (((x) & 0x000000ff) << 16) +#define VGT_GROUP_VECT_1_CNTL 0x00028a34 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN(x) (((x) & 0x00000001) << 0) +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN(x) (((x) & 0x00000001) << 1) +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN(x) (((x) & 0x00000001) << 2) +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN(x) (((x) & 0x00000001) << 3) +#define VGT_GROUP_VECT_1_CNTL__STRIDE(x) (((x) & 0x000000ff) << 8) +#define VGT_GROUP_VECT_1_CNTL__SHIFT(x) (((x) & 0x000000ff) << 16) +#define VGT_GROUP_VECT_0_FMT_CNTL 0x00028a38 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV(x) (((x) & 0x0000000f) << 0) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET(x) (((x) & 0x0000000f) << 4) +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV(x) (((x) & 0x0000000f) << 8) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET(x) (((x) & 0x0000000f) << 12) +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV(x) (((x) & 0x0000000f) << 16) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET(x) (((x) & 0x0000000f) << 20) +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV(x) (((x) & 0x0000000f) << 24) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET(x) (((x) & 0x0000000f) << 28) +#define VGT_GROUP_VECT_1_FMT_CNTL 0x00028a3c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV(x) (((x) & 0x0000000f) << 0) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET(x) (((x) & 0x0000000f) << 4) +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV(x) (((x) & 0x0000000f) << 8) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET(x) (((x) & 0x0000000f) << 12) +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV(x) (((x) & 0x0000000f) << 16) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET(x) (((x) & 0x0000000f) << 20) +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV(x) (((x) & 0x0000000f) << 24) +#define VGT_GRP_INDEX_16 0 +#define VGT_GRP_INDEX_32 1 +#define VGT_GRP_UINT_16 2 +#define VGT_GRP_UINT_32 3 +#define VGT_GRP_SINT_16 4 +#define VGT_GRP_SINT_32 5 +#define VGT_GRP_FLOAT_32 6 +#define VGT_GRP_AUTO_PRIM 7 +#define VGT_GRP_FIX_1_23_TO_FLOAT 8 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET(x) (((x) & 0x0000000f) << 28) +#define VGT_GS_MODE 0x00028a40 +#define VGT_GS_MODE__MODE(x) (((x) & 0x00000003) << 0) +#define GS_OFF 0 +#define GS_SCENARIO_A 1 +#define GS_SCENARIO_B 2 +#define GS_SCENARIO_G 3 +#define VGT_GS_MODE__ES_PASSTHRU(x) (((x) & 0x00000001) << 2) +#define VGT_GS_MODE__CUT_MODE(x) (((x) & 0x00000003) << 3) +#define GS_CUT_1024 0 +#define GS_CUT_512 1 +#define GS_CUT_256 2 +#define GS_CUT_128 3 +#define PA_SC_MPASS_PS_CNTL 0x00028a48 +#define PA_SC_MPASS_PS_CNTL__MPASS_PIX_VEC_PER_PASS(x) (((x) & 0x000fffff) << 0) +#define PA_SC_MPASS_PS_CNTL__MPASS_PS_ENA(x) (((x) & 0x00000001) << 31) +#define PA_SC_MODE_CNTL 0x00028a4c +#define PA_SC_MODE_CNTL__MSAA_ENABLE(x) (((x) & 0x00000001) << 0) +#define PA_SC_MODE_CNTL__CLIPRECT_ENABLE(x) (((x) & 0x00000001) << 1) +#define PA_SC_MODE_CNTL__LINE_STIPPLE_ENABLE(x) (((x) & 0x00000001) << 2) +#define PA_SC_MODE_CNTL__MULTI_CHIP_PRIM_DISCARD_ENAB(x) (((x) & 0x00000001) << 3) +#define PA_SC_MODE_CNTL__WALK_ORDER_ENABLE(x) (((x) & 0x00000001) << 4) +#define PA_SC_MODE_CNTL__HALVE_DETAIL_SAMPLE_PERF(x) (((x) & 0x00000001) << 5) +#define PA_SC_MODE_CNTL__WALK_SIZE(x) (((x) & 0x00000001) << 6) +#define PA_SC_MODE_CNTL__WALK_ALIGNMENT(x) (((x) & 0x00000001) << 7) +#define PA_SC_MODE_CNTL__WALK_ALIGN8_PRIM_FITS_ST(x) (((x) & 0x00000001) << 8) +#define PA_SC_MODE_CNTL__TILE_COVER_NO_SCISSOR(x) (((x) & 0x00000001) << 9) +#define PA_SC_MODE_CNTL__KILL_PIX_POST_HI_Z(x) (((x) & 0x00000001) << 10) +#define PA_SC_MODE_CNTL__KILL_PIX_POST_DETAIL_MASK(x) (((x) & 0x00000001) << 11) +#define PA_SC_MODE_CNTL__MULTI_CHIP_SUPERTILE_ENABLE(x) (((x) & 0x00000001) << 12) +#define PA_SC_MODE_CNTL__TILE_COVER_DISABLE(x) (((x) & 0x00000001) << 13) +#define PA_SC_MODE_CNTL__FORCE_EOV_CNTDWN_ENABLE(x) (((x) & 0x00000001) << 14) +#define PA_SC_MODE_CNTL__FORCE_EOV_TILE_ENABLE(x) (((x) & 0x00000001) << 15) +#define PA_SC_MODE_CNTL__FORCE_EOV_REZ_ENABLE(x) (((x) & 0x00000001) << 16) +#define PA_SC_MODE_CNTL__PS_ITER_SAMPLE(x) (((x) & 0x00000001) << 17) +#define VGT_ENHANCE 0x00028a50 +#define VGT_ENHANCE__MI_TIMESTAMP_RES(x) (((x) & 0x00000003) << 0) +#define X_0_992_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_32 0 +#define X_0_496_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_16 1 +#define X_0_248_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_8 2 +#define X_0_124_CLOCKS_LATENCY_RANGE_IN_STEPS_OF_4 3 +#define VGT_ENHANCE__MISC(x) (((x) & 0x3fffffff) << 2) +#define VGT_GS_OUT_PRIM_TYPE 0x00028a6c +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE(x) (((x) & 0x0000003f) << 0) +#define POINTLIST 0 +#define LINESTRIP 1 +#define TRISTRIP 2 +#define VGT_DMA_SIZE 0x00028a74 +#define VGT_DMA_INDEX_TYPE 0x00028a7c +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE(x) (((x) & 0x00000003) << 0) +#define VGT_INDEX_16 0 +#define VGT_INDEX_32 1 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE(x) (((x) & 0x00000003) << 2) +#define VGT_DMA_SWAP_NONE 0 +#define VGT_DMA_SWAP_16_BIT 1 +#define VGT_DMA_SWAP_32_BIT 2 +#define VGT_DMA_SWAP_WORD 3 +#define VGT_PRIMITIVEID_EN 0x00028a84 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN(x) (((x) & 0x00000001) << 0) +#define VGT_DMA_NUM_INSTANCES 0x00028a88 +#define VGT_EVENT_INITIATOR 0x00028a90 +#define VGT_EVENT_INITIATOR__EVENT_TYPE(x) (((x) & 0x0000003f) << 0) +#define CACHE_FLUSH_TS 4 +#define CONTEXT_DONE 5 +#define CACHE_FLUSH 6 +#define VIZQUERY_START 7 +#define VIZQUERY_END 8 +#define SC_WAIT_WC 9 +#define MPASS_PS_CP_REFETCH 10 +#define MPASS_PS_RST_START 11 +#define MPASS_PS_INCR_START 12 +#define RST_PIX_CNT 13 +#define RST_VTX_CNT 14 +#define VS_PARTIAL_FLUSH 15 +#define PS_PARTIAL_FLUSH 16 +#define CACHE_FLUSH_AND_INV_TS_EVENT 20 +#define ZPASS_DONE 21 +#define CACHE_FLUSH_AND_INV_EVENT 22 +#define PERFCOUNTER_START 23 +#define PERFCOUNTER_STOP 24 +#define PIPELINESTAT_START 25 +#define PIPELINESTAT_STOP 26 +#define PERFCOUNTER_SAMPLE 27 +#define FLUSH_ES_OUTPUT 28 +#define FLUSH_GS_OUTPUT 29 +#define SAMPLE_PIPELINESTAT 30 +#define SO_VGTSTREAMOUT_FLUSH 31 +#define SAMPLE_STREAMOUTSTATS 32 +#define RESET_VTX_CNT 33 +#define BLOCK_CONTEXT_DONE 34 +#define CR_CONTEXT_DONE 35 +#define VGT_FLUSH 36 +#define CR_DONE_TS 37 +#define SQ_NON_EVENT 38 +#define SC_SEND_DB_VPZ 39 +#define BOTTOM_OF_PIPE_TS 40 +#define DB_CACHE_FLUSH_AND_INV 42 +#define VGT_EVENT_INITIATOR__ADDRESS_HI(x) (((x) & 0x000000ff) << 19) +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT(x) (((x) & 0x00000001) << 27) +#define VGT_MULTI_PRIM_IB_RESET_EN 0x00028a94 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN(x) (((x) & 0x00000001) << 0) +#define VGT_INSTANCE_STEP_RATE_0 0x00028aa0 +#define VGT_INSTANCE_STEP_RATE_1 0x00028aa4 +#define VGT_STRMOUT_EN 0x00028ab0 +#define VGT_STRMOUT_EN__STREAMOUT(x) (((x) & 0x00000001) << 0) +#define VGT_REUSE_OFF 0x00028ab4 +#define VGT_REUSE_OFF__REUSE_OFF(x) (((x) & 0x00000001) << 0) +#define VGT_VTX_CNT_EN 0x00028ab8 +#define VGT_VTX_CNT_EN__VTX_CNT_EN(x) (((x) & 0x00000001) << 0) +#define VGT_STRMOUT_BUFFER_SIZE_0 0x00028ad0 +#define VGT_STRMOUT_VTX_STRIDE_0 0x00028ad4 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE(x) (((x) & 0x000003ff) << 0) +#define VGT_STRMOUT_BUFFER_BASE_0 0x00028ad8 +#define VGT_STRMOUT_BUFFER_OFFSET_0 0x00028adc +#define VGT_STRMOUT_BUFFER_SIZE_1 0x00028ae0 +#define VGT_STRMOUT_VTX_STRIDE_1 0x00028ae4 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE(x) (((x) & 0x000003ff) << 0) +#define VGT_STRMOUT_BUFFER_BASE_1 0x00028ae8 +#define VGT_STRMOUT_BUFFER_OFFSET_1 0x00028aec +#define VGT_STRMOUT_BUFFER_SIZE_2 0x00028af0 +#define VGT_STRMOUT_VTX_STRIDE_2 0x00028af4 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE(x) (((x) & 0x000003ff) << 0) +#define VGT_STRMOUT_BUFFER_BASE_2 0x00028af8 +#define VGT_STRMOUT_BUFFER_OFFSET_2 0x00028afc +#define VGT_STRMOUT_BUFFER_SIZE_3 0x00028b00 +#define VGT_STRMOUT_VTX_STRIDE_3 0x00028b04 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE(x) (((x) & 0x000003ff) << 0) +#define VGT_STRMOUT_BUFFER_BASE_3 0x00028b08 +#define VGT_STRMOUT_BUFFER_OFFSET_3 0x00028b0c +#define VGT_STRMOUT_BASE_OFFSET_0 0x00028b10 +#define VGT_STRMOUT_BASE_OFFSET_1 0x00028b14 +#define VGT_STRMOUT_BASE_OFFSET_2 0x00028b18 +#define VGT_STRMOUT_BASE_OFFSET_3 0x00028b1c +#define VGT_STRMOUT_BUFFER_EN 0x00028b20 +#define VGT_STRMOUT_BUFFER_EN__BUFFER_0_EN(x) (((x) & 0x00000001) << 0) +#define VGT_STRMOUT_BUFFER_EN__BUFFER_1_EN(x) (((x) & 0x00000001) << 1) +#define VGT_STRMOUT_BUFFER_EN__BUFFER_2_EN(x) (((x) & 0x00000001) << 2) +#define VGT_STRMOUT_BUFFER_EN__BUFFER_3_EN(x) (((x) & 0x00000001) << 3) +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x00028b28 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x00028b2c +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x00028b30 +#define VGT_STRMOUT_BASE_OFFSET_HI_0 0x00028b44 +#define VGT_STRMOUT_BASE_OFFSET_HI_0__BASE_OFFSET(x) (((x) & 0x0000003f) << 0) +#define VGT_STRMOUT_BASE_OFFSET_HI_1 0x00028b48 +#define VGT_STRMOUT_BASE_OFFSET_HI_1__BASE_OFFSET(x) (((x) & 0x0000003f) << 0) +#define VGT_STRMOUT_BASE_OFFSET_HI_2 0x00028b4c +#define VGT_STRMOUT_BASE_OFFSET_HI_2__BASE_OFFSET(x) (((x) & 0x0000003f) << 0) +#define VGT_STRMOUT_BASE_OFFSET_HI_3 0x00028b50 +#define VGT_STRMOUT_BASE_OFFSET_HI_3__BASE_OFFSET(x) (((x) & 0x0000003f) << 0) +#define PA_SC_LINE_CNTL 0x00028c00 +#define PA_SC_LINE_CNTL__BRES_CNTL(x) (((x) & 0x000000ff) << 0) +#define PA_SC_LINE_CNTL__USE_BRES_CNTL(x) (((x) & 0x00000001) << 8) +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH(x) (((x) & 0x00000001) << 9) +#define PA_SC_LINE_CNTL__LAST_PIXEL(x) (((x) & 0x00000001) << 10) +#define PA_SC_AA_CONFIG 0x00028c04 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES(x) (((x) & 0x00000003) << 0) +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN(x) (((x) & 0x00000001) << 4) +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST(x) (((x) & 0x0000000f) << 13) +#define PA_SU_VTX_CNTL 0x00028c08 +#define PA_SU_VTX_CNTL__PIX_CENTER(x) (((x) & 0x00000001) << 0) +#define PA_SU_VTX_CNTL__ROUND_MODE(x) (((x) & 0x00000003) << 1) +#define X_TRUNCATE 0 +#define X_ROUND 1 +#define X_ROUND_TO_EVEN 2 +#define X_ROUND_TO_ODD 3 +#define PA_SU_VTX_CNTL__QUANT_MODE(x) (((x) & 0x00000007) << 3) +#define X_1_16TH 0 +#define X_1_8TH 1 +#define X_1_4TH 2 +#define X_1_2 3 +#define X_1 4 +#define X_1_256TH 5 +#define PA_CL_GB_VERT_CLIP_ADJ 0x00028c0c +#define PA_CL_GB_VERT_DISC_ADJ 0x00028c10 +#define PA_CL_GB_HORZ_CLIP_ADJ 0x00028c14 +#define PA_CL_GB_HORZ_DISC_ADJ 0x00028c18 +#define PA_SC_AA_SAMPLE_LOCS_MCTX 0x00028c1c +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S0_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S0_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S1_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S1_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S2_X(x) (((x) & 0x0000000f) << 16) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S2_Y(x) (((x) & 0x0000000f) << 20) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S3_X(x) (((x) & 0x0000000f) << 24) +#define PA_SC_AA_SAMPLE_LOCS_MCTX__S3_Y(x) (((x) & 0x0000000f) << 28) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX 0x00028c20 +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S4_X(x) (((x) & 0x0000000f) << 0) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S4_Y(x) (((x) & 0x0000000f) << 4) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S5_X(x) (((x) & 0x0000000f) << 8) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S5_Y(x) (((x) & 0x0000000f) << 12) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S6_X(x) (((x) & 0x0000000f) << 16) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S6_Y(x) (((x) & 0x0000000f) << 20) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S7_X(x) (((x) & 0x0000000f) << 24) +#define PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX__S7_Y(x) (((x) & 0x0000000f) << 28) +#define CB_CLRCMP_CONTROL 0x00028c30 +#define CB_CLRCMP_CONTROL__CLRCMP_FCN_SRC(x) (((x) & 0x00000007) << 0) +#define CLRCMP_DRAW_ALWAYS 0 +#define CLRCMP_DRAW_NEVER 1 +#define CLRCMP_DRAW_ON_NEQ 4 +#define CLRCMP_DRAW_ON_EQ 5 +#define CB_CLRCMP_CONTROL__CLRCMP_FCN_DST(x) (((x) & 0x00000007) << 8) +#define CLRCMP_DRAW_ALWAYS 0 +#define CLRCMP_DRAW_NEVER 1 +#define CLRCMP_DRAW_ON_NEQ 4 +#define CLRCMP_DRAW_ON_EQ 5 +#define CB_CLRCMP_CONTROL__CLRCMP_FCN_SEL(x) (((x) & 0x00000003) << 24) +#define CLRCMP_SEL_DST 0 +#define CLRCMP_SEL_SRC 1 +#define CLRCMP_SEL_AND 2 +#define CB_CLRCMP_SRC 0x00028c34 +#define CB_CLRCMP_DST 0x00028c38 +#define CB_CLRCMP_MSK 0x00028c3c +#define PA_SC_AA_MASK 0x00028c48 +#define VGT_VERTEX_REUSE_BLOCK_CNTL 0x00028c58 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH(x) (((x) & 0x000000ff) << 0) +#define VGT_OUT_DEALLOC_CNTL 0x00028c5c +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST(x) (((x) & 0x0000007f) << 0) +#define DB_RENDER_CONTROL 0x00028d0c +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE(x) (((x) & 0x00000001) << 0) +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE(x) (((x) & 0x00000001) << 1) +#define DB_RENDER_CONTROL__DEPTH_COPY(x) (((x) & 0x00000001) << 2) +#define DB_RENDER_CONTROL__STENCIL_COPY(x) (((x) & 0x00000001) << 3) +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE(x) (((x) & 0x00000001) << 4) +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE(x) (((x) & 0x00000001) << 5) +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE(x) (((x) & 0x00000001) << 6) +#define DB_RENDER_CONTROL__COPY_CENTROID(x) (((x) & 0x00000001) << 7) +#define DB_RENDER_CONTROL__COPY_SAMPLE(x) (((x) & 0x00000007) << 8) +#define DB_RENDER_CONTROL__ZPASS_INCREMENT_DISABLE(x) (((x) & 0x00000001) << 11) +#define DB_RENDER_OVERRIDE 0x00028d10 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE(x) (((x) & 0x00000003) << 0) +#define FORCE_OFF 0 +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define FORCE_RESERVED 3 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0(x) (((x) & 0x00000003) << 2) +#define FORCE_OFF 0 +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define FORCE_RESERVED 3 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1(x) (((x) & 0x00000003) << 4) +#define FORCE_OFF 0 +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define FORCE_RESERVED 3 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER(x) (((x) & 0x00000001) << 6) +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE(x) (((x) & 0x00000001) << 7) +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE(x) (((x) & 0x00000001) << 8) +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE(x) (((x) & 0x00000001) << 9) +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL(x) (((x) & 0x00000001) << 10) +#define DB_RENDER_OVERRIDE__FORCE_Z_READ(x) (((x) & 0x00000001) << 11) +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ(x) (((x) & 0x00000001) << 12) +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE(x) (((x) & 0x00000003) << 13) +#define FORCE_OFF 0 +#define FORCE_ENABLE 1 +#define FORCE_DISABLE 2 +#define FORCE_RESERVED 3 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT(x) (((x) & 0x00000001) << 15) +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP(x) (((x) & 0x00000001) << 16) +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE(x) (((x) & 0x00000001) << 17) +#define DB_HTILE_SURFACE 0x00028d24 +#define DB_HTILE_SURFACE__HTILE_WIDTH(x) (((x) & 0x00000001) << 0) +#define DB_HTILE_SURFACE__HTILE_HEIGHT(x) (((x) & 0x00000001) << 1) +#define DB_HTILE_SURFACE__LINEAR(x) (((x) & 0x00000001) << 2) +#define DB_HTILE_SURFACE__FULL_CACHE(x) (((x) & 0x00000001) << 3) +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN(x) (((x) & 0x00000001) << 4) +#define DB_HTILE_SURFACE__PRELOAD(x) (((x) & 0x00000001) << 5) +#define DB_HTILE_SURFACE__PREFETCH_WIDTH(x) (((x) & 0x0000003f) << 6) +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT(x) (((x) & 0x0000003f) << 12) +#define DB_SRESULTS_COMPARE_STATE0 0x00028d28 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0(x) (((x) & 0x00000007) << 0) +#define REF_NEVER 0 +#define REF_LESS 1 +#define REF_EQUAL 2 +#define REF_LEQUAL 3 +#define REF_GREATER 4 +#define REF_NOTEQUAL 5 +#define REF_GEQUAL 6 +#define REF_ALWAYS 7 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0(x) (((x) & 0x000000ff) << 4) +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0(x) (((x) & 0x000000ff) << 12) +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0(x) (((x) & 0x00000001) << 24) +#define DB_SRESULTS_COMPARE_STATE1 0x00028d2c +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1(x) (((x) & 0x00000007) << 0) +#define REF_NEVER 0 +#define REF_LESS 1 +#define REF_EQUAL 2 +#define REF_LEQUAL 3 +#define REF_GREATER 4 +#define REF_NOTEQUAL 5 +#define REF_GEQUAL 6 +#define REF_ALWAYS 7 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1(x) (((x) & 0x000000ff) << 4) +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1(x) (((x) & 0x000000ff) << 12) +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1(x) (((x) & 0x00000001) << 24) +#define DB_PRELOAD_CONTROL 0x00028d30 +#define DB_PRELOAD_CONTROL__START_X(x) (((x) & 0x000000ff) << 0) +#define DB_PRELOAD_CONTROL__START_Y(x) (((x) & 0x000000ff) << 8) +#define DB_PRELOAD_CONTROL__MAX_X(x) (((x) & 0x000000ff) << 16) +#define DB_PRELOAD_CONTROL__MAX_Y(x) (((x) & 0x000000ff) << 24) +#define DB_PREFETCH_LIMIT 0x00028d34 +#define DB_PREFETCH_LIMIT__DEPTH_HEIGHT_TILE_MAX(x) (((x) & 0x000003ff) << 0) +#define DB_ALPHA_TO_MASK 0x00028d44 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0(x) (((x) & 0x00000003) << 8) +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1(x) (((x) & 0x00000003) << 10) +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2(x) (((x) & 0x00000003) << 12) +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3(x) (((x) & 0x00000003) << 14) +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL 0x00028df8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__NEG_NUM_DB_BITS(x) (((x) & 0x000000ff) << 0) +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__DB_IS_FLOAT_FMT(x) (((x) & 0x00000001) << 8) +#define PA_SU_POLY_OFFSET_CLAMP 0x00028dfc +#define PA_SU_POLY_OFFSET_FRONT_SCALE 0x00028e00 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00028e04 +#define PA_SU_POLY_OFFSET_BACK_SCALE 0x00028e08 +#define PA_SU_POLY_OFFSET_BACK_OFFSET 0x00028e0c +#define PA_CL_POINT_X_RAD 0x00028e10 +#define PA_CL_POINT_Y_RAD 0x00028e14 +#define PA_CL_POINT_SIZE 0x00028e18 +#define PA_CL_POINT_CULL_RAD 0x00028e1c +#define PA_CL_UCP_0_X 0x00028e20 +#define PA_CL_UCP_0_Y 0x00028e24 +#define PA_CL_UCP_0_Z 0x00028e28 + + +/***************************************************************************** + * SET_ALU_CONST [0x00030000 0x00032000] + */ +#define SQ_ALU_CONSTANT0_0 0x00030000 +#define SQ_ALU_CONSTANT1_0 0x00030004 +#define SQ_ALU_CONSTANT2_0 0x00030008 +#define SQ_ALU_CONSTANT3_0 0x0003000c + + +/***************************************************************************** + * SET_RESOURCE [0x00038000 0x0003c000] + */ +/* TEX */ +#define SQ_TEX_RESOURCE_WORD0_0 0x00038000 +#define SQ_TEX_RESOURCE_WORD0_0__DIM(x) (((x) & 0x00000007) << 0) +#define SQ_TEX_DIM_1D 0 +#define SQ_TEX_DIM_2D 1 +#define SQ_TEX_DIM_3D 2 +#define SQ_TEX_DIM_CUBEMAP 3 +#define SQ_TEX_DIM_1D_ARRAY 4 +#define SQ_TEX_DIM_2D_ARRAY 5 +#define SQ_TEX_DIM_2D_MSAA 6 +#define SQ_TEX_DIM_2D_ARRAY_MSAA 7 +#define SQ_TEX_RESOURCE_WORD0_0__TILE_MODE(x) (((x) & 0x0000000f) << 3) +#define SQ_TEX_RESOURCE_WORD0_0__TILE_TYPE(x) (((x) & 0x00000001) << 7) +#define SQ_TEX_RESOURCE_WORD0_0__PITCH(x) (((x) & 0x000007ff) << 8) +#define SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH(x) (((x) & 0x00001fff) << 19) +#define SQ_TEX_RESOURCE_WORD1_0 0x00038004 +#define SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT(x) (((x) & 0x00001fff) << 0) +#define SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH(x) (((x) & 0x00001fff) << 13) +#define SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT(x) (((x) & 0x0000003f) << 26) +#define SQ_TEX_RESOURCE_WORD2_0 0x00038008 +#define SQ_TEX_RESOURCE_WORD3_0 0x0003800c +#define SQ_TEX_RESOURCE_WORD4_0 0x00038010 +#define SQ_TEX_RESOURCE_WORD4_0__FORMAT_COMP_X(x) (((x) & 0x00000003) << 0) +#define SQ_FORMAT_COMP_UNSIGNED 0 +#define SQ_FORMAT_COMP_SIGNED 1 +#define SQ_FORMAT_COMP_UNSIGNED_BIASED 2 +#define SQ_TEX_RESOURCE_WORD4_0__FORMAT_COMP_Y(x) (((x) & 0x00000003) << 2) +#define SQ_FORMAT_COMP_UNSIGNED 0 +#define SQ_FORMAT_COMP_SIGNED 1 +#define SQ_FORMAT_COMP_UNSIGNED_BIASED 2 +#define SQ_TEX_RESOURCE_WORD4_0__FORMAT_COMP_Z(x) (((x) & 0x00000003) << 4) +#define SQ_FORMAT_COMP_UNSIGNED 0 +#define SQ_FORMAT_COMP_SIGNED 1 +#define SQ_FORMAT_COMP_UNSIGNED_BIASED 2 +#define SQ_TEX_RESOURCE_WORD4_0__FORMAT_COMP_W(x) (((x) & 0x00000003) << 6) +#define SQ_FORMAT_COMP_UNSIGNED 0 +#define SQ_FORMAT_COMP_SIGNED 1 +#define SQ_FORMAT_COMP_UNSIGNED_BIASED 2 +#define SQ_TEX_RESOURCE_WORD4_0__NUM_FORMAT_ALL(x) (((x) & 0x00000003) << 8) +#define SQ_NUM_FORMAT_NORM 0 +#define SQ_NUM_FORMAT_INT 1 +#define SQ_NUM_FORMAT_SCALED 2 +#define SQ_TEX_RESOURCE_WORD4_0__SRF_MODE_ALL(x) (((x) & 0x00000001) << 10) +#define SQ_TEX_RESOURCE_WORD4_0__FORCE_DEGAMMA(x) (((x) & 0x00000001) << 11) +#define SQ_TEX_RESOURCE_WORD4_0__ENDIAN_SWAP(x) (((x) & 0x00000003) << 12) +#define SQ_ENDIAN_NONE 0 +#define SQ_ENDIAN_8IN16 1 +#define SQ_ENDIAN_8IN32 2 +#define SQ_TEX_RESOURCE_WORD4_0__REQUEST_SIZE(x) (((x) & 0x00000003) << 14) +#define SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X(x) (((x) & 0x00000007) << 16) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y(x) (((x) & 0x00000007) << 19) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z(x) (((x) & 0x00000007) << 22) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W(x) (((x) & 0x00000007) << 25) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_RESOURCE_WORD4_0__BASE_LEVEL(x) (((x) & 0x0000000f) << 28) +#define SQ_TEX_RESOURCE_WORD5_0 0x00038014 +#define SQ_TEX_RESOURCE_WORD5_0__LAST_LEVEL(x) (((x) & 0x0000000f) << 0) +#define SQ_TEX_RESOURCE_WORD5_0__BASE_ARRAY(x) (((x) & 0x00001fff) << 4) +#define SQ_TEX_RESOURCE_WORD5_0__LAST_ARRAY(x) (((x) & 0x00001fff) << 17) +#define SQ_TEX_RESOURCE_WORD6_0 0x00038018 +#define SQ_TEX_RESOURCE_WORD6_0__MPEG_CLAMP(x) (((x) & 0x00000003) << 0) +#define SQ_TEX_MPEG_CLAMP_OFF 0 +#define SQ_TEX_MPEG_9 1 +#define SQ_TEX_MPEG_10 2 +#define SQ_TEX_RESOURCE_WORD6_0__PERF_MODULATION(x) (((x) & 0x00000007) << 5) +#define SQ_TEX_RESOURCE_WORD6_0__INTERLACED(x) (((x) & 0x00000001) << 8) +#define SQ_TEX_RESOURCE_WORD6_0__TYPE(x) (((x) & 0x00000003) << 30) +#define SQ_TEX_VTX_INVALID_TEXTURE 0 +#define SQ_TEX_VTX_INVALID_BUFFER 1 +#define SQ_TEX_VTX_VALID_TEXTURE 2 +#define SQ_TEX_VTX_VALID_BUFFER 3 +/* VTX */ +#define SQ_VTX_CONSTANT_WORD0_0 0x00038000 +#define SQ_VTX_CONSTANT_WORD1_0 0x00038004 +#define SQ_VTX_CONSTANT_WORD2_0 0x00038008 +#define SQ_VTX_CONSTANT_WORD2_0__BASE_ADDRESS_HI(x) (((x) & 0x000000ff) << 0) +#define SQ_VTX_CONSTANT_WORD2_0__STRIDE(x) (((x) & 0x000007ff) << 8) +#define SQ_VTX_CONSTANT_WORD2_0__CLAMP_X(x) (((x) & 0x00000001) << 19) +#define SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT(x) (((x) & 0x0000003f) << 20) +#define SQ_VTX_CONSTANT_WORD2_0__NUM_FORMAT_ALL(x) (((x) & 0x00000003) << 26) +#define SQ_NUM_FORMAT_NORM 0 +#define SQ_NUM_FORMAT_INT 1 +#define SQ_NUM_FORMAT_SCALED 2 +#define SQ_VTX_CONSTANT_WORD2_0__FORMAT_COMP_ALL(x) (((x) & 0x00000001) << 28) +#define SQ_VTX_CONSTANT_WORD2_0__SRF_MODE_ALL(x) (((x) & 0x00000001) << 29) +#define SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP(x) (((x) & 0x00000003) << 30) +#define SQ_ENDIAN_NONE 0 +#define SQ_ENDIAN_8IN16 1 +#define SQ_ENDIAN_8IN32 2 +#define SQ_VTX_CONSTANT_WORD3_0 0x0003800c +#define SQ_VTX_CONSTANT_WORD3_0__MEM_REQUEST_SIZE(x) (((x) & 0x00000003) << 0) +#define SQ_VTX_CONSTANT_WORD6_0 0x00038018 +#define SQ_VTX_CONSTANT_WORD6_0__TYPE(x) (((x) & 0x00000003) << 30) +#define SQ_TEX_VTX_INVALID_TEXTURE 0 +#define SQ_TEX_VTX_INVALID_BUFFER 1 +#define SQ_TEX_VTX_VALID_TEXTURE 2 +#define SQ_TEX_VTX_VALID_BUFFER 3 + + +/***************************************************************************** + * SET_SAMPLER [0x0003c000 0x0003cff0] + */ +#define SQ_TEX_SAMPLER_WORD0_0 0x0003c000 +#define SQ_TEX_SAMPLER_WORD0_0__CLAMP_X(x) (((x) & 0x00000007) << 0) +#define SQ_TEX_WRAP 0 +#define SQ_TEX_MIRROR 1 +#define SQ_TEX_CLAMP_LAST_TEXEL 2 +#define SQ_TEX_MIRROR_ONCE_LAST_TEXEL 3 +#define SQ_TEX_CLAMP_HALF_BORDER 4 +#define SQ_TEX_MIRROR_ONCE_HALF_BORDER 5 +#define SQ_TEX_CLAMP_BORDER 6 +#define SQ_TEX_MIRROR_ONCE_BORDER 7 +#define SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y(x) (((x) & 0x00000007) << 3) +#define SQ_TEX_WRAP 0 +#define SQ_TEX_MIRROR 1 +#define SQ_TEX_CLAMP_LAST_TEXEL 2 +#define SQ_TEX_MIRROR_ONCE_LAST_TEXEL 3 +#define SQ_TEX_CLAMP_HALF_BORDER 4 +#define SQ_TEX_MIRROR_ONCE_HALF_BORDER 5 +#define SQ_TEX_CLAMP_BORDER 6 +#define SQ_TEX_MIRROR_ONCE_BORDER 7 +#define SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z(x) (((x) & 0x00000007) << 6) +#define SQ_TEX_WRAP 0 +#define SQ_TEX_MIRROR 1 +#define SQ_TEX_CLAMP_LAST_TEXEL 2 +#define SQ_TEX_MIRROR_ONCE_LAST_TEXEL 3 +#define SQ_TEX_CLAMP_HALF_BORDER 4 +#define SQ_TEX_MIRROR_ONCE_HALF_BORDER 5 +#define SQ_TEX_CLAMP_BORDER 6 +#define SQ_TEX_MIRROR_ONCE_BORDER 7 +#define SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER(x) (((x) & 0x00000007) << 9) +#define SQ_TEX_XY_FILTER_POINT 0 +#define SQ_TEX_XY_FILTER_BILINEAR 1 +#define SQ_TEX_XY_FILTER_BICUBIC 2 +#define SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER(x) (((x) & 0x00000007) << 12) +#define SQ_TEX_XY_FILTER_POINT 0 +#define SQ_TEX_XY_FILTER_BILINEAR 1 +#define SQ_TEX_XY_FILTER_BICUBIC 2 +#define SQ_TEX_SAMPLER_WORD0_0__Z_FILTER(x) (((x) & 0x00000003) << 15) +#define SQ_TEX_Z_FILTER_NONE 0 +#define SQ_TEX_Z_FILTER_POINT 1 +#define SQ_TEX_Z_FILTER_LINEAR 2 +#define SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER(x) (((x) & 0x00000003) << 17) +#define SQ_TEX_Z_FILTER_NONE 0 +#define SQ_TEX_Z_FILTER_POINT 1 +#define SQ_TEX_Z_FILTER_LINEAR 2 +#define SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE(x) (((x) & 0x00000003) << 22) +#define SQ_TEX_BORDER_COLOR_TRANS_BLACK 0 +#define SQ_TEX_BORDER_COLOR_OPAQUE_BLACK 1 +#define SQ_TEX_BORDER_COLOR_OPAQUE_WHITE 2 +#define SQ_TEX_BORDER_COLOR_REGISTER 3 +#define SQ_TEX_SAMPLER_WORD0_0__POINT_SAMPLING_CLAMP(x) (((x) & 0x00000001) << 24) +#define SQ_TEX_SAMPLER_WORD0_0__TEX_ARRAY_OVERRIDE(x) (((x) & 0x00000001) << 25) +#define SQ_TEX_SAMPLER_WORD0_0__DEPTH_COMPARE_FUNCTION(x) (((x) & 0x00000007) << 26) +#define SQ_TEX_DEPTH_COMPARE_NEVER 0 +#define SQ_TEX_DEPTH_COMPARE_LESS 1 +#define SQ_TEX_DEPTH_COMPARE_EQUAL 2 +#define SQ_TEX_DEPTH_COMPARE_LESSEQUAL 3 +#define SQ_TEX_DEPTH_COMPARE_GREATER 4 +#define SQ_TEX_DEPTH_COMPARE_NOTEQUAL 5 +#define SQ_TEX_DEPTH_COMPARE_GREATEREQUAL 6 +#define SQ_TEX_DEPTH_COMPARE_ALWAYS 7 +#define SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY(x) (((x) & 0x00000003) << 29) +#define SQ_TEX_CHROMA_KEY_DISABLED 0 +#define SQ_TEX_CHROMA_KEY_KILL 1 +#define SQ_TEX_CHROMA_KEY_BLEND 2 +#define SQ_TEX_SAMPLER_WORD0_0__LOD_USES_MINOR_AXIS(x) (((x) & 0x00000001) << 31) +#define SQ_TEX_SAMPLER_WORD1_0 0x0003c004 +#define SQ_TEX_SAMPLER_WORD1_0__MIN_LOD(x) (((x) & 0x000003ff) << 0) +#define SQ_TEX_SAMPLER_WORD1_0__MAX_LOD(x) (((x) & 0x000003ff) << 10) +#define SQ_TEX_SAMPLER_WORD1_0__LOD_BIAS(x) (((x) & 0x00000fff) << 20) +#define SQ_TEX_SAMPLER_WORD2_0 0x0003c008 +#define SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC(x) (((x) & 0x00000fff) << 0) +#define SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE(x) (((x) & 0x00000001) << 12) +#define SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA(x) (((x) & 0x00000001) << 13) +#define SQ_TEX_SAMPLER_WORD2_0__HIGH_PRECISION_FILTER(x) (((x) & 0x00000001) << 14) +#define SQ_TEX_SAMPLER_WORD2_0__PERF_MIP(x) (((x) & 0x00000007) << 15) +#define SQ_TEX_SAMPLER_WORD2_0__PERF_Z(x) (((x) & 0x00000003) << 18) +#define SQ_TEX_SAMPLER_WORD2_0__FETCH_4(x) (((x) & 0x00000001) << 26) +#define SQ_TEX_SAMPLER_WORD2_0__SAMPLE_IS_PCF(x) (((x) & 0x00000001) << 27) +#define SQ_TEX_SAMPLER_WORD2_0__TYPE(x) (((x) & 0x00000001) << 31) + + +/***************************************************************************** + * SET_CTL_CONST [0x0003cff0 0x0003e200] + */ +#define SQ_VTX_BASE_VTX_LOC 0x0003cff0 +#define SQ_VTX_START_INST_LOC 0x0003cff4 + + +/***************************************************************************** + * SET_LOOP_CONST [0x0003e200 0x0003e380] + */ +#define SQ_LOOP_CONST_DX10_0 0x0003e200 +#define SQ_LOOP_CONST_0 0x0003e200 +#define SQ_LOOP_CONST_0__COUNT(x) (((x) & 0x00000fff) << 0) +#define SQ_LOOP_CONST_0__INIT(x) (((x) & 0x00000fff) << 12) +#define SQ_LOOP_CONST_0__INC(x) (((x) & 0x000000ff) << 24) + + +/***************************************************************************** + * SET_BOOL_CONST [0x0003e380 0x0003e38c] + */ +#define SQ_BOOL_CONST_0 0x0003e380 + + +/***************************************************************************** + * SHADER + */ +/* + * CF + */ +/* SQ_CF_WORD0 */ +#define SQ_CF_WORD0 0x00000000 +#define SQ_CF_WORD0__ADDR(x) (((x) & 0xffffffff) << 0) +/* SQ_CF_WORD1 */ +#define SQ_CF_WORD1 0x00000000 +#define SQ_CF_WORD1__POP_COUNT(x) (((x) & 0x00000007) << 0) +#define SQ_CF_WORD1__CF_CONST(x) (((x) & 0x0000001f) << 3) +#define SQ_CF_WORD1__COND(x) (((x) & 0x00000003) << 8) +#define SQ_CF_COND_ACTIVE 0 +#define SQ_CF_COND_FALSE 1 +#define SQ_CF_COND_BOOL 2 +#define SQ_CF_COND_NOT_BOOL 3 +#define SQ_CF_WORD1__COUNT(x) (((x) & 0x00000007) << 10) +#define SQ_CF_WORD1__CALL_COUNT(x) (((x) & 0x0000003f) << 13) +#define SQ_CF_WORD1__COUNT_3(x) (((x) & 0x00000001) << 19) +#define SQ_CF_WORD1__END_OF_PROGRAM(x) (((x) & 0x00000001) << 21) +#define SQ_CF_WORD1__VALID_PIXEL_MODE(x) (((x) & 0x00000001) << 22) +#define SQ_CF_WORD1__CF_INST(x) (((x) & 0x0000007f) << 23) +#define SQ_CF_INST_NOP 0 +#define SQ_CF_INST_TEX 1 +#define SQ_CF_INST_VTX 2 +#define SQ_CF_INST_VTX_TC 3 +#define SQ_CF_INST_LOOP_START 4 +#define SQ_CF_INST_LOOP_END 5 +#define SQ_CF_INST_LOOP_START_DX10 6 +#define SQ_CF_INST_LOOP_START_NO_AL 7 +#define SQ_CF_INST_LOOP_CONTINUE 8 +#define SQ_CF_INST_LOOP_BREAK 9 +#define SQ_CF_INST_JUMP 10 +#define SQ_CF_INST_PUSH 11 +#define SQ_CF_INST_PUSH_ELSE 12 +#define SQ_CF_INST_ELSE 13 +#define SQ_CF_INST_POP 14 +#define SQ_CF_INST_POP_JUMP 15 +#define SQ_CF_INST_POP_PUSH 16 +#define SQ_CF_INST_POP_PUSH_ELSE 17 +#define SQ_CF_INST_CALL 18 +#define SQ_CF_INST_CALL_FS 19 +#define SQ_CF_INST_RETURN 20 +#define SQ_CF_INST_EMIT_VERTEX 21 +#define SQ_CF_INST_EMIT_CUT_VERTEX 22 +#define SQ_CF_INST_CUT_VERTEX 23 +#define SQ_CF_INST_KILL 24 +#define SQ_CF_WORD1__WHOLE_QUAD_MODE(x) (((x) & 0x00000001) << 30) +#define SQ_CF_WORD1__BARRIER(x) (((x) & 0x00000001) << 31) +/* SQ_CF_ALU_WORD0 */ +#define SQ_CF_ALU_WORD0 0x00000000 +#define SQ_CF_ALU_WORD0__ADDR(x) (((x) & 0x003fffff) << 0) +#define SQ_CF_ALU_WORD0__KCACHE_BANK0(x) (((x) & 0x0000000f) << 22) +#define SQ_CF_ALU_WORD0__KCACHE_BANK1(x) (((x) & 0x0000000f) << 26) +#define SQ_CF_ALU_WORD0__KCACHE_MODE0(x) (((x) & 0x00000003) << 30) +#define SQ_CF_KCACHE_NOP 0 +#define SQ_CF_KCACHE_LOCK_1 1 +#define SQ_CF_KCACHE_LOCK_2 2 +#define SQ_CF_KCACHE_LOCK_LOOP_INDEX 3 +/* SQ_CF_ALU_WORD1 */ +#define SQ_CF_ALU_WORD1 0x00000000 +#define SQ_CF_ALU_WORD1__KCACHE_MODE1(x) (((x) & 0x00000003) << 0) +#define SQ_CF_KCACHE_NOP 0 +#define SQ_CF_KCACHE_LOCK_1 1 +#define SQ_CF_KCACHE_LOCK_2 2 +#define SQ_CF_KCACHE_LOCK_LOOP_INDEX 3 +#define SQ_CF_ALU_WORD1__KCACHE_ADDR0(x) (((x) & 0x000000ff) << 2) +#define SQ_CF_ALU_WORD1__KCACHE_ADDR1(x) (((x) & 0x000000ff) << 10) +#define SQ_CF_ALU_WORD1__COUNT(x) (((x) & 0x0000007f) << 18) +#define SQ_CF_ALU_WORD1__ALT_CONST(x) (((x) & 0x00000001) << 25) +#define SQ_CF_ALU_WORD1__CF_INST(x) (((x) & 0x0000000f) << 26) +#define SQ_CF_INST_ALU 8 +#define SQ_CF_INST_ALU_PUSH_BEFORE 9 +#define SQ_CF_INST_ALU_POP_AFTER 10 +#define SQ_CF_INST_ALU_POP2_AFTER 11 +#define SQ_CF_INST_ALU_CONTINUE 13 +#define SQ_CF_INST_ALU_BREAK 14 +#define SQ_CF_INST_ALU_ELSE_AFTER 15 +#define SQ_CF_ALU_WORD1__WHOLE_QUAD_MODE(x) (((x) & 0x00000001) << 30) +#define SQ_CF_ALU_WORD1__BARRIER(x) (((x) & 0x00000001) << 31) +/* SQ_CF_ALLOC_EXPORT_WORD0 */ +#define SQ_CF_ALLOC_EXPORT_WORD0 0x00000000 +#define SQ_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE(x) (((x) & 0x00001fff) << 0) +#define SQ_EXPORT_PARAM0 0 +#define SQ_EXPORT_PARAM31 31 +#define SQ_EXPORT_CB0 0 +#define SQ_EXPORT_CB1 1 +#define SQ_EXPORT_CB2 2 +#define SQ_EXPORT_CB3 3 +#define SQ_EXPORT_CB4 4 +#define SQ_EXPORT_CB5 5 +#define SQ_EXPORT_CB6 6 +#define SQ_EXPORT_CB7 7 +#define SQ_EXPORT_Z 61 +#define SQ_EXPORT_POS0 60 +#define SQ_EXPORT_POS1 61 +#define SQ_EXPORT_POS2 62 +#define SQ_EXPORT_POS3 63 +#define SQ_CF_ALLOC_EXPORT_WORD0__TYPE(x) (((x) & 0x00000003) << 13) +#define SQ_EXPORT_PIXEL 0 +#define SQ_EXPORT_POS 1 +#define SQ_EXPORT_PARAM 2 +#define X_UNUSED_FOR_SX_EXPORTS 3 +#define SQ_CF_ALLOC_EXPORT_WORD0__RW_GPR(x) (((x) & 0x0000007f) << 15) +#define SQ_CF_ALLOC_EXPORT_WORD0__RW_REL(x) (((x) & 0x00000001) << 22) +#define SQ_CF_ALLOC_EXPORT_WORD0__INDEX_GPR(x) (((x) & 0x0000007f) << 23) +#define SQ_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE(x) (((x) & 0x00000003) << 30) +/* SQ_CF_ALLOC_EXPORT_WORD1 */ +#define SQ_CF_ALLOC_EXPORT_WORD1 0x00000000 +#define SQ_CF_ALLOC_EXPORT_WORD1__BURST_COUNT(x) (((x) & 0x0000000f) << 17) +#define SQ_CF_ALLOC_EXPORT_WORD1__END_OF_PROGRAM(x) (((x) & 0x00000001) << 21) +#define SQ_CF_ALLOC_EXPORT_WORD1__VALID_PIXEL_MODE(x) (((x) & 0x00000001) << 22) +#define SQ_CF_ALLOC_EXPORT_WORD1__CF_INST(x) (((x) & 0x0000007f) << 23) +#define SQ_CF_INST_MEM_STREAM0 32 +#define SQ_CF_INST_MEM_STREAM1 33 +#define SQ_CF_INST_MEM_STREAM2 34 +#define SQ_CF_INST_MEM_STREAM3 35 +#define SQ_CF_INST_MEM_SCRATCH 36 +#define SQ_CF_INST_MEM_REDUCTION 37 +#define SQ_CF_INST_MEM_RING 38 +#define SQ_CF_INST_EXPORT 39 +#define SQ_CF_INST_EXPORT_DONE 40 +#define SQ_CF_ALLOC_EXPORT_WORD1__WHOLE_QUAD_MODE(x) (((x) & 0x00000001) << 30) +#define SQ_CF_ALLOC_EXPORT_WORD1__BARRIER(x) (((x) & 0x00000001) << 31) +/* SQ_CF_ALLOC_EXPORT_WORD1_BUF */ +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF 0x00000000 +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE(x) (((x) & 0x00000fff) << 0) +#define SQ_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK(x) (((x) & 0x0000000f) << 12) +/* SQ_CF_ALLOC_EXPORT_WORD1_SWIZ */ +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ 0x00000000 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X(x) (((x) & 0x00000007) << 0) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y(x) (((x) & 0x00000007) << 3) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z(x) (((x) & 0x00000007) << 6) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W(x) (((x) & 0x00000007) << 9) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 + +/* + * ALU + */ +/* SQ_ALU_WORD0 */ +#define SQ_ALU_WORD0 0x00008dfc +#define SQ_ALU_WORD0__SRC0_SEL(x) (((x) & 0x000001ff) << 0) +#define SQ_ALU_KCACHE0_0 128 +#define SQ_ALU_KCACHE0_31 159 +#define SQ_ALU_KCACHE1_0 160 +#define SQ_ALU_KCACHE1_31 191 +#define SQ_ALU_SRC_0 248 +#define SQ_ALU_SRC_1 249 +#define SQ_ALU_SRC_1_INT 250 +#define SQ_ALU_SRC_M_1_INT 251 +#define SQ_ALU_SRC_0_5 252 +#define SQ_ALU_SRC_LITERAL 253 +#define SQ_ALU_SRC_PV 254 +#define SQ_ALU_SRC_PS 255 +#define SQ_ALU_CFILE_0 256 +#define SQ_ALU_CFILE_255 511 +#define SQ_ALU_WORD0__SRC0_REL(x) (((x) & 0x00000001) << 9) +#define SQ_ALU_WORD0__SRC0_CHAN(x) (((x) & 0x00000003) << 10) +#define SQ_CHAN_X 0 +#define SQ_CHAN_Y 1 +#define SQ_CHAN_Z 2 +#define SQ_CHAN_W 3 +#define SQ_ALU_WORD0__SRC0_NEG(x) (((x) & 0x00000001) << 12) +#define SQ_ALU_WORD0__SRC1_SEL(x) (((x) & 0x000001ff) << 13) +#define SQ_ALU_KCACHE0_0 128 +#define SQ_ALU_KCACHE0_31 159 +#define SQ_ALU_KCACHE1_0 160 +#define SQ_ALU_KCACHE1_31 191 +#define SQ_ALU_SRC_0 248 +#define SQ_ALU_SRC_1 249 +#define SQ_ALU_SRC_1_INT 250 +#define SQ_ALU_SRC_M_1_INT 251 +#define SQ_ALU_SRC_0_5 252 +#define SQ_ALU_SRC_LITERAL 253 +#define SQ_ALU_SRC_PV 254 +#define SQ_ALU_SRC_PS 255 +#define SQ_ALU_CFILE_0 256 +#define SQ_ALU_CFILE_255 511 +#define SQ_ALU_WORD0__SRC1_REL(x) (((x) & 0x00000001) << 22) +#define SQ_ALU_WORD0__SRC1_CHAN(x) (((x) & 0x00000003) << 23) +#define SQ_CHAN_X 0 +#define SQ_CHAN_Y 1 +#define SQ_CHAN_Z 2 +#define SQ_CHAN_W 3 +#define SQ_ALU_WORD0__SRC1_NEG(x) (((x) & 0x00000001) << 25) +#define SQ_ALU_WORD0__INDEX_MODE(x) (((x) & 0x00000007) << 26) +#define SQ_INDEX_AR_X 0 +#define SQ_INDEX_AR_Y 1 +#define SQ_INDEX_AR_Z 2 +#define SQ_INDEX_AR_W 3 +#define SQ_INDEX_LOOP 4 +#define SQ_ALU_WORD0__PRED_SEL(x) (((x) & 0x00000003) << 29) +#define SQ_PRED_SEL_OFF 0 +#define SQ_PRED_SEL_ZERO 2 +#define SQ_PRED_SEL_ONE 3 +#define SQ_ALU_WORD0__LAST(x) (((x) & 0x00000001) << 31) +/* SQ_ALU_WORD1 */ +#define SQ_ALU_WORD1 0x00000000 +#define SQ_ALU_WORD1__ENCODING(x) (((x) & 0x00000007) << 15) +#define SQ_ALU_WORD1__BANK_SWIZZLE(x) (((x) & 0x00000007) << 18) +#define SQ_ALU_VEC_012 0 +#define SQ_ALU_VEC_021 1 +#define SQ_ALU_VEC_120 2 +#define SQ_ALU_VEC_102 3 +#define SQ_ALU_VEC_201 4 +#define SQ_ALU_VEC_210 5 +#define SQ_ALU_WORD1__DST_GPR(x) (((x) & 0x0000007f) << 21) +#define SQ_ALU_WORD1__DST_REL(x) (((x) & 0x00000001) << 28) +#define SQ_ALU_WORD1__DST_CHAN(x) (((x) & 0x00000003) << 29) +#define CHAN_X 0 +#define CHAN_Y 1 +#define CHAN_Z 2 +#define CHAN_W 3 +#define SQ_ALU_WORD1__CLAMP(x) (((x) & 0x00000001) << 31) +/* SQ_ALU_WORD1_OP2 */ +#define SQ_ALU_WORD1_OP2 0x00008dfc +#define SQ_ALU_WORD1_OP2__SRC0_ABS(x) (((x) & 0x00000001) << 0) +#define SQ_ALU_WORD1_OP2__SRC1_ABS(x) (((x) & 0x00000001) << 1) +#define SQ_ALU_WORD1_OP2__UPDATE_EXECUTE_MASK(x) (((x) & 0x00000001) << 2) +#define SQ_ALU_WORD1_OP2__UPDATE_PRED(x) (((x) & 0x00000001) << 3) +#define SQ_ALU_WORD1_OP2__WRITE_MASK(x) (((x) & 0x00000001) << 4) +#define SQ_ALU_WORD1_OP2__FOG_MERGE(x) (((x) & 0x00000001) << 5) +#define SQ_ALU_WORD1_OP2__OMOD(x) (((x) & 0x00000003) << 6) +#define SQ_ALU_OMOD_OFF 0 +#define SQ_ALU_OMOD_M2 1 +#define SQ_ALU_OMOD_M4 2 +#define SQ_ALU_OMOD_D2 3 +#define SQ_ALU_WORD1_OP2__ALU_INST(x) (((x) & 0x000003ff) << 8) +#define SQ_OP2_INST_ADD 0 +#define SQ_OP2_INST_MUL 1 +#define SQ_OP2_INST_MUL_IEEE 2 +#define SQ_OP2_INST_MAX 3 +#define SQ_OP2_INST_MIN 4 +#define SQ_OP2_INST_MAX_DX10 5 +#define SQ_OP2_INST_MIN_DX10 6 +#define SQ_OP2_INST_SETE 8 +#define SQ_OP2_INST_SETGT 9 +#define SQ_OP2_INST_SETGE 10 +#define SQ_OP2_INST_SETNE 11 +#define SQ_OP2_INST_SETE_DX10 12 +#define SQ_OP2_INST_SETGT_DX10 13 +#define SQ_OP2_INST_SETGE_DX10 14 +#define SQ_OP2_INST_SETNE_DX10 15 +#define SQ_OP2_INST_FRACT 16 +#define SQ_OP2_INST_TRUNC 17 +#define SQ_OP2_INST_CEIL 18 +#define SQ_OP2_INST_RNDNE 19 +#define SQ_OP2_INST_FLOOR 20 +#define SQ_OP2_INST_MOVA 21 +#define SQ_OP2_INST_MOVA_FLOOR 22 +#define SQ_OP2_INST_MOVA_INT 24 +#define SQ_OP2_INST_MOV 25 +#define SQ_OP2_INST_NOP 26 +#define SQ_OP2_INST_PRED_SETGT_UINT 30 +#define SQ_OP2_INST_PRED_SETGE_UINT 31 +#define SQ_OP2_INST_PRED_SETE 32 +#define SQ_OP2_INST_PRED_SETGT 33 +#define SQ_OP2_INST_PRED_SETGE 34 +#define SQ_OP2_INST_PRED_SETNE 35 +#define SQ_OP2_INST_PRED_SET_INV 36 +#define SQ_OP2_INST_PRED_SET_POP 37 +#define SQ_OP2_INST_PRED_SET_CLR 38 +#define SQ_OP2_INST_PRED_SET_RESTORE 39 +#define SQ_OP2_INST_PRED_SETE_PUSH 40 +#define SQ_OP2_INST_PRED_SETGT_PUSH 41 +#define SQ_OP2_INST_PRED_SETGE_PUSH 42 +#define SQ_OP2_INST_PRED_SETNE_PUSH 43 +#define SQ_OP2_INST_KILLE 44 +#define SQ_OP2_INST_KILLGT 45 +#define SQ_OP2_INST_KILLGE 46 +#define SQ_OP2_INST_KILLNE 47 +#define SQ_OP2_INST_AND_INT 48 +#define SQ_OP2_INST_OR_INT 49 +#define SQ_OP2_INST_XOR_INT 50 +#define SQ_OP2_INST_NOT_INT 51 +#define SQ_OP2_INST_ADD_INT 52 +#define SQ_OP2_INST_SUB_INT 53 +#define SQ_OP2_INST_MAX_INT 54 +#define SQ_OP2_INST_MIN_INT 55 +#define SQ_OP2_INST_MAX_UINT 56 +#define SQ_OP2_INST_MIN_UINT 57 +#define SQ_OP2_INST_SETE_INT 58 +#define SQ_OP2_INST_SETGT_INT 59 +#define SQ_OP2_INST_SETGE_INT 60 +#define SQ_OP2_INST_SETNE_INT 61 +#define SQ_OP2_INST_SETGT_UINT 62 +#define SQ_OP2_INST_SETGE_UINT 63 +#define SQ_OP2_INST_KILLGT_UINT 64 +#define SQ_OP2_INST_KILLGE_UINT 65 +#define SQ_OP2_INST_PRED_SETE_INT 66 +#define SQ_OP2_INST_PRED_SETGT_INT 67 +#define SQ_OP2_INST_PRED_SETGE_INT 68 +#define SQ_OP2_INST_PRED_SETNE_INT 69 +#define SQ_OP2_INST_KILLE_INT 70 +#define SQ_OP2_INST_KILLGT_INT 71 +#define SQ_OP2_INST_KILLGE_INT 72 +#define SQ_OP2_INST_KILLNE_INT 73 +#define SQ_OP2_INST_PRED_SETE_PUSH_INT 74 +#define SQ_OP2_INST_PRED_SETGT_PUSH_INT 75 +#define SQ_OP2_INST_PRED_SETGE_PUSH_INT 76 +#define SQ_OP2_INST_PRED_SETNE_PUSH_INT 77 +#define SQ_OP2_INST_PRED_SETLT_PUSH_INT 78 +#define SQ_OP2_INST_PRED_SETLE_PUSH_INT 79 +#define SQ_OP2_INST_DOT4 80 +#define SQ_OP2_INST_DOT4_IEEE 81 +#define SQ_OP2_INST_CUBE 82 +#define SQ_OP2_INST_MAX4 83 +#define SQ_OP2_INST_MOVA_GPR_INT 96 +#define SQ_OP2_INST_EXP_IEEE 97 +#define SQ_OP2_INST_LOG_CLAMPED 98 +#define SQ_OP2_INST_LOG_IEEE 99 +#define SQ_OP2_INST_RECIP_CLAMPED 100 +#define SQ_OP2_INST_RECIP_FF 101 +#define SQ_OP2_INST_RECIP_IEEE 102 +#define SQ_OP2_INST_RECIPSQRT_CLAMPED 103 +#define SQ_OP2_INST_RECIPSQRT_FF 104 +#define SQ_OP2_INST_RECIPSQRT_IEEE 105 +#define SQ_OP2_INST_SQRT_IEEE 106 +#define SQ_OP2_INST_FLT_TO_INT 107 +#define SQ_OP2_INST_INT_TO_FLT 108 +#define SQ_OP2_INST_UINT_TO_FLT 109 +#define SQ_OP2_INST_SIN 110 +#define SQ_OP2_INST_COS 111 +#define SQ_OP2_INST_ASHR_INT 112 +#define SQ_OP2_INST_LSHR_INT 113 +#define SQ_OP2_INST_LSHL_INT 114 +#define SQ_OP2_INST_MULLO_INT 115 +#define SQ_OP2_INST_MULHI_INT 116 +#define SQ_OP2_INST_MULLO_UINT 117 +#define SQ_OP2_INST_MULHI_UINT 118 +#define SQ_OP2_INST_RECIP_INT 119 +#define SQ_OP2_INST_RECIP_UINT 120 +#define SQ_OP2_INST_FLT_TO_UINT 121 +/* SQ_ALU_WORD1_OP3 */ +#define SQ_ALU_WORD1_OP3 0x00000000 +#define SQ_ALU_WORD1_OP3__SRC2_SEL(x) (((x) & 0x000001ff) << 0) +#define SQ_ALU_KCACHE0_0 128 +#define SQ_ALU_KCACHE0_31 159 +#define SQ_ALU_KCACHE1_0 160 +#define SQ_ALU_KCACHE1_31 191 +#define SQ_ALU_SRC_0 248 +#define SQ_ALU_SRC_1 249 +#define SQ_ALU_SRC_1_INT 250 +#define SQ_ALU_SRC_M_1_INT 251 +#define SQ_ALU_SRC_0_5 252 +#define SQ_ALU_SRC_LITERAL 253 +#define SQ_ALU_SRC_PV 254 +#define SQ_ALU_SRC_PS 255 +#define SQ_ALU_CFILE_0 256 +#define SQ_ALU_CFILE_255 511 +#define SQ_ALU_WORD1_OP3__SRC2_REL(x) (((x) & 0x00000001) << 9) +#define SQ_ALU_WORD1_OP3__SRC2_CHAN(x) (((x) & 0x00000003) << 10) +#define SQ_CHAN_X 0 +#define SQ_CHAN_Y 1 +#define SQ_CHAN_Z 2 +#define SQ_CHAN_W 3 +#define SQ_ALU_WORD1_OP3__SRC2_NEG(x) (((x) & 0x00000001) << 12) +#define SQ_ALU_WORD1_OP3__ALU_INST(x) (((x) & 0x0000001f) << 13) +#define SQ_OP3_INST_MUL_LIT 12 +#define SQ_OP3_INST_MUL_LIT_M2 13 +#define SQ_OP3_INST_MUL_LIT_M4 14 +#define SQ_OP3_INST_MUL_LIT_D2 15 +#define SQ_OP3_INST_MULADD 16 +#define SQ_OP3_INST_MULADD_M2 17 +#define SQ_OP3_INST_MULADD_M4 18 +#define SQ_OP3_INST_MULADD_D2 19 +#define SQ_OP3_INST_MULADD_IEEE 20 +#define SQ_OP3_INST_MULADD_IEEE_M2 21 +#define SQ_OP3_INST_MULADD_IEEE_M4 22 +#define SQ_OP3_INST_MULADD_IEEE_D2 23 +#define SQ_OP3_INST_CNDE 24 +#define SQ_OP3_INST_CNDGT 25 +#define SQ_OP3_INST_CNDGE 26 +#define SQ_OP3_INST_CNDE_INT 28 +#define SQ_OP3_INST_CNDGT_INT 29 +#define SQ_OP3_INST_CNDGE_INT 30 + +/* + * VTX + */ +/* SQ_VTX_WORD0 */ +#define SQ_VTX_WORD0 0x00008dfc +#define SQ_VTX_WORD0__VTX_INST(x) (((x) & 0x0000001f) << 0) +#define SQ_VTX_INST_FETCH 0 +#define SQ_VTX_INST_SEMANTIC 1 +#define SQ_VTX_WORD0__FETCH_TYPE(x) (((x) & 0x00000003) << 5) +#define SQ_VTX_FETCH_VERTEX_DATA 0 +#define SQ_VTX_FETCH_INSTANCE_DATA 1 +#define SQ_VTX_FETCH_NO_INDEX_OFFSET 2 +#define SQ_VTX_WORD0__FETCH_WHOLE_QUAD(x) (((x) & 0x00000001) << 7) +#define SQ_VTX_WORD0__BUFFER_ID(x) (((x) & 0x000000ff) << 8) +#define SQ_VTX_WORD0__SRC_GPR(x) (((x) & 0x0000007f) << 16) +#define SQ_VTX_WORD0__SRC_REL(x) (((x) & 0x00000001) << 23) +#define SQ_VTX_WORD0__SRC_SEL_X(x) (((x) & 0x00000003) << 24) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_VTX_WORD0__MEGA_FETCH_COUNT(x) (((x) & 0x0000003f) << 26) +/* SQ_VTX_WORD1 */ +#define SQ_VTX_WORD1 0x00000000 +#define SQ_VTX_WORD1__DST_SEL_X(x) (((x) & 0x00000007) << 9) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_VTX_WORD1__DST_SEL_Y(x) (((x) & 0x00000007) << 12) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_VTX_WORD1__DST_SEL_Z(x) (((x) & 0x00000007) << 15) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_VTX_WORD1__DST_SEL_W(x) (((x) & 0x00000007) << 18) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_VTX_WORD1__USE_CONST_FIELDS(x) (((x) & 0x00000001) << 21) +#define SQ_VTX_WORD1__DATA_FORMAT(x) (((x) & 0x0000003f) << 22) +#define FMT_INVALID 0 +#define FMT_8 1 +#define FMT_4_4 2 +#define FMT_3_3_2 3 +#define FMT_16 5 +#define FMT_16_FLOAT 6 +#define FMT_8_8 7 +#define FMT_5_6_5 8 +#define FMT_6_5_5 9 +#define FMT_1_5_5_5 10 +#define FMT_4_4_4_4 11 +#define FMT_5_5_5_1 12 +#define FMT_32 13 +#define FMT_32_FLOAT 14 +#define FMT_16_16 15 +#define FMT_16_16_FLOAT 16 +#define FMT_8_24 17 +#define FMT_8_24_FLOAT 18 +#define FMT_24_8 19 +#define FMT_24_8_FLOAT 20 +#define FMT_10_11_11 21 +#define FMT_10_11_11_FLOAT 22 +#define FMT_11_11_10 23 +#define FMT_11_11_10_FLOAT 24 +#define FMT_2_10_10_10 25 +#define FMT_8_8_8_8 26 +#define FMT_10_10_10_2 27 +#define FMT_X24_8_32_FLOAT 28 +#define FMT_32_32 29 +#define FMT_32_32_FLOAT 30 +#define FMT_16_16_16_16 31 +#define FMT_16_16_16_16_FLOAT 32 +#define FMT_32_32_32_32 34 +#define FMT_32_32_32_32_FLOAT 35 +#define FMT_1 37 +#define FMT_GB_GR 39 +#define FMT_BG_RG 40 +#define FMT_32_AS_8 41 +#define FMT_32_AS_8_8 42 +#define FMT_5_9_9_9_SHAREDEXP 43 +#define FMT_8_8_8 44 +#define FMT_16_16_16 45 +#define FMT_16_16_16_FLOAT 46 +#define FMT_32_32_32 47 +#define FMT_32_32_32_FLOAT 48 +#define SQ_VTX_WORD1__NUM_FORMAT_ALL(x) (((x) & 0x00000003) << 28) +#define SQ_NUM_FORMAT_NORM 0 +#define SQ_NUM_FORMAT_INT 1 +#define SQ_NUM_FORMAT_SCALED 2 +#define SQ_VTX_WORD1__FORMAT_COMP_ALL(x) (((x) & 0x00000001) << 30) +#define SQ_VTX_WORD1__SRF_MODE_ALL(x) (((x) & 0x00000001) << 31) +#define SRF_MODE_ZERO_CLAMP_MINUS_ONE 0 +#define SRF_MODE_NO_ZERO 1 +/* SQ_VTX_WORD1_GPR */ +#define SQ_VTX_WORD1_GPR 0x00000000 +#define SQ_VTX_WORD1_GPR__DST_GPR(x) (((x) & 0x0000007f) << 0) +#define SQ_VTX_WORD1_GPR__DST_REL(x) (((x) & 0x00000001) << 7) +/* SQ_VTX_WORD1_SEM */ +#define SQ_VTX_WORD1_SEM 0x00000000 +#define SQ_VTX_WORD1_SEM__SEMANTIC_ID(x) (((x) & 0x000000ff) << 0) +/* SQ_VTX_WORD2 */ +#define SQ_VTX_WORD2 0x00000000 +#define SQ_VTX_WORD2__OFFSET(x) (((x) & 0x0000ffff) << 0) +#define SQ_VTX_WORD2__ENDIAN_SWAP(x) (((x) & 0x00000003) << 16) +#define SQ_ENDIAN_NONE 0 +#define SQ_ENDIAN_8IN16 1 +#define SQ_ENDIAN_8IN32 2 +#define SQ_VTX_WORD2__CONST_BUF_NO_STRIDE(x) (((x) & 0x00000001) << 18) +#define SQ_VTX_WORD2__MEGA_FETCH(x) (((x) & 0x00000001) << 19) +#define SQ_VTX_WORD2__ALT_CONST(x) (((x) & 0x00000001) << 20) + +/* + * TEX + */ +/* SQ_TEX_WORD0 */ +#define SQ_TEX_WORD0 0x00000000 +#define SQ_TEX_WORD0__TEX_INST(x) (((x) & 0x0000001f) << 0) +#define SQ_TEX_INST_VTX_FETCH 0 +#define SQ_TEX_INST_VTX_SEMANTIC 1 +#define SQ_TEX_INST_LD 3 +#define SQ_TEX_INST_GET_TEXTURE_RESINFO 4 +#define SQ_TEX_INST_GET_NUMBER_OF_SAMPLES 5 +#define SQ_TEX_INST_GET_LOD 6 +#define SQ_TEX_INST_GET_GRADIENTS_H 7 +#define SQ_TEX_INST_GET_GRADIENTS_V 8 +#define SQ_TEX_INST_GET_LERP 9 +#define SQ_TEX_INST_RESERVED_10 10 +#define SQ_TEX_INST_SET_GRADIENTS_H 11 +#define SQ_TEX_INST_SET_GRADIENTS_V 12 +#define SQ_TEX_INST_PASS 13 +#define X_Z_SET_INDEX_FOR_ARRAY_OF_CUBEMAPS 14 +#define SQ_TEX_INST_SAMPLE 16 +#define SQ_TEX_INST_SAMPLE_L 17 +#define SQ_TEX_INST_SAMPLE_LB 18 +#define SQ_TEX_INST_SAMPLE_LZ 19 +#define SQ_TEX_INST_SAMPLE_G 20 +#define SQ_TEX_INST_SAMPLE_G_L 21 +#define SQ_TEX_INST_SAMPLE_G_LB 22 +#define SQ_TEX_INST_SAMPLE_G_LZ 23 +#define SQ_TEX_INST_SAMPLE_C 24 +#define SQ_TEX_INST_SAMPLE_C_L 25 +#define SQ_TEX_INST_SAMPLE_C_LB 26 +#define SQ_TEX_INST_SAMPLE_C_LZ 27 +#define SQ_TEX_INST_SAMPLE_C_G 28 +#define SQ_TEX_INST_SAMPLE_C_G_L 29 +#define SQ_TEX_INST_SAMPLE_C_G_LB 30 +#define SQ_TEX_INST_SAMPLE_C_G_LZ 31 +#define SQ_TEX_WORD0__BC_FRAC_MODE(x) (((x) & 0x00000001) << 5) +#define SQ_TEX_WORD0__FETCH_WHOLE_QUAD(x) (((x) & 0x00000001) << 7) +#define SQ_TEX_WORD0__RESOURCE_ID(x) (((x) & 0x000000ff) << 8) +#define SQ_TEX_WORD0__SRC_GPR(x) (((x) & 0x0000007f) << 16) +#define SQ_TEX_WORD0__SRC_REL(x) (((x) & 0x00000001) << 23) +#define SQ_TEX_WORD0__ALT_CONST(x) (((x) & 0x00000001) << 24) +/* SQ_TEX_WORD1 */ +#define SQ_TEX_WORD1 0x00008dfc +#define SQ_TEX_WORD1__DST_GPR(x) (((x) & 0x0000007f) << 0) +#define SQ_TEX_WORD1__DST_REL(x) (((x) & 0x00000001) << 7) +#define SQ_TEX_WORD1__DST_SEL_X(x) (((x) & 0x00000007) << 9) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_TEX_WORD1__DST_SEL_Y(x) (((x) & 0x00000007) << 12) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_TEX_WORD1__DST_SEL_Z(x) (((x) & 0x00000007) << 15) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_TEX_WORD1__DST_SEL_W(x) (((x) & 0x00000007) << 18) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_SEL_MASK 7 +#define SQ_TEX_WORD1__LOD_BIAS(x) (((x) & 0x0000007f) << 21) +#define SQ_TEX_WORD1__COORD_TYPE_X(x) (((x) & 0x00000001) << 28) +#define SQ_TEX_WORD1__COORD_TYPE_Y(x) (((x) & 0x00000001) << 29) +#define SQ_TEX_WORD1__COORD_TYPE_Z(x) (((x) & 0x00000001) << 30) +#define SQ_TEX_WORD1__COORD_TYPE_W(x) (((x) & 0x00000001) << 31) +/* SQ_TEX_WORD2 */ +#define SQ_TEX_WORD2 0x00008dfc +#define SQ_TEX_WORD2__OFFSET_X(x) (((x) & 0x0000001f) << 0) +#define SQ_TEX_WORD2__OFFSET_Y(x) (((x) & 0x0000001f) << 5) +#define SQ_TEX_WORD2__OFFSET_Z(x) (((x) & 0x0000001f) << 10) +#define SQ_TEX_WORD2__SAMPLER_ID(x) (((x) & 0x0000001f) << 15) +#define SQ_TEX_WORD2__SRC_SEL_X(x) (((x) & 0x00000007) << 20) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_WORD2__SRC_SEL_Y(x) (((x) & 0x00000007) << 23) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_WORD2__SRC_SEL_Z(x) (((x) & 0x00000007) << 26) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 +#define SQ_TEX_WORD2__SRC_SEL_W(x) (((x) & 0x00000007) << 29) +#define SQ_SEL_X 0 +#define SQ_SEL_Y 1 +#define SQ_SEL_Z 2 +#define SQ_SEL_W 3 +#define SQ_SEL_0 4 +#define SQ_SEL_1 5 + +#endif @@ -0,0 +1,64 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Jerome Glisse + */ +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <libdrm/rati_file.h> + +void usage(const char *exename) +{ + printf("%s <filename>\n", exename); + exit(0); +} + +int main(int argc, char *argv[]) +{ + struct rati_file rfile; + char dstname[256], *tmp; + + if (argc != 2) { + usage(argv[0]); + } + + strcpy(dstname, argv[1]); + tmp = strstr(&dstname[strlen(dstname) - 5], ".rati"); + if (tmp == NULL) { + fprintf(stderr, "invalid file suffix %s\n", argv[1]); + return -1; + } + sprintf(tmp, ".tati"); + + if (rati_file_read(&rfile, argv[1])) { + fprintf(stderr, "failed reading %s\n", argv[1]); + return -1; + } + return tati_file_write(&rfile, dstname); +} |