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2014-06-09Encoding: Fix one type error in intra-prediction shader on BDWHEADmasterZhao, Yakui2-2/+2
Otherwise it will cause the incorrect intra-prediction for encoding on Broadwell. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 20bee4c3cb478702155df1779f24ec483aeab059)
2014-06-09Update NEWS for 1.3.2 pre1Xiang, Haihao1-1/+12
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-06-06debug: add g_intel_debug_option_flags for simple driver debugZhao, Halley3-5/+18
VA_INTEL_DEBUG_ASSERT decides assert() is enabled or not VA_INTEL_DEBUG_BENCH decides skipping swapbuffer in dri output (cherry picked from commit 60413182f66c44781456e827b439e98f21cfae4c)
2014-06-06Fix the scaling issue on IVB/HSW/BDWXiang, Haihao2-30/+33
Scaling is done on each 16x16 block. The shader for scaling might write pixels out-of-rectangle if the rectangle width/height isn't aligned to 16. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d560387cc819a31791c2a30026473c9bd8786f07)
2014-06-06VPP: Simplify surface state setting for csc and scaling on IVB/HSW/BDWXiang, Haihao2-197/+162
v2: bpp[] is in unit of bits Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d415357f25fc01b96592ba29ba95da9d6dc82ff3)
2014-06-06New structure i965_fourcc_infoXiang, Haihao2-73/+153
and hold all supported fourcc in an array v2: bpp[] in bit and fix the vertical factor for 411P (Yakui) Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 1de3a2cdc8c3f8b2f6191c0f114fa1167f40f2ec) Conflicts: src/i965_drv_video.c
2014-06-06mpeg2: calculate the slice data length on IVBXiang, Haihao1-2/+27
Sometimes pending datas are added in slice data buffer, however HW requires slice data length excludes pending datas, otherwise the behavior is undefined https://bugs.freedesktop.org/show_bug.cgi?id=77041 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit a9004e6c5c7f33cd1e33e4dab92a5a0017714bbd)
2014-06-06Propagate error codeSebastian Ramacher1-2/+2
Signed-off-by: Sebastian Ramacher <sramacher@debian.org> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit ca1acd54eb59eadabfb40a4b61df2e8968b5e00d)
2014-06-06Define i965_proc_picture in headerSebastian Ramacher2-6/+7
Signed-off-by: Sebastian Ramacher <sramacher@debian.org> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> (cherry picked from commit e9e9b55c769a6c0b90d6af5d89a6baf4c6f742be)
2014-06-06VPP: MADI on SNBXiang, Haihao5-86/+203
Set the right surface states for reference, STMM and output surface, fix the shader as well Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Tested-By: Simon Farnsworth <simon.farnsworth@onelan.co.uk> (cherry picked from commit 1d1b8da1284f7f918733db79428f09af38d7e14a) Conflicts: src/i965_post_processing.c
2014-06-06VPP: i965_vpp_clear_surface() is still used for CSC on BDWXiang, Haihao1-5/+5
https://bugs.freedesktop.org/show_bug.cgi?id=79065 The regression is caused by commit 42258e1 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 0523c58148e9496927f2c3fa9a641885a0350d0f)
2014-06-06Remove unnecessary check with IS_GEN8()Xiang, Haihao4-54/+24
It is always true or false Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 42258e128f19b93aa102672d5f61eb73d9f9808f)
2014-06-05decoder: h264: don't allocate bottom DMV buffer on Broadwell.Gwenole Beauchesne1-12/+2
Broadwell now uses a unique DMV buffer, irrespective of any field coding mode. The dmv_buffer is not used, so it doesn't need to be allocated at all. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-05decoder: h264: only allocate tiled surfaces for Sandybridge an newer.Gwenole Beauchesne1-2/+4
Don't allocate tiled surfaces on Ironlake platforms and earlier, stick to linear surfaces. This is a regression from 6d76944. Reported-by: Haihao Xiang <haihao.xiang@intel.com> Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02decoder: h264: optimize support for grayscale surfaces.Gwenole Beauchesne8-9/+71
Optimize support for grayscale surfaces in two aspects: (i) space by only allocating the luminance component ; (ii) speed by avoiding initialization of the (now inexistent) chrominance planes. Keep backward compatibility with older codec layers that only supported YUV 4:2:0 and not grayscale formats properly. v2: fix check for extra H.264 chroma formats [Haihao] Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02decoder: h264: factor out allocation of reconstructed surfaces.Gwenole Beauchesne6-45/+65
Add new avc_ensure_surface_bo() helper function to factor out the allocatiion and initialization processes of the reconstructed VA surface buffer stores. Keep preferred native format (NV12) and initialize chroma values to 0.0 (0x80) when needed for "fake" grayscale (Y800) surfaces implemented on top of existing NV12. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02config: fix supported set of chroma formats for JPEG decode.Gwenole Beauchesne3-0/+18
If the hardware supports JPEG decoding, then we have to expose the right set of chroma formats for the output (decoded) VA surface. In particular, we could support YUV 4:0:0, 4:1:0, 4:2:2 and 4:4:4. v2: export support for YUV 4:0:0 (grayscale) too [Haihao] Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02config: fix vaCreateConfig() to not override user chroma format.Gwenole Beauchesne1-24/+66
Only validate the user-defined chroma format (VAConfigAttribRTFormat) attribute, if any. Don't override it. i.e. append a pre-defined value only if it was not defined by the user beforehand. Propertly return VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT if the supplied chroma format is not supported. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02config: fix vaGetConfigAttributes() to validate profile/entrypoint.Gwenole Beauchesne1-67/+78
Factor out code to validate profile/entrypoint per the underlying hardware capabilities. Also fix vaGetConfigAttributes() to really validate the profile/entrypoint pair. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02surface: factor out release of surface buffer storage.Gwenole Beauchesne4-13/+16
Introduce a new i965_destroy_surface_storage() helper function to unreference the underlying GEM buffer object, and any associated private data, if any. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-06-02surface: fix geometry (size, layout) of grayscale surfaces.Gwenole Beauchesne3-4/+11
Fix size of the allocated buffer used to represent grayscale (Y800) surfaces. Only the luminance component is needed, thus implying a single plane. Likewise, update render routines to only submit the first plane. The existing render kernels readily only care about that single plane. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-05-26mpeg2: check frame_pred_frame_dct instead of progressive_frameXiang, Haihao1-1/+1
Some MPEG-2 videos set progressive_frame to 1 and set frame_pred_frame_dct to 0, which is not conformed to MPEG-2 spec. bottom field may be used to form prediction if frame_pred_frame_dct is 0. Previously the bottom field is excluded from the frame store list https://bugs.freedesktop.org/show_bug.cgi?id=73424 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit b3031d16b1ea9ef2ab95bc09e59f0db5214a1125)
2014-05-26Limit the minimum pitch for linear surfaceXiang, Haihao3-6/+22
pitch must be 64 at least for linear surface for most functions on IVB/HSW/BDW such VEBOX, Data port media read/write https://bugs.freedesktop.org/show_bug.cgi?id=72522 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 57db5c2524f4e3cb6ae2301bddfdf1c40cdbb626)
2014-05-26Rename HAS_PP() to HAS_VPP()Xiang, Haihao2-14/+5
Directly check the flag of has_vpp in codec_info Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 1c4d3468229797e787f4b99b0729baf90a115a1d) Conflicts: src/gen8_post_processing.c src/i965_post_processing.c
2014-05-26posst_processing_context_init()/finalize() callback functions for each platformXiang, Haihao5-26/+24
It is to reduce the usage of IS_GENxxx() as well. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 77b6a72504d917af9335ab94f6ecbefb8b087206)
2014-05-26render_init()/render_terminate() callback functions for each platformXiang, Haihao5-86/+109
It is to reduce the usage of IS_GENxxx() Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f150fbf444ca63b5e9c3e8f7e17aa3386f7061fa)
2014-05-26Simplify some macrosXiang, Haihao17-376/+119
Now it can directly use the information in intel_device_info instead of checking the pci id. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit f1b3f83953cd5f6e39900d98b4858a7cb825dee0) Conflicts: src/gen8_post_processing.c src/i965_post_processing.c src/intel_driver.h
2014-05-26Remove max_wm_threads from render_stateXiang, Haihao3-38/+5
Instead directly use the value stored in intel_device_info Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 6ba787b29e4bcebdceda52906e33cb84f24a63b5)
2014-05-26Remove URB_SIZE()Xiang, Haihao7-15/+9
Instead directly use the value stored in intel_device_info Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit a0fe5a6262f9ff1398a512c83d193556bbd0eae9)
2014-05-26Dump chipset information in the vendor stringXiang, Haihao1-1/+12
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 2518c1e741cb21c5412a4b5252ebe861a52c2900)
2014-05-26Add a new intel_device_info structureXiang, Haihao3-0/+135
To store statically known device information Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit eb014a09fde988ba3ed2d2be6e8d6f0c650d281e)
2014-05-26Move all of PCIIDs and codec info into separated filesXiang, Haihao5-160/+328
The redundant code will be removed soon. Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit d20db5984989626728f62eb3e02b60093d914d01) Conflicts: src/i965_drv_video.c
2014-05-26i965_DeriveImage() support JPEG color formatsZhong Li1-0/+6
Signed-off-by: Zhong Li <zhong.li@intel.com> (cherry picked from commit 9f9c505ed5212ae0704f71f45532b9716ac0bd51)
2014-05-091.3.2.pre1 for developmentXiang, Haihao1-2/+2
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-05-09Intel driver 1.3.1Xiang, Haihao2-3/+3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-05-05Update NEWSXiang, Haihao1-1/+9
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
2014-05-05Return error when trying to decoding an interlaced VC-1 videoXiang, Haihao1-1/+6
https://bugs.freedesktop.org/show_bug.cgi?id=77386 Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2014-05-05Make it buildable against libva 1.3.0Xiang, Haihao1-0/+6
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
2014-05-05Fix over assigned callback "QueryConfigEntrypoints".qing.zhang1-1/+0
2014-04-25VPP: Enable Skin tone detection and enhancement - Added STDE coefficients.Sirisha Muppavarapu1-34/+173
In this commit, I added the optimized STDE coefficients to the vebox state table. (cherry picked from commit 150f67c67bd92cd201b75a92388fe3a63b00cd8a)
2014-04-25VPP: Enable Skin Tone Detection and Enhancement feature in the driver.Sirisha Muppavarapu3-6/+19
The VPP-STDE feature is enabled in the driver code for gen75 and gen8. In this commit, I added the filter and made appropriate changes to the hw_codec_info and the supporting methods. (cherry picked from commit 691b149b7afe578889a423841a29db3ac56aad83)
2014-04-24vp8: fix support for segmentation-enabled streams.Gwenole Beauchesne4-5/+59
If segmentation is enabled, then the segmentation map shall be live across frames until the current frame updates the segment ids. This means that the driver needs to maintain the segmentation map buffer allocation and enable writes (resp. reads) whenever necessary. This fixes decoding of 00-comprehensive-010. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
2014-04-23VPP: Set the alpha channel when doing the conversion from NV12 to RGBA on ↵Zhao Yakui3-1/+3
Ivy/Haswell/BDW Currently zero is written to alpha channel when doing the conversion from NV12 to RGBA(BGRA), which affects the following the rendering operation. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 4082c9db1eef45bc117fc151d60a178926ab9f73)
2014-04-23Fix bound checkingXiang, Haihao1-1/+1
Otherwise it might result in buffer overflow. Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> (cherry picked from commit 782b8afdda14f000874d8acf51c3e8c490d55773)
2014-04-23Rendering/BDW:Follow the hardware spec to update the 3DSTATE_URB_VS commandZhao Yakui1-1/+1
This is to fix the GPU hang when doing the color-space conversion from NV12 to RGB on BDW GT3 machine. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 4a3f17ae44bae58daf65dcc706332b28a6d478ac)
2014-04-23vp8: fix loop filter for bitexact reconstruction.Gwenole Beauchesne1-8/+8
Each loop filter delta update value shall be encoded within 7 bits, including the sign bit and 6-bit magnitude in 2's complement. So, don't propagate the sign bit while packing the filter level values. Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com> (cherry picked from commit 36ccd9c3e47766edc70ecbdf82acc89ed67e26c4)
2014-04-23BDW: Fix one error in shader binaray for media encodingZhao Yakui1-1/+1
The commit 7ac4263ff2dae5c877b92356d04df4ccfe10d7c9 updates the shader binary more than it required. So it is removed. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit b1319c7f7cb9d20179b20dac2308330bd0e51ffe)
2014-04-23V3: Add 422H support.Alex wu3-2/+15
Changes between V3 to V2: 1. Add 422H support into gen8_post_processing.c, according to yakui's comments. changes between V2 and V1: 1. Rebase on staging branch. 2. Add 422H support for pp. 3. Reword the commit title. Signed-off-by: Alex wu <zhiwen.wu@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit 347dd731d31dd37b242bbace744125554f2c09e7)
2014-04-23Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)Zhao Yakui16-71/+71
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D). Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> (cherry picked from commit acea969011bceee36a57fe2c0e4ee96c0c5e79c7)
2014-04-23VEBOX: Use the VA_FOURCC_ABCD constant to replace the VA_FOURCC(A,B,C,D)Zhao Yakui1-42/+41
This is helpful to avoid the typo error when using VA_FOURCC(A, B, C, D). Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> -- src/gen75_vpp_vebox.c | 83 ++++++++++++++++++++++++-------------------------- 1 file changed, 41 insertions(+), 42 deletions(-) (cherry picked from commit 2a31ad7e200cfb5df95b11875ee33795cdc7e343)
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-14 07:19:34 +0000