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authorBen Avison <bavison@riscosopen.org>2015-03-03 15:24:16 +0000
committerMatt Turner <mattst88@gmail.com>2015-04-01 18:38:36 -0700
commit978dd9fc6527f476fe980c764f0019a7a0bd451d (patch)
treeb91a436e6c57c03122eddd5ce8f2d11e3203cb1a
parent594e6a6c93e92fcfb495e987aec5617f6c37f467 (diff)
armv6: Fix typo in preload macro
Missing "lsl" meant that cases with a 32-bit source and/or mask, and an 8-bit destination, the code would not assemble.
-rw-r--r--pixman/pixman-arm-simd-asm.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/pixman/pixman-arm-simd-asm.h b/pixman/pixman-arm-simd-asm.h
index 8de060a..da153c3 100644
--- a/pixman/pixman-arm-simd-asm.h
+++ b/pixman/pixman-arm-simd-asm.h
@@ -211,8 +211,8 @@
PF add, SCRATCH, base, WK0, lsl #bpp_shift-dst_bpp_shift
PF and, SCRATCH, SCRATCH, #31
PF rsb, SCRATCH, SCRATCH, WK0, lsl #bpp_shift-dst_bpp_shift
- PF sub, SCRATCH, SCRATCH, #1 /* so now ranges are -16..-1 / 0..31 / 32..63 */
- PF movs, SCRATCH, SCRATCH, #32-6 /* so this sets NC / nc / Nc */
+ PF sub, SCRATCH, SCRATCH, #1 /* so now ranges are -16..-1 / 0..31 / 32..63 */
+ PF movs, SCRATCH, SCRATCH, lsl #32-6 /* so this sets NC / nc / Nc */
PF bcs, 61f
PF bpl, 60f
PF pld, [ptr, #32*(prefetch_distance+2)]