[InstCombine][X86][SSE41] The SSE41 PMOVSX intrinsics are auto upgraded now and aren't handled by InstCombine any more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270561 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 67 deletions

diff --git a/test/Transforms/InstCombine/x86-pmovsx.ll b/test/Transforms/InstCombine/x86-pmovsx.ll
index b22d86acb13..52cf4124210 100644
--- a/test/Transforms/InstCombine/x86-pmovsx.ll
+++ b/test/Transforms/InstCombine/x86-pmovsx.ll
@@ -1,13 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
-declare <4 x i32>  @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
-declare <2 x i64>  @llvm.x86.sse41.pmovsxbq(<16 x i8>) nounwind readnone
-declare <8 x i16>  @llvm.x86.sse41.pmovsxbw(<16 x i8>) nounwind readnone
-declare <2 x i64>  @llvm.x86.sse41.pmovsxdq(<4 x i32>) nounwind readnone
-declare <4 x i32>  @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
-declare <2 x i64>  @llvm.x86.sse41.pmovsxwq(<8 x i16>) nounwind readnone
-
 declare <8 x i32>  @llvm.x86.avx2.pmovsxbd(<16 x i8>) nounwind readnone
 declare <4 x i64>  @llvm.x86.avx2.pmovsxbq(<16 x i8>) nounwind readnone
 declare <16 x i16> @llvm.x86.avx2.pmovsxbw(<16 x i8>) nounwind readnone
@@ -19,66 +12,6 @@ declare <4 x i64>  @llvm.x86.avx2.pmovsxwq(<8 x i16>) nounwind readnone
 ; Basic sign extension tests
 ;
 
-define <4 x i32> @sse41_pmovsxbd(<16 x i8> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxbd(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i32>
-; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
-;
-  %res = call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %v)
-  ret <4 x i32> %res
-}
-
-define <2 x i64> @sse41_pmovsxbq(<16 x i8> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxbq(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
-;
-  %res = call <2 x i64> @llvm.x86.sse41.pmovsxbq(<16 x i8> %v)
-  ret <2 x i64> %res
-}
-
-define <8 x i16> @sse41_pmovsxbw(<16 x i8> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxbw(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>
-; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
-;
-  %res = call <8 x i16> @llvm.x86.sse41.pmovsxbw(<16 x i8> %v)
-  ret <8 x i16> %res
-}
-
-define <2 x i64> @sse41_pmovsxdq(<4 x i32> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxdq(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> %v, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
-;
-  %res = call <2 x i64> @llvm.x86.sse41.pmovsxdq(<4 x i32> %v)
-  ret <2 x i64> %res
-}
-
-define <4 x i32> @sse41_pmovsxwd(<8 x i16> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxwd(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
-; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
-;
-  %res = call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %v)
-  ret <4 x i32> %res
-}
-
-define <2 x i64> @sse41_pmovsxwq(<8 x i16> %v) nounwind readnone {
-; CHECK-LABEL: @sse41_pmovsxwq(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> %v, <8 x i16> undef, <2 x i32> <i32 0, i32 1>
-; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i16> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
-;
-  %res = call <2 x i64> @llvm.x86.sse41.pmovsxwq(<8 x i16> %v)
-  ret <2 x i64> %res
-}
-
 define <8 x i32> @avx2_pmovsxbd(<16 x i8> %v) nounwind readnone {
 ; CHECK-LABEL: @avx2_pmovsxbd(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> %v, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>