~fziglio/qemu - Qemu experimental branch

Age	Commit message (Expand)	Author	Files	Lines
2018-11-27	vmstate: constify VMStateField	Marc-André Lureau	1	-2/+3
2018-10-31	decodetree: Remove "insn" argument from trans_* expanders	Richard Henderson	2	-112/+111
2018-07-03	target/openrisc: Fix writes to interrupt mask register	Stafford Horne	1	-1/+1
2018-07-03	target/openrisc: Fix delay slot exception flag to match spec	Stafford Horne	1	-7/+12
2018-07-03	linux-user: Implement signals for openrisc	Richard Henderson	1	-0/+1
2018-07-03	target/openrisc: Reorg tlb lookup	Richard Henderson	2	-170/+88
2018-07-03	target/openrisc: Increase the TLB size	Richard Henderson	3	-6/+7
2018-07-03	target/openrisc: Stub out handle_mmu_fault for softmmu	Richard Henderson	1	-30/+5
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	4	-18/+16
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	6	-32/+49
2018-07-03	target/openrisc: Fix tlb flushing in mtspr	Richard Henderson	1	-6/+15
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	4	-32/+30
2018-07-03	target/openrisc: Merge mmu_helper.c into mmu.c	Richard Henderson	3	-41/+12
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	7	-119/+32
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	6	-49/+46
2018-07-03	target/openrisc: Form the spr index from tcg	Richard Henderson	3	-15/+14
2018-07-03	target/openrisc: Exit the TB after l.mtspr	Richard Henderson	1	-1/+16
2018-07-03	target/openrisc: Split out is_user	Richard Henderson	1	-15/+12
2018-07-03	target/openrisc: Link more translation blocks	Richard Henderson	1	-41/+55
2018-07-03	target/openrisc: Fix singlestep_enabled	Richard Henderson	1	-18/+17
2018-07-03	target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB	Richard Henderson	2	-5/+4
2018-07-03	target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP	Richard Henderson	1	-4/+0
2018-07-03	target/openrisc: Log interrupts	Richard Henderson	1	-5/+25
2018-07-03	target/openrisc: Add print_insn_or1k	Richard Henderson	5	-115/+179
2018-07-02	target/openrisc: Fix mtspr shadow gprs	Richard Henderson	1	-0/+1
2018-06-04	Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into st...	Peter Maydell	1	-3/+3
2018-06-01	tcg: Pass tb and index to tcg_gen_exit_tb separately	Richard Henderson	1	-3/+3
2018-06-01	target: Do not include "exec/exec-all.h" if it is not necessary	Philippe Mathieu-Daudé	1	-1/+0
2018-05-14	target/openrisc: Merge disas_openrisc_insn	Richard Henderson	1	-9/+4
2018-05-14	target/openrisc: Convert dec_float	Richard Henderson	2	-230/+149
2018-05-14	target/openrisc: Convert dec_compi	Richard Henderson	2	-58/+70
2018-05-14	target/openrisc: Convert dec_comp	Richard Henderson	2	-62/+73
2018-05-14	target/openrisc: Convert dec_M	Richard Henderson	2	-28/+16
2018-05-14	target/openrisc: Convert dec_logic	Richard Henderson	2	-36/+32
2018-05-14	target/openrisc: Convert dec_mac	Richard Henderson	2	-33/+27
2018-05-14	target/openrisc: Convert dec_calc	Richard Henderson	2	-169/+229
2018-05-14	target/openrisc: Convert remainder of dec_misc insns	Richard Henderson	2	-153/+141
2018-05-14	target/openrisc: Convert memory insns	Richard Henderson	2	-139/+160
2018-05-14	target/openrisc: Convert branch insns	Richard Henderson	2	-78/+84
2018-05-14	target/openrisc: Start conversion to decodetree.py	Richard Henderson	3	-43/+78
2018-05-14	target-openrisc: Write back result before FPE exception	Richard Henderson	3	-252/+126
2018-05-09	target/openrisc: convert to TranslatorOps	Emilio G. Cota	1	-84/+79
2018-05-09	target/openrisc: convert to DisasContextBase	Emilio G. Cota	1	-47/+46
2018-04-11	icount: fix cpu_restore_state_from_tb for non-tb-exit cases	Pavel Dovgalyuk	1	-4/+4
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov	1	-2/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	2	-1/+1
2018-02-05	qdev: use device_class_set_parent_realize/unrealize/reset()	Philippe Mathieu-Daudé	1	-3/+2
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	3	-8/+8
2017-12-27	target/*helper: don't check retaddr before calling cpu_restore_state	Alex Bennée	1	-5/+1