path: root/src/lib/ip/gmc60_regs.i

	{ "ixMC_IO_DEBUG_UP_0", REG_SMC, 0x0000, &ixMC_IO_DEBUG_UP_0[0], sizeof(ixMC_IO_DEBUG_UP_0)/sizeof(ixMC_IO_DEBUG_UP_0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_1", REG_SMC, 0x0001, &ixMC_IO_DEBUG_UP_1[0], sizeof(ixMC_IO_DEBUG_UP_1)/sizeof(ixMC_IO_DEBUG_UP_1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_2", REG_SMC, 0x0002, &ixMC_IO_DEBUG_UP_2[0], sizeof(ixMC_IO_DEBUG_UP_2)/sizeof(ixMC_IO_DEBUG_UP_2[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_3", REG_SMC, 0x0003, &ixMC_IO_DEBUG_UP_3[0], sizeof(ixMC_IO_DEBUG_UP_3)/sizeof(ixMC_IO_DEBUG_UP_3[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_4", REG_SMC, 0x0004, &ixMC_IO_DEBUG_UP_4[0], sizeof(ixMC_IO_DEBUG_UP_4)/sizeof(ixMC_IO_DEBUG_UP_4[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_5", REG_SMC, 0x0005, &ixMC_IO_DEBUG_UP_5[0], sizeof(ixMC_IO_DEBUG_UP_5)/sizeof(ixMC_IO_DEBUG_UP_5[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_6", REG_SMC, 0x0006, &ixMC_IO_DEBUG_UP_6[0], sizeof(ixMC_IO_DEBUG_UP_6)/sizeof(ixMC_IO_DEBUG_UP_6[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_7", REG_SMC, 0x0007, &ixMC_IO_DEBUG_UP_7[0], sizeof(ixMC_IO_DEBUG_UP_7)/sizeof(ixMC_IO_DEBUG_UP_7[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_8", REG_SMC, 0x0008, &ixMC_IO_DEBUG_UP_8[0], sizeof(ixMC_IO_DEBUG_UP_8)/sizeof(ixMC_IO_DEBUG_UP_8[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_9", REG_SMC, 0x0009, &ixMC_IO_DEBUG_UP_9[0], sizeof(ixMC_IO_DEBUG_UP_9)/sizeof(ixMC_IO_DEBUG_UP_9[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_10", REG_SMC, 0x000A, &ixMC_IO_DEBUG_UP_10[0], sizeof(ixMC_IO_DEBUG_UP_10)/sizeof(ixMC_IO_DEBUG_UP_10[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_11", REG_SMC, 0x000B, &ixMC_IO_DEBUG_UP_11[0], sizeof(ixMC_IO_DEBUG_UP_11)/sizeof(ixMC_IO_DEBUG_UP_11[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_12", REG_SMC, 0x000C, &ixMC_IO_DEBUG_UP_12[0], sizeof(ixMC_IO_DEBUG_UP_12)/sizeof(ixMC_IO_DEBUG_UP_12[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_13", REG_SMC, 0x000D, &ixMC_IO_DEBUG_UP_13[0], sizeof(ixMC_IO_DEBUG_UP_13)/sizeof(ixMC_IO_DEBUG_UP_13[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_14", REG_SMC, 0x000E, &ixMC_IO_DEBUG_UP_14[0], sizeof(ixMC_IO_DEBUG_UP_14)/sizeof(ixMC_IO_DEBUG_UP_14[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_15", REG_SMC, 0x000F, &ixMC_IO_DEBUG_UP_15[0], sizeof(ixMC_IO_DEBUG_UP_15)/sizeof(ixMC_IO_DEBUG_UP_15[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_16", REG_SMC, 0x0010, &ixMC_IO_DEBUG_UP_16[0], sizeof(ixMC_IO_DEBUG_UP_16)/sizeof(ixMC_IO_DEBUG_UP_16[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_17", REG_SMC, 0x0011, &ixMC_IO_DEBUG_UP_17[0], sizeof(ixMC_IO_DEBUG_UP_17)/sizeof(ixMC_IO_DEBUG_UP_17[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_18", REG_SMC, 0x0012, &ixMC_IO_DEBUG_UP_18[0], sizeof(ixMC_IO_DEBUG_UP_18)/sizeof(ixMC_IO_DEBUG_UP_18[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_19", REG_SMC, 0x0013, &ixMC_IO_DEBUG_UP_19[0], sizeof(ixMC_IO_DEBUG_UP_19)/sizeof(ixMC_IO_DEBUG_UP_19[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_20", REG_SMC, 0x0014, &ixMC_IO_DEBUG_UP_20[0], sizeof(ixMC_IO_DEBUG_UP_20)/sizeof(ixMC_IO_DEBUG_UP_20[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_21", REG_SMC, 0x0015, &ixMC_IO_DEBUG_UP_21[0], sizeof(ixMC_IO_DEBUG_UP_21)/sizeof(ixMC_IO_DEBUG_UP_21[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_22", REG_SMC, 0x0016, &ixMC_IO_DEBUG_UP_22[0], sizeof(ixMC_IO_DEBUG_UP_22)/sizeof(ixMC_IO_DEBUG_UP_22[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_23", REG_SMC, 0x0017, &ixMC_IO_DEBUG_UP_23[0], sizeof(ixMC_IO_DEBUG_UP_23)/sizeof(ixMC_IO_DEBUG_UP_23[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_24", REG_SMC, 0x0018, &ixMC_IO_DEBUG_UP_24[0], sizeof(ixMC_IO_DEBUG_UP_24)/sizeof(ixMC_IO_DEBUG_UP_24[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_25", REG_SMC, 0x0019, &ixMC_IO_DEBUG_UP_25[0], sizeof(ixMC_IO_DEBUG_UP_25)/sizeof(ixMC_IO_DEBUG_UP_25[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_26", REG_SMC, 0x001A, &ixMC_IO_DEBUG_UP_26[0], sizeof(ixMC_IO_DEBUG_UP_26)/sizeof(ixMC_IO_DEBUG_UP_26[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_27", REG_SMC, 0x001B, &ixMC_IO_DEBUG_UP_27[0], sizeof(ixMC_IO_DEBUG_UP_27)/sizeof(ixMC_IO_DEBUG_UP_27[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_28", REG_SMC, 0x001C, &ixMC_IO_DEBUG_UP_28[0], sizeof(ixMC_IO_DEBUG_UP_28)/sizeof(ixMC_IO_DEBUG_UP_28[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_29", REG_SMC, 0x001D, &ixMC_IO_DEBUG_UP_29[0], sizeof(ixMC_IO_DEBUG_UP_29)/sizeof(ixMC_IO_DEBUG_UP_29[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_30", REG_SMC, 0x001E, &ixMC_IO_DEBUG_UP_30[0], sizeof(ixMC_IO_DEBUG_UP_30)/sizeof(ixMC_IO_DEBUG_UP_30[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_31", REG_SMC, 0x001F, &ixMC_IO_DEBUG_UP_31[0], sizeof(ixMC_IO_DEBUG_UP_31)/sizeof(ixMC_IO_DEBUG_UP_31[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_32", REG_SMC, 0x0020, &ixMC_IO_DEBUG_UP_32[0], sizeof(ixMC_IO_DEBUG_UP_32)/sizeof(ixMC_IO_DEBUG_UP_32[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_33", REG_SMC, 0x0021, &ixMC_IO_DEBUG_UP_33[0], sizeof(ixMC_IO_DEBUG_UP_33)/sizeof(ixMC_IO_DEBUG_UP_33[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_34", REG_SMC, 0x0022, &ixMC_IO_DEBUG_UP_34[0], sizeof(ixMC_IO_DEBUG_UP_34)/sizeof(ixMC_IO_DEBUG_UP_34[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_35", REG_SMC, 0x0023, &ixMC_IO_DEBUG_UP_35[0], sizeof(ixMC_IO_DEBUG_UP_35)/sizeof(ixMC_IO_DEBUG_UP_35[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_36", REG_SMC, 0x0024, &ixMC_IO_DEBUG_UP_36[0], sizeof(ixMC_IO_DEBUG_UP_36)/sizeof(ixMC_IO_DEBUG_UP_36[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_37", REG_SMC, 0x0025, &ixMC_IO_DEBUG_UP_37[0], sizeof(ixMC_IO_DEBUG_UP_37)/sizeof(ixMC_IO_DEBUG_UP_37[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_38", REG_SMC, 0x0026, &ixMC_IO_DEBUG_UP_38[0], sizeof(ixMC_IO_DEBUG_UP_38)/sizeof(ixMC_IO_DEBUG_UP_38[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_39", REG_SMC, 0x0027, &ixMC_IO_DEBUG_UP_39[0], sizeof(ixMC_IO_DEBUG_UP_39)/sizeof(ixMC_IO_DEBUG_UP_39[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_40", REG_SMC, 0x0028, &ixMC_IO_DEBUG_UP_40[0], sizeof(ixMC_IO_DEBUG_UP_40)/sizeof(ixMC_IO_DEBUG_UP_40[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_41", REG_SMC, 0x0029, &ixMC_IO_DEBUG_UP_41[0], sizeof(ixMC_IO_DEBUG_UP_41)/sizeof(ixMC_IO_DEBUG_UP_41[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_42", REG_SMC, 0x002A, &ixMC_IO_DEBUG_UP_42[0], sizeof(ixMC_IO_DEBUG_UP_42)/sizeof(ixMC_IO_DEBUG_UP_42[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_43", REG_SMC, 0x002B, &ixMC_IO_DEBUG_UP_43[0], sizeof(ixMC_IO_DEBUG_UP_43)/sizeof(ixMC_IO_DEBUG_UP_43[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_44", REG_SMC, 0x002C, &ixMC_IO_DEBUG_UP_44[0], sizeof(ixMC_IO_DEBUG_UP_44)/sizeof(ixMC_IO_DEBUG_UP_44[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_45", REG_SMC, 0x002D, &ixMC_IO_DEBUG_UP_45[0], sizeof(ixMC_IO_DEBUG_UP_45)/sizeof(ixMC_IO_DEBUG_UP_45[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_46", REG_SMC, 0x002E, &ixMC_IO_DEBUG_UP_46[0], sizeof(ixMC_IO_DEBUG_UP_46)/sizeof(ixMC_IO_DEBUG_UP_46[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_47", REG_SMC, 0x002F, &ixMC_IO_DEBUG_UP_47[0], sizeof(ixMC_IO_DEBUG_UP_47)/sizeof(ixMC_IO_DEBUG_UP_47[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_48", REG_SMC, 0x0030, &ixMC_IO_DEBUG_UP_48[0], sizeof(ixMC_IO_DEBUG_UP_48)/sizeof(ixMC_IO_DEBUG_UP_48[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_49", REG_SMC, 0x0031, &ixMC_IO_DEBUG_UP_49[0], sizeof(ixMC_IO_DEBUG_UP_49)/sizeof(ixMC_IO_DEBUG_UP_49[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_50", REG_SMC, 0x0032, &ixMC_IO_DEBUG_UP_50[0], sizeof(ixMC_IO_DEBUG_UP_50)/sizeof(ixMC_IO_DEBUG_UP_50[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_51", REG_SMC, 0x0033, &ixMC_IO_DEBUG_UP_51[0], sizeof(ixMC_IO_DEBUG_UP_51)/sizeof(ixMC_IO_DEBUG_UP_51[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_52", REG_SMC, 0x0034, &ixMC_IO_DEBUG_UP_52[0], sizeof(ixMC_IO_DEBUG_UP_52)/sizeof(ixMC_IO_DEBUG_UP_52[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_53", REG_SMC, 0x0035, &ixMC_IO_DEBUG_UP_53[0], sizeof(ixMC_IO_DEBUG_UP_53)/sizeof(ixMC_IO_DEBUG_UP_53[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_54", REG_SMC, 0x0036, &ixMC_IO_DEBUG_UP_54[0], sizeof(ixMC_IO_DEBUG_UP_54)/sizeof(ixMC_IO_DEBUG_UP_54[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_55", REG_SMC, 0x0037, &ixMC_IO_DEBUG_UP_55[0], sizeof(ixMC_IO_DEBUG_UP_55)/sizeof(ixMC_IO_DEBUG_UP_55[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_56", REG_SMC, 0x0038, &ixMC_IO_DEBUG_UP_56[0], sizeof(ixMC_IO_DEBUG_UP_56)/sizeof(ixMC_IO_DEBUG_UP_56[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_57", REG_SMC, 0x0039, &ixMC_IO_DEBUG_UP_57[0], sizeof(ixMC_IO_DEBUG_UP_57)/sizeof(ixMC_IO_DEBUG_UP_57[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_58", REG_SMC, 0x003A, &ixMC_IO_DEBUG_UP_58[0], sizeof(ixMC_IO_DEBUG_UP_58)/sizeof(ixMC_IO_DEBUG_UP_58[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_59", REG_SMC, 0x003B, &ixMC_IO_DEBUG_UP_59[0], sizeof(ixMC_IO_DEBUG_UP_59)/sizeof(ixMC_IO_DEBUG_UP_59[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_60", REG_SMC, 0x003C, &ixMC_IO_DEBUG_UP_60[0], sizeof(ixMC_IO_DEBUG_UP_60)/sizeof(ixMC_IO_DEBUG_UP_60[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_61", REG_SMC, 0x003D, &ixMC_IO_DEBUG_UP_61[0], sizeof(ixMC_IO_DEBUG_UP_61)/sizeof(ixMC_IO_DEBUG_UP_61[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_62", REG_SMC, 0x003E, &ixMC_IO_DEBUG_UP_62[0], sizeof(ixMC_IO_DEBUG_UP_62)/sizeof(ixMC_IO_DEBUG_UP_62[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_63", REG_SMC, 0x003F, &ixMC_IO_DEBUG_UP_63[0], sizeof(ixMC_IO_DEBUG_UP_63)/sizeof(ixMC_IO_DEBUG_UP_63[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_64", REG_SMC, 0x0040, &ixMC_IO_DEBUG_UP_64[0], sizeof(ixMC_IO_DEBUG_UP_64)/sizeof(ixMC_IO_DEBUG_UP_64[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_65", REG_SMC, 0x0041, &ixMC_IO_DEBUG_UP_65[0], sizeof(ixMC_IO_DEBUG_UP_65)/sizeof(ixMC_IO_DEBUG_UP_65[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_66", REG_SMC, 0x0042, &ixMC_IO_DEBUG_UP_66[0], sizeof(ixMC_IO_DEBUG_UP_66)/sizeof(ixMC_IO_DEBUG_UP_66[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_67", REG_SMC, 0x0043, &ixMC_IO_DEBUG_UP_67[0], sizeof(ixMC_IO_DEBUG_UP_67)/sizeof(ixMC_IO_DEBUG_UP_67[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_68", REG_SMC, 0x0044, &ixMC_IO_DEBUG_UP_68[0], sizeof(ixMC_IO_DEBUG_UP_68)/sizeof(ixMC_IO_DEBUG_UP_68[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_69", REG_SMC, 0x0045, &ixMC_IO_DEBUG_UP_69[0], sizeof(ixMC_IO_DEBUG_UP_69)/sizeof(ixMC_IO_DEBUG_UP_69[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_70", REG_SMC, 0x0046, &ixMC_IO_DEBUG_UP_70[0], sizeof(ixMC_IO_DEBUG_UP_70)/sizeof(ixMC_IO_DEBUG_UP_70[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_71", REG_SMC, 0x0047, &ixMC_IO_DEBUG_UP_71[0], sizeof(ixMC_IO_DEBUG_UP_71)/sizeof(ixMC_IO_DEBUG_UP_71[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_72", REG_SMC, 0x0048, &ixMC_IO_DEBUG_UP_72[0], sizeof(ixMC_IO_DEBUG_UP_72)/sizeof(ixMC_IO_DEBUG_UP_72[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_73", REG_SMC, 0x0049, &ixMC_IO_DEBUG_UP_73[0], sizeof(ixMC_IO_DEBUG_UP_73)/sizeof(ixMC_IO_DEBUG_UP_73[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_74", REG_SMC, 0x004A, &ixMC_IO_DEBUG_UP_74[0], sizeof(ixMC_IO_DEBUG_UP_74)/sizeof(ixMC_IO_DEBUG_UP_74[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_75", REG_SMC, 0x004B, &ixMC_IO_DEBUG_UP_75[0], sizeof(ixMC_IO_DEBUG_UP_75)/sizeof(ixMC_IO_DEBUG_UP_75[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_76", REG_SMC, 0x004C, &ixMC_IO_DEBUG_UP_76[0], sizeof(ixMC_IO_DEBUG_UP_76)/sizeof(ixMC_IO_DEBUG_UP_76[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_77", REG_SMC, 0x004D, &ixMC_IO_DEBUG_UP_77[0], sizeof(ixMC_IO_DEBUG_UP_77)/sizeof(ixMC_IO_DEBUG_UP_77[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_78", REG_SMC, 0x004E, &ixMC_IO_DEBUG_UP_78[0], sizeof(ixMC_IO_DEBUG_UP_78)/sizeof(ixMC_IO_DEBUG_UP_78[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_79", REG_SMC, 0x004F, &ixMC_IO_DEBUG_UP_79[0], sizeof(ixMC_IO_DEBUG_UP_79)/sizeof(ixMC_IO_DEBUG_UP_79[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_80", REG_SMC, 0x0050, &ixMC_IO_DEBUG_UP_80[0], sizeof(ixMC_IO_DEBUG_UP_80)/sizeof(ixMC_IO_DEBUG_UP_80[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_81", REG_SMC, 0x0051, &ixMC_IO_DEBUG_UP_81[0], sizeof(ixMC_IO_DEBUG_UP_81)/sizeof(ixMC_IO_DEBUG_UP_81[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_82", REG_SMC, 0x0052, &ixMC_IO_DEBUG_UP_82[0], sizeof(ixMC_IO_DEBUG_UP_82)/sizeof(ixMC_IO_DEBUG_UP_82[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_83", REG_SMC, 0x0053, &ixMC_IO_DEBUG_UP_83[0], sizeof(ixMC_IO_DEBUG_UP_83)/sizeof(ixMC_IO_DEBUG_UP_83[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_84", REG_SMC, 0x0054, &ixMC_IO_DEBUG_UP_84[0], sizeof(ixMC_IO_DEBUG_UP_84)/sizeof(ixMC_IO_DEBUG_UP_84[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_85", REG_SMC, 0x0055, &ixMC_IO_DEBUG_UP_85[0], sizeof(ixMC_IO_DEBUG_UP_85)/sizeof(ixMC_IO_DEBUG_UP_85[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_86", REG_SMC, 0x0056, &ixMC_IO_DEBUG_UP_86[0], sizeof(ixMC_IO_DEBUG_UP_86)/sizeof(ixMC_IO_DEBUG_UP_86[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_87", REG_SMC, 0x0057, &ixMC_IO_DEBUG_UP_87[0], sizeof(ixMC_IO_DEBUG_UP_87)/sizeof(ixMC_IO_DEBUG_UP_87[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_88", REG_SMC, 0x0058, &ixMC_IO_DEBUG_UP_88[0], sizeof(ixMC_IO_DEBUG_UP_88)/sizeof(ixMC_IO_DEBUG_UP_88[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_89", REG_SMC, 0x0059, &ixMC_IO_DEBUG_UP_89[0], sizeof(ixMC_IO_DEBUG_UP_89)/sizeof(ixMC_IO_DEBUG_UP_89[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_90", REG_SMC, 0x005A, &ixMC_IO_DEBUG_UP_90[0], sizeof(ixMC_IO_DEBUG_UP_90)/sizeof(ixMC_IO_DEBUG_UP_90[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_91", REG_SMC, 0x005B, &ixMC_IO_DEBUG_UP_91[0], sizeof(ixMC_IO_DEBUG_UP_91)/sizeof(ixMC_IO_DEBUG_UP_91[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_92", REG_SMC, 0x005C, &ixMC_IO_DEBUG_UP_92[0], sizeof(ixMC_IO_DEBUG_UP_92)/sizeof(ixMC_IO_DEBUG_UP_92[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_93", REG_SMC, 0x005D, &ixMC_IO_DEBUG_UP_93[0], sizeof(ixMC_IO_DEBUG_UP_93)/sizeof(ixMC_IO_DEBUG_UP_93[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_94", REG_SMC, 0x005E, &ixMC_IO_DEBUG_UP_94[0], sizeof(ixMC_IO_DEBUG_UP_94)/sizeof(ixMC_IO_DEBUG_UP_94[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_95", REG_SMC, 0x005F, &ixMC_IO_DEBUG_UP_95[0], sizeof(ixMC_IO_DEBUG_UP_95)/sizeof(ixMC_IO_DEBUG_UP_95[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_96", REG_SMC, 0x0060, &ixMC_IO_DEBUG_UP_96[0], sizeof(ixMC_IO_DEBUG_UP_96)/sizeof(ixMC_IO_DEBUG_UP_96[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_97", REG_SMC, 0x0061, &ixMC_IO_DEBUG_UP_97[0], sizeof(ixMC_IO_DEBUG_UP_97)/sizeof(ixMC_IO_DEBUG_UP_97[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_98", REG_SMC, 0x0062, &ixMC_IO_DEBUG_UP_98[0], sizeof(ixMC_IO_DEBUG_UP_98)/sizeof(ixMC_IO_DEBUG_UP_98[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_99", REG_SMC, 0x0063, &ixMC_IO_DEBUG_UP_99[0], sizeof(ixMC_IO_DEBUG_UP_99)/sizeof(ixMC_IO_DEBUG_UP_99[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_100", REG_SMC, 0x0064, &ixMC_IO_DEBUG_UP_100[0], sizeof(ixMC_IO_DEBUG_UP_100)/sizeof(ixMC_IO_DEBUG_UP_100[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_101", REG_SMC, 0x0065, &ixMC_IO_DEBUG_UP_101[0], sizeof(ixMC_IO_DEBUG_UP_101)/sizeof(ixMC_IO_DEBUG_UP_101[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_102", REG_SMC, 0x0066, &ixMC_IO_DEBUG_UP_102[0], sizeof(ixMC_IO_DEBUG_UP_102)/sizeof(ixMC_IO_DEBUG_UP_102[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_103", REG_SMC, 0x0067, &ixMC_IO_DEBUG_UP_103[0], sizeof(ixMC_IO_DEBUG_UP_103)/sizeof(ixMC_IO_DEBUG_UP_103[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_104", REG_SMC, 0x0068, &ixMC_IO_DEBUG_UP_104[0], sizeof(ixMC_IO_DEBUG_UP_104)/sizeof(ixMC_IO_DEBUG_UP_104[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_105", REG_SMC, 0x0069, &ixMC_IO_DEBUG_UP_105[0], sizeof(ixMC_IO_DEBUG_UP_105)/sizeof(ixMC_IO_DEBUG_UP_105[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_106", REG_SMC, 0x006A, &ixMC_IO_DEBUG_UP_106[0], sizeof(ixMC_IO_DEBUG_UP_106)/sizeof(ixMC_IO_DEBUG_UP_106[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_107", REG_SMC, 0x006B, &ixMC_IO_DEBUG_UP_107[0], sizeof(ixMC_IO_DEBUG_UP_107)/sizeof(ixMC_IO_DEBUG_UP_107[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_108", REG_SMC, 0x006C, &ixMC_IO_DEBUG_UP_108[0], sizeof(ixMC_IO_DEBUG_UP_108)/sizeof(ixMC_IO_DEBUG_UP_108[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_109", REG_SMC, 0x006D, &ixMC_IO_DEBUG_UP_109[0], sizeof(ixMC_IO_DEBUG_UP_109)/sizeof(ixMC_IO_DEBUG_UP_109[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_110", REG_SMC, 0x006E, &ixMC_IO_DEBUG_UP_110[0], sizeof(ixMC_IO_DEBUG_UP_110)/sizeof(ixMC_IO_DEBUG_UP_110[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_111", REG_SMC, 0x006F, &ixMC_IO_DEBUG_UP_111[0], sizeof(ixMC_IO_DEBUG_UP_111)/sizeof(ixMC_IO_DEBUG_UP_111[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_112", REG_SMC, 0x0070, &ixMC_IO_DEBUG_UP_112[0], sizeof(ixMC_IO_DEBUG_UP_112)/sizeof(ixMC_IO_DEBUG_UP_112[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_113", REG_SMC, 0x0071, &ixMC_IO_DEBUG_UP_113[0], sizeof(ixMC_IO_DEBUG_UP_113)/sizeof(ixMC_IO_DEBUG_UP_113[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_114", REG_SMC, 0x0072, &ixMC_IO_DEBUG_UP_114[0], sizeof(ixMC_IO_DEBUG_UP_114)/sizeof(ixMC_IO_DEBUG_UP_114[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_115", REG_SMC, 0x0073, &ixMC_IO_DEBUG_UP_115[0], sizeof(ixMC_IO_DEBUG_UP_115)/sizeof(ixMC_IO_DEBUG_UP_115[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_116", REG_SMC, 0x0074, &ixMC_IO_DEBUG_UP_116[0], sizeof(ixMC_IO_DEBUG_UP_116)/sizeof(ixMC_IO_DEBUG_UP_116[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_117", REG_SMC, 0x0075, &ixMC_IO_DEBUG_UP_117[0], sizeof(ixMC_IO_DEBUG_UP_117)/sizeof(ixMC_IO_DEBUG_UP_117[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_118", REG_SMC, 0x0076, &ixMC_IO_DEBUG_UP_118[0], sizeof(ixMC_IO_DEBUG_UP_118)/sizeof(ixMC_IO_DEBUG_UP_118[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_119", REG_SMC, 0x0077, &ixMC_IO_DEBUG_UP_119[0], sizeof(ixMC_IO_DEBUG_UP_119)/sizeof(ixMC_IO_DEBUG_UP_119[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_120", REG_SMC, 0x0078, &ixMC_IO_DEBUG_UP_120[0], sizeof(ixMC_IO_DEBUG_UP_120)/sizeof(ixMC_IO_DEBUG_UP_120[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_121", REG_SMC, 0x0079, &ixMC_IO_DEBUG_UP_121[0], sizeof(ixMC_IO_DEBUG_UP_121)/sizeof(ixMC_IO_DEBUG_UP_121[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_122", REG_SMC, 0x007A, &ixMC_IO_DEBUG_UP_122[0], sizeof(ixMC_IO_DEBUG_UP_122)/sizeof(ixMC_IO_DEBUG_UP_122[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_123", REG_SMC, 0x007B, &ixMC_IO_DEBUG_UP_123[0], sizeof(ixMC_IO_DEBUG_UP_123)/sizeof(ixMC_IO_DEBUG_UP_123[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_124", REG_SMC, 0x007C, &ixMC_IO_DEBUG_UP_124[0], sizeof(ixMC_IO_DEBUG_UP_124)/sizeof(ixMC_IO_DEBUG_UP_124[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_125", REG_SMC, 0x007D, &ixMC_IO_DEBUG_UP_125[0], sizeof(ixMC_IO_DEBUG_UP_125)/sizeof(ixMC_IO_DEBUG_UP_125[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_126", REG_SMC, 0x007E, &ixMC_IO_DEBUG_UP_126[0], sizeof(ixMC_IO_DEBUG_UP_126)/sizeof(ixMC_IO_DEBUG_UP_126[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_127", REG_SMC, 0x007F, &ixMC_IO_DEBUG_UP_127[0], sizeof(ixMC_IO_DEBUG_UP_127)/sizeof(ixMC_IO_DEBUG_UP_127[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_128", REG_SMC, 0x0080, &ixMC_IO_DEBUG_UP_128[0], sizeof(ixMC_IO_DEBUG_UP_128)/sizeof(ixMC_IO_DEBUG_UP_128[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_129", REG_SMC, 0x0081, &ixMC_IO_DEBUG_UP_129[0], sizeof(ixMC_IO_DEBUG_UP_129)/sizeof(ixMC_IO_DEBUG_UP_129[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_130", REG_SMC, 0x0082, &ixMC_IO_DEBUG_UP_130[0], sizeof(ixMC_IO_DEBUG_UP_130)/sizeof(ixMC_IO_DEBUG_UP_130[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_131", REG_SMC, 0x0083, &ixMC_IO_DEBUG_UP_131[0], sizeof(ixMC_IO_DEBUG_UP_131)/sizeof(ixMC_IO_DEBUG_UP_131[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_132", REG_SMC, 0x0084, &ixMC_IO_DEBUG_UP_132[0], sizeof(ixMC_IO_DEBUG_UP_132)/sizeof(ixMC_IO_DEBUG_UP_132[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_133", REG_SMC, 0x0085, &ixMC_IO_DEBUG_UP_133[0], sizeof(ixMC_IO_DEBUG_UP_133)/sizeof(ixMC_IO_DEBUG_UP_133[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_134", REG_SMC, 0x0086, &ixMC_IO_DEBUG_UP_134[0], sizeof(ixMC_IO_DEBUG_UP_134)/sizeof(ixMC_IO_DEBUG_UP_134[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_135", REG_SMC, 0x0087, &ixMC_IO_DEBUG_UP_135[0], sizeof(ixMC_IO_DEBUG_UP_135)/sizeof(ixMC_IO_DEBUG_UP_135[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_136", REG_SMC, 0x0088, &ixMC_IO_DEBUG_UP_136[0], sizeof(ixMC_IO_DEBUG_UP_136)/sizeof(ixMC_IO_DEBUG_UP_136[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_137", REG_SMC, 0x0089, &ixMC_IO_DEBUG_UP_137[0], sizeof(ixMC_IO_DEBUG_UP_137)/sizeof(ixMC_IO_DEBUG_UP_137[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_138", REG_SMC, 0x008A, &ixMC_IO_DEBUG_UP_138[0], sizeof(ixMC_IO_DEBUG_UP_138)/sizeof(ixMC_IO_DEBUG_UP_138[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_139", REG_SMC, 0x008B, &ixMC_IO_DEBUG_UP_139[0], sizeof(ixMC_IO_DEBUG_UP_139)/sizeof(ixMC_IO_DEBUG_UP_139[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_140", REG_SMC, 0x008C, &ixMC_IO_DEBUG_UP_140[0], sizeof(ixMC_IO_DEBUG_UP_140)/sizeof(ixMC_IO_DEBUG_UP_140[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_141", REG_SMC, 0x008D, &ixMC_IO_DEBUG_UP_141[0], sizeof(ixMC_IO_DEBUG_UP_141)/sizeof(ixMC_IO_DEBUG_UP_141[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_142", REG_SMC, 0x008E, &ixMC_IO_DEBUG_UP_142[0], sizeof(ixMC_IO_DEBUG_UP_142)/sizeof(ixMC_IO_DEBUG_UP_142[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_143", REG_SMC, 0x008F, &ixMC_IO_DEBUG_UP_143[0], sizeof(ixMC_IO_DEBUG_UP_143)/sizeof(ixMC_IO_DEBUG_UP_143[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_144", REG_SMC, 0x0090, &ixMC_IO_DEBUG_UP_144[0], sizeof(ixMC_IO_DEBUG_UP_144)/sizeof(ixMC_IO_DEBUG_UP_144[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_145", REG_SMC, 0x0091, &ixMC_IO_DEBUG_UP_145[0], sizeof(ixMC_IO_DEBUG_UP_145)/sizeof(ixMC_IO_DEBUG_UP_145[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_146", REG_SMC, 0x0092, &ixMC_IO_DEBUG_UP_146[0], sizeof(ixMC_IO_DEBUG_UP_146)/sizeof(ixMC_IO_DEBUG_UP_146[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_147", REG_SMC, 0x0093, &ixMC_IO_DEBUG_UP_147[0], sizeof(ixMC_IO_DEBUG_UP_147)/sizeof(ixMC_IO_DEBUG_UP_147[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_148", REG_SMC, 0x0094, &ixMC_IO_DEBUG_UP_148[0], sizeof(ixMC_IO_DEBUG_UP_148)/sizeof(ixMC_IO_DEBUG_UP_148[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_149", REG_SMC, 0x0095, &ixMC_IO_DEBUG_UP_149[0], sizeof(ixMC_IO_DEBUG_UP_149)/sizeof(ixMC_IO_DEBUG_UP_149[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_150", REG_SMC, 0x0096, &ixMC_IO_DEBUG_UP_150[0], sizeof(ixMC_IO_DEBUG_UP_150)/sizeof(ixMC_IO_DEBUG_UP_150[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_151", REG_SMC, 0x0097, &ixMC_IO_DEBUG_UP_151[0], sizeof(ixMC_IO_DEBUG_UP_151)/sizeof(ixMC_IO_DEBUG_UP_151[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_152", REG_SMC, 0x0098, &ixMC_IO_DEBUG_UP_152[0], sizeof(ixMC_IO_DEBUG_UP_152)/sizeof(ixMC_IO_DEBUG_UP_152[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_153", REG_SMC, 0x0099, &ixMC_IO_DEBUG_UP_153[0], sizeof(ixMC_IO_DEBUG_UP_153)/sizeof(ixMC_IO_DEBUG_UP_153[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_154", REG_SMC, 0x009A, &ixMC_IO_DEBUG_UP_154[0], sizeof(ixMC_IO_DEBUG_UP_154)/sizeof(ixMC_IO_DEBUG_UP_154[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_155", REG_SMC, 0x009B, &ixMC_IO_DEBUG_UP_155[0], sizeof(ixMC_IO_DEBUG_UP_155)/sizeof(ixMC_IO_DEBUG_UP_155[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_156", REG_SMC, 0x009C, &ixMC_IO_DEBUG_UP_156[0], sizeof(ixMC_IO_DEBUG_UP_156)/sizeof(ixMC_IO_DEBUG_UP_156[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_157", REG_SMC, 0x009D, &ixMC_IO_DEBUG_UP_157[0], sizeof(ixMC_IO_DEBUG_UP_157)/sizeof(ixMC_IO_DEBUG_UP_157[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_158", REG_SMC, 0x009E, &ixMC_IO_DEBUG_UP_158[0], sizeof(ixMC_IO_DEBUG_UP_158)/sizeof(ixMC_IO_DEBUG_UP_158[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_UP_159", REG_SMC, 0x009F, &ixMC_IO_DEBUG_UP_159[0], sizeof(ixMC_IO_DEBUG_UP_159)/sizeof(ixMC_IO_DEBUG_UP_159[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_MISC_D0", REG_SMC, 0x00A0, &ixMC_IO_DEBUG_DQB0L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_MISC_D0", REG_SMC, 0x00A1, &ixMC_IO_DEBUG_DQB0H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_MISC_D0", REG_SMC, 0x00A2, &ixMC_IO_DEBUG_DQB1L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_MISC_D0", REG_SMC, 0x00A3, &ixMC_IO_DEBUG_DQB1H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_MISC_D0", REG_SMC, 0x00A4, &ixMC_IO_DEBUG_DQB2L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_MISC_D0", REG_SMC, 0x00A5, &ixMC_IO_DEBUG_DQB2H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_MISC_D0", REG_SMC, 0x00A6, &ixMC_IO_DEBUG_DQB3L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_MISC_D0", REG_SMC, 0x00A7, &ixMC_IO_DEBUG_DQB3H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_MISC_D0", REG_SMC, 0x00A8, &ixMC_IO_DEBUG_DBI_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D0)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_MISC_D0", REG_SMC, 0x00A9, &ixMC_IO_DEBUG_EDC_MISC_D0[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D0)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_MISC_D0", REG_SMC, 0x00AA, &ixMC_IO_DEBUG_WCK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_MISC_D0", REG_SMC, 0x00AB, &ixMC_IO_DEBUG_CK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D0)/sizeof(ixMC_IO_DEBUG_CK_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_MISC_D0", REG_SMC, 0x00AC, &ixMC_IO_DEBUG_ADDRL_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_MISC_D0", REG_SMC, 0x00AD, &ixMC_IO_DEBUG_ADDRH_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_MISC_D0", REG_SMC, 0x00AE, &ixMC_IO_DEBUG_ACMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_MISC_D0", REG_SMC, 0x00AF, &ixMC_IO_DEBUG_CMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_MISC_D1", REG_SMC, 0x00B0, &ixMC_IO_DEBUG_DQB0L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_MISC_D1", REG_SMC, 0x00B1, &ixMC_IO_DEBUG_DQB0H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_MISC_D1", REG_SMC, 0x00B2, &ixMC_IO_DEBUG_DQB1L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_MISC_D1", REG_SMC, 0x00B3, &ixMC_IO_DEBUG_DQB1H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_MISC_D1", REG_SMC, 0x00B4, &ixMC_IO_DEBUG_DQB2L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_MISC_D1", REG_SMC, 0x00B5, &ixMC_IO_DEBUG_DQB2H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_MISC_D1", REG_SMC, 0x00B6, &ixMC_IO_DEBUG_DQB3L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_MISC_D1", REG_SMC, 0x00B7, &ixMC_IO_DEBUG_DQB3H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_MISC_D1", REG_SMC, 0x00B8, &ixMC_IO_DEBUG_DBI_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D1)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_MISC_D1", REG_SMC, 0x00B9, &ixMC_IO_DEBUG_EDC_MISC_D1[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D1)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_MISC_D1", REG_SMC, 0x00BA, &ixMC_IO_DEBUG_WCK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_MISC_D1", REG_SMC, 0x00BB, &ixMC_IO_DEBUG_CK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D1)/sizeof(ixMC_IO_DEBUG_CK_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_MISC_D1", REG_SMC, 0x00BC, &ixMC_IO_DEBUG_ADDRL_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_MISC_D1", REG_SMC, 0x00BD, &ixMC_IO_DEBUG_ADDRH_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_MISC_D1", REG_SMC, 0x00BE, &ixMC_IO_DEBUG_ACMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_MISC_D1", REG_SMC, 0x00BF, &ixMC_IO_DEBUG_CMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D0", REG_SMC, 0x00C0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D0", REG_SMC, 0x00C1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D0", REG_SMC, 0x00C2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D0", REG_SMC, 0x00C3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D0", REG_SMC, 0x00C4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D0", REG_SMC, 0x00C5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D0", REG_SMC, 0x00C6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D0", REG_SMC, 0x00C7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D0", REG_SMC, 0x00C8, &ixMC_IO_DEBUG_DBI_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D0", REG_SMC, 0x00C9, &ixMC_IO_DEBUG_EDC_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D0", REG_SMC, 0x00CA, &ixMC_IO_DEBUG_WCK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_CLKSEL_D0", REG_SMC, 0x00CB, &ixMC_IO_DEBUG_CK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D0", REG_SMC, 0x00CC, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D0", REG_SMC, 0x00CD, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D0", REG_SMC, 0x00CE, &ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D0", REG_SMC, 0x00CF, &ixMC_IO_DEBUG_CMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D1", REG_SMC, 0x00D0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D1", REG_SMC, 0x00D1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D1", REG_SMC, 0x00D2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D1", REG_SMC, 0x00D3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D1", REG_SMC, 0x00D4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D1", REG_SMC, 0x00D5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D1", REG_SMC, 0x00D6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D1", REG_SMC, 0x00D7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D1", REG_SMC, 0x00D8, &ixMC_IO_DEBUG_DBI_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D1", REG_SMC, 0x00D9, &ixMC_IO_DEBUG_EDC_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D1", REG_SMC, 0x00DA, &ixMC_IO_DEBUG_WCK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_CLKSEL_D1", REG_SMC, 0x00DB, &ixMC_IO_DEBUG_CK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D1", REG_SMC, 0x00DC, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D1", REG_SMC, 0x00DD, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D1", REG_SMC, 0x00DE, &ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D1", REG_SMC, 0x00DF, &ixMC_IO_DEBUG_CMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D0", REG_SMC, 0x00E0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D0", REG_SMC, 0x00E1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D0", REG_SMC, 0x00E2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D0", REG_SMC, 0x00E3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D0", REG_SMC, 0x00E4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D0", REG_SMC, 0x00E5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D0", REG_SMC, 0x00E6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D0", REG_SMC, 0x00E7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D0", REG_SMC, 0x00E8, &ixMC_IO_DEBUG_DBI_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D0", REG_SMC, 0x00E9, &ixMC_IO_DEBUG_EDC_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D0", REG_SMC, 0x00EA, &ixMC_IO_DEBUG_WCK_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0", REG_SMC, 0x00EB, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0", REG_SMC, 0x00EC, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0", REG_SMC, 0x00ED, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D0", REG_SMC, 0x00EE, &ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D0", REG_SMC, 0x00EF, &ixMC_IO_DEBUG_CMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D1", REG_SMC, 0x00F0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D1", REG_SMC, 0x00F1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D1", REG_SMC, 0x00F2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D1", REG_SMC, 0x00F3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D1", REG_SMC, 0x00F4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D1", REG_SMC, 0x00F5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D1", REG_SMC, 0x00F6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D1", REG_SMC, 0x00F7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D1", REG_SMC, 0x00F8, &ixMC_IO_DEBUG_DBI_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D1", REG_SMC, 0x00F9, &ixMC_IO_DEBUG_EDC_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D1", REG_SMC, 0x00FA, &ixMC_IO_DEBUG_WCK_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1", REG_SMC, 0x00FB, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1", REG_SMC, 0x00FC, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1", REG_SMC, 0x00FD, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D1", REG_SMC, 0x00FE, &ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D1", REG_SMC, 0x00FF, &ixMC_IO_DEBUG_CMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D0", REG_SMC, 0x0100, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D0", REG_SMC, 0x0101, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D0", REG_SMC, 0x0102, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D0", REG_SMC, 0x0103, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D0", REG_SMC, 0x0104, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D0", REG_SMC, 0x0105, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D0", REG_SMC, 0x0106, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D0", REG_SMC, 0x0107, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D0", REG_SMC, 0x0108, &ixMC_IO_DEBUG_DBI_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D0", REG_SMC, 0x0109, &ixMC_IO_DEBUG_EDC_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D0", REG_SMC, 0x010A, &ixMC_IO_DEBUG_WCK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_RXPHASE_D0", REG_SMC, 0x010B, &ixMC_IO_DEBUG_CK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D0", REG_SMC, 0x010C, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D0", REG_SMC, 0x010D, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D0", REG_SMC, 0x010E, &ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D0", REG_SMC, 0x010F, &ixMC_IO_DEBUG_CMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D1", REG_SMC, 0x0110, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D1", REG_SMC, 0x0111, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D1", REG_SMC, 0x0112, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D1", REG_SMC, 0x0113, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D1", REG_SMC, 0x0114, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D1", REG_SMC, 0x0115, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D1", REG_SMC, 0x0116, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D1", REG_SMC, 0x0117, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D1", REG_SMC, 0x0118, &ixMC_IO_DEBUG_DBI_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D1", REG_SMC, 0x0119, &ixMC_IO_DEBUG_EDC_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D1", REG_SMC, 0x011A, &ixMC_IO_DEBUG_WCK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_RXPHASE_D1", REG_SMC, 0x011B, &ixMC_IO_DEBUG_CK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D1", REG_SMC, 0x011C, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D1", REG_SMC, 0x011D, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D1", REG_SMC, 0x011E, &ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D1", REG_SMC, 0x011F, &ixMC_IO_DEBUG_CMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D0", REG_SMC, 0x0120, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D0", REG_SMC, 0x0121, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D0", REG_SMC, 0x0122, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D0", REG_SMC, 0x0123, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D0", REG_SMC, 0x0124, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D0", REG_SMC, 0x0125, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D0", REG_SMC, 0x0126, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D0", REG_SMC, 0x0127, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D0", REG_SMC, 0x0128, &ixMC_IO_DEBUG_DBI_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D0", REG_SMC, 0x0129, &ixMC_IO_DEBUG_EDC_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D0", REG_SMC, 0x012A, &ixMC_IO_DEBUG_WCK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXPHASE_D0", REG_SMC, 0x012B, &ixMC_IO_DEBUG_CK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D0", REG_SMC, 0x012C, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D0", REG_SMC, 0x012D, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D0", REG_SMC, 0x012E, &ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D0", REG_SMC, 0x012F, &ixMC_IO_DEBUG_CMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D1", REG_SMC, 0x0130, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D1", REG_SMC, 0x0131, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D1", REG_SMC, 0x0132, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D1", REG_SMC, 0x0133, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D1", REG_SMC, 0x0134, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D1", REG_SMC, 0x0135, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D1", REG_SMC, 0x0136, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D1", REG_SMC, 0x0137, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D1", REG_SMC, 0x0138, &ixMC_IO_DEBUG_DBI_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D1", REG_SMC, 0x0139, &ixMC_IO_DEBUG_EDC_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D1", REG_SMC, 0x013A, &ixMC_IO_DEBUG_WCK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXPHASE_D1", REG_SMC, 0x013B, &ixMC_IO_DEBUG_CK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D1", REG_SMC, 0x013C, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D1", REG_SMC, 0x013D, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D1", REG_SMC, 0x013E, &ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D1", REG_SMC, 0x013F, &ixMC_IO_DEBUG_CMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0", REG_SMC, 0x0140, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0", REG_SMC, 0x0141, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0", REG_SMC, 0x0142, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0", REG_SMC, 0x0143, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0", REG_SMC, 0x0144, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0", REG_SMC, 0x0145, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0", REG_SMC, 0x0146, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0", REG_SMC, 0x0147, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0", REG_SMC, 0x0148, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0", REG_SMC, 0x0149, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0", REG_SMC, 0x014A, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0", REG_SMC, 0x014B, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0", REG_SMC, 0x014C, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0", REG_SMC, 0x014D, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0", REG_SMC, 0x014E, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0", REG_SMC, 0x014F, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1", REG_SMC, 0x0150, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1", REG_SMC, 0x0151, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1", REG_SMC, 0x0152, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1", REG_SMC, 0x0153, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1", REG_SMC, 0x0154, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1", REG_SMC, 0x0155, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1", REG_SMC, 0x0156, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1", REG_SMC, 0x0157, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1", REG_SMC, 0x0158, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1", REG_SMC, 0x0159, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1", REG_SMC, 0x015A, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1", REG_SMC, 0x015B, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1", REG_SMC, 0x015C, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1", REG_SMC, 0x015D, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1", REG_SMC, 0x015E, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1", REG_SMC, 0x015F, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D0", REG_SMC, 0x0160, &ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D0", REG_SMC, 0x0161, &ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D0", REG_SMC, 0x0162, &ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D0", REG_SMC, 0x0163, &ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D0", REG_SMC, 0x0164, &ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D0", REG_SMC, 0x0165, &ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D0", REG_SMC, 0x0166, &ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D0", REG_SMC, 0x0167, &ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXSLF_D0", REG_SMC, 0x0168, &ixMC_IO_DEBUG_DBI_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXSLF_D0", REG_SMC, 0x0169, &ixMC_IO_DEBUG_EDC_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXSLF_D0", REG_SMC, 0x016A, &ixMC_IO_DEBUG_WCK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXSLF_D0", REG_SMC, 0x016B, &ixMC_IO_DEBUG_CK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D0", REG_SMC, 0x016C, &ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D0", REG_SMC, 0x016D, &ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D0", REG_SMC, 0x016E, &ixMC_IO_DEBUG_ACMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXSLF_D0", REG_SMC, 0x016F, &ixMC_IO_DEBUG_CMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D1", REG_SMC, 0x0170, &ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D1", REG_SMC, 0x0171, &ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D1", REG_SMC, 0x0172, &ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D1", REG_SMC, 0x0173, &ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D1", REG_SMC, 0x0174, &ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D1", REG_SMC, 0x0175, &ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D1", REG_SMC, 0x0176, &ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D1", REG_SMC, 0x0177, &ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXSLF_D1", REG_SMC, 0x0178, &ixMC_IO_DEBUG_DBI_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXSLF_D1", REG_SMC, 0x0179, &ixMC_IO_DEBUG_EDC_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXSLF_D1", REG_SMC, 0x017A, &ixMC_IO_DEBUG_WCK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXSLF_D1", REG_SMC, 0x017B, &ixMC_IO_DEBUG_CK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D1", REG_SMC, 0x017C, &ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D1", REG_SMC, 0x017D, &ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D1", REG_SMC, 0x017E, &ixMC_IO_DEBUG_ACMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXSLF_D1", REG_SMC, 0x017F, &ixMC_IO_DEBUG_CMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0", REG_SMC, 0x0180, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0", REG_SMC, 0x0181, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0", REG_SMC, 0x0182, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0", REG_SMC, 0x0183, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0", REG_SMC, 0x0184, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0", REG_SMC, 0x0185, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0", REG_SMC, 0x0186, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0", REG_SMC, 0x0187, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D0", REG_SMC, 0x0188, &ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D0", REG_SMC, 0x0189, &ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D0", REG_SMC, 0x018A, &ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D0", REG_SMC, 0x018B, &ixMC_IO_DEBUG_CK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0", REG_SMC, 0x018C, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0", REG_SMC, 0x018D, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D0", REG_SMC, 0x018E, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D0", REG_SMC, 0x018F, &ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1", REG_SMC, 0x0190, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1", REG_SMC, 0x0191, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1", REG_SMC, 0x0192, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1", REG_SMC, 0x0193, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1", REG_SMC, 0x0194, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1", REG_SMC, 0x0195, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1", REG_SMC, 0x0196, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1", REG_SMC, 0x0197, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D1", REG_SMC, 0x0198, &ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D1", REG_SMC, 0x0199, &ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D1", REG_SMC, 0x019A, &ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D1", REG_SMC, 0x019B, &ixMC_IO_DEBUG_CK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1", REG_SMC, 0x019C, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1", REG_SMC, 0x019D, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D1", REG_SMC, 0x019E, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D1", REG_SMC, 0x019F, &ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0", REG_SMC, 0x01A0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0", REG_SMC, 0x01A1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0", REG_SMC, 0x01A2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0", REG_SMC, 0x01A3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0", REG_SMC, 0x01A4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0", REG_SMC, 0x01A5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0", REG_SMC, 0x01A6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0", REG_SMC, 0x01A7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D0", REG_SMC, 0x01A8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D0", REG_SMC, 0x01A9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D0", REG_SMC, 0x01AA, &ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D0", REG_SMC, 0x01AB, &ixMC_IO_DEBUG_CK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0", REG_SMC, 0x01AC, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0", REG_SMC, 0x01AD, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D0", REG_SMC, 0x01AE, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D0", REG_SMC, 0x01AF, &ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1", REG_SMC, 0x01B0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1", REG_SMC, 0x01B1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1", REG_SMC, 0x01B2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1", REG_SMC, 0x01B3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1", REG_SMC, 0x01B4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1", REG_SMC, 0x01B5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1", REG_SMC, 0x01B6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1", REG_SMC, 0x01B7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D1", REG_SMC, 0x01B8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D1", REG_SMC, 0x01B9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D1", REG_SMC, 0x01BA, &ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D1", REG_SMC, 0x01BB, &ixMC_IO_DEBUG_CK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1", REG_SMC, 0x01BC, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1", REG_SMC, 0x01BD, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D1", REG_SMC, 0x01BE, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D1", REG_SMC, 0x01BF, &ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D0", REG_SMC, 0x01C0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D0", REG_SMC, 0x01C1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D0", REG_SMC, 0x01C2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D0", REG_SMC, 0x01C3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D0", REG_SMC, 0x01C4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D0", REG_SMC, 0x01C5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D0", REG_SMC, 0x01C6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D0", REG_SMC, 0x01C7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D0", REG_SMC, 0x01C8, &ixMC_IO_DEBUG_DBI_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D0", REG_SMC, 0x01C9, &ixMC_IO_DEBUG_EDC_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D0", REG_SMC, 0x01CA, &ixMC_IO_DEBUG_WCK_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0", REG_SMC, 0x01CB, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0", REG_SMC, 0x01CC, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0", REG_SMC, 0x01CD, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0", REG_SMC, 0x01CE, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D0", REG_SMC, 0x01CF, &ixMC_IO_DEBUG_CMD_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D1", REG_SMC, 0x01D0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D1", REG_SMC, 0x01D1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D1", REG_SMC, 0x01D2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D1", REG_SMC, 0x01D3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D1", REG_SMC, 0x01D4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D1", REG_SMC, 0x01D5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D1", REG_SMC, 0x01D6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D1", REG_SMC, 0x01D7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D1", REG_SMC, 0x01D8, &ixMC_IO_DEBUG_DBI_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D1", REG_SMC, 0x01D9, &ixMC_IO_DEBUG_EDC_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D1", REG_SMC, 0x01DA, &ixMC_IO_DEBUG_WCK_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1", REG_SMC, 0x01DB, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1", REG_SMC, 0x01DC, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1", REG_SMC, 0x01DD, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1", REG_SMC, 0x01DE, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D1", REG_SMC, 0x01DF, &ixMC_IO_DEBUG_CMD_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_MISC_D0", REG_SMC, 0x01E0, &ixMC_IO_DEBUG_WCDR_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D0", REG_SMC, 0x01E1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D0", REG_SMC, 0x01E2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D0", REG_SMC, 0x01E3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D0", REG_SMC, 0x01E4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0", REG_SMC, 0x01E5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D0", REG_SMC, 0x01E6, &ixMC_IO_DEBUG_WCDR_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D0", REG_SMC, 0x01E7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D0", REG_SMC, 0x01E8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D0", REG_SMC, 0x01E9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0", REG_SMC, 0x01EA, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0", REG_SMC, 0x01EB, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0", REG_SMC, 0x01EC, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_MISC_D1", REG_SMC, 0x01F0, &ixMC_IO_DEBUG_WCDR_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D1", REG_SMC, 0x01F1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D1", REG_SMC, 0x01F2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D1", REG_SMC, 0x01F3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D1", REG_SMC, 0x01F4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1", REG_SMC, 0x01F5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D1", REG_SMC, 0x01F6, &ixMC_IO_DEBUG_WCDR_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D1", REG_SMC, 0x01F7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D1", REG_SMC, 0x01F8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D1", REG_SMC, 0x01F9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1", REG_SMC, 0x01FA, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1", REG_SMC, 0x01FB, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0]), 0, 0 },
	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1", REG_SMC, 0x01FC, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0]), 0, 0 },
	{ "mmVM_L2_CNTL", REG_MMIO, 0x0500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
	{ "mmVM_L2_CNTL2", REG_MMIO, 0x0501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
	{ "mmVM_L2_CNTL3", REG_MMIO, 0x0502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
	{ "mmVM_L2_STATUS", REG_MMIO, 0x0503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x0504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x0505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x0506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x0507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x050C, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x050D, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x050E, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x050F, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x051E, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x051F, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x052C, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x052D, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x052E, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x052F, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x0530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x0531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x0532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x0533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
	{ "mmVM_PRT_CNTL", REG_MMIO, 0x0534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x0535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x0536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x0537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x053E, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x053F, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x0546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x0547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x054E, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x054F, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x0557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x0558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x055F, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x0560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
	{ "mmVM_DEBUG", REG_MMIO, 0x056F, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
	{ "mmVM_L2_CG", REG_MMIO, 0x0570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x0572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x0573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x0575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x0576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x0577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
	{ "mmMC_CONFIG", REG_MMIO, 0x0800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x0801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x0802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x0803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x0804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x0805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x0806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x0807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x0808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x0809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x080A, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x080B, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x080C, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x080D, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x080E, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x080F, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x0810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x0811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x0812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x0813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x0814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x0815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x0816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x0817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x0818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x081A, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x0828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x0829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x082A, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x082B, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x082D, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x082E, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x082F, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x0830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
	{ "mmMC_HUB_MISC_DBG", REG_MMIO, 0x0831, &mmMC_HUB_MISC_DBG[0], sizeof(mmMC_HUB_MISC_DBG)/sizeof(mmMC_HUB_MISC_DBG[0]), 0, 0 },
	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x0832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x0833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x0834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x0835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x0836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x0837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x0838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x0839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x083A, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x083B, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x083C, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x083D, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x083E, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x083F, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MGPU2", REG_MMIO, 0x0840, &mmMC_HUB_WDP_MGPU2[0], sizeof(mmMC_HUB_WDP_MGPU2)/sizeof(mmMC_HUB_WDP_MGPU2[0]), 0, 0 },
	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x0841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x0842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MGPU", REG_MMIO, 0x0843, &mmMC_HUB_WDP_MGPU[0], sizeof(mmMC_HUB_WDP_MGPU)/sizeof(mmMC_HUB_WDP_MGPU[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x0844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x0845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x0846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x0847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x0848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x0851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x0852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x0853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x0854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x0855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x0856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x0857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x0858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x085B, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x085D, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x085E, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_VCE", REG_MMIO, 0x085F, &mmMC_HUB_RDREQ_VCE[0], sizeof(mmMC_HUB_RDREQ_VCE)/sizeof(mmMC_HUB_RDREQ_VCE[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x0860, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x0861, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x0863, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x0864, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x0865, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_VCEU", REG_MMIO, 0x0866, &mmMC_HUB_RDREQ_VCEU[0], sizeof(mmMC_HUB_RDREQ_VCEU)/sizeof(mmMC_HUB_RDREQ_VCEU[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x0867, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x0868, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x0869, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x086A, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x086B, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x086E, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x086F, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
	{ "mmMC_HUB_WDP_VCE", REG_MMIO, 0x0870, &mmMC_HUB_WDP_VCE[0], sizeof(mmMC_HUB_WDP_VCE)/sizeof(mmMC_HUB_WDP_VCE[0]), 0, 0 },
	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x0871, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x0872, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x0873, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x0874, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x0875, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x0876, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x0877, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x0878, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x0879, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x087B, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x087C, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x087D, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x087E, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
	{ "mmMC_HUB_WDP_VCEU", REG_MMIO, 0x087F, &mmMC_HUB_WDP_VCEU[0], sizeof(mmMC_HUB_WDP_VCEU)/sizeof(mmMC_HUB_WDP_VCEU[0]), 0, 0 },
	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x0880, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x0881, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x0882, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x0891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x0893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x0895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x0896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x0897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x08A1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x08A5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x08A6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x08CD, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x08CE, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x08CF, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x08D0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x08D1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x08D2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x08D3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x08D4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x08D5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x08D6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x08D7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x08D8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x08D9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x08DA, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x08DB, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x08DC, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x08DD, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x08DE, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x08DF, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x08E0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x08E1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x08E2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x08E3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x08E4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x08E5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x08E6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x08E7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x08E8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x08E9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x08EA, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x08EB, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x08EC, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x08ED, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x08EE, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x08EF, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x08F0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x08F1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x08F2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x08F3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x08F4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x08F5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x08F6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x08F7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x08F8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x08F9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x08FA, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x08FB, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x08FC, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x08FD, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x08FE, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x08FF, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x0900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x0901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x0902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x0903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x0904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x0905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x0906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x0907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x0908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x0909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x090A, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x090B, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x090C, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x090D, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x090E, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x090F, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x0910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x0911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x0912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x0913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x0914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x0915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x0916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x0917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x0918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x0919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x091A, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x091B, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x091C, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x091D, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x091E, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x091F, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x0920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x0921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x0922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x0923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x0924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
	{ "mmMC_XPB_STICKY", REG_MMIO, 0x0925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x0926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x0927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x0928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x0929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x092A, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x092B, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x092C, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x092D, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x092E, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x092F, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x0930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x0931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x0932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x0933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x0934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x0935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x0936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x0937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x0938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x0939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x093A, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
	{ "mmMC_RPB_CONF", REG_MMIO, 0x094D, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x094E, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
	{ "mmMC_RPB_DBG1", REG_MMIO, 0x094F, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x0950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x0951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x0952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x0953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x0954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x0955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x0956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x0957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x0958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x0959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x095A, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x095B, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x096D, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x096E, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
	{ "mmMC_CG_CONFIG", REG_MMIO, 0x096F, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
	{ "mmMC_CITF_CNTL", REG_MMIO, 0x0970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x0971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x0972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x0973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x0974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x0975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x0976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x0977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x0978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x0979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x097A, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
	{ "mmMC_WR_TC0", REG_MMIO, 0x097B, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
	{ "mmMC_WR_TC1", REG_MMIO, 0x097C, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x097D, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x097F, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x0980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
	{ "mmMC_RD_CB", REG_MMIO, 0x0981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
	{ "mmMC_RD_DB", REG_MMIO, 0x0982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
	{ "mmMC_RD_TC0", REG_MMIO, 0x0983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
	{ "mmMC_RD_TC1", REG_MMIO, 0x0984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
	{ "mmMC_RD_HUB", REG_MMIO, 0x0985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
	{ "mmMC_WR_CB", REG_MMIO, 0x0986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
	{ "mmMC_WR_DB", REG_MMIO, 0x0987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
	{ "mmMC_WR_HUB", REG_MMIO, 0x0988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x0989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x098A, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x098B, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x098E, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x0991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x0992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x0993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x0994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x0998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x0999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x099A, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x099B, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x099C, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x099D, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x09A4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x09A7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x09A8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x09C1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x09C2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x09C3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x09C4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x09C5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
	{ "mmMC_ARB_GECC2", REG_MMIO, 0x09C9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x09CA, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
	{ "mmMC_ARB_WCDR_2", REG_MMIO, 0x09CE, &mmMC_ARB_WCDR_2[0], sizeof(mmMC_ARB_WCDR_2)/sizeof(mmMC_ARB_WCDR_2[0]), 0, 0 },
	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x09CF, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x09D0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x09D1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x09D2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x09D3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x09D4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_MISC2", REG_MMIO, 0x09D5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
	{ "mmMC_ARB_MISC", REG_MMIO, 0x09D6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x09D7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x09D8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
	{ "mmMC_ARB_POP", REG_MMIO, 0x09D9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x09DA, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x09DB, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x09DC, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x09DD, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x09DE, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x09DF, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x09E0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x09E1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x09E2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x09E3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x09E4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x09E5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x09E6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x09E7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x09E8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x09E9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x09EA, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x09EB, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x09EC, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x09ED, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x09EE, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x09EF, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x09F0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x09F1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x09F2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x09F3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x09F4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x09F5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
	{ "mmMC_ARB_CG", REG_MMIO, 0x09FA, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
	{ "mmMC_ARB_WCDR", REG_MMIO, 0x09FB, &mmMC_ARB_WCDR[0], sizeof(mmMC_ARB_WCDR)/sizeof(mmMC_ARB_WCDR[0]), 0, 0 },
	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x09FC, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x09FF, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0x0A02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
	{ "mmMC_BIST_CNTL", REG_MMIO, 0x0A05, &mmMC_BIST_CNTL[0], sizeof(mmMC_BIST_CNTL)/sizeof(mmMC_BIST_CNTL[0]), 0, 0 },
	{ "mmMC_BIST_AUTO_CNTL", REG_MMIO, 0x0A06, &mmMC_BIST_AUTO_CNTL[0], sizeof(mmMC_BIST_AUTO_CNTL)/sizeof(mmMC_BIST_AUTO_CNTL[0]), 0, 0 },
	{ "mmMC_BIST_DIR_CNTL", REG_MMIO, 0x0A07, &mmMC_BIST_DIR_CNTL[0], sizeof(mmMC_BIST_DIR_CNTL)/sizeof(mmMC_BIST_DIR_CNTL[0]), 0, 0 },
	{ "mmMC_BIST_SADDR", REG_MMIO, 0x0A08, &mmMC_BIST_SADDR[0], sizeof(mmMC_BIST_SADDR)/sizeof(mmMC_BIST_SADDR[0]), 0, 0 },
	{ "mmMC_BIST_EADDR", REG_MMIO, 0x0A09, &mmMC_BIST_EADDR[0], sizeof(mmMC_BIST_EADDR)/sizeof(mmMC_BIST_EADDR[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD0", REG_MMIO, 0x0A0A, &mmMC_BIST_DATA_WORD0[0], sizeof(mmMC_BIST_DATA_WORD0)/sizeof(mmMC_BIST_DATA_WORD0[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD1", REG_MMIO, 0x0A0B, &mmMC_BIST_DATA_WORD1[0], sizeof(mmMC_BIST_DATA_WORD1)/sizeof(mmMC_BIST_DATA_WORD1[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD2", REG_MMIO, 0x0A0C, &mmMC_BIST_DATA_WORD2[0], sizeof(mmMC_BIST_DATA_WORD2)/sizeof(mmMC_BIST_DATA_WORD2[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD3", REG_MMIO, 0x0A0D, &mmMC_BIST_DATA_WORD3[0], sizeof(mmMC_BIST_DATA_WORD3)/sizeof(mmMC_BIST_DATA_WORD3[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD4", REG_MMIO, 0x0A0E, &mmMC_BIST_DATA_WORD4[0], sizeof(mmMC_BIST_DATA_WORD4)/sizeof(mmMC_BIST_DATA_WORD4[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD5", REG_MMIO, 0x0A0F, &mmMC_BIST_DATA_WORD5[0], sizeof(mmMC_BIST_DATA_WORD5)/sizeof(mmMC_BIST_DATA_WORD5[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD6", REG_MMIO, 0x0A10, &mmMC_BIST_DATA_WORD6[0], sizeof(mmMC_BIST_DATA_WORD6)/sizeof(mmMC_BIST_DATA_WORD6[0]), 0, 0 },
	{ "mmMC_BIST_DATA_WORD7", REG_MMIO, 0x0A11, &mmMC_BIST_DATA_WORD7[0], sizeof(mmMC_BIST_DATA_WORD7)/sizeof(mmMC_BIST_DATA_WORD7[0]), 0, 0 },
	{ "mmMC_BIST_DATA_MASK", REG_MMIO, 0x0A12, &mmMC_BIST_DATA_MASK[0], sizeof(mmMC_BIST_DATA_MASK)/sizeof(mmMC_BIST_DATA_MASK[0]), 0, 0 },
	{ "mmMC_BIST_MISMATCH_ADDR", REG_MMIO, 0x0A13, &mmMC_BIST_MISMATCH_ADDR[0], sizeof(mmMC_BIST_MISMATCH_ADDR)/sizeof(mmMC_BIST_MISMATCH_ADDR[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD0", REG_MMIO, 0x0A14, &mmMC_BIST_RDATA_WORD0[0], sizeof(mmMC_BIST_RDATA_WORD0)/sizeof(mmMC_BIST_RDATA_WORD0[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD1", REG_MMIO, 0x0A15, &mmMC_BIST_RDATA_WORD1[0], sizeof(mmMC_BIST_RDATA_WORD1)/sizeof(mmMC_BIST_RDATA_WORD1[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD2", REG_MMIO, 0x0A16, &mmMC_BIST_RDATA_WORD2[0], sizeof(mmMC_BIST_RDATA_WORD2)/sizeof(mmMC_BIST_RDATA_WORD2[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD3", REG_MMIO, 0x0A17, &mmMC_BIST_RDATA_WORD3[0], sizeof(mmMC_BIST_RDATA_WORD3)/sizeof(mmMC_BIST_RDATA_WORD3[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD4", REG_MMIO, 0x0A18, &mmMC_BIST_RDATA_WORD4[0], sizeof(mmMC_BIST_RDATA_WORD4)/sizeof(mmMC_BIST_RDATA_WORD4[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD5", REG_MMIO, 0x0A19, &mmMC_BIST_RDATA_WORD5[0], sizeof(mmMC_BIST_RDATA_WORD5)/sizeof(mmMC_BIST_RDATA_WORD5[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD6", REG_MMIO, 0x0A1A, &mmMC_BIST_RDATA_WORD6[0], sizeof(mmMC_BIST_RDATA_WORD6)/sizeof(mmMC_BIST_RDATA_WORD6[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_WORD7", REG_MMIO, 0x0A1B, &mmMC_BIST_RDATA_WORD7[0], sizeof(mmMC_BIST_RDATA_WORD7)/sizeof(mmMC_BIST_RDATA_WORD7[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_MASK", REG_MMIO, 0x0A1C, &mmMC_BIST_RDATA_MASK[0], sizeof(mmMC_BIST_RDATA_MASK)/sizeof(mmMC_BIST_RDATA_MASK[0]), 0, 0 },
	{ "mmMC_BIST_RDATA_EDC", REG_MMIO, 0x0A1D, &mmMC_BIST_RDATA_EDC[0], sizeof(mmMC_BIST_RDATA_EDC)/sizeof(mmMC_BIST_RDATA_EDC[0]), 0, 0 },
	{ "mmMC_SEQ_RESERVE_0_S", REG_MMIO, 0x0A1E, &mmMC_SEQ_RESERVE_0_S[0], sizeof(mmMC_SEQ_RESERVE_0_S)/sizeof(mmMC_SEQ_RESERVE_0_S[0]), 0, 0 },
	{ "mmMC_SEQ_RESERVE_1_S", REG_MMIO, 0x0A1F, &mmMC_SEQ_RESERVE_1_S[0], sizeof(mmMC_SEQ_RESERVE_1_S)/sizeof(mmMC_SEQ_RESERVE_1_S[0]), 0, 0 },
	{ "mmMC_SEQ_STATUS_S", REG_MMIO, 0x0A20, &mmMC_SEQ_STATUS_S[0], sizeof(mmMC_SEQ_STATUS_S)/sizeof(mmMC_SEQ_STATUS_S[0]), 0, 0 },
	{ "mmMC_CG_DATAPORT", REG_MMIO, 0x0A21, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
	{ "mmMC_SEQ_MPLL_OVERRIDE", REG_MMIO, 0x0A22, &mmMC_SEQ_MPLL_OVERRIDE[0], sizeof(mmMC_SEQ_MPLL_OVERRIDE)/sizeof(mmMC_SEQ_MPLL_OVERRIDE[0]), 0, 0 },
	{ "mmMC_SEQ_CNTL", REG_MMIO, 0x0A25, &mmMC_SEQ_CNTL[0], sizeof(mmMC_SEQ_CNTL)/sizeof(mmMC_SEQ_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_DRAM", REG_MMIO, 0x0A26, &mmMC_SEQ_DRAM[0], sizeof(mmMC_SEQ_DRAM)/sizeof(mmMC_SEQ_DRAM[0]), 0, 0 },
	{ "mmMC_SEQ_DRAM_2", REG_MMIO, 0x0A27, &mmMC_SEQ_DRAM_2[0], sizeof(mmMC_SEQ_DRAM_2)/sizeof(mmMC_SEQ_DRAM_2[0]), 0, 0 },
	{ "mmMC_SEQ_RAS_TIMING", REG_MMIO, 0x0A28, &mmMC_SEQ_RAS_TIMING[0], sizeof(mmMC_SEQ_RAS_TIMING)/sizeof(mmMC_SEQ_RAS_TIMING[0]), 0, 0 },
	{ "mmMC_SEQ_CAS_TIMING", REG_MMIO, 0x0A29, &mmMC_SEQ_CAS_TIMING[0], sizeof(mmMC_SEQ_CAS_TIMING)/sizeof(mmMC_SEQ_CAS_TIMING[0]), 0, 0 },
	{ "mmMC_SEQ_MISC_TIMING", REG_MMIO, 0x0A2A, &mmMC_SEQ_MISC_TIMING[0], sizeof(mmMC_SEQ_MISC_TIMING)/sizeof(mmMC_SEQ_MISC_TIMING[0]), 0, 0 },
	{ "mmMC_SEQ_MISC_TIMING2", REG_MMIO, 0x0A2B, &mmMC_SEQ_MISC_TIMING2[0], sizeof(mmMC_SEQ_MISC_TIMING2)/sizeof(mmMC_SEQ_MISC_TIMING2[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_TIMING", REG_MMIO, 0x0A2C, &mmMC_SEQ_PMG_TIMING[0], sizeof(mmMC_SEQ_PMG_TIMING)/sizeof(mmMC_SEQ_PMG_TIMING[0]), 0, 0 },
	{ "mmMC_SEQ_RD_CTL_D0", REG_MMIO, 0x0A2D, &mmMC_SEQ_RD_CTL_D0[0], sizeof(mmMC_SEQ_RD_CTL_D0)/sizeof(mmMC_SEQ_RD_CTL_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RD_CTL_D1", REG_MMIO, 0x0A2E, &mmMC_SEQ_RD_CTL_D1[0], sizeof(mmMC_SEQ_RD_CTL_D1)/sizeof(mmMC_SEQ_RD_CTL_D1[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_D0", REG_MMIO, 0x0A2F, &mmMC_SEQ_WR_CTL_D0[0], sizeof(mmMC_SEQ_WR_CTL_D0)/sizeof(mmMC_SEQ_WR_CTL_D0[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_D1", REG_MMIO, 0x0A30, &mmMC_SEQ_WR_CTL_D1[0], sizeof(mmMC_SEQ_WR_CTL_D1)/sizeof(mmMC_SEQ_WR_CTL_D1[0]), 0, 0 },
	{ "mmMC_SEQ_CMD", REG_MMIO, 0x0A31, &mmMC_SEQ_CMD[0], sizeof(mmMC_SEQ_CMD)/sizeof(mmMC_SEQ_CMD[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_CNTL", REG_MMIO, 0x0A32, &mmMC_SEQ_SUP_CNTL[0], sizeof(mmMC_SEQ_SUP_CNTL)/sizeof(mmMC_SEQ_SUP_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_PGM", REG_MMIO, 0x0A33, &mmMC_SEQ_SUP_PGM[0], sizeof(mmMC_SEQ_SUP_PGM)/sizeof(mmMC_SEQ_SUP_PGM[0]), 0, 0 },
	{ "mmMC_PMG_AUTO_CMD", REG_MMIO, 0x0A34, &mmMC_PMG_AUTO_CMD[0], sizeof(mmMC_PMG_AUTO_CMD)/sizeof(mmMC_PMG_AUTO_CMD[0]), 0, 0 },
	{ "mmMC_PMG_AUTO_CFG", REG_MMIO, 0x0A35, &mmMC_PMG_AUTO_CFG[0], sizeof(mmMC_PMG_AUTO_CFG)/sizeof(mmMC_PMG_AUTO_CFG[0]), 0, 0 },
	{ "mmMC_IMP_CNTL", REG_MMIO, 0x0A36, &mmMC_IMP_CNTL[0], sizeof(mmMC_IMP_CNTL)/sizeof(mmMC_IMP_CNTL[0]), 0, 0 },
	{ "mmMC_IMP_DEBUG", REG_MMIO, 0x0A37, &mmMC_IMP_DEBUG[0], sizeof(mmMC_IMP_DEBUG)/sizeof(mmMC_IMP_DEBUG[0]), 0, 0 },
	{ "mmMC_IMP_STATUS", REG_MMIO, 0x0A38, &mmMC_IMP_STATUS[0], sizeof(mmMC_IMP_STATUS)/sizeof(mmMC_IMP_STATUS[0]), 0, 0 },
	{ "mmMC_SEQ_WCDR_CTRL", REG_MMIO, 0x0A39, &mmMC_SEQ_WCDR_CTRL[0], sizeof(mmMC_SEQ_WCDR_CTRL)/sizeof(mmMC_SEQ_WCDR_CTRL[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_WAKEUP_CNTL", REG_MMIO, 0x0A3A, &mmMC_SEQ_TRAIN_WAKEUP_CNTL[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD", REG_MMIO, 0x0A3B, &mmMC_SEQ_TRAIN_EDC_THRESHOLD[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_WAKEUP_EDGE", REG_MMIO, 0x0A3C, &mmMC_SEQ_TRAIN_WAKEUP_EDGE[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_WAKEUP_MASK", REG_MMIO, 0x0A3D, &mmMC_SEQ_TRAIN_WAKEUP_MASK[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_CAPTURE", REG_MMIO, 0x0A3E, &mmMC_SEQ_TRAIN_CAPTURE[0], sizeof(mmMC_SEQ_TRAIN_CAPTURE)/sizeof(mmMC_SEQ_TRAIN_CAPTURE[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_WAKEUP_CLEAR", REG_MMIO, 0x0A3F, &mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_TIMING", REG_MMIO, 0x0A40, &mmMC_SEQ_TRAIN_TIMING[0], sizeof(mmMC_SEQ_TRAIN_TIMING)/sizeof(mmMC_SEQ_TRAIN_TIMING[0]), 0, 0 },
	{ "mmMC_TRAIN_EDCCDR_R_D0", REG_MMIO, 0x0A41, &mmMC_TRAIN_EDCCDR_R_D0[0], sizeof(mmMC_TRAIN_EDCCDR_R_D0)/sizeof(mmMC_TRAIN_EDCCDR_R_D0[0]), 0, 0 },
	{ "mmMC_TRAIN_EDCCDR_R_D1", REG_MMIO, 0x0A42, &mmMC_TRAIN_EDCCDR_R_D1[0], sizeof(mmMC_TRAIN_EDCCDR_R_D1)/sizeof(mmMC_TRAIN_EDCCDR_R_D1[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_0_D0", REG_MMIO, 0x0A43, &mmMC_TRAIN_PRBSERR_0_D0[0], sizeof(mmMC_TRAIN_PRBSERR_0_D0)/sizeof(mmMC_TRAIN_PRBSERR_0_D0[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_1_D0", REG_MMIO, 0x0A44, &mmMC_TRAIN_PRBSERR_1_D0[0], sizeof(mmMC_TRAIN_PRBSERR_1_D0)/sizeof(mmMC_TRAIN_PRBSERR_1_D0[0]), 0, 0 },
	{ "mmMC_TRAIN_EDC_STATUS_D0", REG_MMIO, 0x0A45, &mmMC_TRAIN_EDC_STATUS_D0[0], sizeof(mmMC_TRAIN_EDC_STATUS_D0)/sizeof(mmMC_TRAIN_EDC_STATUS_D0[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_0_D1", REG_MMIO, 0x0A46, &mmMC_TRAIN_PRBSERR_0_D1[0], sizeof(mmMC_TRAIN_PRBSERR_0_D1)/sizeof(mmMC_TRAIN_PRBSERR_0_D1[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_1_D1", REG_MMIO, 0x0A47, &mmMC_TRAIN_PRBSERR_1_D1[0], sizeof(mmMC_TRAIN_PRBSERR_1_D1)/sizeof(mmMC_TRAIN_PRBSERR_1_D1[0]), 0, 0 },
	{ "mmMC_TRAIN_EDC_STATUS_D1", REG_MMIO, 0x0A48, &mmMC_TRAIN_EDC_STATUS_D1[0], sizeof(mmMC_TRAIN_EDC_STATUS_D1)/sizeof(mmMC_TRAIN_EDC_STATUS_D1[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_DPHY0_D0", REG_MMIO, 0x0A49, &mmMC_IO_TXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D0)/sizeof(mmMC_IO_TXCNTL_DPHY0_D0[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_DPHY1_D0", REG_MMIO, 0x0A4A, &mmMC_IO_TXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D0)/sizeof(mmMC_IO_TXCNTL_DPHY1_D0[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_APHY_D0", REG_MMIO, 0x0A4B, &mmMC_IO_TXCNTL_APHY_D0[0], sizeof(mmMC_IO_TXCNTL_APHY_D0)/sizeof(mmMC_IO_TXCNTL_APHY_D0[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL_DPHY0_D0", REG_MMIO, 0x0A4C, &mmMC_IO_RXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL_DPHY0_D0[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL_DPHY1_D0", REG_MMIO, 0x0A4D, &mmMC_IO_RXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL_DPHY1_D0[0]), 0, 0 },
	{ "mmMC_IO_DPHY_STR_CNTL_D0", REG_MMIO, 0x0A4E, &mmMC_IO_DPHY_STR_CNTL_D0[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D0)/sizeof(mmMC_IO_DPHY_STR_CNTL_D0[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_DPHY0_D1", REG_MMIO, 0x0A4F, &mmMC_IO_TXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D1)/sizeof(mmMC_IO_TXCNTL_DPHY0_D1[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_DPHY1_D1", REG_MMIO, 0x0A50, &mmMC_IO_TXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D1)/sizeof(mmMC_IO_TXCNTL_DPHY1_D1[0]), 0, 0 },
	{ "mmMC_IO_TXCNTL_APHY_D1", REG_MMIO, 0x0A51, &mmMC_IO_TXCNTL_APHY_D1[0], sizeof(mmMC_IO_TXCNTL_APHY_D1)/sizeof(mmMC_IO_TXCNTL_APHY_D1[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL_DPHY0_D1", REG_MMIO, 0x0A52, &mmMC_IO_RXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL_DPHY0_D1[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL_DPHY1_D1", REG_MMIO, 0x0A53, &mmMC_IO_RXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL_DPHY1_D1[0]), 0, 0 },
	{ "mmMC_IO_DPHY_STR_CNTL_D1", REG_MMIO, 0x0A54, &mmMC_IO_DPHY_STR_CNTL_D1[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D1)/sizeof(mmMC_IO_DPHY_STR_CNTL_D1[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL_D0", REG_MMIO, 0x0A55, &mmMC_IO_CDRCNTL_D0[0], sizeof(mmMC_IO_CDRCNTL_D0)/sizeof(mmMC_IO_CDRCNTL_D0[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL_D1", REG_MMIO, 0x0A56, &mmMC_IO_CDRCNTL_D1[0], sizeof(mmMC_IO_CDRCNTL_D1)/sizeof(mmMC_IO_CDRCNTL_D1[0]), 0, 0 },
	{ "mmMC_SEQ_FIFO_CTL", REG_MMIO, 0x0A57, &mmMC_SEQ_FIFO_CTL[0], sizeof(mmMC_SEQ_FIFO_CTL)/sizeof(mmMC_SEQ_FIFO_CTL[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE0_D0", REG_MMIO, 0x0A58, &mmMC_SEQ_TXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE1_D0", REG_MMIO, 0x0A59, &mmMC_SEQ_TXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE2_D0", REG_MMIO, 0x0A5A, &mmMC_SEQ_TXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE3_D0", REG_MMIO, 0x0A5B, &mmMC_SEQ_TXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_DBI_D0", REG_MMIO, 0x0A5C, &mmMC_SEQ_TXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_EDC_D0", REG_MMIO, 0x0A5D, &mmMC_SEQ_TXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D0[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_FCK_D0", REG_MMIO, 0x0A5E, &mmMC_SEQ_TXFRAMING_FCK_D0[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D0)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D0[0]), 0, 0 },
	{ "mmMC_SEQ_MISC8", REG_MMIO, 0x0A5F, &mmMC_SEQ_MISC8[0], sizeof(mmMC_SEQ_MISC8)/sizeof(mmMC_SEQ_MISC8[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE0_D1", REG_MMIO, 0x0A60, &mmMC_SEQ_TXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE1_D1", REG_MMIO, 0x0A61, &mmMC_SEQ_TXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE2_D1", REG_MMIO, 0x0A62, &mmMC_SEQ_TXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_BYTE3_D1", REG_MMIO, 0x0A63, &mmMC_SEQ_TXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_DBI_D1", REG_MMIO, 0x0A64, &mmMC_SEQ_TXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_EDC_D1", REG_MMIO, 0x0A65, &mmMC_SEQ_TXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TXFRAMING_FCK_D1", REG_MMIO, 0x0A66, &mmMC_SEQ_TXFRAMING_FCK_D1[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D1)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE0_D0", REG_MMIO, 0x0A67, &mmMC_SEQ_RXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE1_D0", REG_MMIO, 0x0A68, &mmMC_SEQ_RXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE2_D0", REG_MMIO, 0x0A69, &mmMC_SEQ_RXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE3_D0", REG_MMIO, 0x0A6A, &mmMC_SEQ_RXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_DBI_D0", REG_MMIO, 0x0A6B, &mmMC_SEQ_RXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_EDC_D0", REG_MMIO, 0x0A6C, &mmMC_SEQ_RXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D0[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE0_D1", REG_MMIO, 0x0A6D, &mmMC_SEQ_RXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE1_D1", REG_MMIO, 0x0A6E, &mmMC_SEQ_RXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE2_D1", REG_MMIO, 0x0A6F, &mmMC_SEQ_RXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_BYTE3_D1", REG_MMIO, 0x0A70, &mmMC_SEQ_RXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_DBI_D1", REG_MMIO, 0x0A71, &mmMC_SEQ_RXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D1[0]), 0, 0 },
	{ "mmMC_SEQ_RXFRAMING_EDC_D1", REG_MMIO, 0x0A72, &mmMC_SEQ_RXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D1[0]), 0, 0 },
	{ "mmMC_IO_PAD_CNTL", REG_MMIO, 0x0A73, &mmMC_IO_PAD_CNTL[0], sizeof(mmMC_IO_PAD_CNTL)/sizeof(mmMC_IO_PAD_CNTL[0]), 0, 0 },
	{ "mmMC_IO_PAD_CNTL_D0", REG_MMIO, 0x0A74, &mmMC_IO_PAD_CNTL_D0[0], sizeof(mmMC_IO_PAD_CNTL_D0)/sizeof(mmMC_IO_PAD_CNTL_D0[0]), 0, 0 },
	{ "mmMC_IO_PAD_CNTL_D1", REG_MMIO, 0x0A75, &mmMC_IO_PAD_CNTL_D1[0], sizeof(mmMC_IO_PAD_CNTL_D1)/sizeof(mmMC_IO_PAD_CNTL_D1[0]), 0, 0 },
	{ "mmMC_NPL_STATUS", REG_MMIO, 0x0A76, &mmMC_NPL_STATUS[0], sizeof(mmMC_NPL_STATUS)/sizeof(mmMC_NPL_STATUS[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_CNTL", REG_MMIO, 0x0A77, &mmMC_SEQ_PERF_CNTL[0], sizeof(mmMC_SEQ_PERF_CNTL)/sizeof(mmMC_SEQ_PERF_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CTL", REG_MMIO, 0x0A78, &mmMC_SEQ_PERF_SEQ_CTL[0], sizeof(mmMC_SEQ_PERF_SEQ_CTL)/sizeof(mmMC_SEQ_PERF_SEQ_CTL[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I0", REG_MMIO, 0x0A79, &mmMC_SEQ_PERF_SEQ_CNT_A_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I1", REG_MMIO, 0x0A7A, &mmMC_SEQ_PERF_SEQ_CNT_A_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I0", REG_MMIO, 0x0A7B, &mmMC_SEQ_PERF_SEQ_CNT_B_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I1", REG_MMIO, 0x0A7C, &mmMC_SEQ_PERF_SEQ_CNT_B_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1[0]), 0, 0 },
	{ "mmMC_SEQ_STATUS_M", REG_MMIO, 0x0A7D, &mmMC_SEQ_STATUS_M[0], sizeof(mmMC_SEQ_STATUS_M)/sizeof(mmMC_SEQ_STATUS_M[0]), 0, 0 },
	{ "mmMC_SEQ_VENDOR_ID_I0", REG_MMIO, 0x0A7E, &mmMC_SEQ_VENDOR_ID_I0[0], sizeof(mmMC_SEQ_VENDOR_ID_I0)/sizeof(mmMC_SEQ_VENDOR_ID_I0[0]), 0, 0 },
	{ "mmMC_SEQ_VENDOR_ID_I1", REG_MMIO, 0x0A7F, &mmMC_SEQ_VENDOR_ID_I1[0], sizeof(mmMC_SEQ_VENDOR_ID_I1)/sizeof(mmMC_SEQ_VENDOR_ID_I1[0]), 0, 0 },
	{ "mmMC_SEQ_MISC0", REG_MMIO, 0x0A80, &mmMC_SEQ_MISC0[0], sizeof(mmMC_SEQ_MISC0)/sizeof(mmMC_SEQ_MISC0[0]), 0, 0 },
	{ "mmMC_SEQ_MISC1", REG_MMIO, 0x0A81, &mmMC_SEQ_MISC1[0], sizeof(mmMC_SEQ_MISC1)/sizeof(mmMC_SEQ_MISC1[0]), 0, 0 },
	{ "mmMC_SEQ_RESERVE_M", REG_MMIO, 0x0A82, &mmMC_SEQ_RESERVE_M[0], sizeof(mmMC_SEQ_RESERVE_M)/sizeof(mmMC_SEQ_RESERVE_M[0]), 0, 0 },
	{ "mmMC_PMG_CMD_EMRS", REG_MMIO, 0x0A83, &mmMC_PMG_CMD_EMRS[0], sizeof(mmMC_PMG_CMD_EMRS)/sizeof(mmMC_PMG_CMD_EMRS[0]), 0, 0 },
	{ "mmMC_PMG_CFG", REG_MMIO, 0x0A84, &mmMC_PMG_CFG[0], sizeof(mmMC_PMG_CFG)/sizeof(mmMC_PMG_CFG[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_GP2_STAT", REG_MMIO, 0x0A85, &mmMC_SEQ_SUP_GP2_STAT[0], sizeof(mmMC_SEQ_SUP_GP2_STAT)/sizeof(mmMC_SEQ_SUP_GP2_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_GP3_STAT", REG_MMIO, 0x0A86, &mmMC_SEQ_SUP_GP3_STAT[0], sizeof(mmMC_SEQ_SUP_GP3_STAT)/sizeof(mmMC_SEQ_SUP_GP3_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_IR_STAT", REG_MMIO, 0x0A87, &mmMC_SEQ_SUP_IR_STAT[0], sizeof(mmMC_SEQ_SUP_IR_STAT)/sizeof(mmMC_SEQ_SUP_IR_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_DEC_STAT", REG_MMIO, 0x0A88, &mmMC_SEQ_SUP_DEC_STAT[0], sizeof(mmMC_SEQ_SUP_DEC_STAT)/sizeof(mmMC_SEQ_SUP_DEC_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_PGM_STAT", REG_MMIO, 0x0A89, &mmMC_SEQ_SUP_PGM_STAT[0], sizeof(mmMC_SEQ_SUP_PGM_STAT)/sizeof(mmMC_SEQ_SUP_PGM_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_R_PGM", REG_MMIO, 0x0A8A, &mmMC_SEQ_SUP_R_PGM[0], sizeof(mmMC_SEQ_SUP_R_PGM)/sizeof(mmMC_SEQ_SUP_R_PGM[0]), 0, 0 },
	{ "mmMC_SEQ_MISC3", REG_MMIO, 0x0A8B, &mmMC_SEQ_MISC3[0], sizeof(mmMC_SEQ_MISC3)/sizeof(mmMC_SEQ_MISC3[0]), 0, 0 },
	{ "mmMC_SEQ_MISC4", REG_MMIO, 0x0A8C, &mmMC_SEQ_MISC4[0], sizeof(mmMC_SEQ_MISC4)/sizeof(mmMC_SEQ_MISC4[0]), 0, 0 },
	{ "mmMC_BIST_CMP_CNTL", REG_MMIO, 0x0A8D, &mmMC_BIST_CMP_CNTL[0], sizeof(mmMC_BIST_CMP_CNTL)/sizeof(mmMC_BIST_CMP_CNTL[0]), 0, 0 },
	{ "mmMC_BIST_CMD_CNTL", REG_MMIO, 0x0A8E, &mmMC_BIST_CMD_CNTL[0], sizeof(mmMC_BIST_CMD_CNTL)/sizeof(mmMC_BIST_CMD_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_GP0_STAT", REG_MMIO, 0x0A8F, &mmMC_SEQ_SUP_GP0_STAT[0], sizeof(mmMC_SEQ_SUP_GP0_STAT)/sizeof(mmMC_SEQ_SUP_GP0_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_SUP_GP1_STAT", REG_MMIO, 0x0A90, &mmMC_SEQ_SUP_GP1_STAT[0], sizeof(mmMC_SEQ_SUP_GP1_STAT)/sizeof(mmMC_SEQ_SUP_GP1_STAT[0]), 0, 0 },
	{ "mmMC_SEQ_IO_DEBUG_INDEX", REG_MMIO, 0x0A91, &mmMC_SEQ_IO_DEBUG_INDEX[0], sizeof(mmMC_SEQ_IO_DEBUG_INDEX)/sizeof(mmMC_SEQ_IO_DEBUG_INDEX[0]), 0, 0 },
	{ "mmMC_SEQ_IO_DEBUG_DATA", REG_MMIO, 0x0A92, &mmMC_SEQ_IO_DEBUG_DATA[0], sizeof(mmMC_SEQ_IO_DEBUG_DATA)/sizeof(mmMC_SEQ_IO_DEBUG_DATA[0]), 0, 0 },
	{ "mmMC_SEQ_BYTE_REMAP_D0", REG_MMIO, 0x0A93, &mmMC_SEQ_BYTE_REMAP_D0[0], sizeof(mmMC_SEQ_BYTE_REMAP_D0)/sizeof(mmMC_SEQ_BYTE_REMAP_D0[0]), 0, 0 },
	{ "mmMC_SEQ_BYTE_REMAP_D1", REG_MMIO, 0x0A94, &mmMC_SEQ_BYTE_REMAP_D1[0], sizeof(mmMC_SEQ_BYTE_REMAP_D1)/sizeof(mmMC_SEQ_BYTE_REMAP_D1[0]), 0, 0 },
	{ "mmMC_SEQ_MISC5", REG_MMIO, 0x0A95, &mmMC_SEQ_MISC5[0], sizeof(mmMC_SEQ_MISC5)/sizeof(mmMC_SEQ_MISC5[0]), 0, 0 },
	{ "mmMC_SEQ_MISC6", REG_MMIO, 0x0A96, &mmMC_SEQ_MISC6[0], sizeof(mmMC_SEQ_MISC6)/sizeof(mmMC_SEQ_MISC6[0]), 0, 0 },
	{ "mmMC_IO_APHY_STR_CNTL_D0", REG_MMIO, 0x0A97, &mmMC_IO_APHY_STR_CNTL_D0[0], sizeof(mmMC_IO_APHY_STR_CNTL_D0)/sizeof(mmMC_IO_APHY_STR_CNTL_D0[0]), 0, 0 },
	{ "mmMC_IO_APHY_STR_CNTL_D1", REG_MMIO, 0x0A98, &mmMC_IO_APHY_STR_CNTL_D1[0], sizeof(mmMC_IO_APHY_STR_CNTL_D1)/sizeof(mmMC_IO_APHY_STR_CNTL_D1[0]), 0, 0 },
	{ "mmMC_SEQ_MISC7", REG_MMIO, 0x0A99, &mmMC_SEQ_MISC7[0], sizeof(mmMC_SEQ_MISC7)/sizeof(mmMC_SEQ_MISC7[0]), 0, 0 },
	{ "mmMC_SEQ_CG", REG_MMIO, 0x0A9A, &mmMC_SEQ_CG[0], sizeof(mmMC_SEQ_CG)/sizeof(mmMC_SEQ_CG[0]), 0, 0 },
	{ "mmMC_SEQ_RAS_TIMING_LP", REG_MMIO, 0x0A9B, &mmMC_SEQ_RAS_TIMING_LP[0], sizeof(mmMC_SEQ_RAS_TIMING_LP)/sizeof(mmMC_SEQ_RAS_TIMING_LP[0]), 0, 0 },
	{ "mmMC_SEQ_CAS_TIMING_LP", REG_MMIO, 0x0A9C, &mmMC_SEQ_CAS_TIMING_LP[0], sizeof(mmMC_SEQ_CAS_TIMING_LP)/sizeof(mmMC_SEQ_CAS_TIMING_LP[0]), 0, 0 },
	{ "mmMC_SEQ_MISC_TIMING_LP", REG_MMIO, 0x0A9D, &mmMC_SEQ_MISC_TIMING_LP[0], sizeof(mmMC_SEQ_MISC_TIMING_LP)/sizeof(mmMC_SEQ_MISC_TIMING_LP[0]), 0, 0 },
	{ "mmMC_SEQ_MISC_TIMING2_LP", REG_MMIO, 0x0A9E, &mmMC_SEQ_MISC_TIMING2_LP[0], sizeof(mmMC_SEQ_MISC_TIMING2_LP)/sizeof(mmMC_SEQ_MISC_TIMING2_LP[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_D0_LP", REG_MMIO, 0x0A9F, &mmMC_SEQ_WR_CTL_D0_LP[0], sizeof(mmMC_SEQ_WR_CTL_D0_LP)/sizeof(mmMC_SEQ_WR_CTL_D0_LP[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_D1_LP", REG_MMIO, 0x0AA0, &mmMC_SEQ_WR_CTL_D1_LP[0], sizeof(mmMC_SEQ_WR_CTL_D1_LP)/sizeof(mmMC_SEQ_WR_CTL_D1_LP[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_CMD_EMRS_LP", REG_MMIO, 0x0AA1, &mmMC_SEQ_PMG_CMD_EMRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_CMD_MRS_LP", REG_MMIO, 0x0AA2, &mmMC_SEQ_PMG_CMD_MRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS_LP[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B0_D0", REG_MMIO, 0x0AA3, &mmMC_SEQ_BIT_REMAP_B0_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D0[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B1_D0", REG_MMIO, 0x0AA4, &mmMC_SEQ_BIT_REMAP_B1_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D0[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B2_D0", REG_MMIO, 0x0AA5, &mmMC_SEQ_BIT_REMAP_B2_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D0[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B3_D0", REG_MMIO, 0x0AA6, &mmMC_SEQ_BIT_REMAP_B3_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D0[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B0_D1", REG_MMIO, 0x0AA7, &mmMC_SEQ_BIT_REMAP_B0_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D1[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B1_D1", REG_MMIO, 0x0AA8, &mmMC_SEQ_BIT_REMAP_B1_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D1[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B2_D1", REG_MMIO, 0x0AA9, &mmMC_SEQ_BIT_REMAP_B2_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D1[0]), 0, 0 },
	{ "mmMC_SEQ_BIT_REMAP_B3_D1", REG_MMIO, 0x0AAA, &mmMC_SEQ_BIT_REMAP_B3_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D1[0]), 0, 0 },
	{ "mmMC_PMG_CMD_MRS", REG_MMIO, 0x0AAB, &mmMC_PMG_CMD_MRS[0], sizeof(mmMC_PMG_CMD_MRS)/sizeof(mmMC_PMG_CMD_MRS[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD0", REG_MMIO, 0x0AAC, &mmMC_SEQ_IO_RWORD0[0], sizeof(mmMC_SEQ_IO_RWORD0)/sizeof(mmMC_SEQ_IO_RWORD0[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD1", REG_MMIO, 0x0AAD, &mmMC_SEQ_IO_RWORD1[0], sizeof(mmMC_SEQ_IO_RWORD1)/sizeof(mmMC_SEQ_IO_RWORD1[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD2", REG_MMIO, 0x0AAE, &mmMC_SEQ_IO_RWORD2[0], sizeof(mmMC_SEQ_IO_RWORD2)/sizeof(mmMC_SEQ_IO_RWORD2[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD3", REG_MMIO, 0x0AAF, &mmMC_SEQ_IO_RWORD3[0], sizeof(mmMC_SEQ_IO_RWORD3)/sizeof(mmMC_SEQ_IO_RWORD3[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD4", REG_MMIO, 0x0AB0, &mmMC_SEQ_IO_RWORD4[0], sizeof(mmMC_SEQ_IO_RWORD4)/sizeof(mmMC_SEQ_IO_RWORD4[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD5", REG_MMIO, 0x0AB1, &mmMC_SEQ_IO_RWORD5[0], sizeof(mmMC_SEQ_IO_RWORD5)/sizeof(mmMC_SEQ_IO_RWORD5[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD6", REG_MMIO, 0x0AB2, &mmMC_SEQ_IO_RWORD6[0], sizeof(mmMC_SEQ_IO_RWORD6)/sizeof(mmMC_SEQ_IO_RWORD6[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RWORD7", REG_MMIO, 0x0AB3, &mmMC_SEQ_IO_RWORD7[0], sizeof(mmMC_SEQ_IO_RWORD7)/sizeof(mmMC_SEQ_IO_RWORD7[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RDBI", REG_MMIO, 0x0AB4, &mmMC_SEQ_IO_RDBI[0], sizeof(mmMC_SEQ_IO_RDBI)/sizeof(mmMC_SEQ_IO_RDBI[0]), 0, 0 },
	{ "mmMC_SEQ_IO_REDC", REG_MMIO, 0x0AB5, &mmMC_SEQ_IO_REDC[0], sizeof(mmMC_SEQ_IO_REDC)/sizeof(mmMC_SEQ_IO_REDC[0]), 0, 0 },
	{ "mmMC_BIST_CMP_CNTL_2", REG_MMIO, 0x0AB6, &mmMC_BIST_CMP_CNTL_2[0], sizeof(mmMC_BIST_CMP_CNTL_2)/sizeof(mmMC_BIST_CMP_CNTL_2[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RESERVE_D0", REG_MMIO, 0x0AB7, &mmMC_SEQ_IO_RESERVE_D0[0], sizeof(mmMC_SEQ_IO_RESERVE_D0)/sizeof(mmMC_SEQ_IO_RESERVE_D0[0]), 0, 0 },
	{ "mmMC_SEQ_IO_RESERVE_D1", REG_MMIO, 0x0AB8, &mmMC_SEQ_IO_RESERVE_D1[0], sizeof(mmMC_SEQ_IO_RESERVE_D1)/sizeof(mmMC_SEQ_IO_RESERVE_D1[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_PG_HWCNTL", REG_MMIO, 0x0AB9, &mmMC_SEQ_PMG_PG_HWCNTL[0], sizeof(mmMC_SEQ_PMG_PG_HWCNTL)/sizeof(mmMC_SEQ_PMG_PG_HWCNTL[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_PG_SWCNTL_0", REG_MMIO, 0x0ABA, &mmMC_SEQ_PMG_PG_SWCNTL_0[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_PG_SWCNTL_1", REG_MMIO, 0x0ABB, &mmMC_SEQ_PMG_PG_SWCNTL_1[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1[0]), 0, 0 },
	{ "mmMC_IMP_DQ_STATUS", REG_MMIO, 0x0ABC, &mmMC_IMP_DQ_STATUS[0], sizeof(mmMC_IMP_DQ_STATUS)/sizeof(mmMC_IMP_DQ_STATUS[0]), 0, 0 },
	{ "mmMC_SEQ_TCG_CNTL", REG_MMIO, 0x0ABD, &mmMC_SEQ_TCG_CNTL[0], sizeof(mmMC_SEQ_TCG_CNTL)/sizeof(mmMC_SEQ_TCG_CNTL[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_CTRL", REG_MMIO, 0x0ABE, &mmMC_SEQ_TSM_CTRL[0], sizeof(mmMC_SEQ_TSM_CTRL)/sizeof(mmMC_SEQ_TSM_CTRL[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_GCNT", REG_MMIO, 0x0ABF, &mmMC_SEQ_TSM_GCNT[0], sizeof(mmMC_SEQ_TSM_GCNT)/sizeof(mmMC_SEQ_TSM_GCNT[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_OCNT", REG_MMIO, 0x0AC0, &mmMC_SEQ_TSM_OCNT[0], sizeof(mmMC_SEQ_TSM_OCNT)/sizeof(mmMC_SEQ_TSM_OCNT[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_NCNT", REG_MMIO, 0x0AC1, &mmMC_SEQ_TSM_NCNT[0], sizeof(mmMC_SEQ_TSM_NCNT)/sizeof(mmMC_SEQ_TSM_NCNT[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_BCNT", REG_MMIO, 0x0AC2, &mmMC_SEQ_TSM_BCNT[0], sizeof(mmMC_SEQ_TSM_BCNT)/sizeof(mmMC_SEQ_TSM_BCNT[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_FLAG", REG_MMIO, 0x0AC3, &mmMC_SEQ_TSM_FLAG[0], sizeof(mmMC_SEQ_TSM_FLAG)/sizeof(mmMC_SEQ_TSM_FLAG[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_UPDATE", REG_MMIO, 0x0AC4, &mmMC_SEQ_TSM_UPDATE[0], sizeof(mmMC_SEQ_TSM_UPDATE)/sizeof(mmMC_SEQ_TSM_UPDATE[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_EDC", REG_MMIO, 0x0AC5, &mmMC_SEQ_TSM_EDC[0], sizeof(mmMC_SEQ_TSM_EDC)/sizeof(mmMC_SEQ_TSM_EDC[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_DBI", REG_MMIO, 0x0AC6, &mmMC_SEQ_TSM_DBI[0], sizeof(mmMC_SEQ_TSM_DBI)/sizeof(mmMC_SEQ_TSM_DBI[0]), 0, 0 },
	{ "mmMC_SEQ_RD_CTL_D0_LP", REG_MMIO, 0x0AC7, &mmMC_SEQ_RD_CTL_D0_LP[0], sizeof(mmMC_SEQ_RD_CTL_D0_LP)/sizeof(mmMC_SEQ_RD_CTL_D0_LP[0]), 0, 0 },
	{ "mmMC_SEQ_RD_CTL_D1_LP", REG_MMIO, 0x0AC8, &mmMC_SEQ_RD_CTL_D1_LP[0], sizeof(mmMC_SEQ_RD_CTL_D1_LP)/sizeof(mmMC_SEQ_RD_CTL_D1_LP[0]), 0, 0 },
	{ "mmMC_SEQ_TIMER_WR", REG_MMIO, 0x0AC9, &mmMC_SEQ_TIMER_WR[0], sizeof(mmMC_SEQ_TIMER_WR)/sizeof(mmMC_SEQ_TIMER_WR[0]), 0, 0 },
	{ "mmMC_SEQ_TIMER_RD", REG_MMIO, 0x0ACA, &mmMC_SEQ_TIMER_RD[0], sizeof(mmMC_SEQ_TIMER_RD)/sizeof(mmMC_SEQ_TIMER_RD[0]), 0, 0 },
	{ "mmMC_SEQ_DRAM_ERROR_INSERTION", REG_MMIO, 0x0ACB, &mmMC_SEQ_DRAM_ERROR_INSERTION[0], sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION)/sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION[0]), 0, 0 },
	{ "mmMC_PHY_TIMING_D0", REG_MMIO, 0x0ACC, &mmMC_PHY_TIMING_D0[0], sizeof(mmMC_PHY_TIMING_D0)/sizeof(mmMC_PHY_TIMING_D0[0]), 0, 0 },
	{ "mmMC_PHY_TIMING_D1", REG_MMIO, 0x0ACD, &mmMC_PHY_TIMING_D1[0], sizeof(mmMC_PHY_TIMING_D1)/sizeof(mmMC_PHY_TIMING_D1[0]), 0, 0 },
	{ "mmMC_PHY_TIMING_2", REG_MMIO, 0x0ACE, &mmMC_PHY_TIMING_2[0], sizeof(mmMC_PHY_TIMING_2)/sizeof(mmMC_PHY_TIMING_2[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_DEBUG_INDEX", REG_MMIO, 0x0ACF, &mmMC_SEQ_TSM_DEBUG_INDEX[0], sizeof(mmMC_SEQ_TSM_DEBUG_INDEX)/sizeof(mmMC_SEQ_TSM_DEBUG_INDEX[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_DEBUG_DATA", REG_MMIO, 0x0AD0, &mmMC_SEQ_TSM_DEBUG_DATA[0], sizeof(mmMC_SEQ_TSM_DEBUG_DATA)/sizeof(mmMC_SEQ_TSM_DEBUG_DATA[0]), 0, 0 },
	{ "mmMC_PMG_CMD_MRS1", REG_MMIO, 0x0AD1, &mmMC_PMG_CMD_MRS1[0], sizeof(mmMC_PMG_CMD_MRS1)/sizeof(mmMC_PMG_CMD_MRS1[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_CMD_MRS1_LP", REG_MMIO, 0x0AD2, &mmMC_SEQ_PMG_CMD_MRS1_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_TIMING_LP", REG_MMIO, 0x0AD3, &mmMC_SEQ_PMG_TIMING_LP[0], sizeof(mmMC_SEQ_PMG_TIMING_LP)/sizeof(mmMC_SEQ_PMG_TIMING_LP[0]), 0, 0 },
	{ "mmMC_SEQ_CNTL_2", REG_MMIO, 0x0AD4, &mmMC_SEQ_CNTL_2[0], sizeof(mmMC_SEQ_CNTL_2)/sizeof(mmMC_SEQ_CNTL_2[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_2", REG_MMIO, 0x0AD5, &mmMC_SEQ_WR_CTL_2[0], sizeof(mmMC_SEQ_WR_CTL_2)/sizeof(mmMC_SEQ_WR_CTL_2[0]), 0, 0 },
	{ "mmMC_SEQ_WR_CTL_2_LP", REG_MMIO, 0x0AD6, &mmMC_SEQ_WR_CTL_2_LP[0], sizeof(mmMC_SEQ_WR_CTL_2_LP)/sizeof(mmMC_SEQ_WR_CTL_2_LP[0]), 0, 0 },
	{ "mmMC_PMG_CMD_MRS2", REG_MMIO, 0x0AD7, &mmMC_PMG_CMD_MRS2[0], sizeof(mmMC_PMG_CMD_MRS2)/sizeof(mmMC_PMG_CMD_MRS2[0]), 0, 0 },
	{ "mmMC_SEQ_PMG_CMD_MRS2_LP", REG_MMIO, 0x0AD8, &mmMC_SEQ_PMG_CMD_MRS2_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I0", REG_MMIO, 0x0AD9, &mmMC_SEQ_PERF_SEQ_CNT_C_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I1", REG_MMIO, 0x0ADA, &mmMC_SEQ_PERF_SEQ_CNT_C_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I0", REG_MMIO, 0x0ADB, &mmMC_SEQ_PERF_SEQ_CNT_D_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I1", REG_MMIO, 0x0ADC, &mmMC_SEQ_PERF_SEQ_CNT_D_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL1_D0", REG_MMIO, 0x0ADD, &mmMC_IO_CDRCNTL1_D0[0], sizeof(mmMC_IO_CDRCNTL1_D0)/sizeof(mmMC_IO_CDRCNTL1_D0[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL1_D1", REG_MMIO, 0x0ADE, &mmMC_IO_CDRCNTL1_D1[0], sizeof(mmMC_IO_CDRCNTL1_D1)/sizeof(mmMC_IO_CDRCNTL1_D1[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL1_DPHY0_D0", REG_MMIO, 0x0ADF, &mmMC_IO_RXCNTL1_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D0[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL1_DPHY1_D0", REG_MMIO, 0x0AE0, &mmMC_IO_RXCNTL1_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D0[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL1_DPHY0_D1", REG_MMIO, 0x0AE1, &mmMC_IO_RXCNTL1_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D1[0]), 0, 0 },
	{ "mmMC_IO_RXCNTL1_DPHY1_D1", REG_MMIO, 0x0AE2, &mmMC_IO_RXCNTL1_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_WCDR", REG_MMIO, 0x0AE3, &mmMC_SEQ_TSM_WCDR[0], sizeof(mmMC_SEQ_TSM_WCDR)/sizeof(mmMC_SEQ_TSM_WCDR[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL2_D0", REG_MMIO, 0x0AE4, &mmMC_IO_CDRCNTL2_D0[0], sizeof(mmMC_IO_CDRCNTL2_D0)/sizeof(mmMC_IO_CDRCNTL2_D0[0]), 0, 0 },
	{ "mmMC_IO_CDRCNTL2_D1", REG_MMIO, 0x0AE5, &mmMC_IO_CDRCNTL2_D1[0], sizeof(mmMC_IO_CDRCNTL2_D1)/sizeof(mmMC_IO_CDRCNTL2_D1[0]), 0, 0 },
	{ "mmMC_SEQ_TSM_MISC", REG_MMIO, 0x0AE6, &mmMC_SEQ_TSM_MISC[0], sizeof(mmMC_SEQ_TSM_MISC)/sizeof(mmMC_SEQ_TSM_MISC[0]), 0, 0 },
	{ "mmMC_SEQ_MISC9", REG_MMIO, 0x0AE7, &mmMC_SEQ_MISC9[0], sizeof(mmMC_SEQ_MISC9)/sizeof(mmMC_SEQ_MISC9[0]), 0, 0 },
	{ "mmMCLK_PWRMGT_CNTL", REG_MMIO, 0x0AE8, &mmMCLK_PWRMGT_CNTL[0], sizeof(mmMCLK_PWRMGT_CNTL)/sizeof(mmMCLK_PWRMGT_CNTL[0]), 0, 0 },
	{ "mmDLL_CNTL", REG_MMIO, 0x0AE9, &mmDLL_CNTL[0], sizeof(mmDLL_CNTL)/sizeof(mmDLL_CNTL[0]), 0, 0 },
	{ "mmMPLL_SEQ_UCODE_1", REG_MMIO, 0x0AEA, &mmMPLL_SEQ_UCODE_1[0], sizeof(mmMPLL_SEQ_UCODE_1)/sizeof(mmMPLL_SEQ_UCODE_1[0]), 0, 0 },
	{ "mmMPLL_SEQ_UCODE_2", REG_MMIO, 0x0AEB, &mmMPLL_SEQ_UCODE_2[0], sizeof(mmMPLL_SEQ_UCODE_2)/sizeof(mmMPLL_SEQ_UCODE_2[0]), 0, 0 },
	{ "mmMPLL_CNTL_MODE", REG_MMIO, 0x0AEC, &mmMPLL_CNTL_MODE[0], sizeof(mmMPLL_CNTL_MODE)/sizeof(mmMPLL_CNTL_MODE[0]), 0, 0 },
	{ "mmMPLL_FUNC_CNTL", REG_MMIO, 0x0AED, &mmMPLL_FUNC_CNTL[0], sizeof(mmMPLL_FUNC_CNTL)/sizeof(mmMPLL_FUNC_CNTL[0]), 0, 0 },
	{ "mmMPLL_FUNC_CNTL_1", REG_MMIO, 0x0AEE, &mmMPLL_FUNC_CNTL_1[0], sizeof(mmMPLL_FUNC_CNTL_1)/sizeof(mmMPLL_FUNC_CNTL_1[0]), 0, 0 },
	{ "mmMPLL_FUNC_CNTL_2", REG_MMIO, 0x0AEF, &mmMPLL_FUNC_CNTL_2[0], sizeof(mmMPLL_FUNC_CNTL_2)/sizeof(mmMPLL_FUNC_CNTL_2[0]), 0, 0 },
	{ "mmMPLL_AD_FUNC_CNTL", REG_MMIO, 0x0AF0, &mmMPLL_AD_FUNC_CNTL[0], sizeof(mmMPLL_AD_FUNC_CNTL)/sizeof(mmMPLL_AD_FUNC_CNTL[0]), 0, 0 },
	{ "mmMPLL_DQ_FUNC_CNTL", REG_MMIO, 0x0AF1, &mmMPLL_DQ_FUNC_CNTL[0], sizeof(mmMPLL_DQ_FUNC_CNTL)/sizeof(mmMPLL_DQ_FUNC_CNTL[0]), 0, 0 },
	{ "mmMPLL_TIME", REG_MMIO, 0x0AF2, &mmMPLL_TIME[0], sizeof(mmMPLL_TIME)/sizeof(mmMPLL_TIME[0]), 0, 0 },
	{ "mmMPLL_SS1", REG_MMIO, 0x0AF3, &mmMPLL_SS1[0], sizeof(mmMPLL_SS1)/sizeof(mmMPLL_SS1[0]), 0, 0 },
	{ "mmMPLL_SS2", REG_MMIO, 0x0AF4, &mmMPLL_SS2[0], sizeof(mmMPLL_SS2)/sizeof(mmMPLL_SS2[0]), 0, 0 },
	{ "mmMPLL_CONTROL", REG_MMIO, 0x0AF5, &mmMPLL_CONTROL[0], sizeof(mmMPLL_CONTROL)/sizeof(mmMPLL_CONTROL[0]), 0, 0 },
	{ "mmMPLL_AD_STATUS", REG_MMIO, 0x0AF6, &mmMPLL_AD_STATUS[0], sizeof(mmMPLL_AD_STATUS)/sizeof(mmMPLL_AD_STATUS[0]), 0, 0 },
	{ "mmMPLL_DQ_0_0_STATUS", REG_MMIO, 0x0AF7, &mmMPLL_DQ_0_0_STATUS[0], sizeof(mmMPLL_DQ_0_0_STATUS)/sizeof(mmMPLL_DQ_0_0_STATUS[0]), 0, 0 },
	{ "mmMPLL_DQ_0_1_STATUS", REG_MMIO, 0x0AF8, &mmMPLL_DQ_0_1_STATUS[0], sizeof(mmMPLL_DQ_0_1_STATUS)/sizeof(mmMPLL_DQ_0_1_STATUS[0]), 0, 0 },
	{ "mmMPLL_DQ_1_0_STATUS", REG_MMIO, 0x0AF9, &mmMPLL_DQ_1_0_STATUS[0], sizeof(mmMPLL_DQ_1_0_STATUS)/sizeof(mmMPLL_DQ_1_0_STATUS[0]), 0, 0 },
	{ "mmMPLL_DQ_1_1_STATUS", REG_MMIO, 0x0AFA, &mmMPLL_DQ_1_1_STATUS[0], sizeof(mmMPLL_DQ_1_1_STATUS)/sizeof(mmMPLL_DQ_1_1_STATUS[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_2_D0", REG_MMIO, 0x0AFB, &mmMC_TRAIN_PRBSERR_2_D0[0], sizeof(mmMC_TRAIN_PRBSERR_2_D0)/sizeof(mmMC_TRAIN_PRBSERR_2_D0[0]), 0, 0 },
	{ "mmMC_TRAIN_PRBSERR_2_D1", REG_MMIO, 0x0AFC, &mmMC_TRAIN_PRBSERR_2_D1[0], sizeof(mmMC_TRAIN_PRBSERR_2_D1)/sizeof(mmMC_TRAIN_PRBSERR_2_D1[0]), 0, 0 },
	{ "mmMC_SEQ_PERF_CNTL_1", REG_MMIO, 0x0AFD, &mmMC_SEQ_PERF_CNTL_1[0], sizeof(mmMC_SEQ_PERF_CNTL_1)/sizeof(mmMC_SEQ_PERF_CNTL_1[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD2", REG_MMIO, 0x0AFE, &mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0]), 0, 0 },
	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD3", REG_MMIO, 0x0AFF, &mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0]), 0, 0 },
	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0x0C80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0x0C81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0x0C82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0x0C83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0x0C84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0x0C85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0x0C86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0x0C87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0x0C88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0x0C89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0x0C8A, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0x0C8B, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0x0C8C, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
	{ "mmMC_XBAR_ARB", REG_MMIO, 0x0C8D, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0x0C8E, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_CNTL0", REG_MMIO, 0x0C8F, &mmMC_XBAR_PERF_MON_CNTL0[0], sizeof(mmMC_XBAR_PERF_MON_CNTL0)/sizeof(mmMC_XBAR_PERF_MON_CNTL0[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_CNTL1", REG_MMIO, 0x0C90, &mmMC_XBAR_PERF_MON_CNTL1[0], sizeof(mmMC_XBAR_PERF_MON_CNTL1)/sizeof(mmMC_XBAR_PERF_MON_CNTL1[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_CNTL2", REG_MMIO, 0x0C91, &mmMC_XBAR_PERF_MON_CNTL2[0], sizeof(mmMC_XBAR_PERF_MON_CNTL2)/sizeof(mmMC_XBAR_PERF_MON_CNTL2[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_RSLT0", REG_MMIO, 0x0C92, &mmMC_XBAR_PERF_MON_RSLT0[0], sizeof(mmMC_XBAR_PERF_MON_RSLT0)/sizeof(mmMC_XBAR_PERF_MON_RSLT0[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_RSLT1", REG_MMIO, 0x0C93, &mmMC_XBAR_PERF_MON_RSLT1[0], sizeof(mmMC_XBAR_PERF_MON_RSLT1)/sizeof(mmMC_XBAR_PERF_MON_RSLT1[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_RSLT2", REG_MMIO, 0x0C94, &mmMC_XBAR_PERF_MON_RSLT2[0], sizeof(mmMC_XBAR_PERF_MON_RSLT2)/sizeof(mmMC_XBAR_PERF_MON_RSLT2[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_RSLT3", REG_MMIO, 0x0C95, &mmMC_XBAR_PERF_MON_RSLT3[0], sizeof(mmMC_XBAR_PERF_MON_RSLT3)/sizeof(mmMC_XBAR_PERF_MON_RSLT3[0]), 0, 0 },
	{ "mmMC_XBAR_PERF_MON_MAX_THSH", REG_MMIO, 0x0C96, &mmMC_XBAR_PERF_MON_MAX_THSH[0], sizeof(mmMC_XBAR_PERF_MON_MAX_THSH)/sizeof(mmMC_XBAR_PERF_MON_MAX_THSH[0]), 0, 0 },
	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0x0C97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0x0C98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0x0CC0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0x0CC1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0x0CC2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0x0CC3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0x0CC4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0x0CC5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0x0CC6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0x0CC7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
	{ "mmATC_ATS_CNTL", REG_MMIO, 0x0CC9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
	{ "mmATC_ATS_DEBUG", REG_MMIO, 0x0CCA, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0x0CCB, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
	{ "mmATC_ATS_STATUS", REG_MMIO, 0x0CCC, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0x0CCD, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0x0CCE, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0x0CCF, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0x0CD0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0x0CD1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
	{ "mmATC_MISC_CG", REG_MMIO, 0x0CD4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
	{ "mmATC_L2_CNTL", REG_MMIO, 0x0CD5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
	{ "mmATC_L2_DEBUG", REG_MMIO, 0x0CD7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
	{ "mmATC_L1_CNTL", REG_MMIO, 0x0CDC, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0x0CDD, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0x0CDE, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0x0CDF, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
	{ "mmATC_L1RD_STATUS", REG_MMIO, 0x0CE0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
	{ "mmATC_L1WR_STATUS", REG_MMIO, 0x0CE1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0x0CE6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0x0CE7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0x0CE8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0x0CE9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0x0CEA, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0x0CEB, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0x0CEC, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0x0CED, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0x0CEE, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0x0CEF, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0x0CF0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0x0CF1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0x0CF2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0x0CF3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0x0CF4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0x0CF5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0x0CF6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0x0D40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0x0D41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0x0D42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
	{ "mmGMCON_MISC", REG_MMIO, 0x0D43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
	{ "mmGMCON_MISC2", REG_MMIO, 0x0D44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0x0D45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0x0D46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0x0D47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0x0D48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0x0D49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0x0D4A, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0x0D4B, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0x0D4C, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0x0D4D, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0x0D4E, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0x0D4F, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0x0D50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
	{ "mmGMCON_MISC3", REG_MMIO, 0x0D51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
	{ "mmGMCON_DEBUG", REG_MMIO, 0x0D5F, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },