path: root/src/lib/ip/gfx72_regs.i

	{ "ixCLIPPER_DEBUG_REG00", REG_SMC, 0x0, &ixCLIPPER_DEBUG_REG00[0], sizeof(ixCLIPPER_DEBUG_REG00)/sizeof(ixCLIPPER_DEBUG_REG00[0]), 0, 0 },
	{ "ixPA_SC_DEBUG_REG0", REG_SMC, 0x0, &ixPA_SC_DEBUG_REG0[0], sizeof(ixPA_SC_DEBUG_REG0)/sizeof(ixPA_SC_DEBUG_REG0[0]), 0, 0 },
	{ "mmCSPRIV_CONNECT", REG_MMIO, 0x0, &mmCSPRIV_CONNECT[0], sizeof(mmCSPRIV_CONNECT)/sizeof(mmCSPRIV_CONNECT[0]), 0, 0 },
	{ "ixWD_DEBUG_REG0", REG_SMC, 0x0, &ixWD_DEBUG_REG0[0], sizeof(ixWD_DEBUG_REG0)/sizeof(ixWD_DEBUG_REG0[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG01", REG_SMC, 0x1, &ixCLIPPER_DEBUG_REG01[0], sizeof(ixCLIPPER_DEBUG_REG01)/sizeof(ixCLIPPER_DEBUG_REG01[0]), 0, 0 },
	{ "ixPA_SC_DEBUG_REG1", REG_SMC, 0x1, &ixPA_SC_DEBUG_REG1[0], sizeof(ixPA_SC_DEBUG_REG1)/sizeof(ixPA_SC_DEBUG_REG1[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG1", REG_SMC, 0x1, &ixGDS_DEBUG_REG1[0], sizeof(ixGDS_DEBUG_REG1)/sizeof(ixGDS_DEBUG_REG1[0]), 0, 0 },
	{ "ixWD_DEBUG_REG1", REG_SMC, 0x1, &ixWD_DEBUG_REG1[0], sizeof(ixWD_DEBUG_REG1)/sizeof(ixWD_DEBUG_REG1[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG16", REG_SMC, 0x10, &ixCLIPPER_DEBUG_REG16[0], sizeof(ixCLIPPER_DEBUG_REG16)/sizeof(ixCLIPPER_DEBUG_REG16[0]), 0, 0 },
	{ "ixDIDT_SQ_WEIGHT0_3", REG_SMC, 0x10, &ixDIDT_SQ_WEIGHT0_3[0], sizeof(ixDIDT_SQ_WEIGHT0_3)/sizeof(ixDIDT_SQ_WEIGHT0_3[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG16", REG_SMC, 0x10, &ixVGT_DEBUG_REG16[0], sizeof(ixVGT_DEBUG_REG16)/sizeof(ixVGT_DEBUG_REG16[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG17", REG_SMC, 0x11, &ixCLIPPER_DEBUG_REG17[0], sizeof(ixCLIPPER_DEBUG_REG17)/sizeof(ixCLIPPER_DEBUG_REG17[0]), 0, 0 },
	{ "ixDIDT_SQ_WEIGHT4_7", REG_SMC, 0x11, &ixDIDT_SQ_WEIGHT4_7[0], sizeof(ixDIDT_SQ_WEIGHT4_7)/sizeof(ixDIDT_SQ_WEIGHT4_7[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG17", REG_SMC, 0x11, &ixVGT_DEBUG_REG17[0], sizeof(ixVGT_DEBUG_REG17)/sizeof(ixVGT_DEBUG_REG17[0]), 0, 0 },
	{ "ixSQ_WAVE_MODE", REG_SMC, 0x11, &ixSQ_WAVE_MODE[0], sizeof(ixSQ_WAVE_MODE)/sizeof(ixSQ_WAVE_MODE[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG18", REG_SMC, 0x12, &ixCLIPPER_DEBUG_REG18[0], sizeof(ixCLIPPER_DEBUG_REG18)/sizeof(ixCLIPPER_DEBUG_REG18[0]), 0, 0 },
	{ "ixDIDT_SQ_WEIGHT8_11", REG_SMC, 0x12, &ixDIDT_SQ_WEIGHT8_11[0], sizeof(ixDIDT_SQ_WEIGHT8_11)/sizeof(ixDIDT_SQ_WEIGHT8_11[0]), 0, 0 },
	{ "ixSQ_WAVE_STATUS", REG_SMC, 0x12, &ixSQ_WAVE_STATUS[0], sizeof(ixSQ_WAVE_STATUS)/sizeof(ixSQ_WAVE_STATUS[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG19", REG_SMC, 0x13, &ixCLIPPER_DEBUG_REG19[0], sizeof(ixCLIPPER_DEBUG_REG19)/sizeof(ixCLIPPER_DEBUG_REG19[0]), 0, 0 },
	{ "ixSQ_WAVE_TRAPSTS", REG_SMC, 0x13, &ixSQ_WAVE_TRAPSTS[0], sizeof(ixSQ_WAVE_TRAPSTS)/sizeof(ixSQ_WAVE_TRAPSTS[0]), 0, 0 },
	{ "ixSXIFCCG_DEBUG_REG0", REG_SMC, 0x14, &ixSXIFCCG_DEBUG_REG0[0], sizeof(ixSXIFCCG_DEBUG_REG0)/sizeof(ixSXIFCCG_DEBUG_REG0[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG20", REG_SMC, 0x14, &ixVGT_DEBUG_REG20[0], sizeof(ixVGT_DEBUG_REG20)/sizeof(ixVGT_DEBUG_REG20[0]), 0, 0 },
	{ "ixSQ_WAVE_HW_ID", REG_SMC, 0x14, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 },
	{ "ixSXIFCCG_DEBUG_REG1", REG_SMC, 0x15, &ixSXIFCCG_DEBUG_REG1[0], sizeof(ixSXIFCCG_DEBUG_REG1)/sizeof(ixSXIFCCG_DEBUG_REG1[0]), 0, 0 },
	{ "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x15, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG21", REG_SMC, 0x15, &ixVGT_DEBUG_REG21[0], sizeof(ixVGT_DEBUG_REG21)/sizeof(ixVGT_DEBUG_REG21[0]), 0, 0 },
	{ "ixSXIFCCG_DEBUG_REG2", REG_SMC, 0x16, &ixSXIFCCG_DEBUG_REG2[0], sizeof(ixSXIFCCG_DEBUG_REG2)/sizeof(ixSXIFCCG_DEBUG_REG2[0]), 0, 0 },
	{ "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x16, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG22", REG_SMC, 0x16, &ixVGT_DEBUG_REG22[0], sizeof(ixVGT_DEBUG_REG22)/sizeof(ixVGT_DEBUG_REG22[0]), 0, 0 },
	{ "ixSXIFCCG_DEBUG_REG3", REG_SMC, 0x17, &ixSXIFCCG_DEBUG_REG3[0], sizeof(ixSXIFCCG_DEBUG_REG3)/sizeof(ixSXIFCCG_DEBUG_REG3[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG23", REG_SMC, 0x17, &ixVGT_DEBUG_REG23[0], sizeof(ixVGT_DEBUG_REG23)/sizeof(ixVGT_DEBUG_REG23[0]), 0, 0 },
	{ "ixSQ_WAVE_IB_STS", REG_SMC, 0x17, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG0", REG_SMC, 0x18, &ixSETUP_DEBUG_REG0[0], sizeof(ixSETUP_DEBUG_REG0)/sizeof(ixSETUP_DEBUG_REG0[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG24", REG_SMC, 0x18, &ixVGT_DEBUG_REG24[0], sizeof(ixVGT_DEBUG_REG24)/sizeof(ixVGT_DEBUG_REG24[0]), 0, 0 },
	{ "ixSQ_WAVE_PC_LO", REG_SMC, 0x18, &ixSQ_WAVE_PC_LO[0], sizeof(ixSQ_WAVE_PC_LO)/sizeof(ixSQ_WAVE_PC_LO[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG1", REG_SMC, 0x19, &ixSETUP_DEBUG_REG1[0], sizeof(ixSETUP_DEBUG_REG1)/sizeof(ixSETUP_DEBUG_REG1[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG25", REG_SMC, 0x19, &ixVGT_DEBUG_REG25[0], sizeof(ixVGT_DEBUG_REG25)/sizeof(ixVGT_DEBUG_REG25[0]), 0, 0 },
	{ "ixSQ_WAVE_PC_HI", REG_SMC, 0x19, &ixSQ_WAVE_PC_HI[0], sizeof(ixSQ_WAVE_PC_HI)/sizeof(ixSQ_WAVE_PC_HI[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG2", REG_SMC, 0x1a, &ixSETUP_DEBUG_REG2[0], sizeof(ixSETUP_DEBUG_REG2)/sizeof(ixSETUP_DEBUG_REG2[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG3", REG_SMC, 0x1b, &ixSETUP_DEBUG_REG3[0], sizeof(ixSETUP_DEBUG_REG3)/sizeof(ixSETUP_DEBUG_REG3[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG27", REG_SMC, 0x1b, &ixVGT_DEBUG_REG27[0], sizeof(ixVGT_DEBUG_REG27)/sizeof(ixVGT_DEBUG_REG27[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG4", REG_SMC, 0x1c, &ixSETUP_DEBUG_REG4[0], sizeof(ixSETUP_DEBUG_REG4)/sizeof(ixSETUP_DEBUG_REG4[0]), 0, 0 },
	{ "ixSQ_WAVE_IB_DBG0", REG_SMC, 0x1c, &ixSQ_WAVE_IB_DBG0[0], sizeof(ixSQ_WAVE_IB_DBG0)/sizeof(ixSQ_WAVE_IB_DBG0[0]), 0, 0 },
	{ "ixSETUP_DEBUG_REG5", REG_SMC, 0x1d, &ixSETUP_DEBUG_REG5[0], sizeof(ixSETUP_DEBUG_REG5)/sizeof(ixSETUP_DEBUG_REG5[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG29", REG_SMC, 0x1d, &ixVGT_DEBUG_REG29[0], sizeof(ixVGT_DEBUG_REG29)/sizeof(ixVGT_DEBUG_REG29[0]), 0, 0 },
	{ "mmCSPRIV_THREAD_TRACE_TG0", REG_MMIO, 0x1e, &mmCSPRIV_THREAD_TRACE_TG0[0], sizeof(mmCSPRIV_THREAD_TRACE_TG0)/sizeof(mmCSPRIV_THREAD_TRACE_TG0[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG2", REG_SMC, 0x1e, &ixVGT_DEBUG_REG2[0], sizeof(ixVGT_DEBUG_REG2)/sizeof(ixVGT_DEBUG_REG2[0]), 0, 0 },
	{ "mmCSPRIV_THREAD_TRACE_EVENT", REG_MMIO, 0x1f, &mmCSPRIV_THREAD_TRACE_EVENT[0], sizeof(mmCSPRIV_THREAD_TRACE_EVENT)/sizeof(mmCSPRIV_THREAD_TRACE_EVENT[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG3", REG_SMC, 0x1f, &ixVGT_DEBUG_REG3[0], sizeof(ixVGT_DEBUG_REG3)/sizeof(ixVGT_DEBUG_REG3[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG02", REG_SMC, 0x2, &ixCLIPPER_DEBUG_REG02[0], sizeof(ixCLIPPER_DEBUG_REG02)/sizeof(ixCLIPPER_DEBUG_REG02[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG2", REG_SMC, 0x2, &ixGDS_DEBUG_REG2[0], sizeof(ixGDS_DEBUG_REG2)/sizeof(ixGDS_DEBUG_REG2[0]), 0, 0 },
	{ "ixWD_DEBUG_REG2", REG_SMC, 0x2, &ixWD_DEBUG_REG2[0], sizeof(ixWD_DEBUG_REG2)/sizeof(ixWD_DEBUG_REG2[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG4", REG_SMC, 0x20, &ixVGT_DEBUG_REG4[0], sizeof(ixVGT_DEBUG_REG4)/sizeof(ixVGT_DEBUG_REG4[0]), 0, 0 },
	{ "ixDIDT_DB_CTRL0", REG_SMC, 0x20, &ixDIDT_DB_CTRL0[0], sizeof(ixDIDT_DB_CTRL0)/sizeof(ixDIDT_DB_CTRL0[0]), 0, 0 },
	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 },
	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 },
	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 },
	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 },
	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 },
	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 },
	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 },
	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 },
	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &mmGRBM_DEBUG_CNTL[0], sizeof(mmGRBM_DEBUG_CNTL)/sizeof(mmGRBM_DEBUG_CNTL[0]), 0, 0 },
	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200a, &mmGRBM_DEBUG_DATA[0], sizeof(mmGRBM_DEBUG_DATA)/sizeof(mmGRBM_DEBUG_DATA[0]), 0, 0 },
	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200c, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200d, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
	{ "mmGRBM_STATUS_SE2", REG_MMIO, 0x200e, &mmGRBM_STATUS_SE2[0], sizeof(mmGRBM_STATUS_SE2)/sizeof(mmGRBM_STATUS_SE2[0]), 0, 0 },
	{ "mmGRBM_STATUS_SE3", REG_MMIO, 0x200f, &mmGRBM_STATUS_SE3[0], sizeof(mmGRBM_STATUS_SE3)/sizeof(mmGRBM_STATUS_SE3[0]), 0, 0 },
	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &mmGRBM_DEBUG[0], sizeof(mmGRBM_DEBUG)/sizeof(mmGRBM_DEBUG[0]), 0, 0 },
	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &mmGRBM_DEBUG_SNAPSHOT[0], sizeof(mmGRBM_DEBUG_SNAPSHOT)/sizeof(mmGRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 },
	{ "mmGRBM_READ_ERROR2", REG_MMIO, 0x2017, &mmGRBM_READ_ERROR2[0], sizeof(mmGRBM_READ_ERROR2)/sizeof(mmGRBM_READ_ERROR2[0]), 0, 0 },
	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 },
	{ "mmDEBUG_INDEX", REG_MMIO, 0x203c, &mmDEBUG_INDEX[0], sizeof(mmDEBUG_INDEX)/sizeof(mmDEBUG_INDEX[0]), 0, 0 },
	{ "mmDEBUG_DATA", REG_MMIO, 0x203d, &mmDEBUG_DATA[0], sizeof(mmDEBUG_DATA)/sizeof(mmDEBUG_DATA[0]), 0, 0 },
	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203f, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 },
	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 },
	{ "mmCP_CPC_STATUS", REG_MMIO, 0x2084, &mmCP_CPC_STATUS[0], sizeof(mmCP_CPC_STATUS)/sizeof(mmCP_CPC_STATUS[0]), 0, 0 },
	{ "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x2085, &mmCP_CPC_BUSY_STAT[0], sizeof(mmCP_CPC_BUSY_STAT)/sizeof(mmCP_CPC_BUSY_STAT[0]), 0, 0 },
	{ "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x2086, &mmCP_CPC_STALLED_STAT1[0], sizeof(mmCP_CPC_STALLED_STAT1)/sizeof(mmCP_CPC_STALLED_STAT1[0]), 0, 0 },
	{ "mmCP_CPF_STATUS", REG_MMIO, 0x2087, &mmCP_CPF_STATUS[0], sizeof(mmCP_CPF_STATUS)/sizeof(mmCP_CPF_STATUS[0]), 0, 0 },
	{ "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x2088, &mmCP_CPF_BUSY_STAT[0], sizeof(mmCP_CPF_BUSY_STAT)/sizeof(mmCP_CPF_BUSY_STAT[0]), 0, 0 },
	{ "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x2089, &mmCP_CPF_STALLED_STAT1[0], sizeof(mmCP_CPF_STALLED_STAT1)/sizeof(mmCP_CPF_STALLED_STAT1[0]), 0, 0 },
	{ "mmCP_CPC_MC_CNTL", REG_MMIO, 0x208a, &mmCP_CPC_MC_CNTL[0], sizeof(mmCP_CPC_MC_CNTL)/sizeof(mmCP_CPC_MC_CNTL[0]), 0, 0 },
	{ "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x208b, &mmCP_CPC_GRBM_FREE_COUNT[0], sizeof(mmCP_CPC_GRBM_FREE_COUNT)/sizeof(mmCP_CPC_GRBM_FREE_COUNT[0]), 0, 0 },
	{ "mmCP_MEC_CNTL", REG_MMIO, 0x208d, &mmCP_MEC_CNTL[0], sizeof(mmCP_MEC_CNTL)/sizeof(mmCP_MEC_CNTL[0]), 0, 0 },
	{ "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x208e, &mmCP_MEC_ME1_HEADER_DUMP[0], sizeof(mmCP_MEC_ME1_HEADER_DUMP)/sizeof(mmCP_MEC_ME1_HEADER_DUMP[0]), 0, 0 },
	{ "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x208f, &mmCP_MEC_ME2_HEADER_DUMP[0], sizeof(mmCP_MEC_ME2_HEADER_DUMP)/sizeof(mmCP_MEC_ME2_HEADER_DUMP[0]), 0, 0 },
	{ "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x2090, &mmCP_CPC_SCRATCH_INDEX[0], sizeof(mmCP_CPC_SCRATCH_INDEX)/sizeof(mmCP_CPC_SCRATCH_INDEX[0]), 0, 0 },
	{ "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x2091, &mmCP_CPC_SCRATCH_DATA[0], sizeof(mmCP_CPC_SCRATCH_DATA)/sizeof(mmCP_CPC_SCRATCH_DATA[0]), 0, 0 },
	{ "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x20a7, &mmCP_CPC_HALT_HYST_COUNT[0], sizeof(mmCP_CPC_HALT_HYST_COUNT)/sizeof(mmCP_CPC_HALT_HYST_COUNT[0]), 0, 0 },
	{ "mmCP_PRT_LOD_STATS_CNTL0", REG_MMIO, 0x20ad, &mmCP_PRT_LOD_STATS_CNTL0[0], sizeof(mmCP_PRT_LOD_STATS_CNTL0)/sizeof(mmCP_PRT_LOD_STATS_CNTL0[0]), 0, 0 },
	{ "mmCP_PRT_LOD_STATS_CNTL1", REG_MMIO, 0x20ae, &mmCP_PRT_LOD_STATS_CNTL1[0], sizeof(mmCP_PRT_LOD_STATS_CNTL1)/sizeof(mmCP_PRT_LOD_STATS_CNTL1[0]), 0, 0 },
	{ "mmCP_PRT_LOD_STATS_CNTL2", REG_MMIO, 0x20af, &mmCP_PRT_LOD_STATS_CNTL2[0], sizeof(mmCP_PRT_LOD_STATS_CNTL2)/sizeof(mmCP_PRT_LOD_STATS_CNTL2[0]), 0, 0 },
	{ "ixSQ_INTERRUPT_WORD_AUTO", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_AUTO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO[0]), 0, 0 },
	{ "ixSQ_INTERRUPT_WORD_CMN", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_CMN[0], sizeof(ixSQ_INTERRUPT_WORD_CMN)/sizeof(ixSQ_INTERRUPT_WORD_CMN[0]), 0, 0 },
	{ "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x20c0, &mmCP_CE_COMPARE_COUNT[0], sizeof(mmCP_CE_COMPARE_COUNT)/sizeof(mmCP_CE_COMPARE_COUNT[0]), 0, 0 },
	{ "mmCP_CE_DE_COUNT", REG_MMIO, 0x20c1, &mmCP_CE_DE_COUNT[0], sizeof(mmCP_CE_DE_COUNT)/sizeof(mmCP_CE_DE_COUNT[0]), 0, 0 },
	{ "mmCP_DE_CE_COUNT", REG_MMIO, 0x20c2, &mmCP_DE_CE_COUNT[0], sizeof(mmCP_DE_CE_COUNT)/sizeof(mmCP_DE_CE_COUNT[0]), 0, 0 },
	{ "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x20c3, &mmCP_DE_LAST_INVAL_COUNT[0], sizeof(mmCP_DE_LAST_INVAL_COUNT)/sizeof(mmCP_DE_LAST_INVAL_COUNT[0]), 0, 0 },
	{ "mmCP_DE_DE_COUNT", REG_MMIO, 0x20c4, &mmCP_DE_DE_COUNT[0], sizeof(mmCP_DE_DE_COUNT)/sizeof(mmCP_DE_DE_COUNT[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG5", REG_SMC, 0x21, &ixVGT_DEBUG_REG5[0], sizeof(ixVGT_DEBUG_REG5)/sizeof(ixVGT_DEBUG_REG5[0]), 0, 0 },
	{ "ixDIDT_DB_CTRL1", REG_SMC, 0x21, &ixDIDT_DB_CTRL1[0], sizeof(ixDIDT_DB_CTRL1)/sizeof(ixDIDT_DB_CTRL1[0]), 0, 0 },
	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219c, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 },
	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219d, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 },
	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219e, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 },
	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219f, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 },
	{ "mmCP_STAT", REG_MMIO, 0x21a0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 },
	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21a1, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 },
	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21a2, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 },
	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21a3, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 },
	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21a4, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 },
	{ "mmCP_MC_PACK_DELAY_CNT", REG_MMIO, 0x21a7, &mmCP_MC_PACK_DELAY_CNT[0], sizeof(mmCP_MC_PACK_DELAY_CNT)/sizeof(mmCP_MC_PACK_DELAY_CNT[0]), 0, 0 },
	{ "mmCP_MC_TAG_CNTL", REG_MMIO, 0x21a8, &mmCP_MC_TAG_CNTL[0], sizeof(mmCP_MC_TAG_CNTL)/sizeof(mmCP_MC_TAG_CNTL[0]), 0, 0 },
	{ "mmCP_MC_TAG_DATA", REG_MMIO, 0x21a9, &mmCP_MC_TAG_DATA[0], sizeof(mmCP_MC_TAG_DATA)/sizeof(mmCP_MC_TAG_DATA[0]), 0, 0 },
	{ "mmCP_CSF_STAT", REG_MMIO, 0x21b4, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 },
	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21b5, &mmCP_CSF_CNTL[0], sizeof(mmCP_CSF_CNTL)/sizeof(mmCP_CSF_CNTL[0]), 0, 0 },
	{ "mmCP_ME_CNTL", REG_MMIO, 0x21b6, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 },
	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21b8, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 },
	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21b9, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 },
	{ "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x21bc, &mmCP_ROQ_THRESHOLDS[0], sizeof(mmCP_ROQ_THRESHOLDS)/sizeof(mmCP_ROQ_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x21bd, &mmCP_MEQ_STQ_THRESHOLD[0], sizeof(mmCP_MEQ_STQ_THRESHOLD)/sizeof(mmCP_MEQ_STQ_THRESHOLD[0]), 0, 0 },
	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21be, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 },
	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21bf, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 },
	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21c0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 },
	{ "mmCP_RB_RPTR", REG_MMIO, 0x21c0, &mmCP_RB_RPTR[0], sizeof(mmCP_RB_RPTR)/sizeof(mmCP_RB_RPTR[0]), 0, 0 },
	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21c1, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 },
	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21c2, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21d5, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21d6, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21d7, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21d8, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21d9, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 },
	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21da, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 },
	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21db, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 },
	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21dc, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 },
	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21dd, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 },
	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21de, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 },
	{ "mmCP_CMD_DATA", REG_MMIO, 0x21df, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 },
	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21e0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 },
	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21e1, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 },
	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21e2, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 },
	{ "mmCP_STQ_STAT", REG_MMIO, 0x21e3, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 },
	{ "mmCP_STQ_WR_STAT", REG_MMIO, 0x21e4, &mmCP_STQ_WR_STAT[0], sizeof(mmCP_STQ_WR_STAT)/sizeof(mmCP_STQ_WR_STAT[0]), 0, 0 },
	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21e5, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 },
	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21e6, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 },
	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21e7, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 },
	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21e8, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 },
	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21e9, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 },
	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21ea, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 },
	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21f7, &mmCP_INT_STAT_DEBUG[0], sizeof(mmCP_INT_STAT_DEBUG)/sizeof(mmCP_INT_STAT_DEBUG[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG6", REG_SMC, 0x22, &ixVGT_DEBUG_REG6[0], sizeof(ixVGT_DEBUG_REG6)/sizeof(ixVGT_DEBUG_REG6[0]), 0, 0 },
	{ "ixDIDT_DB_CTRL2", REG_SMC, 0x22, &ixDIDT_DB_CTRL2[0], sizeof(ixDIDT_DB_CTRL2)/sizeof(ixDIDT_DB_CTRL2[0]), 0, 0 },
	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222c, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222d, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222e, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222f, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 },
	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 },
	{ "mmVGT_RESET_DEBUG", REG_MMIO, 0x2232, &mmVGT_RESET_DEBUG[0], sizeof(mmVGT_RESET_DEBUG)/sizeof(mmVGT_RESET_DEBUG[0]), 0, 0 },
	{ "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x2233, &mmVGT_STRMOUT_DELAY[0], sizeof(mmVGT_STRMOUT_DELAY)/sizeof(mmVGT_STRMOUT_DELAY[0]), 0, 0 },
	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 },
	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 },
	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 },
	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 },
	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &mmVGT_DEBUG_CNTL[0], sizeof(mmVGT_DEBUG_CNTL)/sizeof(mmVGT_DEBUG_CNTL[0]), 0, 0 },
	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &mmVGT_DEBUG_DATA[0], sizeof(mmVGT_DEBUG_DATA)/sizeof(mmVGT_DEBUG_DATA[0]), 0, 0 },
	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223a, &mmIA_DEBUG_CNTL[0], sizeof(mmIA_DEBUG_CNTL)/sizeof(mmIA_DEBUG_CNTL[0]), 0, 0 },
	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223b, &mmIA_DEBUG_DATA[0], sizeof(mmIA_DEBUG_DATA)/sizeof(mmIA_DEBUG_DATA[0]), 0, 0 },
	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223c, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 },
	{ "mmWD_DEBUG_CNTL", REG_MMIO, 0x223d, &mmWD_DEBUG_CNTL[0], sizeof(mmWD_DEBUG_CNTL)/sizeof(mmWD_DEBUG_CNTL[0]), 0, 0 },
	{ "mmWD_DEBUG_DATA", REG_MMIO, 0x223e, &mmWD_DEBUG_DATA[0], sizeof(mmWD_DEBUG_DATA)/sizeof(mmWD_DEBUG_DATA[0]), 0, 0 },
	{ "mmWD_CNTL_STATUS", REG_MMIO, 0x223f, &mmWD_CNTL_STATUS[0], sizeof(mmWD_CNTL_STATUS)/sizeof(mmWD_CNTL_STATUS[0]), 0, 0 },
	{ "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x2240, &mmCC_GC_PRIM_CONFIG[0], sizeof(mmCC_GC_PRIM_CONFIG)/sizeof(mmCC_GC_PRIM_CONFIG[0]), 0, 0 },
	{ "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x2241, &mmGC_USER_PRIM_CONFIG[0], sizeof(mmGC_USER_PRIM_CONFIG)/sizeof(mmGC_USER_PRIM_CONFIG[0]), 0, 0 },
	{ "mmIA_VMID_OVERRIDE", REG_MMIO, 0x2260, &mmIA_VMID_OVERRIDE[0], sizeof(mmIA_VMID_OVERRIDE)/sizeof(mmIA_VMID_OVERRIDE[0]), 0, 0 },
	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 },
	{ "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x2268, &mmVGT_VS_MAX_WAVE_ID[0], sizeof(mmVGT_VS_MAX_WAVE_ID)/sizeof(mmVGT_VS_MAX_WAVE_ID[0]), 0, 0 },
	{ "mmGFX_PIPE_CONTROL", REG_MMIO, 0x226d, &mmGFX_PIPE_CONTROL[0], sizeof(mmGFX_PIPE_CONTROL)/sizeof(mmGFX_PIPE_CONTROL[0]), 0, 0 },
	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226f, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
	{ "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x2271, &mmVGT_DMA_PRIMITIVE_TYPE[0], sizeof(mmVGT_DMA_PRIMITIVE_TYPE)/sizeof(mmVGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 },
	{ "mmVGT_DMA_CONTROL", REG_MMIO, 0x2272, &mmVGT_DMA_CONTROL[0], sizeof(mmVGT_DMA_CONTROL)/sizeof(mmVGT_DMA_CONTROL[0]), 0, 0 },
	{ "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x2273, &mmVGT_DMA_LS_HS_CONFIG[0], sizeof(mmVGT_DMA_LS_HS_CONFIG)/sizeof(mmVGT_DMA_LS_HS_CONFIG[0]), 0, 0 },
	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &mmPA_SU_DEBUG_CNTL[0], sizeof(mmPA_SU_DEBUG_CNTL)/sizeof(mmPA_SU_DEBUG_CNTL[0]), 0, 0 },
	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &mmPA_SU_DEBUG_DATA[0], sizeof(mmPA_SU_DEBUG_DATA)/sizeof(mmPA_SU_DEBUG_DATA[0]), 0, 0 },
	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 },
	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 },
	{ "mmPA_CL_RESET_DEBUG", REG_MMIO, 0x2286, &mmPA_CL_RESET_DEBUG[0], sizeof(mmPA_CL_RESET_DEBUG)/sizeof(mmPA_CL_RESET_DEBUG[0]), 0, 0 },
	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 },
	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c0, &mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c1, &mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c2, &mmPA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22c9, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22f3, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 },
	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22f5, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 },
	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22f6, &mmPA_SC_DEBUG_CNTL[0], sizeof(mmPA_SC_DEBUG_CNTL)/sizeof(mmPA_SC_DEBUG_CNTL[0]), 0, 0 },
	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22f7, &mmPA_SC_DEBUG_DATA[0], sizeof(mmPA_SC_DEBUG_DATA)/sizeof(mmPA_SC_DEBUG_DATA[0]), 0, 0 },
	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22fc, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG7", REG_SMC, 0x23, &ixVGT_DEBUG_REG7[0], sizeof(ixVGT_DEBUG_REG7)/sizeof(ixVGT_DEBUG_REG7[0]), 0, 0 },
	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 },
	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 },
	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 },
	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 },
	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 },
	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &mmCC_SQC_BANK_DISABLE[0], sizeof(mmCC_SQC_BANK_DISABLE)/sizeof(mmCC_SQC_BANK_DISABLE[0]), 0, 0 },
	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &mmUSER_SQC_BANK_DISABLE[0], sizeof(mmUSER_SQC_BANK_DISABLE)/sizeof(mmUSER_SQC_BANK_DISABLE[0]), 0, 0 },
	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &mmSQ_DEBUG_STS_GLOBAL[0], sizeof(mmSQ_DEBUG_STS_GLOBAL)/sizeof(mmSQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
	{ "mmSH_MEM_BASES", REG_MMIO, 0x230a, &mmSH_MEM_BASES[0], sizeof(mmSH_MEM_BASES)/sizeof(mmSH_MEM_BASES[0]), 0, 0 },
	{ "mmSH_MEM_APE1_BASE", REG_MMIO, 0x230b, &mmSH_MEM_APE1_BASE[0], sizeof(mmSH_MEM_APE1_BASE)/sizeof(mmSH_MEM_APE1_BASE[0]), 0, 0 },
	{ "mmSH_MEM_APE1_LIMIT", REG_MMIO, 0x230c, &mmSH_MEM_APE1_LIMIT[0], sizeof(mmSH_MEM_APE1_LIMIT)/sizeof(mmSH_MEM_APE1_LIMIT[0]), 0, 0 },
	{ "mmSH_MEM_CONFIG", REG_MMIO, 0x230d, &mmSH_MEM_CONFIG[0], sizeof(mmSH_MEM_CONFIG)/sizeof(mmSH_MEM_CONFIG[0]), 0, 0 },
	{ "mmSQC_POLICY", REG_MMIO, 0x230e, &mmSQC_POLICY[0], sizeof(mmSQC_POLICY)/sizeof(mmSQC_POLICY[0]), 0, 0 },
	{ "mmSQC_VOLATILE", REG_MMIO, 0x230f, &mmSQC_VOLATILE[0], sizeof(mmSQC_VOLATILE)/sizeof(mmSQC_VOLATILE[0]), 0, 0 },
	{ "mmSQ_DEBUG_STS_GLOBAL2", REG_MMIO, 0x2310, &mmSQ_DEBUG_STS_GLOBAL2[0], sizeof(mmSQ_DEBUG_STS_GLOBAL2)/sizeof(mmSQ_DEBUG_STS_GLOBAL2[0]), 0, 0 },
	{ "mmSQ_DEBUG_STS_GLOBAL3", REG_MMIO, 0x2311, &mmSQ_DEBUG_STS_GLOBAL3[0], sizeof(mmSQ_DEBUG_STS_GLOBAL3)/sizeof(mmSQ_DEBUG_STS_GLOBAL3[0]), 0, 0 },
	{ "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x2314, &mmSQ_INTERRUPT_AUTO_MASK[0], sizeof(mmSQ_INTERRUPT_AUTO_MASK)/sizeof(mmSQ_INTERRUPT_AUTO_MASK[0]), 0, 0 },
	{ "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x2315, &mmSQ_INTERRUPT_MSG_CTRL[0], sizeof(mmSQ_INTERRUPT_MSG_CTRL)/sizeof(mmSQ_INTERRUPT_MSG_CTRL[0]), 0, 0 },
	{ "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x2374, &mmSQ_REG_TIMESTAMP[0], sizeof(mmSQ_REG_TIMESTAMP)/sizeof(mmSQ_REG_TIMESTAMP[0]), 0, 0 },
	{ "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x2375, &mmSQ_CMD_TIMESTAMP[0], sizeof(mmSQ_CMD_TIMESTAMP)/sizeof(mmSQ_CMD_TIMESTAMP[0]), 0, 0 },
	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 },
	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 },
	{ "mmSQ_IND_CMD", REG_MMIO, 0x237a, NULL, 0, 0, 0 },
	{ "mmSQ_CMD", REG_MMIO, 0x237b, &mmSQ_CMD[0], sizeof(mmSQ_CMD)/sizeof(mmSQ_CMD[0]), 0, 0 },
	{ "mmSQ_TIME_HI", REG_MMIO, 0x237c, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 },
	{ "mmSQ_TIME_LO", REG_MMIO, 0x237d, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 },
	{ "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x237f, &mmSQ_VOP3_0_SDST_ENC[0], sizeof(mmSQ_VOP3_0_SDST_ENC)/sizeof(mmSQ_VOP3_0_SDST_ENC[0]), 0, 0 },
	{ "mmSQ_MTBUF_1", REG_MMIO, 0x237f, &mmSQ_MTBUF_1[0], sizeof(mmSQ_MTBUF_1)/sizeof(mmSQ_MTBUF_1[0]), 0, 0 },
	{ "mmSQ_VOP3_0", REG_MMIO, 0x237f, &mmSQ_VOP3_0[0], sizeof(mmSQ_VOP3_0)/sizeof(mmSQ_VOP3_0[0]), 0, 0 },
	{ "mmSQ_EXP_1", REG_MMIO, 0x237f, &mmSQ_EXP_1[0], sizeof(mmSQ_EXP_1)/sizeof(mmSQ_EXP_1[0]), 0, 0 },
	{ "mmSQ_SOP2", REG_MMIO, 0x237f, &mmSQ_SOP2[0], sizeof(mmSQ_SOP2)/sizeof(mmSQ_SOP2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0x2380, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0x2381, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0x2382, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0x2383, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0x2384, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0x2385, &mmSQ_THREAD_TRACE_BASE2[0], sizeof(mmSQ_THREAD_TRACE_BASE2)/sizeof(mmSQ_THREAD_TRACE_BASE2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0x2386, &mmSQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0x238c, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0x238d, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0x238e, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0x238f, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0x2392, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 },
	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &mmSQ_LB_DATA_ALU_CYCLES[0], sizeof(mmSQ_LB_DATA_ALU_CYCLES)/sizeof(mmSQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239a, &mmSQ_LB_DATA_TEX_CYCLES[0], sizeof(mmSQ_LB_DATA_TEX_CYCLES)/sizeof(mmSQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239b, &mmSQ_LB_DATA_ALU_STALLS[0], sizeof(mmSQ_LB_DATA_ALU_STALLS)/sizeof(mmSQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239c, &mmSQ_LB_DATA_TEX_STALLS[0], sizeof(mmSQ_LB_DATA_TEX_STALLS)/sizeof(mmSQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
	{ "mmSQC_SECDED_CNT", REG_MMIO, 0x23a0, &mmSQC_SECDED_CNT[0], sizeof(mmSQC_SECDED_CNT)/sizeof(mmSQC_SECDED_CNT[0]), 0, 0 },
	{ "mmSQ_SEC_CNT", REG_MMIO, 0x23a1, &mmSQ_SEC_CNT[0], sizeof(mmSQ_SEC_CNT)/sizeof(mmSQ_SEC_CNT[0]), 0, 0 },
	{ "mmSQ_DED_CNT", REG_MMIO, 0x23a2, &mmSQ_DED_CNT[0], sizeof(mmSQ_DED_CNT)/sizeof(mmSQ_DED_CNT[0]), 0, 0 },
	{ "mmSQ_DED_INFO", REG_MMIO, 0x23a3, &mmSQ_DED_INFO[0], sizeof(mmSQ_DED_INFO)/sizeof(mmSQ_DED_INFO[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_EVENT[0], sizeof(mmSQ_THREAD_TRACE_WORD_EVENT)/sizeof(mmSQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST)/sizeof(mmSQ_THREAD_TRACE_WORD_INST[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 },
	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23c0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 },
	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23c1, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 },
	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23c2, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 },
	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23c3, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23c4, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23c5, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23c6, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23c7, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23c8, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23c9, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23ca, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 },
	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23cb, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 },
	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23cc, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 },
	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23cd, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 },
	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23ce, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 },
	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23cf, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 },
	{ "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x23d0, &mmSQ_FLAT_SCRATCH_WORD0[0], sizeof(mmSQ_FLAT_SCRATCH_WORD0)/sizeof(mmSQ_FLAT_SCRATCH_WORD0[0]), 0, 0 },
	{ "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x23d1, &mmSQ_FLAT_SCRATCH_WORD1[0], sizeof(mmSQ_FLAT_SCRATCH_WORD1)/sizeof(mmSQ_FLAT_SCRATCH_WORD1[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG26", REG_SMC, 0x24, &ixVGT_DEBUG_REG26[0], sizeof(ixVGT_DEBUG_REG26)/sizeof(ixVGT_DEBUG_REG26[0]), 0, 0 },
	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &mmSX_DEBUG_BUSY[0], sizeof(mmSX_DEBUG_BUSY)/sizeof(mmSX_DEBUG_BUSY[0]), 0, 0 },
	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &mmSX_DEBUG_BUSY_2[0], sizeof(mmSX_DEBUG_BUSY_2)/sizeof(mmSX_DEBUG_BUSY_2[0]), 0, 0 },
	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &mmSX_DEBUG_BUSY_3[0], sizeof(mmSX_DEBUG_BUSY_3)/sizeof(mmSX_DEBUG_BUSY_3[0]), 0, 0 },
	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &mmSX_DEBUG_BUSY_4[0], sizeof(mmSX_DEBUG_BUSY_4)/sizeof(mmSX_DEBUG_BUSY_4[0]), 0, 0 },
	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 },
	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243a, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 },
	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 },
	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &mmSPI_DEBUG_CNTL[0], sizeof(mmSPI_DEBUG_CNTL)/sizeof(mmSPI_DEBUG_CNTL[0]), 0, 0 },
	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &mmSPI_DEBUG_READ[0], sizeof(mmSPI_DEBUG_READ)/sizeof(mmSPI_DEBUG_READ[0]), 0, 0 },
	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244f, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 },
	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &mmSPI_DEBUG_BUSY[0], sizeof(mmSPI_DEBUG_BUSY)/sizeof(mmSPI_DEBUG_BUSY[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x24aa, &mmSPI_WF_LIFETIME_CNTL[0], sizeof(mmSPI_WF_LIFETIME_CNTL)/sizeof(mmSPI_WF_LIFETIME_CNTL[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x24ab, &mmSPI_WF_LIFETIME_LIMIT_0[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_0)/sizeof(mmSPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x24ac, &mmSPI_WF_LIFETIME_LIMIT_1[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_1)/sizeof(mmSPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x24ad, &mmSPI_WF_LIFETIME_LIMIT_2[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_2)/sizeof(mmSPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x24ae, &mmSPI_WF_LIFETIME_LIMIT_3[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_3)/sizeof(mmSPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x24af, &mmSPI_WF_LIFETIME_LIMIT_4[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_4)/sizeof(mmSPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x24b0, &mmSPI_WF_LIFETIME_LIMIT_5[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_5)/sizeof(mmSPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x24b1, &mmSPI_WF_LIFETIME_LIMIT_6[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_6)/sizeof(mmSPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x24b2, &mmSPI_WF_LIFETIME_LIMIT_7[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_7)/sizeof(mmSPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x24b3, &mmSPI_WF_LIFETIME_LIMIT_8[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_8)/sizeof(mmSPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x24b4, &mmSPI_WF_LIFETIME_LIMIT_9[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_9)/sizeof(mmSPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x24b5, &mmSPI_WF_LIFETIME_STATUS_0[0], sizeof(mmSPI_WF_LIFETIME_STATUS_0)/sizeof(mmSPI_WF_LIFETIME_STATUS_0[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x24b6, &mmSPI_WF_LIFETIME_STATUS_1[0], sizeof(mmSPI_WF_LIFETIME_STATUS_1)/sizeof(mmSPI_WF_LIFETIME_STATUS_1[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x24b7, &mmSPI_WF_LIFETIME_STATUS_2[0], sizeof(mmSPI_WF_LIFETIME_STATUS_2)/sizeof(mmSPI_WF_LIFETIME_STATUS_2[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x24b8, &mmSPI_WF_LIFETIME_STATUS_3[0], sizeof(mmSPI_WF_LIFETIME_STATUS_3)/sizeof(mmSPI_WF_LIFETIME_STATUS_3[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x24b9, &mmSPI_WF_LIFETIME_STATUS_4[0], sizeof(mmSPI_WF_LIFETIME_STATUS_4)/sizeof(mmSPI_WF_LIFETIME_STATUS_4[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x24ba, &mmSPI_WF_LIFETIME_STATUS_5[0], sizeof(mmSPI_WF_LIFETIME_STATUS_5)/sizeof(mmSPI_WF_LIFETIME_STATUS_5[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x24bb, &mmSPI_WF_LIFETIME_STATUS_6[0], sizeof(mmSPI_WF_LIFETIME_STATUS_6)/sizeof(mmSPI_WF_LIFETIME_STATUS_6[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x24bc, &mmSPI_WF_LIFETIME_STATUS_7[0], sizeof(mmSPI_WF_LIFETIME_STATUS_7)/sizeof(mmSPI_WF_LIFETIME_STATUS_7[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x24bd, &mmSPI_WF_LIFETIME_STATUS_8[0], sizeof(mmSPI_WF_LIFETIME_STATUS_8)/sizeof(mmSPI_WF_LIFETIME_STATUS_8[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x24be, &mmSPI_WF_LIFETIME_STATUS_9[0], sizeof(mmSPI_WF_LIFETIME_STATUS_9)/sizeof(mmSPI_WF_LIFETIME_STATUS_9[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x24bf, &mmSPI_WF_LIFETIME_STATUS_10[0], sizeof(mmSPI_WF_LIFETIME_STATUS_10)/sizeof(mmSPI_WF_LIFETIME_STATUS_10[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x24c0, &mmSPI_WF_LIFETIME_STATUS_11[0], sizeof(mmSPI_WF_LIFETIME_STATUS_11)/sizeof(mmSPI_WF_LIFETIME_STATUS_11[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x24c1, &mmSPI_WF_LIFETIME_STATUS_12[0], sizeof(mmSPI_WF_LIFETIME_STATUS_12)/sizeof(mmSPI_WF_LIFETIME_STATUS_12[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x24c2, &mmSPI_WF_LIFETIME_STATUS_13[0], sizeof(mmSPI_WF_LIFETIME_STATUS_13)/sizeof(mmSPI_WF_LIFETIME_STATUS_13[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x24c3, &mmSPI_WF_LIFETIME_STATUS_14[0], sizeof(mmSPI_WF_LIFETIME_STATUS_14)/sizeof(mmSPI_WF_LIFETIME_STATUS_14[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x24c4, &mmSPI_WF_LIFETIME_STATUS_15[0], sizeof(mmSPI_WF_LIFETIME_STATUS_15)/sizeof(mmSPI_WF_LIFETIME_STATUS_15[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x24c5, &mmSPI_WF_LIFETIME_STATUS_16[0], sizeof(mmSPI_WF_LIFETIME_STATUS_16)/sizeof(mmSPI_WF_LIFETIME_STATUS_16[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x24c6, &mmSPI_WF_LIFETIME_STATUS_17[0], sizeof(mmSPI_WF_LIFETIME_STATUS_17)/sizeof(mmSPI_WF_LIFETIME_STATUS_17[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x24c7, &mmSPI_WF_LIFETIME_STATUS_18[0], sizeof(mmSPI_WF_LIFETIME_STATUS_18)/sizeof(mmSPI_WF_LIFETIME_STATUS_18[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x24c8, &mmSPI_WF_LIFETIME_STATUS_19[0], sizeof(mmSPI_WF_LIFETIME_STATUS_19)/sizeof(mmSPI_WF_LIFETIME_STATUS_19[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x24c9, &mmSPI_WF_LIFETIME_STATUS_20[0], sizeof(mmSPI_WF_LIFETIME_STATUS_20)/sizeof(mmSPI_WF_LIFETIME_STATUS_20[0]), 0, 0 },
	{ "mmSPI_WF_LIFETIME_DEBUG", REG_MMIO, 0x24ca, &mmSPI_WF_LIFETIME_DEBUG[0], sizeof(mmSPI_WF_LIFETIME_DEBUG)/sizeof(mmSPI_WF_LIFETIME_DEBUG[0]), 0, 0 },
	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24d3, &mmSPI_SLAVE_DEBUG_BUSY[0], sizeof(mmSPI_SLAVE_DEBUG_BUSY)/sizeof(mmSPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24d4, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 },
	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24d5, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 },
	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24d6, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 },
	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24d7, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24d8, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 },
	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24d9, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24da, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x24db, &mmSPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS)/sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x24dc, &mmSPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x24dd, &mmSPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x24de, &mmSPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x24df, &mmSPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x24e0, &mmSPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x24e1, &mmSPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x24e2, &mmSPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 },
	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x24e3, &mmSPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 },
	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24eb, &mmBCI_DEBUG_READ[0], sizeof(mmBCI_DEBUG_READ)/sizeof(mmBCI_DEBUG_READ[0]), 0, 0 },
	{ "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24ec, &mmSPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
	{ "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24ed, &mmSPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
	{ "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24ee, &mmSPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
	{ "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24ef, &mmSPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
	{ "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f0, &mmSPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
	{ "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24f1, &mmSPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
	{ "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24f2, &mmSPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
	{ "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24f3, &mmSPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
	{ "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24f4, &mmSPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
	{ "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f5, &mmSPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG30", REG_SMC, 0x25, &ixVGT_DEBUG_REG30[0], sizeof(ixVGT_DEBUG_REG30)/sizeof(ixVGT_DEBUG_REG30[0]), 0, 0 },
	{ "mmTD_CNTL", REG_MMIO, 0x2525, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 },
	{ "mmTD_STATUS", REG_MMIO, 0x2526, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 },
	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &mmTD_DEBUG_INDEX[0], sizeof(mmTD_DEBUG_INDEX)/sizeof(mmTD_DEBUG_INDEX[0]), 0, 0 },
	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &mmTD_DEBUG_DATA[0], sizeof(mmTD_DEBUG_DATA)/sizeof(mmTD_DEBUG_DATA[0]), 0, 0 },
	{ "mmTD_SCRATCH", REG_MMIO, 0x2533, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 },
	{ "mmTA_CNTL", REG_MMIO, 0x2541, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
	{ "mmTA_RESERVED_010C", REG_MMIO, 0x2543, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 },
	{ "mmTA_STATUS", REG_MMIO, 0x2548, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254c, &mmTA_DEBUG_INDEX[0], sizeof(mmTA_DEBUG_INDEX)/sizeof(mmTA_DEBUG_INDEX[0]), 0, 0 },
	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254d, &mmTA_DEBUG_DATA[0], sizeof(mmTA_DEBUG_DATA)/sizeof(mmTA_DEBUG_DATA[0]), 0, 0 },
	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
	{ "mmSH_HIDDEN_PRIVATE_BASE_VMID", REG_MMIO, 0x2580, &mmSH_HIDDEN_PRIVATE_BASE_VMID[0], sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID)/sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID[0]), 0, 0 },
	{ "mmSH_STATIC_MEM_CONFIG", REG_MMIO, 0x2581, &mmSH_STATIC_MEM_CONFIG[0], sizeof(mmSH_STATIC_MEM_CONFIG)/sizeof(mmSH_STATIC_MEM_CONFIG[0]), 0, 0 },
	{ "mmGDS_CONFIG", REG_MMIO, 0x25c0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25c1, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 },
	{ "mmGDS_ENHANCE2", REG_MMIO, 0x25c2, &mmGDS_ENHANCE2[0], sizeof(mmGDS_ENHANCE2)/sizeof(mmGDS_ENHANCE2[0]), 0, 0 },
	{ "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x25c3, &mmGDS_PROTECTION_FAULT[0], sizeof(mmGDS_PROTECTION_FAULT)/sizeof(mmGDS_PROTECTION_FAULT[0]), 0, 0 },
	{ "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x25c4, &mmGDS_VM_PROTECTION_FAULT[0], sizeof(mmGDS_VM_PROTECTION_FAULT)/sizeof(mmGDS_VM_PROTECTION_FAULT[0]), 0, 0 },
	{ "mmGDS_SECDED_CNT", REG_MMIO, 0x25c5, &mmGDS_SECDED_CNT[0], sizeof(mmGDS_SECDED_CNT)/sizeof(mmGDS_SECDED_CNT[0]), 0, 0 },
	{ "mmGDS_GRBM_SECDED_CNT", REG_MMIO, 0x25c6, &mmGDS_GRBM_SECDED_CNT[0], sizeof(mmGDS_GRBM_SECDED_CNT)/sizeof(mmGDS_GRBM_SECDED_CNT[0]), 0, 0 },
	{ "mmGDS_OA_DED", REG_MMIO, 0x25c7, &mmGDS_OA_DED[0], sizeof(mmGDS_OA_DED)/sizeof(mmGDS_OA_DED[0]), 0, 0 },
	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25c8, &mmGDS_DEBUG_CNTL[0], sizeof(mmGDS_DEBUG_CNTL)/sizeof(mmGDS_DEBUG_CNTL[0]), 0, 0 },
	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25c9, &mmGDS_DEBUG_DATA[0], sizeof(mmGDS_DEBUG_DATA)/sizeof(mmGDS_DEBUG_DATA[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG31", REG_SMC, 0x26, &ixVGT_DEBUG_REG31[0], sizeof(ixVGT_DEBUG_REG31)/sizeof(ixVGT_DEBUG_REG31[0]), 0, 0 },
	{ "mmDB_DEBUG", REG_MMIO, 0x260c, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 },
	{ "mmDB_DEBUG2", REG_MMIO, 0x260d, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 },
	{ "mmDB_DEBUG3", REG_MMIO, 0x260e, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 },
	{ "mmDB_DEBUG4", REG_MMIO, 0x260f, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 },
	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 },
	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 },
	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 },
	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 },
	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 },
	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 },
	{ "mmDB_RING_CONTROL", REG_MMIO, 0x261b, &mmDB_RING_CONTROL[0], sizeof(mmDB_RING_CONTROL)/sizeof(mmDB_RING_CONTROL[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &mmDB_READ_DEBUG_0[0], sizeof(mmDB_READ_DEBUG_0)/sizeof(mmDB_READ_DEBUG_0[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &mmDB_READ_DEBUG_1[0], sizeof(mmDB_READ_DEBUG_1)/sizeof(mmDB_READ_DEBUG_1[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &mmDB_READ_DEBUG_2[0], sizeof(mmDB_READ_DEBUG_2)/sizeof(mmDB_READ_DEBUG_2[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &mmDB_READ_DEBUG_3[0], sizeof(mmDB_READ_DEBUG_3)/sizeof(mmDB_READ_DEBUG_3[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &mmDB_READ_DEBUG_4[0], sizeof(mmDB_READ_DEBUG_4)/sizeof(mmDB_READ_DEBUG_4[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &mmDB_READ_DEBUG_5[0], sizeof(mmDB_READ_DEBUG_5)/sizeof(mmDB_READ_DEBUG_5[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &mmDB_READ_DEBUG_6[0], sizeof(mmDB_READ_DEBUG_6)/sizeof(mmDB_READ_DEBUG_6[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &mmDB_READ_DEBUG_7[0], sizeof(mmDB_READ_DEBUG_7)/sizeof(mmDB_READ_DEBUG_7[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &mmDB_READ_DEBUG_8[0], sizeof(mmDB_READ_DEBUG_8)/sizeof(mmDB_READ_DEBUG_8[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &mmDB_READ_DEBUG_9[0], sizeof(mmDB_READ_DEBUG_9)/sizeof(mmDB_READ_DEBUG_9[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262a, &mmDB_READ_DEBUG_A[0], sizeof(mmDB_READ_DEBUG_A)/sizeof(mmDB_READ_DEBUG_A[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262b, &mmDB_READ_DEBUG_B[0], sizeof(mmDB_READ_DEBUG_B)/sizeof(mmDB_READ_DEBUG_B[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262c, &mmDB_READ_DEBUG_C[0], sizeof(mmDB_READ_DEBUG_C)/sizeof(mmDB_READ_DEBUG_C[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262d, &mmDB_READ_DEBUG_D[0], sizeof(mmDB_READ_DEBUG_D)/sizeof(mmDB_READ_DEBUG_D[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262e, &mmDB_READ_DEBUG_E[0], sizeof(mmDB_READ_DEBUG_E)/sizeof(mmDB_READ_DEBUG_E[0]), 0, 0 },
	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262f, &mmDB_READ_DEBUG_F[0], sizeof(mmDB_READ_DEBUG_F)/sizeof(mmDB_READ_DEBUG_F[0]), 0, 0 },
	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263c, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 },
	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263d, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 },
	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263e, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 },
	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263f, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 },
	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 },
	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 },
	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 },
	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 },
	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 },
	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 },
	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 },
	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 },
	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264a, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 },
	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264b, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 },
	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264c, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 },
	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264d, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 },
	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264e, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 },
	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264f, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 },
	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 },
	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 },
	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 },
	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 },
	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 },
	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 },
	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 },
	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 },
	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 },
	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 },
	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265a, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 },
	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265b, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 },
	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265c, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 },
	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265d, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 },
	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265e, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 },
	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265f, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 },
	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 },
	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 },
	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 },
	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE0", REG_MMIO, 0x2664, &mmGB_MACROTILE_MODE0[0], sizeof(mmGB_MACROTILE_MODE0)/sizeof(mmGB_MACROTILE_MODE0[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE1", REG_MMIO, 0x2665, &mmGB_MACROTILE_MODE1[0], sizeof(mmGB_MACROTILE_MODE1)/sizeof(mmGB_MACROTILE_MODE1[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE2", REG_MMIO, 0x2666, &mmGB_MACROTILE_MODE2[0], sizeof(mmGB_MACROTILE_MODE2)/sizeof(mmGB_MACROTILE_MODE2[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE3", REG_MMIO, 0x2667, &mmGB_MACROTILE_MODE3[0], sizeof(mmGB_MACROTILE_MODE3)/sizeof(mmGB_MACROTILE_MODE3[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE4", REG_MMIO, 0x2668, &mmGB_MACROTILE_MODE4[0], sizeof(mmGB_MACROTILE_MODE4)/sizeof(mmGB_MACROTILE_MODE4[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE5", REG_MMIO, 0x2669, &mmGB_MACROTILE_MODE5[0], sizeof(mmGB_MACROTILE_MODE5)/sizeof(mmGB_MACROTILE_MODE5[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE6", REG_MMIO, 0x266a, &mmGB_MACROTILE_MODE6[0], sizeof(mmGB_MACROTILE_MODE6)/sizeof(mmGB_MACROTILE_MODE6[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE7", REG_MMIO, 0x266b, &mmGB_MACROTILE_MODE7[0], sizeof(mmGB_MACROTILE_MODE7)/sizeof(mmGB_MACROTILE_MODE7[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE8", REG_MMIO, 0x266c, &mmGB_MACROTILE_MODE8[0], sizeof(mmGB_MACROTILE_MODE8)/sizeof(mmGB_MACROTILE_MODE8[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE9", REG_MMIO, 0x266d, &mmGB_MACROTILE_MODE9[0], sizeof(mmGB_MACROTILE_MODE9)/sizeof(mmGB_MACROTILE_MODE9[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE10", REG_MMIO, 0x266e, &mmGB_MACROTILE_MODE10[0], sizeof(mmGB_MACROTILE_MODE10)/sizeof(mmGB_MACROTILE_MODE10[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE11", REG_MMIO, 0x266f, &mmGB_MACROTILE_MODE11[0], sizeof(mmGB_MACROTILE_MODE11)/sizeof(mmGB_MACROTILE_MODE11[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE12", REG_MMIO, 0x2670, &mmGB_MACROTILE_MODE12[0], sizeof(mmGB_MACROTILE_MODE12)/sizeof(mmGB_MACROTILE_MODE12[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE13", REG_MMIO, 0x2671, &mmGB_MACROTILE_MODE13[0], sizeof(mmGB_MACROTILE_MODE13)/sizeof(mmGB_MACROTILE_MODE13[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE14", REG_MMIO, 0x2672, &mmGB_MACROTILE_MODE14[0], sizeof(mmGB_MACROTILE_MODE14)/sizeof(mmGB_MACROTILE_MODE14[0]), 0, 0 },
	{ "mmGB_MACROTILE_MODE15", REG_MMIO, 0x2673, &mmGB_MACROTILE_MODE15[0], sizeof(mmGB_MACROTILE_MODE15)/sizeof(mmGB_MACROTILE_MODE15[0]), 0, 0 },
	{ "mmCB_HW_CONTROL_3", REG_MMIO, 0x2683, &mmCB_HW_CONTROL_3[0], sizeof(mmCB_HW_CONTROL_3)/sizeof(mmCB_HW_CONTROL_3[0]), 0, 0 },
	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 },
	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 },
	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269a, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269b, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269c, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269d, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269e, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269f, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26a0, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26a1, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26a2, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26a3, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26a4, NULL, 0, 0, 0 },
	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26a5, &mmCB_DEBUG_BUS_13[0], sizeof(mmCB_DEBUG_BUS_13)/sizeof(mmCB_DEBUG_BUS_13[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26a6, &mmCB_DEBUG_BUS_14[0], sizeof(mmCB_DEBUG_BUS_14)/sizeof(mmCB_DEBUG_BUS_14[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26a7, &mmCB_DEBUG_BUS_15[0], sizeof(mmCB_DEBUG_BUS_15)/sizeof(mmCB_DEBUG_BUS_15[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26a8, &mmCB_DEBUG_BUS_16[0], sizeof(mmCB_DEBUG_BUS_16)/sizeof(mmCB_DEBUG_BUS_16[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26a9, &mmCB_DEBUG_BUS_17[0], sizeof(mmCB_DEBUG_BUS_17)/sizeof(mmCB_DEBUG_BUS_17[0]), 0, 0 },
	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26aa, &mmCB_DEBUG_BUS_18[0], sizeof(mmCB_DEBUG_BUS_18)/sizeof(mmCB_DEBUG_BUS_18[0]), 0, 0 },
	{ "ixSQ_WAVE_TBA_LO", REG_SMC, 0x26c, &ixSQ_WAVE_TBA_LO[0], sizeof(ixSQ_WAVE_TBA_LO)/sizeof(ixSQ_WAVE_TBA_LO[0]), 0, 0 },
	{ "ixSQ_WAVE_TBA_HI", REG_SMC, 0x26d, &ixSQ_WAVE_TBA_HI[0], sizeof(ixSQ_WAVE_TBA_HI)/sizeof(ixSQ_WAVE_TBA_HI[0]), 0, 0 },
	{ "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x26de, &mmGC_USER_RB_REDUNDANCY[0], sizeof(mmGC_USER_RB_REDUNDANCY)/sizeof(mmGC_USER_RB_REDUNDANCY[0]), 0, 0 },
	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26df, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
	{ "ixSQ_WAVE_TMA_LO", REG_SMC, 0x26e, &ixSQ_WAVE_TMA_LO[0], sizeof(ixSQ_WAVE_TMA_LO)/sizeof(ixSQ_WAVE_TMA_LO[0]), 0, 0 },
	{ "ixSQ_WAVE_TMA_HI", REG_SMC, 0x26f, &ixSQ_WAVE_TMA_HI[0], sizeof(ixSQ_WAVE_TMA_HI)/sizeof(ixSQ_WAVE_TMA_HI[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG32", REG_SMC, 0x27, &ixVGT_DEBUG_REG32[0], sizeof(ixVGT_DEBUG_REG32)/sizeof(ixVGT_DEBUG_REG32[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP0", REG_SMC, 0x270, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP1", REG_SMC, 0x271, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP2", REG_SMC, 0x272, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP3", REG_SMC, 0x273, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP4", REG_SMC, 0x274, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP5", REG_SMC, 0x275, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP6", REG_SMC, 0x276, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP7", REG_SMC, 0x277, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP8", REG_SMC, 0x278, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP9", REG_SMC, 0x279, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP10", REG_SMC, 0x27a, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 },
	{ "ixSQ_WAVE_TTMP11", REG_SMC, 0x27b, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 },
	{ "ixSQ_WAVE_M0", REG_SMC, 0x27c, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 },
	{ "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x27e, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 },
	{ "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x27f, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG33", REG_SMC, 0x28, &ixVGT_DEBUG_REG33[0], sizeof(ixVGT_DEBUG_REG33)/sizeof(ixVGT_DEBUG_REG33[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG34", REG_SMC, 0x29, &ixVGT_DEBUG_REG34[0], sizeof(ixVGT_DEBUG_REG34)/sizeof(ixVGT_DEBUG_REG34[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG35", REG_SMC, 0x2a, &ixVGT_DEBUG_REG35[0], sizeof(ixVGT_DEBUG_REG35)/sizeof(ixVGT_DEBUG_REG35[0]), 0, 0 },
	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2b00, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 },
	{ "mmTCP_STATUS", REG_MMIO, 0x2b01, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 },
	{ "mmTCP_CNTL", REG_MMIO, 0x2b02, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 },
	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2b03, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 },
	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2b04, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 },
	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2b05, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 },
	{ "mmTCP_CREDIT", REG_MMIO, 0x2b06, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 },
	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2b16, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
	{ "mmTCP_EDC_COUNTER", REG_MMIO, 0x2b17, &mmTCP_EDC_COUNTER[0], sizeof(mmTCP_EDC_COUNTER)/sizeof(mmTCP_EDC_COUNTER[0]), 0, 0 },
	{ "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x2b1a, &mmTC_CFG_L1_LOAD_POLICY0[0], sizeof(mmTC_CFG_L1_LOAD_POLICY0)/sizeof(mmTC_CFG_L1_LOAD_POLICY0[0]), 0, 0 },
	{ "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x2b1b, &mmTC_CFG_L1_LOAD_POLICY1[0], sizeof(mmTC_CFG_L1_LOAD_POLICY1)/sizeof(mmTC_CFG_L1_LOAD_POLICY1[0]), 0, 0 },
	{ "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x2b1c, &mmTC_CFG_L1_STORE_POLICY[0], sizeof(mmTC_CFG_L1_STORE_POLICY)/sizeof(mmTC_CFG_L1_STORE_POLICY[0]), 0, 0 },
	{ "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x2b1d, &mmTC_CFG_L2_LOAD_POLICY0[0], sizeof(mmTC_CFG_L2_LOAD_POLICY0)/sizeof(mmTC_CFG_L2_LOAD_POLICY0[0]), 0, 0 },
	{ "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x2b1e, &mmTC_CFG_L2_LOAD_POLICY1[0], sizeof(mmTC_CFG_L2_LOAD_POLICY1)/sizeof(mmTC_CFG_L2_LOAD_POLICY1[0]), 0, 0 },
	{ "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x2b1f, &mmTC_CFG_L2_STORE_POLICY0[0], sizeof(mmTC_CFG_L2_STORE_POLICY0)/sizeof(mmTC_CFG_L2_STORE_POLICY0[0]), 0, 0 },
	{ "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x2b20, &mmTC_CFG_L2_STORE_POLICY1[0], sizeof(mmTC_CFG_L2_STORE_POLICY1)/sizeof(mmTC_CFG_L2_STORE_POLICY1[0]), 0, 0 },
	{ "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x2b21, &mmTC_CFG_L2_ATOMIC_POLICY[0], sizeof(mmTC_CFG_L2_ATOMIC_POLICY)/sizeof(mmTC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 },
	{ "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x2b22, &mmTC_CFG_L1_VOLATILE[0], sizeof(mmTC_CFG_L1_VOLATILE)/sizeof(mmTC_CFG_L1_VOLATILE[0]), 0, 0 },
	{ "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x2b23, &mmTC_CFG_L2_VOLATILE[0], sizeof(mmTC_CFG_L2_VOLATILE)/sizeof(mmTC_CFG_L2_VOLATILE[0]), 0, 0 },
	{ "mmTCI_STATUS", REG_MMIO, 0x2b61, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 },
	{ "mmTCI_CNTL_1", REG_MMIO, 0x2b62, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 },
	{ "mmTCI_CNTL_2", REG_MMIO, 0x2b63, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 },
	{ "mmTCC_CTRL", REG_MMIO, 0x2b80, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 },
	{ "mmTCC_EDC_COUNTER", REG_MMIO, 0x2b82, &mmTCC_EDC_COUNTER[0], sizeof(mmTCC_EDC_COUNTER)/sizeof(mmTCC_EDC_COUNTER[0]), 0, 0 },
	{ "mmTCC_REDUNDANCY", REG_MMIO, 0x2b83, &mmTCC_REDUNDANCY[0], sizeof(mmTCC_REDUNDANCY)/sizeof(mmTCC_REDUNDANCY[0]), 0, 0 },
	{ "mmTCA_CTRL", REG_MMIO, 0x2bc0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 },
	{ "mmTCS_CTRL", REG_MMIO, 0x2be0, &mmTCS_CTRL[0], sizeof(mmTCS_CTRL)/sizeof(mmTCS_CTRL[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2c00, &mmSPI_SHADER_TBA_LO_PS[0], sizeof(mmSPI_SHADER_TBA_LO_PS)/sizeof(mmSPI_SHADER_TBA_LO_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2c01, &mmSPI_SHADER_TBA_HI_PS[0], sizeof(mmSPI_SHADER_TBA_HI_PS)/sizeof(mmSPI_SHADER_TBA_HI_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2c02, &mmSPI_SHADER_TMA_LO_PS[0], sizeof(mmSPI_SHADER_TMA_LO_PS)/sizeof(mmSPI_SHADER_TMA_LO_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2c03, &mmSPI_SHADER_TMA_HI_PS[0], sizeof(mmSPI_SHADER_TMA_HI_PS)/sizeof(mmSPI_SHADER_TMA_HI_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x2c07, &mmSPI_SHADER_PGM_RSRC3_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_PS)/sizeof(mmSPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2c08, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2c09, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2c0a, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2c0b, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2c0c, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2c0d, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2c0e, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2c0f, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2c10, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2c11, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2c12, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2c13, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2c14, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2c15, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2c16, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2c17, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2c18, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2c19, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2c1a, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2c1b, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2c40, &mmSPI_SHADER_TBA_LO_VS[0], sizeof(mmSPI_SHADER_TBA_LO_VS)/sizeof(mmSPI_SHADER_TBA_LO_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2c41, &mmSPI_SHADER_TBA_HI_VS[0], sizeof(mmSPI_SHADER_TBA_HI_VS)/sizeof(mmSPI_SHADER_TBA_HI_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2c42, &mmSPI_SHADER_TMA_LO_VS[0], sizeof(mmSPI_SHADER_TMA_LO_VS)/sizeof(mmSPI_SHADER_TMA_LO_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2c43, &mmSPI_SHADER_TMA_HI_VS[0], sizeof(mmSPI_SHADER_TMA_HI_VS)/sizeof(mmSPI_SHADER_TMA_HI_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x2c46, &mmSPI_SHADER_PGM_RSRC3_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_VS)/sizeof(mmSPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x2c47, &mmSPI_SHADER_LATE_ALLOC_VS[0], sizeof(mmSPI_SHADER_LATE_ALLOC_VS)/sizeof(mmSPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2c48, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2c49, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2c4a, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2c4b, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2c4c, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2c4d, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2c4e, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2c4f, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2c50, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2c51, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2c52, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2c53, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2c54, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2c55, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2c56, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2c57, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2c58, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2c59, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2c5a, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2c5b, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_ES_VS", REG_MMIO, 0x2c7c, &mmSPI_SHADER_PGM_RSRC2_ES_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_LS_VS", REG_MMIO, 0x2c7d, &mmSPI_SHADER_PGM_RSRC2_LS_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2c80, &mmSPI_SHADER_TBA_LO_GS[0], sizeof(mmSPI_SHADER_TBA_LO_GS)/sizeof(mmSPI_SHADER_TBA_LO_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2c81, &mmSPI_SHADER_TBA_HI_GS[0], sizeof(mmSPI_SHADER_TBA_HI_GS)/sizeof(mmSPI_SHADER_TBA_HI_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2c82, &mmSPI_SHADER_TMA_LO_GS[0], sizeof(mmSPI_SHADER_TMA_LO_GS)/sizeof(mmSPI_SHADER_TMA_LO_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2c83, &mmSPI_SHADER_TMA_HI_GS[0], sizeof(mmSPI_SHADER_TMA_HI_GS)/sizeof(mmSPI_SHADER_TMA_HI_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x2c87, &mmSPI_SHADER_PGM_RSRC3_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_GS)/sizeof(mmSPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2c88, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2c89, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2c8a, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2c8b, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2c8c, &mmSPI_SHADER_USER_DATA_GS_0[0], sizeof(mmSPI_SHADER_USER_DATA_GS_0)/sizeof(mmSPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2c8d, &mmSPI_SHADER_USER_DATA_GS_1[0], sizeof(mmSPI_SHADER_USER_DATA_GS_1)/sizeof(mmSPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2c8e, &mmSPI_SHADER_USER_DATA_GS_2[0], sizeof(mmSPI_SHADER_USER_DATA_GS_2)/sizeof(mmSPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2c8f, &mmSPI_SHADER_USER_DATA_GS_3[0], sizeof(mmSPI_SHADER_USER_DATA_GS_3)/sizeof(mmSPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2c90, &mmSPI_SHADER_USER_DATA_GS_4[0], sizeof(mmSPI_SHADER_USER_DATA_GS_4)/sizeof(mmSPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2c91, &mmSPI_SHADER_USER_DATA_GS_5[0], sizeof(mmSPI_SHADER_USER_DATA_GS_5)/sizeof(mmSPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2c92, &mmSPI_SHADER_USER_DATA_GS_6[0], sizeof(mmSPI_SHADER_USER_DATA_GS_6)/sizeof(mmSPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2c93, &mmSPI_SHADER_USER_DATA_GS_7[0], sizeof(mmSPI_SHADER_USER_DATA_GS_7)/sizeof(mmSPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2c94, &mmSPI_SHADER_USER_DATA_GS_8[0], sizeof(mmSPI_SHADER_USER_DATA_GS_8)/sizeof(mmSPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2c95, &mmSPI_SHADER_USER_DATA_GS_9[0], sizeof(mmSPI_SHADER_USER_DATA_GS_9)/sizeof(mmSPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2c96, &mmSPI_SHADER_USER_DATA_GS_10[0], sizeof(mmSPI_SHADER_USER_DATA_GS_10)/sizeof(mmSPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2c97, &mmSPI_SHADER_USER_DATA_GS_11[0], sizeof(mmSPI_SHADER_USER_DATA_GS_11)/sizeof(mmSPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2c98, &mmSPI_SHADER_USER_DATA_GS_12[0], sizeof(mmSPI_SHADER_USER_DATA_GS_12)/sizeof(mmSPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2c99, &mmSPI_SHADER_USER_DATA_GS_13[0], sizeof(mmSPI_SHADER_USER_DATA_GS_13)/sizeof(mmSPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2c9a, &mmSPI_SHADER_USER_DATA_GS_14[0], sizeof(mmSPI_SHADER_USER_DATA_GS_14)/sizeof(mmSPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2c9b, &mmSPI_SHADER_USER_DATA_GS_15[0], sizeof(mmSPI_SHADER_USER_DATA_GS_15)/sizeof(mmSPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_ES_GS", REG_MMIO, 0x2cbc, &mmSPI_SHADER_PGM_RSRC2_ES_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2cc0, &mmSPI_SHADER_TBA_LO_ES[0], sizeof(mmSPI_SHADER_TBA_LO_ES)/sizeof(mmSPI_SHADER_TBA_LO_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2cc1, &mmSPI_SHADER_TBA_HI_ES[0], sizeof(mmSPI_SHADER_TBA_HI_ES)/sizeof(mmSPI_SHADER_TBA_HI_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2cc2, &mmSPI_SHADER_TMA_LO_ES[0], sizeof(mmSPI_SHADER_TMA_LO_ES)/sizeof(mmSPI_SHADER_TMA_LO_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2cc3, &mmSPI_SHADER_TMA_HI_ES[0], sizeof(mmSPI_SHADER_TMA_HI_ES)/sizeof(mmSPI_SHADER_TMA_HI_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_ES", REG_MMIO, 0x2cc7, &mmSPI_SHADER_PGM_RSRC3_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC3_ES)/sizeof(mmSPI_SHADER_PGM_RSRC3_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2cc8, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2cc9, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2cca, &mmSPI_SHADER_PGM_RSRC1_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC1_ES)/sizeof(mmSPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2ccb, &mmSPI_SHADER_PGM_RSRC2_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2ccc, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2ccd, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2cce, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2ccf, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2cd0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2cd1, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2cd2, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2cd3, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2cd4, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2cd5, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2cd6, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2cd7, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2cd8, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2cd9, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2cda, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2cdb, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_LS_ES", REG_MMIO, 0x2cfd, &mmSPI_SHADER_PGM_RSRC2_LS_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2d00, &mmSPI_SHADER_TBA_LO_HS[0], sizeof(mmSPI_SHADER_TBA_LO_HS)/sizeof(mmSPI_SHADER_TBA_LO_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2d01, &mmSPI_SHADER_TBA_HI_HS[0], sizeof(mmSPI_SHADER_TBA_HI_HS)/sizeof(mmSPI_SHADER_TBA_HI_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2d02, &mmSPI_SHADER_TMA_LO_HS[0], sizeof(mmSPI_SHADER_TMA_LO_HS)/sizeof(mmSPI_SHADER_TMA_LO_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2d03, &mmSPI_SHADER_TMA_HI_HS[0], sizeof(mmSPI_SHADER_TMA_HI_HS)/sizeof(mmSPI_SHADER_TMA_HI_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x2d07, &mmSPI_SHADER_PGM_RSRC3_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_HS)/sizeof(mmSPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2d08, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2d09, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2d0a, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2d0b, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2d0c, &mmSPI_SHADER_USER_DATA_HS_0[0], sizeof(mmSPI_SHADER_USER_DATA_HS_0)/sizeof(mmSPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2d0d, &mmSPI_SHADER_USER_DATA_HS_1[0], sizeof(mmSPI_SHADER_USER_DATA_HS_1)/sizeof(mmSPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2d0e, &mmSPI_SHADER_USER_DATA_HS_2[0], sizeof(mmSPI_SHADER_USER_DATA_HS_2)/sizeof(mmSPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2d0f, &mmSPI_SHADER_USER_DATA_HS_3[0], sizeof(mmSPI_SHADER_USER_DATA_HS_3)/sizeof(mmSPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2d10, &mmSPI_SHADER_USER_DATA_HS_4[0], sizeof(mmSPI_SHADER_USER_DATA_HS_4)/sizeof(mmSPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2d11, &mmSPI_SHADER_USER_DATA_HS_5[0], sizeof(mmSPI_SHADER_USER_DATA_HS_5)/sizeof(mmSPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2d12, &mmSPI_SHADER_USER_DATA_HS_6[0], sizeof(mmSPI_SHADER_USER_DATA_HS_6)/sizeof(mmSPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2d13, &mmSPI_SHADER_USER_DATA_HS_7[0], sizeof(mmSPI_SHADER_USER_DATA_HS_7)/sizeof(mmSPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2d14, &mmSPI_SHADER_USER_DATA_HS_8[0], sizeof(mmSPI_SHADER_USER_DATA_HS_8)/sizeof(mmSPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2d15, &mmSPI_SHADER_USER_DATA_HS_9[0], sizeof(mmSPI_SHADER_USER_DATA_HS_9)/sizeof(mmSPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2d16, &mmSPI_SHADER_USER_DATA_HS_10[0], sizeof(mmSPI_SHADER_USER_DATA_HS_10)/sizeof(mmSPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2d17, &mmSPI_SHADER_USER_DATA_HS_11[0], sizeof(mmSPI_SHADER_USER_DATA_HS_11)/sizeof(mmSPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2d18, &mmSPI_SHADER_USER_DATA_HS_12[0], sizeof(mmSPI_SHADER_USER_DATA_HS_12)/sizeof(mmSPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2d19, &mmSPI_SHADER_USER_DATA_HS_13[0], sizeof(mmSPI_SHADER_USER_DATA_HS_13)/sizeof(mmSPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2d1a, &mmSPI_SHADER_USER_DATA_HS_14[0], sizeof(mmSPI_SHADER_USER_DATA_HS_14)/sizeof(mmSPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2d1b, &mmSPI_SHADER_USER_DATA_HS_15[0], sizeof(mmSPI_SHADER_USER_DATA_HS_15)/sizeof(mmSPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_LS_HS", REG_MMIO, 0x2d3d, &mmSPI_SHADER_PGM_RSRC2_LS_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2d40, &mmSPI_SHADER_TBA_LO_LS[0], sizeof(mmSPI_SHADER_TBA_LO_LS)/sizeof(mmSPI_SHADER_TBA_LO_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2d41, &mmSPI_SHADER_TBA_HI_LS[0], sizeof(mmSPI_SHADER_TBA_HI_LS)/sizeof(mmSPI_SHADER_TBA_HI_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2d42, &mmSPI_SHADER_TMA_LO_LS[0], sizeof(mmSPI_SHADER_TMA_LO_LS)/sizeof(mmSPI_SHADER_TMA_LO_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2d43, &mmSPI_SHADER_TMA_HI_LS[0], sizeof(mmSPI_SHADER_TMA_HI_LS)/sizeof(mmSPI_SHADER_TMA_HI_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC3_LS", REG_MMIO, 0x2d47, &mmSPI_SHADER_PGM_RSRC3_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_LS)/sizeof(mmSPI_SHADER_PGM_RSRC3_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2d48, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2d49, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2d4a, &mmSPI_SHADER_PGM_RSRC1_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_LS)/sizeof(mmSPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2d4b, &mmSPI_SHADER_PGM_RSRC2_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2d4c, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2d4d, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2d4e, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2d4f, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2d50, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2d51, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2d52, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2d53, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2d54, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2d55, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2d56, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2d57, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2d58, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2d59, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2d5a, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2d5b, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2e00, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2e01, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 },
	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2e02, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 },
	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2e03, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 },
	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2e04, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 },
	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2e05, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 },
	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2e06, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 },
	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2e07, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 },
	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2e08, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 },
	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2e09, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 },
	{ "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x2e0a, &mmCOMPUTE_PIPELINESTAT_ENABLE[0], sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE)/sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 },
	{ "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x2e0b, &mmCOMPUTE_PERFCOUNT_ENABLE[0], sizeof(mmCOMPUTE_PERFCOUNT_ENABLE)/sizeof(mmCOMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 },
	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2e0c, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 },
	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2e0d, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 },
	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2e0e, &mmCOMPUTE_TBA_LO[0], sizeof(mmCOMPUTE_TBA_LO)/sizeof(mmCOMPUTE_TBA_LO[0]), 0, 0 },
	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2e0f, &mmCOMPUTE_TBA_HI[0], sizeof(mmCOMPUTE_TBA_HI)/sizeof(mmCOMPUTE_TBA_HI[0]), 0, 0 },
	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2e10, &mmCOMPUTE_TMA_LO[0], sizeof(mmCOMPUTE_TMA_LO)/sizeof(mmCOMPUTE_TMA_LO[0]), 0, 0 },
	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2e11, &mmCOMPUTE_TMA_HI[0], sizeof(mmCOMPUTE_TMA_HI)/sizeof(mmCOMPUTE_TMA_HI[0]), 0, 0 },
	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2e12, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 },
	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2e13, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 },
	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2e14, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 },
	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2e15, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2e16, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2e17, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2e18, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 },
	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x2e19, &mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 },
	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x2e1a, &mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 },
	{ "mmCOMPUTE_RESTART_X", REG_MMIO, 0x2e1b, &mmCOMPUTE_RESTART_X[0], sizeof(mmCOMPUTE_RESTART_X)/sizeof(mmCOMPUTE_RESTART_X[0]), 0, 0 },
	{ "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x2e1c, &mmCOMPUTE_RESTART_Y[0], sizeof(mmCOMPUTE_RESTART_Y)/sizeof(mmCOMPUTE_RESTART_Y[0]), 0, 0 },
	{ "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x2e1d, &mmCOMPUTE_RESTART_Z[0], sizeof(mmCOMPUTE_RESTART_Z)/sizeof(mmCOMPUTE_RESTART_Z[0]), 0, 0 },
	{ "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x2e1e, &mmCOMPUTE_THREAD_TRACE_ENABLE[0], sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE)/sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 },
	{ "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x2e1f, &mmCOMPUTE_MISC_RESERVED[0], sizeof(mmCOMPUTE_MISC_RESERVED)/sizeof(mmCOMPUTE_MISC_RESERVED[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2e40, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2e41, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2e42, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2e43, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2e44, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2e45, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2e46, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2e47, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2e48, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2e49, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2e4a, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2e4b, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2e4c, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2e4d, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2e4e, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 },
	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2e4f, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG03", REG_SMC, 0x3, &ixCLIPPER_DEBUG_REG03[0], sizeof(ixCLIPPER_DEBUG_REG03)/sizeof(ixCLIPPER_DEBUG_REG03[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG3", REG_SMC, 0x3, &ixGDS_DEBUG_REG3[0], sizeof(ixGDS_DEBUG_REG3)/sizeof(ixGDS_DEBUG_REG3[0]), 0, 0 },
	{ "ixWD_DEBUG_REG3", REG_SMC, 0x3, &ixWD_DEBUG_REG3[0], sizeof(ixWD_DEBUG_REG3)/sizeof(ixWD_DEBUG_REG3[0]), 0, 0 },
	{ "ixDIDT_DB_WEIGHT0_3", REG_SMC, 0x30, &ixDIDT_DB_WEIGHT0_3[0], sizeof(ixDIDT_DB_WEIGHT0_3)/sizeof(ixDIDT_DB_WEIGHT0_3[0]), 0, 0 },
	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0x3000, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 },
	{ "mmGRBM_CAM_DATA", REG_MMIO, 0x3001, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 },
	{ "mmCP_DFY_CNTL", REG_MMIO, 0x3020, &mmCP_DFY_CNTL[0], sizeof(mmCP_DFY_CNTL)/sizeof(mmCP_DFY_CNTL[0]), 0, 0 },
	{ "mmCP_DFY_STAT", REG_MMIO, 0x3021, &mmCP_DFY_STAT[0], sizeof(mmCP_DFY_STAT)/sizeof(mmCP_DFY_STAT[0]), 0, 0 },
	{ "mmCP_DFY_ADDR_HI", REG_MMIO, 0x3022, &mmCP_DFY_ADDR_HI[0], sizeof(mmCP_DFY_ADDR_HI)/sizeof(mmCP_DFY_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DFY_ADDR_LO", REG_MMIO, 0x3023, &mmCP_DFY_ADDR_LO[0], sizeof(mmCP_DFY_ADDR_LO)/sizeof(mmCP_DFY_ADDR_LO[0]), 0, 0 },
	{ "mmCP_DFY_DATA_0", REG_MMIO, 0x3024, &mmCP_DFY_DATA_0[0], sizeof(mmCP_DFY_DATA_0)/sizeof(mmCP_DFY_DATA_0[0]), 0, 0 },
	{ "mmCP_DFY_DATA_1", REG_MMIO, 0x3025, &mmCP_DFY_DATA_1[0], sizeof(mmCP_DFY_DATA_1)/sizeof(mmCP_DFY_DATA_1[0]), 0, 0 },
	{ "mmCP_DFY_DATA_2", REG_MMIO, 0x3026, &mmCP_DFY_DATA_2[0], sizeof(mmCP_DFY_DATA_2)/sizeof(mmCP_DFY_DATA_2[0]), 0, 0 },
	{ "mmCP_DFY_DATA_3", REG_MMIO, 0x3027, &mmCP_DFY_DATA_3[0], sizeof(mmCP_DFY_DATA_3)/sizeof(mmCP_DFY_DATA_3[0]), 0, 0 },
	{ "mmCP_DFY_DATA_4", REG_MMIO, 0x3028, &mmCP_DFY_DATA_4[0], sizeof(mmCP_DFY_DATA_4)/sizeof(mmCP_DFY_DATA_4[0]), 0, 0 },
	{ "mmCP_DFY_DATA_5", REG_MMIO, 0x3029, &mmCP_DFY_DATA_5[0], sizeof(mmCP_DFY_DATA_5)/sizeof(mmCP_DFY_DATA_5[0]), 0, 0 },
	{ "mmCP_DFY_DATA_6", REG_MMIO, 0x302a, &mmCP_DFY_DATA_6[0], sizeof(mmCP_DFY_DATA_6)/sizeof(mmCP_DFY_DATA_6[0]), 0, 0 },
	{ "mmCP_DFY_DATA_7", REG_MMIO, 0x302b, &mmCP_DFY_DATA_7[0], sizeof(mmCP_DFY_DATA_7)/sizeof(mmCP_DFY_DATA_7[0]), 0, 0 },
	{ "mmCP_DFY_DATA_8", REG_MMIO, 0x302c, &mmCP_DFY_DATA_8[0], sizeof(mmCP_DFY_DATA_8)/sizeof(mmCP_DFY_DATA_8[0]), 0, 0 },
	{ "mmCP_DFY_DATA_9", REG_MMIO, 0x302d, &mmCP_DFY_DATA_9[0], sizeof(mmCP_DFY_DATA_9)/sizeof(mmCP_DFY_DATA_9[0]), 0, 0 },
	{ "mmCP_DFY_DATA_10", REG_MMIO, 0x302e, &mmCP_DFY_DATA_10[0], sizeof(mmCP_DFY_DATA_10)/sizeof(mmCP_DFY_DATA_10[0]), 0, 0 },
	{ "mmCP_DFY_DATA_11", REG_MMIO, 0x302f, &mmCP_DFY_DATA_11[0], sizeof(mmCP_DFY_DATA_11)/sizeof(mmCP_DFY_DATA_11[0]), 0, 0 },
	{ "mmCP_DFY_DATA_12", REG_MMIO, 0x3030, &mmCP_DFY_DATA_12[0], sizeof(mmCP_DFY_DATA_12)/sizeof(mmCP_DFY_DATA_12[0]), 0, 0 },
	{ "mmCP_DFY_DATA_13", REG_MMIO, 0x3031, &mmCP_DFY_DATA_13[0], sizeof(mmCP_DFY_DATA_13)/sizeof(mmCP_DFY_DATA_13[0]), 0, 0 },
	{ "mmCP_DFY_DATA_14", REG_MMIO, 0x3032, &mmCP_DFY_DATA_14[0], sizeof(mmCP_DFY_DATA_14)/sizeof(mmCP_DFY_DATA_14[0]), 0, 0 },
	{ "mmCP_DFY_DATA_15", REG_MMIO, 0x3033, &mmCP_DFY_DATA_15[0], sizeof(mmCP_DFY_DATA_15)/sizeof(mmCP_DFY_DATA_15[0]), 0, 0 },
	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 },
	{ "mmCP_RB_BASE", REG_MMIO, 0x3040, &mmCP_RB_BASE[0], sizeof(mmCP_RB_BASE)/sizeof(mmCP_RB_BASE[0]), 0, 0 },
	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 },
	{ "mmCP_RB_CNTL", REG_MMIO, 0x3041, &mmCP_RB_CNTL[0], sizeof(mmCP_RB_CNTL)/sizeof(mmCP_RB_CNTL[0]), 0, 0 },
	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 },
	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 },
	{ "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB_RPTR_ADDR[0], sizeof(mmCP_RB_RPTR_ADDR)/sizeof(mmCP_RB_RPTR_ADDR[0]), 0, 0 },
	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB_RPTR_ADDR_HI[0], sizeof(mmCP_RB_RPTR_ADDR_HI)/sizeof(mmCP_RB_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 },
	{ "mmCP_RB_WPTR", REG_MMIO, 0x3045, &mmCP_RB_WPTR[0], sizeof(mmCP_RB_WPTR)/sizeof(mmCP_RB_WPTR[0]), 0, 0 },
	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 },
	{ "mmCP_INT_STATUS", REG_MMIO, 0x304a, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 },
	{ "mmCP_DEVICE_ID", REG_MMIO, 0x304b, &mmCP_DEVICE_ID[0], sizeof(mmCP_DEVICE_ID)/sizeof(mmCP_DEVICE_ID[0]), 0, 0 },
	{ "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 },
	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 },
	{ "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x304d, &mmCP_ME0_PIPE0_PRIORITY[0], sizeof(mmCP_ME0_PIPE0_PRIORITY)/sizeof(mmCP_ME0_PIPE0_PRIORITY[0]), 0, 0 },
	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304d, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x304e, &mmCP_ME0_PIPE1_PRIORITY[0], sizeof(mmCP_ME0_PIPE1_PRIORITY)/sizeof(mmCP_ME0_PIPE1_PRIORITY[0]), 0, 0 },
	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304e, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x304f, &mmCP_ME0_PIPE2_PRIORITY[0], sizeof(mmCP_ME0_PIPE2_PRIORITY)/sizeof(mmCP_ME0_PIPE2_PRIORITY[0]), 0, 0 },
	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304f, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 },
	{ "mmCP_ENDIAN_SWAP", REG_MMIO, 0x3050, &mmCP_ENDIAN_SWAP[0], sizeof(mmCP_ENDIAN_SWAP)/sizeof(mmCP_ENDIAN_SWAP[0]), 0, 0 },
	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 },
	{ "mmCP_ME0_PIPE0_VMID", REG_MMIO, 0x3052, &mmCP_ME0_PIPE0_VMID[0], sizeof(mmCP_ME0_PIPE0_VMID)/sizeof(mmCP_ME0_PIPE0_VMID[0]), 0, 0 },
	{ "mmCP_ME0_PIPE1_VMID", REG_MMIO, 0x3053, &mmCP_ME0_PIPE1_VMID[0], sizeof(mmCP_ME0_PIPE1_VMID)/sizeof(mmCP_ME0_PIPE1_VMID[0]), 0, 0 },
	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0x3054, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 },
	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0x3055, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 },
	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0x3056, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 },
	{ "mmCP_ME_RAM_WADDR", REG_MMIO, 0x3057, &mmCP_ME_RAM_WADDR[0], sizeof(mmCP_ME_RAM_WADDR)/sizeof(mmCP_ME_RAM_WADDR[0]), 0, 0 },
	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0x3058, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 },
	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0x305a, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 },
	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0x305b, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 },
	{ "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0x305c, &mmCP_MEC_ME1_UCODE_ADDR[0], sizeof(mmCP_MEC_ME1_UCODE_ADDR)/sizeof(mmCP_MEC_ME1_UCODE_ADDR[0]), 0, 0 },
	{ "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0x305d, &mmCP_MEC_ME1_UCODE_DATA[0], sizeof(mmCP_MEC_ME1_UCODE_DATA)/sizeof(mmCP_MEC_ME1_UCODE_DATA[0]), 0, 0 },
	{ "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0x305e, &mmCP_MEC_ME2_UCODE_ADDR[0], sizeof(mmCP_MEC_ME2_UCODE_ADDR)/sizeof(mmCP_MEC_ME2_UCODE_ADDR[0]), 0, 0 },
	{ "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0x305f, &mmCP_MEC_ME2_UCODE_DATA[0], sizeof(mmCP_MEC_ME2_UCODE_DATA)/sizeof(mmCP_MEC_ME2_UCODE_DATA[0]), 0, 0 },
	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 },
	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 },
	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 },
	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 },
	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 },
	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 },
	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 },
	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 },
	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306a, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 },
	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306b, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 },
	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306c, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 },
	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306d, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 },
	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306e, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 },
	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306f, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 },
	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 },
	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 },
	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307a, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307b, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307c, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307d, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
	{ "mmGB_EDC_MODE", REG_MMIO, 0x307e, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 },
	{ "mmCP_CPF_DEBUG", REG_MMIO, 0x3080, NULL, 0, 0, 0 },
	{ "mmCP_FETCHER_SOURCE", REG_MMIO, 0x3082, &mmCP_FETCHER_SOURCE[0], sizeof(mmCP_FETCHER_SOURCE)/sizeof(mmCP_FETCHER_SOURCE[0]), 0, 0 },
	{ "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x3083, &mmCP_PQ_WPTR_POLL_CNTL[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL)/sizeof(mmCP_PQ_WPTR_POLL_CNTL[0]), 0, 0 },
	{ "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x3084, &mmCP_PQ_WPTR_POLL_CNTL1[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL1)/sizeof(mmCP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 },
	{ "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x3085, &mmCP_ME1_PIPE0_INT_CNTL[0], sizeof(mmCP_ME1_PIPE0_INT_CNTL)/sizeof(mmCP_ME1_PIPE0_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x3086, &mmCP_ME1_PIPE1_INT_CNTL[0], sizeof(mmCP_ME1_PIPE1_INT_CNTL)/sizeof(mmCP_ME1_PIPE1_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x3087, &mmCP_ME1_PIPE2_INT_CNTL[0], sizeof(mmCP_ME1_PIPE2_INT_CNTL)/sizeof(mmCP_ME1_PIPE2_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x3088, &mmCP_ME1_PIPE3_INT_CNTL[0], sizeof(mmCP_ME1_PIPE3_INT_CNTL)/sizeof(mmCP_ME1_PIPE3_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x3089, &mmCP_ME2_PIPE0_INT_CNTL[0], sizeof(mmCP_ME2_PIPE0_INT_CNTL)/sizeof(mmCP_ME2_PIPE0_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x308a, &mmCP_ME2_PIPE1_INT_CNTL[0], sizeof(mmCP_ME2_PIPE1_INT_CNTL)/sizeof(mmCP_ME2_PIPE1_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x308b, &mmCP_ME2_PIPE2_INT_CNTL[0], sizeof(mmCP_ME2_PIPE2_INT_CNTL)/sizeof(mmCP_ME2_PIPE2_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x308c, &mmCP_ME2_PIPE3_INT_CNTL[0], sizeof(mmCP_ME2_PIPE3_INT_CNTL)/sizeof(mmCP_ME2_PIPE3_INT_CNTL[0]), 0, 0 },
	{ "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x308d, &mmCP_ME1_PIPE0_INT_STATUS[0], sizeof(mmCP_ME1_PIPE0_INT_STATUS)/sizeof(mmCP_ME1_PIPE0_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x308e, &mmCP_ME1_PIPE1_INT_STATUS[0], sizeof(mmCP_ME1_PIPE1_INT_STATUS)/sizeof(mmCP_ME1_PIPE1_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x308f, &mmCP_ME1_PIPE2_INT_STATUS[0], sizeof(mmCP_ME1_PIPE2_INT_STATUS)/sizeof(mmCP_ME1_PIPE2_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x3090, &mmCP_ME1_PIPE3_INT_STATUS[0], sizeof(mmCP_ME1_PIPE3_INT_STATUS)/sizeof(mmCP_ME1_PIPE3_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x3091, &mmCP_ME2_PIPE0_INT_STATUS[0], sizeof(mmCP_ME2_PIPE0_INT_STATUS)/sizeof(mmCP_ME2_PIPE0_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x3092, &mmCP_ME2_PIPE1_INT_STATUS[0], sizeof(mmCP_ME2_PIPE1_INT_STATUS)/sizeof(mmCP_ME2_PIPE1_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x3093, &mmCP_ME2_PIPE2_INT_STATUS[0], sizeof(mmCP_ME2_PIPE2_INT_STATUS)/sizeof(mmCP_ME2_PIPE2_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x3094, &mmCP_ME2_PIPE3_INT_STATUS[0], sizeof(mmCP_ME2_PIPE3_INT_STATUS)/sizeof(mmCP_ME2_PIPE3_INT_STATUS[0]), 0, 0 },
	{ "mmCP_ME1_INT_STAT_DEBUG", REG_MMIO, 0x3095, &mmCP_ME1_INT_STAT_DEBUG[0], sizeof(mmCP_ME1_INT_STAT_DEBUG)/sizeof(mmCP_ME1_INT_STAT_DEBUG[0]), 0, 0 },
	{ "mmCP_ME2_INT_STAT_DEBUG", REG_MMIO, 0x3096, &mmCP_ME2_INT_STAT_DEBUG[0], sizeof(mmCP_ME2_INT_STAT_DEBUG)/sizeof(mmCP_ME2_INT_STAT_DEBUG[0]), 0, 0 },
	{ "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x3098, &mmCC_GC_EDC_CONFIG[0], sizeof(mmCC_GC_EDC_CONFIG)/sizeof(mmCC_GC_EDC_CONFIG[0]), 0, 0 },
	{ "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x3099, &mmCP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 },
	{ "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x309a, &mmCP_ME1_PIPE0_PRIORITY[0], sizeof(mmCP_ME1_PIPE0_PRIORITY)/sizeof(mmCP_ME1_PIPE0_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x309b, &mmCP_ME1_PIPE1_PRIORITY[0], sizeof(mmCP_ME1_PIPE1_PRIORITY)/sizeof(mmCP_ME1_PIPE1_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x309c, &mmCP_ME1_PIPE2_PRIORITY[0], sizeof(mmCP_ME1_PIPE2_PRIORITY)/sizeof(mmCP_ME1_PIPE2_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x309d, &mmCP_ME1_PIPE3_PRIORITY[0], sizeof(mmCP_ME1_PIPE3_PRIORITY)/sizeof(mmCP_ME1_PIPE3_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x309e, &mmCP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 },
	{ "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x309f, &mmCP_ME2_PIPE0_PRIORITY[0], sizeof(mmCP_ME2_PIPE0_PRIORITY)/sizeof(mmCP_ME2_PIPE0_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x30a0, &mmCP_ME2_PIPE1_PRIORITY[0], sizeof(mmCP_ME2_PIPE1_PRIORITY)/sizeof(mmCP_ME2_PIPE1_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x30a1, &mmCP_ME2_PIPE2_PRIORITY[0], sizeof(mmCP_ME2_PIPE2_PRIORITY)/sizeof(mmCP_ME2_PIPE2_PRIORITY[0]), 0, 0 },
	{ "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x30a2, &mmCP_ME2_PIPE3_PRIORITY[0], sizeof(mmCP_ME2_PIPE3_PRIORITY)/sizeof(mmCP_ME2_PIPE3_PRIORITY[0]), 0, 0 },
	{ "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x30a3, &mmCP_CE_PRGRM_CNTR_START[0], sizeof(mmCP_CE_PRGRM_CNTR_START)/sizeof(mmCP_CE_PRGRM_CNTR_START[0]), 0, 0 },
	{ "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x30a4, &mmCP_PFP_PRGRM_CNTR_START[0], sizeof(mmCP_PFP_PRGRM_CNTR_START)/sizeof(mmCP_PFP_PRGRM_CNTR_START[0]), 0, 0 },
	{ "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x30a5, &mmCP_ME_PRGRM_CNTR_START[0], sizeof(mmCP_ME_PRGRM_CNTR_START)/sizeof(mmCP_ME_PRGRM_CNTR_START[0]), 0, 0 },
	{ "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x30a6, &mmCP_MEC1_PRGRM_CNTR_START[0], sizeof(mmCP_MEC1_PRGRM_CNTR_START)/sizeof(mmCP_MEC1_PRGRM_CNTR_START[0]), 0, 0 },
	{ "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x30a7, &mmCP_MEC2_PRGRM_CNTR_START[0], sizeof(mmCP_MEC2_PRGRM_CNTR_START)/sizeof(mmCP_MEC2_PRGRM_CNTR_START[0]), 0, 0 },
	{ "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x30a8, &mmCP_CE_INTR_ROUTINE_START[0], sizeof(mmCP_CE_INTR_ROUTINE_START)/sizeof(mmCP_CE_INTR_ROUTINE_START[0]), 0, 0 },
	{ "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x30a9, &mmCP_PFP_INTR_ROUTINE_START[0], sizeof(mmCP_PFP_INTR_ROUTINE_START)/sizeof(mmCP_PFP_INTR_ROUTINE_START[0]), 0, 0 },
	{ "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x30aa, &mmCP_ME_INTR_ROUTINE_START[0], sizeof(mmCP_ME_INTR_ROUTINE_START)/sizeof(mmCP_ME_INTR_ROUTINE_START[0]), 0, 0 },
	{ "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x30ab, &mmCP_MEC1_INTR_ROUTINE_START[0], sizeof(mmCP_MEC1_INTR_ROUTINE_START)/sizeof(mmCP_MEC1_INTR_ROUTINE_START[0]), 0, 0 },
	{ "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x30ac, &mmCP_MEC2_INTR_ROUTINE_START[0], sizeof(mmCP_MEC2_INTR_ROUTINE_START)/sizeof(mmCP_MEC2_INTR_ROUTINE_START[0]), 0, 0 },
	{ "mmCP_CONTEXT_CNTL", REG_MMIO, 0x30ad, &mmCP_CONTEXT_CNTL[0], sizeof(mmCP_CONTEXT_CNTL)/sizeof(mmCP_CONTEXT_CNTL[0]), 0, 0 },
	{ "mmCP_MAX_CONTEXT", REG_MMIO, 0x30ae, &mmCP_MAX_CONTEXT[0], sizeof(mmCP_MAX_CONTEXT)/sizeof(mmCP_MAX_CONTEXT[0]), 0, 0 },
	{ "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x30af, &mmCP_IQ_WAIT_TIME1[0], sizeof(mmCP_IQ_WAIT_TIME1)/sizeof(mmCP_IQ_WAIT_TIME1[0]), 0, 0 },
	{ "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x30b0, &mmCP_IQ_WAIT_TIME2[0], sizeof(mmCP_IQ_WAIT_TIME2)/sizeof(mmCP_IQ_WAIT_TIME2[0]), 0, 0 },
	{ "mmCP_RB0_BASE_HI", REG_MMIO, 0x30b1, &mmCP_RB0_BASE_HI[0], sizeof(mmCP_RB0_BASE_HI)/sizeof(mmCP_RB0_BASE_HI[0]), 0, 0 },
	{ "mmCP_RB1_BASE_HI", REG_MMIO, 0x30b2, &mmCP_RB1_BASE_HI[0], sizeof(mmCP_RB1_BASE_HI)/sizeof(mmCP_RB1_BASE_HI[0]), 0, 0 },
	{ "mmCP_VMID_RESET", REG_MMIO, 0x30b3, &mmCP_VMID_RESET[0], sizeof(mmCP_VMID_RESET)/sizeof(mmCP_VMID_RESET[0]), 0, 0 },
	{ "mmCPC_INT_CNTL", REG_MMIO, 0x30b4, &mmCPC_INT_CNTL[0], sizeof(mmCPC_INT_CNTL)/sizeof(mmCPC_INT_CNTL[0]), 0, 0 },
	{ "mmCPC_INT_STATUS", REG_MMIO, 0x30b5, &mmCPC_INT_STATUS[0], sizeof(mmCPC_INT_STATUS)/sizeof(mmCPC_INT_STATUS[0]), 0, 0 },
	{ "mmCP_VMID_PREEMPT", REG_MMIO, 0x30b6, &mmCP_VMID_PREEMPT[0], sizeof(mmCP_VMID_PREEMPT)/sizeof(mmCP_VMID_PREEMPT[0]), 0, 0 },
	{ "mmCPC_INT_CNTX_ID", REG_MMIO, 0x30b7, &mmCPC_INT_CNTX_ID[0], sizeof(mmCPC_INT_CNTX_ID)/sizeof(mmCPC_INT_CNTX_ID[0]), 0, 0 },
	{ "mmCP_PQ_STATUS", REG_MMIO, 0x30b8, &mmCP_PQ_STATUS[0], sizeof(mmCP_PQ_STATUS)/sizeof(mmCP_PQ_STATUS[0]), 0, 0 },
	{ "mmRLC_CNTL", REG_MMIO, 0x30c0, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 },
	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0x30c1, &mmRLC_DEBUG_SELECT[0], sizeof(mmRLC_DEBUG_SELECT)/sizeof(mmRLC_DEBUG_SELECT[0]), 0, 0 },
	{ "mmRLC_DEBUG", REG_MMIO, 0x30c2, &mmRLC_DEBUG[0], sizeof(mmRLC_DEBUG)/sizeof(mmRLC_DEBUG[0]), 0, 0 },
	{ "mmRLC_MC_CNTL", REG_MMIO, 0x30c3, &mmRLC_MC_CNTL[0], sizeof(mmRLC_MC_CNTL)/sizeof(mmRLC_MC_CNTL[0]), 0, 0 },
	{ "mmRLC_STAT", REG_MMIO, 0x30c4, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 },
	{ "mmRLC_SOFT_RESET_GPU", REG_MMIO, 0x30c5, &mmRLC_SOFT_RESET_GPU[0], sizeof(mmRLC_SOFT_RESET_GPU)/sizeof(mmRLC_SOFT_RESET_GPU[0]), 0, 0 },
	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0x30c6, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 },
	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0x30d2, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 },
	{ "mmRLC_LB_CNTL", REG_MMIO, 0x30d9, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 },
	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0x30db, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 },
	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0x30dc, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
	{ "mmRLC_SAVE_AND_RESTORE_BASE", REG_MMIO, 0x30dd, &mmRLC_SAVE_AND_RESTORE_BASE[0], sizeof(mmRLC_SAVE_AND_RESTORE_BASE)/sizeof(mmRLC_SAVE_AND_RESTORE_BASE[0]), 0, 0 },
	{ "mmRLC_DRIVER_CPDMA_STATUS", REG_MMIO, 0x30de, &mmRLC_DRIVER_CPDMA_STATUS[0], sizeof(mmRLC_DRIVER_CPDMA_STATUS)/sizeof(mmRLC_DRIVER_CPDMA_STATUS[0]), 0, 0 },
	{ "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0x30de, &mmRLC_JUMP_TABLE_RESTORE[0], sizeof(mmRLC_JUMP_TABLE_RESTORE)/sizeof(mmRLC_JUMP_TABLE_RESTORE[0]), 0, 0 },
	{ "mmRLC_PG_DELAY_2", REG_MMIO, 0x30df, &mmRLC_PG_DELAY_2[0], sizeof(mmRLC_PG_DELAY_2)/sizeof(mmRLC_PG_DELAY_2[0]), 0, 0 },
	{ "mmRLC_GPM_DEBUG_SELECT", REG_MMIO, 0x30e0, &mmRLC_GPM_DEBUG_SELECT[0], sizeof(mmRLC_GPM_DEBUG_SELECT)/sizeof(mmRLC_GPM_DEBUG_SELECT[0]), 0, 0 },
	{ "mmRLC_GPM_DEBUG", REG_MMIO, 0x30e1, &mmRLC_GPM_DEBUG[0], sizeof(mmRLC_GPM_DEBUG)/sizeof(mmRLC_GPM_DEBUG[0]), 0, 0 },
	{ "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0x30e2, &mmRLC_GPM_UCODE_ADDR[0], sizeof(mmRLC_GPM_UCODE_ADDR)/sizeof(mmRLC_GPM_UCODE_ADDR[0]), 0, 0 },
	{ "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0x30e3, &mmRLC_GPM_UCODE_DATA[0], sizeof(mmRLC_GPM_UCODE_DATA)/sizeof(mmRLC_GPM_UCODE_DATA[0]), 0, 0 },
	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0x30e4, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0x30e5, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0x30e6, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0x30e7, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 },
	{ "ixDIDT_DB_WEIGHT4_7", REG_SMC, 0x31, &ixDIDT_DB_WEIGHT4_7[0], sizeof(ixDIDT_DB_WEIGHT4_7)/sizeof(ixDIDT_DB_WEIGHT4_7[0]), 0, 0 },
	{ "mmRLC_GPM_STAT", REG_MMIO, 0x3100, &mmRLC_GPM_STAT[0], sizeof(mmRLC_GPM_STAT)/sizeof(mmRLC_GPM_STAT[0]), 0, 0 },
	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0x3101, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0x3102, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 },
	{ "mmRLC_PG_CNTL", REG_MMIO, 0x3103, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 },
	{ "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0x3104, &mmRLC_GPM_THREAD_PRIORITY[0], sizeof(mmRLC_GPM_THREAD_PRIORITY)/sizeof(mmRLC_GPM_THREAD_PRIORITY[0]), 0, 0 },
	{ "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0x3105, &mmRLC_GPM_THREAD_ENABLE[0], sizeof(mmRLC_GPM_THREAD_ENABLE)/sizeof(mmRLC_GPM_THREAD_ENABLE[0]), 0, 0 },
	{ "mmRLC_GPM_VMID_THREAD0", REG_MMIO, 0x3106, &mmRLC_GPM_VMID_THREAD0[0], sizeof(mmRLC_GPM_VMID_THREAD0)/sizeof(mmRLC_GPM_VMID_THREAD0[0]), 0, 0 },
	{ "mmRLC_GPM_VMID_THREAD1", REG_MMIO, 0x3107, &mmRLC_GPM_VMID_THREAD1[0], sizeof(mmRLC_GPM_VMID_THREAD1)/sizeof(mmRLC_GPM_VMID_THREAD1[0]), 0, 0 },
	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0x3108, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0x3109, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 },
	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0x310a, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 },
	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0x310b, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 },
	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0x310c, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 },
	{ "mmRLC_PG_DELAY", REG_MMIO, 0x310d, &mmRLC_PG_DELAY[0], sizeof(mmRLC_PG_DELAY)/sizeof(mmRLC_PG_DELAY[0]), 0, 0 },
	{ "mmRLC_CU_STATUS", REG_MMIO, 0x310e, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 },
	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0x310f, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 },
	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0x3110, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
	{ "mmRLC_LB_PARAMS", REG_MMIO, 0x3111, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 },
	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0x3112, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 },
	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0x3113, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0x3114, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 },
	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0x3115, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 },
	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0x3116, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
	{ "mmRLC_SMU_PG_CTRL", REG_MMIO, 0x3117, &mmRLC_SMU_PG_CTRL[0], sizeof(mmRLC_SMU_PG_CTRL)/sizeof(mmRLC_SMU_PG_CTRL[0]), 0, 0 },
	{ "mmRLC_SMU_PG_WAKE_UP_CTRL", REG_MMIO, 0x3118, &mmRLC_SMU_PG_WAKE_UP_CTRL[0], sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL)/sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL[0]), 0, 0 },
	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0x3119, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0x311a, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 },
	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0x311b, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 },
	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0x311c, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 },
	{ "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0x311d, &mmRLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 },
	{ "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0x311e, &mmRLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 },
	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0x311f, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 },
	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0x3120, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 },
	{ "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0x3121, &mmRLC_SERDES_CU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_CU_MASTER_BUSY)/sizeof(mmRLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 },
	{ "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0x3122, &mmRLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_0", REG_MMIO, 0x3123, &mmRLC_GPM_GENERAL_0[0], sizeof(mmRLC_GPM_GENERAL_0)/sizeof(mmRLC_GPM_GENERAL_0[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_1", REG_MMIO, 0x3124, &mmRLC_GPM_GENERAL_1[0], sizeof(mmRLC_GPM_GENERAL_1)/sizeof(mmRLC_GPM_GENERAL_1[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_2", REG_MMIO, 0x3125, &mmRLC_GPM_GENERAL_2[0], sizeof(mmRLC_GPM_GENERAL_2)/sizeof(mmRLC_GPM_GENERAL_2[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_3", REG_MMIO, 0x3126, &mmRLC_GPM_GENERAL_3[0], sizeof(mmRLC_GPM_GENERAL_3)/sizeof(mmRLC_GPM_GENERAL_3[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_4", REG_MMIO, 0x3127, &mmRLC_GPM_GENERAL_4[0], sizeof(mmRLC_GPM_GENERAL_4)/sizeof(mmRLC_GPM_GENERAL_4[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_5", REG_MMIO, 0x3128, &mmRLC_GPM_GENERAL_5[0], sizeof(mmRLC_GPM_GENERAL_5)/sizeof(mmRLC_GPM_GENERAL_5[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_6", REG_MMIO, 0x3129, &mmRLC_GPM_GENERAL_6[0], sizeof(mmRLC_GPM_GENERAL_6)/sizeof(mmRLC_GPM_GENERAL_6[0]), 0, 0 },
	{ "mmRLC_GPM_GENERAL_7", REG_MMIO, 0x312a, &mmRLC_GPM_GENERAL_7[0], sizeof(mmRLC_GPM_GENERAL_7)/sizeof(mmRLC_GPM_GENERAL_7[0]), 0, 0 },
	{ "mmRLC_GPM_CU_PD_TIMEOUT", REG_MMIO, 0x312b, &mmRLC_GPM_CU_PD_TIMEOUT[0], sizeof(mmRLC_GPM_CU_PD_TIMEOUT)/sizeof(mmRLC_GPM_CU_PD_TIMEOUT[0]), 0, 0 },
	{ "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0x312c, &mmRLC_GPM_SCRATCH_ADDR[0], sizeof(mmRLC_GPM_SCRATCH_ADDR)/sizeof(mmRLC_GPM_SCRATCH_ADDR[0]), 0, 0 },
	{ "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0x312d, &mmRLC_GPM_SCRATCH_DATA[0], sizeof(mmRLC_GPM_SCRATCH_DATA)/sizeof(mmRLC_GPM_SCRATCH_DATA[0]), 0, 0 },
	{ "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0x312e, &mmRLC_STATIC_PG_STATUS[0], sizeof(mmRLC_STATIC_PG_STATUS)/sizeof(mmRLC_STATIC_PG_STATUS[0]), 0, 0 },
	{ "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0x312f, &mmRLC_GPM_PERF_COUNT_0[0], sizeof(mmRLC_GPM_PERF_COUNT_0)/sizeof(mmRLC_GPM_PERF_COUNT_0[0]), 0, 0 },
	{ "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0x3130, &mmRLC_GPM_PERF_COUNT_1[0], sizeof(mmRLC_GPM_PERF_COUNT_1)/sizeof(mmRLC_GPM_PERF_COUNT_1[0]), 0, 0 },
	{ "mmRLC_SPM_VMID", REG_MMIO, 0x3131, &mmRLC_SPM_VMID[0], sizeof(mmRLC_SPM_VMID)/sizeof(mmRLC_SPM_VMID[0]), 0, 0 },
	{ "mmRLC_SPM_INT_CNTL", REG_MMIO, 0x3132, &mmRLC_SPM_INT_CNTL[0], sizeof(mmRLC_SPM_INT_CNTL)/sizeof(mmRLC_SPM_INT_CNTL[0]), 0, 0 },
	{ "mmRLC_SPM_INT_STATUS", REG_MMIO, 0x3133, &mmRLC_SPM_INT_STATUS[0], sizeof(mmRLC_SPM_INT_STATUS)/sizeof(mmRLC_SPM_INT_STATUS[0]), 0, 0 },
	{ "mmRLC_SPM_DEBUG_SELECT", REG_MMIO, 0x3134, &mmRLC_SPM_DEBUG_SELECT[0], sizeof(mmRLC_SPM_DEBUG_SELECT)/sizeof(mmRLC_SPM_DEBUG_SELECT[0]), 0, 0 },
	{ "mmRLC_SPM_DEBUG", REG_MMIO, 0x3135, &mmRLC_SPM_DEBUG[0], sizeof(mmRLC_SPM_DEBUG)/sizeof(mmRLC_SPM_DEBUG[0]), 0, 0 },
	{ "mmRLC_GPM_LOG_ADDR", REG_MMIO, 0x3136, &mmRLC_GPM_LOG_ADDR[0], sizeof(mmRLC_GPM_LOG_ADDR)/sizeof(mmRLC_GPM_LOG_ADDR[0]), 0, 0 },
	{ "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0x3137, &mmRLC_GPM_LOG_SIZE[0], sizeof(mmRLC_GPM_LOG_SIZE)/sizeof(mmRLC_GPM_LOG_SIZE[0]), 0, 0 },
	{ "mmRLC_GPM_LOG_CONT", REG_MMIO, 0x3138, &mmRLC_GPM_LOG_CONT[0], sizeof(mmRLC_GPM_LOG_CONT)/sizeof(mmRLC_GPM_LOG_CONT[0]), 0, 0 },
	{ "mmRLC_GPR_REG1", REG_MMIO, 0x3139, &mmRLC_GPR_REG1[0], sizeof(mmRLC_GPR_REG1)/sizeof(mmRLC_GPR_REG1[0]), 0, 0 },
	{ "mmRLC_SAFE_MODE", REG_MMIO, 0x313a, &mmRLC_SAFE_MODE[0], sizeof(mmRLC_SAFE_MODE)/sizeof(mmRLC_SAFE_MODE[0]), 0, 0 },
	{ "mmRLC_GPR_REG2", REG_MMIO, 0x313a, &mmRLC_GPR_REG2[0], sizeof(mmRLC_GPR_REG2)/sizeof(mmRLC_GPR_REG2[0]), 0, 0 },
	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x31c0, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 },
	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x31c1, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 },
	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x31c2, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 },
	{ "mmSPI_CDBG_SYS_GFX", REG_MMIO, 0x31c3, &mmSPI_CDBG_SYS_GFX[0], sizeof(mmSPI_CDBG_SYS_GFX)/sizeof(mmSPI_CDBG_SYS_GFX[0]), 0, 0 },
	{ "mmSPI_CDBG_SYS_HP3D", REG_MMIO, 0x31c4, &mmSPI_CDBG_SYS_HP3D[0], sizeof(mmSPI_CDBG_SYS_HP3D)/sizeof(mmSPI_CDBG_SYS_HP3D[0]), 0, 0 },
	{ "mmSPI_CDBG_SYS_CS0", REG_MMIO, 0x31c5, &mmSPI_CDBG_SYS_CS0[0], sizeof(mmSPI_CDBG_SYS_CS0)/sizeof(mmSPI_CDBG_SYS_CS0[0]), 0, 0 },
	{ "mmSPI_CDBG_SYS_CS1", REG_MMIO, 0x31c6, &mmSPI_CDBG_SYS_CS1[0], sizeof(mmSPI_CDBG_SYS_CS1)/sizeof(mmSPI_CDBG_SYS_CS1[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x31c7, &mmSPI_WCL_PIPE_PERCENT_GFX[0], sizeof(mmSPI_WCL_PIPE_PERCENT_GFX)/sizeof(mmSPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x31c8, &mmSPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D)/sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x31c9, &mmSPI_WCL_PIPE_PERCENT_CS0[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS0)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x31ca, &mmSPI_WCL_PIPE_PERCENT_CS1[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS1)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x31cb, &mmSPI_WCL_PIPE_PERCENT_CS2[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS2)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x31cc, &mmSPI_WCL_PIPE_PERCENT_CS3[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS3)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x31cd, &mmSPI_WCL_PIPE_PERCENT_CS4[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS4)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x31ce, &mmSPI_WCL_PIPE_PERCENT_CS5[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS5)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x31cf, &mmSPI_WCL_PIPE_PERCENT_CS6[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS6)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 },
	{ "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x31d0, &mmSPI_WCL_PIPE_PERCENT_CS7[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS7)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 },
	{ "mmSPI_GDBG_WAVE_CNTL", REG_MMIO, 0x31d1, &mmSPI_GDBG_WAVE_CNTL[0], sizeof(mmSPI_GDBG_WAVE_CNTL)/sizeof(mmSPI_GDBG_WAVE_CNTL[0]), 0, 0 },
	{ "mmSPI_GDBG_TRAP_CONFIG", REG_MMIO, 0x31d2, &mmSPI_GDBG_TRAP_CONFIG[0], sizeof(mmSPI_GDBG_TRAP_CONFIG)/sizeof(mmSPI_GDBG_TRAP_CONFIG[0]), 0, 0 },
	{ "mmSPI_GDBG_TRAP_MASK", REG_MMIO, 0x31d3, &mmSPI_GDBG_TRAP_MASK[0], sizeof(mmSPI_GDBG_TRAP_MASK)/sizeof(mmSPI_GDBG_TRAP_MASK[0]), 0, 0 },
	{ "mmSPI_GDBG_TBA_LO", REG_MMIO, 0x31d4, &mmSPI_GDBG_TBA_LO[0], sizeof(mmSPI_GDBG_TBA_LO)/sizeof(mmSPI_GDBG_TBA_LO[0]), 0, 0 },
	{ "mmSPI_GDBG_TBA_HI", REG_MMIO, 0x31d5, &mmSPI_GDBG_TBA_HI[0], sizeof(mmSPI_GDBG_TBA_HI)/sizeof(mmSPI_GDBG_TBA_HI[0]), 0, 0 },
	{ "mmSPI_GDBG_TMA_LO", REG_MMIO, 0x31d6, &mmSPI_GDBG_TMA_LO[0], sizeof(mmSPI_GDBG_TMA_LO)/sizeof(mmSPI_GDBG_TMA_LO[0]), 0, 0 },
	{ "mmSPI_GDBG_TMA_HI", REG_MMIO, 0x31d7, &mmSPI_GDBG_TMA_HI[0], sizeof(mmSPI_GDBG_TMA_HI)/sizeof(mmSPI_GDBG_TMA_HI[0]), 0, 0 },
	{ "mmSPI_GDBG_TRAP_DATA0", REG_MMIO, 0x31d8, &mmSPI_GDBG_TRAP_DATA0[0], sizeof(mmSPI_GDBG_TRAP_DATA0)/sizeof(mmSPI_GDBG_TRAP_DATA0[0]), 0, 0 },
	{ "mmSPI_GDBG_TRAP_DATA1", REG_MMIO, 0x31d9, &mmSPI_GDBG_TRAP_DATA1[0], sizeof(mmSPI_GDBG_TRAP_DATA1)/sizeof(mmSPI_GDBG_TRAP_DATA1[0]), 0, 0 },
	{ "mmSPI_RESET_DEBUG", REG_MMIO, 0x31da, &mmSPI_RESET_DEBUG[0], sizeof(mmSPI_RESET_DEBUG)/sizeof(mmSPI_RESET_DEBUG[0]), 0, 0 },
	{ "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x31db, &mmSPI_COMPUTE_QUEUE_RESET[0], sizeof(mmSPI_COMPUTE_QUEUE_RESET)/sizeof(mmSPI_COMPUTE_QUEUE_RESET[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x31dc, &mmSPI_RESOURCE_RESERVE_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x31dd, &mmSPI_RESOURCE_RESERVE_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x31de, &mmSPI_RESOURCE_RESERVE_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x31df, &mmSPI_RESOURCE_RESERVE_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x31e0, &mmSPI_RESOURCE_RESERVE_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x31e1, &mmSPI_RESOURCE_RESERVE_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x31e2, &mmSPI_RESOURCE_RESERVE_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x31e3, &mmSPI_RESOURCE_RESERVE_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x31e4, &mmSPI_RESOURCE_RESERVE_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x31e5, &mmSPI_RESOURCE_RESERVE_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x31e6, &mmSPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x31e7, &mmSPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x31e8, &mmSPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x31e9, &mmSPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x31ea, &mmSPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x31eb, &mmSPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x31ec, &mmSPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x31ed, &mmSPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x31ee, &mmSPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x31ef, &mmSPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_10", REG_MMIO, 0x31f0, &mmSPI_RESOURCE_RESERVE_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_CU_10[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_CU_11", REG_MMIO, 0x31f1, &mmSPI_RESOURCE_RESERVE_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_CU_11[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_10", REG_MMIO, 0x31f2, &mmSPI_RESOURCE_RESERVE_EN_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10[0]), 0, 0 },
	{ "mmSPI_RESOURCE_RESERVE_EN_CU_11", REG_MMIO, 0x31f3, &mmSPI_RESOURCE_RESERVE_EN_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11[0]), 0, 0 },
	{ "ixDIDT_DB_WEIGHT8_11", REG_SMC, 0x32, &ixDIDT_DB_WEIGHT8_11[0], sizeof(ixDIDT_DB_WEIGHT8_11)/sizeof(ixDIDT_DB_WEIGHT8_11[0]), 0, 0 },
	{ "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x3240, &mmCP_HPD_ROQ_OFFSETS[0], sizeof(mmCP_HPD_ROQ_OFFSETS)/sizeof(mmCP_HPD_ROQ_OFFSETS[0]), 0, 0 },
	{ "mmCP_HPD_EOP_BASE_ADDR", REG_MMIO, 0x3241, &mmCP_HPD_EOP_BASE_ADDR[0], sizeof(mmCP_HPD_EOP_BASE_ADDR)/sizeof(mmCP_HPD_EOP_BASE_ADDR[0]), 0, 0 },
	{ "mmCP_HPD_EOP_BASE_ADDR_HI", REG_MMIO, 0x3242, &mmCP_HPD_EOP_BASE_ADDR_HI[0], sizeof(mmCP_HPD_EOP_BASE_ADDR_HI)/sizeof(mmCP_HPD_EOP_BASE_ADDR_HI[0]), 0, 0 },
	{ "mmCP_HPD_EOP_VMID", REG_MMIO, 0x3243, &mmCP_HPD_EOP_VMID[0], sizeof(mmCP_HPD_EOP_VMID)/sizeof(mmCP_HPD_EOP_VMID[0]), 0, 0 },
	{ "mmCP_HPD_EOP_CONTROL", REG_MMIO, 0x3244, &mmCP_HPD_EOP_CONTROL[0], sizeof(mmCP_HPD_EOP_CONTROL)/sizeof(mmCP_HPD_EOP_CONTROL[0]), 0, 0 },
	{ "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x3245, &mmCP_MQD_BASE_ADDR[0], sizeof(mmCP_MQD_BASE_ADDR)/sizeof(mmCP_MQD_BASE_ADDR[0]), 0, 0 },
	{ "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x3246, &mmCP_MQD_BASE_ADDR_HI[0], sizeof(mmCP_MQD_BASE_ADDR_HI)/sizeof(mmCP_MQD_BASE_ADDR_HI[0]), 0, 0 },
	{ "mmCP_HQD_ACTIVE", REG_MMIO, 0x3247, &mmCP_HQD_ACTIVE[0], sizeof(mmCP_HQD_ACTIVE)/sizeof(mmCP_HQD_ACTIVE[0]), 0, 0 },
	{ "mmCP_HQD_VMID", REG_MMIO, 0x3248, &mmCP_HQD_VMID[0], sizeof(mmCP_HQD_VMID)/sizeof(mmCP_HQD_VMID[0]), 0, 0 },
	{ "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x3249, &mmCP_HQD_PERSISTENT_STATE[0], sizeof(mmCP_HQD_PERSISTENT_STATE)/sizeof(mmCP_HQD_PERSISTENT_STATE[0]), 0, 0 },
	{ "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x324a, &mmCP_HQD_PIPE_PRIORITY[0], sizeof(mmCP_HQD_PIPE_PRIORITY)/sizeof(mmCP_HQD_PIPE_PRIORITY[0]), 0, 0 },
	{ "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x324b, &mmCP_HQD_QUEUE_PRIORITY[0], sizeof(mmCP_HQD_QUEUE_PRIORITY)/sizeof(mmCP_HQD_QUEUE_PRIORITY[0]), 0, 0 },
	{ "mmCP_HQD_QUANTUM", REG_MMIO, 0x324c, &mmCP_HQD_QUANTUM[0], sizeof(mmCP_HQD_QUANTUM)/sizeof(mmCP_HQD_QUANTUM[0]), 0, 0 },
	{ "mmCP_HQD_PQ_BASE", REG_MMIO, 0x324d, &mmCP_HQD_PQ_BASE[0], sizeof(mmCP_HQD_PQ_BASE)/sizeof(mmCP_HQD_PQ_BASE[0]), 0, 0 },
	{ "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x324e, &mmCP_HQD_PQ_BASE_HI[0], sizeof(mmCP_HQD_PQ_BASE_HI)/sizeof(mmCP_HQD_PQ_BASE_HI[0]), 0, 0 },
	{ "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x324f, &mmCP_HQD_PQ_RPTR[0], sizeof(mmCP_HQD_PQ_RPTR)/sizeof(mmCP_HQD_PQ_RPTR[0]), 0, 0 },
	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x3250, &mmCP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 },
	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x3251, &mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 },
	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x3252, &mmCP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 },
	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3253, &mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 },
	{ "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x3254, &mmCP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL)/sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 },
	{ "mmCP_HQD_PQ_WPTR", REG_MMIO, 0x3255, &mmCP_HQD_PQ_WPTR[0], sizeof(mmCP_HQD_PQ_WPTR)/sizeof(mmCP_HQD_PQ_WPTR[0]), 0, 0 },
	{ "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x3256, &mmCP_HQD_PQ_CONTROL[0], sizeof(mmCP_HQD_PQ_CONTROL)/sizeof(mmCP_HQD_PQ_CONTROL[0]), 0, 0 },
	{ "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x3257, &mmCP_HQD_IB_BASE_ADDR[0], sizeof(mmCP_HQD_IB_BASE_ADDR)/sizeof(mmCP_HQD_IB_BASE_ADDR[0]), 0, 0 },
	{ "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x3258, &mmCP_HQD_IB_BASE_ADDR_HI[0], sizeof(mmCP_HQD_IB_BASE_ADDR_HI)/sizeof(mmCP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 },
	{ "mmCP_HQD_IB_RPTR", REG_MMIO, 0x3259, &mmCP_HQD_IB_RPTR[0], sizeof(mmCP_HQD_IB_RPTR)/sizeof(mmCP_HQD_IB_RPTR[0]), 0, 0 },
	{ "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x325a, &mmCP_HQD_IB_CONTROL[0], sizeof(mmCP_HQD_IB_CONTROL)/sizeof(mmCP_HQD_IB_CONTROL[0]), 0, 0 },
	{ "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x325b, &mmCP_HQD_IQ_TIMER[0], sizeof(mmCP_HQD_IQ_TIMER)/sizeof(mmCP_HQD_IQ_TIMER[0]), 0, 0 },
	{ "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x325c, &mmCP_HQD_IQ_RPTR[0], sizeof(mmCP_HQD_IQ_RPTR)/sizeof(mmCP_HQD_IQ_RPTR[0]), 0, 0 },
	{ "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x325d, &mmCP_HQD_DEQUEUE_REQUEST[0], sizeof(mmCP_HQD_DEQUEUE_REQUEST)/sizeof(mmCP_HQD_DEQUEUE_REQUEST[0]), 0, 0 },
	{ "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_DMA_OFFLOAD[0], sizeof(mmCP_HQD_DMA_OFFLOAD)/sizeof(mmCP_HQD_DMA_OFFLOAD[0]), 0, 0 },
	{ "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x325f, &mmCP_HQD_SEMA_CMD[0], sizeof(mmCP_HQD_SEMA_CMD)/sizeof(mmCP_HQD_SEMA_CMD[0]), 0, 0 },
	{ "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x3260, &mmCP_HQD_MSG_TYPE[0], sizeof(mmCP_HQD_MSG_TYPE)/sizeof(mmCP_HQD_MSG_TYPE[0]), 0, 0 },
	{ "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x3261, &mmCP_HQD_ATOMIC0_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 },
	{ "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x3262, &mmCP_HQD_ATOMIC0_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 },
	{ "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x3263, &mmCP_HQD_ATOMIC1_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 },
	{ "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x3264, &mmCP_HQD_ATOMIC1_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 },
	{ "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_SCHEDULER0[0], sizeof(mmCP_HQD_HQ_SCHEDULER0)/sizeof(mmCP_HQD_HQ_SCHEDULER0[0]), 0, 0 },
	{ "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x3266, &mmCP_HQD_HQ_SCHEDULER1[0], sizeof(mmCP_HQD_HQ_SCHEDULER1)/sizeof(mmCP_HQD_HQ_SCHEDULER1[0]), 0, 0 },
	{ "mmCP_MQD_CONTROL", REG_MMIO, 0x3267, &mmCP_MQD_CONTROL[0], sizeof(mmCP_MQD_CONTROL)/sizeof(mmCP_MQD_CONTROL[0]), 0, 0 },
	{ "mmDIDT_IND_INDEX", REG_MMIO, 0x3280, &mmDIDT_IND_INDEX[0], sizeof(mmDIDT_IND_INDEX)/sizeof(mmDIDT_IND_INDEX[0]), 0, 0 },
	{ "mmDIDT_IND_DATA", REG_MMIO, 0x3281, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
	{ "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x32a0, &mmTCP_WATCH0_ADDR_H[0], sizeof(mmTCP_WATCH0_ADDR_H)/sizeof(mmTCP_WATCH0_ADDR_H[0]), 0, 0 },
	{ "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x32a1, &mmTCP_WATCH0_ADDR_L[0], sizeof(mmTCP_WATCH0_ADDR_L)/sizeof(mmTCP_WATCH0_ADDR_L[0]), 0, 0 },
	{ "mmTCP_WATCH0_CNTL", REG_MMIO, 0x32a2, &mmTCP_WATCH0_CNTL[0], sizeof(mmTCP_WATCH0_CNTL)/sizeof(mmTCP_WATCH0_CNTL[0]), 0, 0 },
	{ "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x32a3, &mmTCP_WATCH1_ADDR_H[0], sizeof(mmTCP_WATCH1_ADDR_H)/sizeof(mmTCP_WATCH1_ADDR_H[0]), 0, 0 },
	{ "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x32a4, &mmTCP_WATCH1_ADDR_L[0], sizeof(mmTCP_WATCH1_ADDR_L)/sizeof(mmTCP_WATCH1_ADDR_L[0]), 0, 0 },
	{ "mmTCP_WATCH1_CNTL", REG_MMIO, 0x32a5, &mmTCP_WATCH1_CNTL[0], sizeof(mmTCP_WATCH1_CNTL)/sizeof(mmTCP_WATCH1_CNTL[0]), 0, 0 },
	{ "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x32a6, &mmTCP_WATCH2_ADDR_H[0], sizeof(mmTCP_WATCH2_ADDR_H)/sizeof(mmTCP_WATCH2_ADDR_H[0]), 0, 0 },
	{ "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x32a7, &mmTCP_WATCH2_ADDR_L[0], sizeof(mmTCP_WATCH2_ADDR_L)/sizeof(mmTCP_WATCH2_ADDR_L[0]), 0, 0 },
	{ "mmTCP_WATCH2_CNTL", REG_MMIO, 0x32a8, &mmTCP_WATCH2_CNTL[0], sizeof(mmTCP_WATCH2_CNTL)/sizeof(mmTCP_WATCH2_CNTL[0]), 0, 0 },
	{ "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x32a9, &mmTCP_WATCH3_ADDR_H[0], sizeof(mmTCP_WATCH3_ADDR_H)/sizeof(mmTCP_WATCH3_ADDR_H[0]), 0, 0 },
	{ "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x32aa, &mmTCP_WATCH3_ADDR_L[0], sizeof(mmTCP_WATCH3_ADDR_L)/sizeof(mmTCP_WATCH3_ADDR_L[0]), 0, 0 },
	{ "mmTCP_WATCH3_CNTL", REG_MMIO, 0x32ab, &mmTCP_WATCH3_CNTL[0], sizeof(mmTCP_WATCH3_CNTL)/sizeof(mmTCP_WATCH3_CNTL[0]), 0, 0 },
	{ "mmGDS_VMID0_BASE", REG_MMIO, 0x3300, &mmGDS_VMID0_BASE[0], sizeof(mmGDS_VMID0_BASE)/sizeof(mmGDS_VMID0_BASE[0]), 0, 0 },
	{ "mmGDS_VMID0_SIZE", REG_MMIO, 0x3301, &mmGDS_VMID0_SIZE[0], sizeof(mmGDS_VMID0_SIZE)/sizeof(mmGDS_VMID0_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID1_BASE", REG_MMIO, 0x3302, &mmGDS_VMID1_BASE[0], sizeof(mmGDS_VMID1_BASE)/sizeof(mmGDS_VMID1_BASE[0]), 0, 0 },
	{ "mmGDS_VMID1_SIZE", REG_MMIO, 0x3303, &mmGDS_VMID1_SIZE[0], sizeof(mmGDS_VMID1_SIZE)/sizeof(mmGDS_VMID1_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID2_BASE", REG_MMIO, 0x3304, &mmGDS_VMID2_BASE[0], sizeof(mmGDS_VMID2_BASE)/sizeof(mmGDS_VMID2_BASE[0]), 0, 0 },
	{ "mmGDS_VMID2_SIZE", REG_MMIO, 0x3305, &mmGDS_VMID2_SIZE[0], sizeof(mmGDS_VMID2_SIZE)/sizeof(mmGDS_VMID2_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID3_BASE", REG_MMIO, 0x3306, &mmGDS_VMID3_BASE[0], sizeof(mmGDS_VMID3_BASE)/sizeof(mmGDS_VMID3_BASE[0]), 0, 0 },
	{ "mmGDS_VMID3_SIZE", REG_MMIO, 0x3307, &mmGDS_VMID3_SIZE[0], sizeof(mmGDS_VMID3_SIZE)/sizeof(mmGDS_VMID3_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID4_BASE", REG_MMIO, 0x3308, &mmGDS_VMID4_BASE[0], sizeof(mmGDS_VMID4_BASE)/sizeof(mmGDS_VMID4_BASE[0]), 0, 0 },
	{ "mmGDS_VMID4_SIZE", REG_MMIO, 0x3309, &mmGDS_VMID4_SIZE[0], sizeof(mmGDS_VMID4_SIZE)/sizeof(mmGDS_VMID4_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID5_BASE", REG_MMIO, 0x330a, &mmGDS_VMID5_BASE[0], sizeof(mmGDS_VMID5_BASE)/sizeof(mmGDS_VMID5_BASE[0]), 0, 0 },
	{ "mmGDS_VMID5_SIZE", REG_MMIO, 0x330b, &mmGDS_VMID5_SIZE[0], sizeof(mmGDS_VMID5_SIZE)/sizeof(mmGDS_VMID5_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID6_BASE", REG_MMIO, 0x330c, &mmGDS_VMID6_BASE[0], sizeof(mmGDS_VMID6_BASE)/sizeof(mmGDS_VMID6_BASE[0]), 0, 0 },
	{ "mmGDS_VMID6_SIZE", REG_MMIO, 0x330d, &mmGDS_VMID6_SIZE[0], sizeof(mmGDS_VMID6_SIZE)/sizeof(mmGDS_VMID6_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID7_BASE", REG_MMIO, 0x330e, &mmGDS_VMID7_BASE[0], sizeof(mmGDS_VMID7_BASE)/sizeof(mmGDS_VMID7_BASE[0]), 0, 0 },
	{ "mmGDS_VMID7_SIZE", REG_MMIO, 0x330f, &mmGDS_VMID7_SIZE[0], sizeof(mmGDS_VMID7_SIZE)/sizeof(mmGDS_VMID7_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID8_BASE", REG_MMIO, 0x3310, &mmGDS_VMID8_BASE[0], sizeof(mmGDS_VMID8_BASE)/sizeof(mmGDS_VMID8_BASE[0]), 0, 0 },
	{ "mmGDS_VMID8_SIZE", REG_MMIO, 0x3311, &mmGDS_VMID8_SIZE[0], sizeof(mmGDS_VMID8_SIZE)/sizeof(mmGDS_VMID8_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID9_BASE", REG_MMIO, 0x3312, &mmGDS_VMID9_BASE[0], sizeof(mmGDS_VMID9_BASE)/sizeof(mmGDS_VMID9_BASE[0]), 0, 0 },
	{ "mmGDS_VMID9_SIZE", REG_MMIO, 0x3313, &mmGDS_VMID9_SIZE[0], sizeof(mmGDS_VMID9_SIZE)/sizeof(mmGDS_VMID9_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID10_BASE", REG_MMIO, 0x3314, &mmGDS_VMID10_BASE[0], sizeof(mmGDS_VMID10_BASE)/sizeof(mmGDS_VMID10_BASE[0]), 0, 0 },
	{ "mmGDS_VMID10_SIZE", REG_MMIO, 0x3315, &mmGDS_VMID10_SIZE[0], sizeof(mmGDS_VMID10_SIZE)/sizeof(mmGDS_VMID10_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID11_BASE", REG_MMIO, 0x3316, &mmGDS_VMID11_BASE[0], sizeof(mmGDS_VMID11_BASE)/sizeof(mmGDS_VMID11_BASE[0]), 0, 0 },
	{ "mmGDS_VMID11_SIZE", REG_MMIO, 0x3317, &mmGDS_VMID11_SIZE[0], sizeof(mmGDS_VMID11_SIZE)/sizeof(mmGDS_VMID11_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID12_BASE", REG_MMIO, 0x3318, &mmGDS_VMID12_BASE[0], sizeof(mmGDS_VMID12_BASE)/sizeof(mmGDS_VMID12_BASE[0]), 0, 0 },
	{ "mmGDS_VMID12_SIZE", REG_MMIO, 0x3319, &mmGDS_VMID12_SIZE[0], sizeof(mmGDS_VMID12_SIZE)/sizeof(mmGDS_VMID12_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID13_BASE", REG_MMIO, 0x331a, &mmGDS_VMID13_BASE[0], sizeof(mmGDS_VMID13_BASE)/sizeof(mmGDS_VMID13_BASE[0]), 0, 0 },
	{ "mmGDS_VMID13_SIZE", REG_MMIO, 0x331b, &mmGDS_VMID13_SIZE[0], sizeof(mmGDS_VMID13_SIZE)/sizeof(mmGDS_VMID13_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID14_BASE", REG_MMIO, 0x331c, &mmGDS_VMID14_BASE[0], sizeof(mmGDS_VMID14_BASE)/sizeof(mmGDS_VMID14_BASE[0]), 0, 0 },
	{ "mmGDS_VMID14_SIZE", REG_MMIO, 0x331d, &mmGDS_VMID14_SIZE[0], sizeof(mmGDS_VMID14_SIZE)/sizeof(mmGDS_VMID14_SIZE[0]), 0, 0 },
	{ "mmGDS_VMID15_BASE", REG_MMIO, 0x331e, &mmGDS_VMID15_BASE[0], sizeof(mmGDS_VMID15_BASE)/sizeof(mmGDS_VMID15_BASE[0]), 0, 0 },
	{ "mmGDS_VMID15_SIZE", REG_MMIO, 0x331f, &mmGDS_VMID15_SIZE[0], sizeof(mmGDS_VMID15_SIZE)/sizeof(mmGDS_VMID15_SIZE[0]), 0, 0 },
	{ "mmGDS_GWS_VMID0", REG_MMIO, 0x3320, &mmGDS_GWS_VMID0[0], sizeof(mmGDS_GWS_VMID0)/sizeof(mmGDS_GWS_VMID0[0]), 0, 0 },
	{ "mmGDS_GWS_VMID1", REG_MMIO, 0x3321, &mmGDS_GWS_VMID1[0], sizeof(mmGDS_GWS_VMID1)/sizeof(mmGDS_GWS_VMID1[0]), 0, 0 },
	{ "mmGDS_GWS_VMID2", REG_MMIO, 0x3322, &mmGDS_GWS_VMID2[0], sizeof(mmGDS_GWS_VMID2)/sizeof(mmGDS_GWS_VMID2[0]), 0, 0 },
	{ "mmGDS_GWS_VMID3", REG_MMIO, 0x3323, &mmGDS_GWS_VMID3[0], sizeof(mmGDS_GWS_VMID3)/sizeof(mmGDS_GWS_VMID3[0]), 0, 0 },
	{ "mmGDS_GWS_VMID4", REG_MMIO, 0x3324, &mmGDS_GWS_VMID4[0], sizeof(mmGDS_GWS_VMID4)/sizeof(mmGDS_GWS_VMID4[0]), 0, 0 },
	{ "mmGDS_GWS_VMID5", REG_MMIO, 0x3325, &mmGDS_GWS_VMID5[0], sizeof(mmGDS_GWS_VMID5)/sizeof(mmGDS_GWS_VMID5[0]), 0, 0 },
	{ "mmGDS_GWS_VMID6", REG_MMIO, 0x3326, &mmGDS_GWS_VMID6[0], sizeof(mmGDS_GWS_VMID6)/sizeof(mmGDS_GWS_VMID6[0]), 0, 0 },
	{ "mmGDS_GWS_VMID7", REG_MMIO, 0x3327, &mmGDS_GWS_VMID7[0], sizeof(mmGDS_GWS_VMID7)/sizeof(mmGDS_GWS_VMID7[0]), 0, 0 },
	{ "mmGDS_GWS_VMID8", REG_MMIO, 0x3328, &mmGDS_GWS_VMID8[0], sizeof(mmGDS_GWS_VMID8)/sizeof(mmGDS_GWS_VMID8[0]), 0, 0 },
	{ "mmGDS_GWS_VMID9", REG_MMIO, 0x3329, &mmGDS_GWS_VMID9[0], sizeof(mmGDS_GWS_VMID9)/sizeof(mmGDS_GWS_VMID9[0]), 0, 0 },
	{ "mmGDS_GWS_VMID10", REG_MMIO, 0x332a, &mmGDS_GWS_VMID10[0], sizeof(mmGDS_GWS_VMID10)/sizeof(mmGDS_GWS_VMID10[0]), 0, 0 },
	{ "mmGDS_GWS_VMID11", REG_MMIO, 0x332b, &mmGDS_GWS_VMID11[0], sizeof(mmGDS_GWS_VMID11)/sizeof(mmGDS_GWS_VMID11[0]), 0, 0 },
	{ "mmGDS_GWS_VMID12", REG_MMIO, 0x332c, &mmGDS_GWS_VMID12[0], sizeof(mmGDS_GWS_VMID12)/sizeof(mmGDS_GWS_VMID12[0]), 0, 0 },
	{ "mmGDS_GWS_VMID13", REG_MMIO, 0x332d, &mmGDS_GWS_VMID13[0], sizeof(mmGDS_GWS_VMID13)/sizeof(mmGDS_GWS_VMID13[0]), 0, 0 },
	{ "mmGDS_GWS_VMID14", REG_MMIO, 0x332e, &mmGDS_GWS_VMID14[0], sizeof(mmGDS_GWS_VMID14)/sizeof(mmGDS_GWS_VMID14[0]), 0, 0 },
	{ "mmGDS_GWS_VMID15", REG_MMIO, 0x332f, &mmGDS_GWS_VMID15[0], sizeof(mmGDS_GWS_VMID15)/sizeof(mmGDS_GWS_VMID15[0]), 0, 0 },
	{ "mmGDS_OA_VMID0", REG_MMIO, 0x3330, &mmGDS_OA_VMID0[0], sizeof(mmGDS_OA_VMID0)/sizeof(mmGDS_OA_VMID0[0]), 0, 0 },
	{ "mmGDS_OA_VMID1", REG_MMIO, 0x3331, &mmGDS_OA_VMID1[0], sizeof(mmGDS_OA_VMID1)/sizeof(mmGDS_OA_VMID1[0]), 0, 0 },
	{ "mmGDS_OA_VMID2", REG_MMIO, 0x3332, &mmGDS_OA_VMID2[0], sizeof(mmGDS_OA_VMID2)/sizeof(mmGDS_OA_VMID2[0]), 0, 0 },
	{ "mmGDS_OA_VMID3", REG_MMIO, 0x3333, &mmGDS_OA_VMID3[0], sizeof(mmGDS_OA_VMID3)/sizeof(mmGDS_OA_VMID3[0]), 0, 0 },
	{ "mmGDS_OA_VMID4", REG_MMIO, 0x3334, &mmGDS_OA_VMID4[0], sizeof(mmGDS_OA_VMID4)/sizeof(mmGDS_OA_VMID4[0]), 0, 0 },
	{ "mmGDS_OA_VMID5", REG_MMIO, 0x3335, &mmGDS_OA_VMID5[0], sizeof(mmGDS_OA_VMID5)/sizeof(mmGDS_OA_VMID5[0]), 0, 0 },
	{ "mmGDS_OA_VMID6", REG_MMIO, 0x3336, &mmGDS_OA_VMID6[0], sizeof(mmGDS_OA_VMID6)/sizeof(mmGDS_OA_VMID6[0]), 0, 0 },
	{ "mmGDS_OA_VMID7", REG_MMIO, 0x3337, &mmGDS_OA_VMID7[0], sizeof(mmGDS_OA_VMID7)/sizeof(mmGDS_OA_VMID7[0]), 0, 0 },
	{ "mmGDS_OA_VMID8", REG_MMIO, 0x3338, &mmGDS_OA_VMID8[0], sizeof(mmGDS_OA_VMID8)/sizeof(mmGDS_OA_VMID8[0]), 0, 0 },
	{ "mmGDS_OA_VMID9", REG_MMIO, 0x3339, &mmGDS_OA_VMID9[0], sizeof(mmGDS_OA_VMID9)/sizeof(mmGDS_OA_VMID9[0]), 0, 0 },
	{ "mmGDS_OA_VMID10", REG_MMIO, 0x333a, &mmGDS_OA_VMID10[0], sizeof(mmGDS_OA_VMID10)/sizeof(mmGDS_OA_VMID10[0]), 0, 0 },
	{ "mmGDS_OA_VMID11", REG_MMIO, 0x333b, &mmGDS_OA_VMID11[0], sizeof(mmGDS_OA_VMID11)/sizeof(mmGDS_OA_VMID11[0]), 0, 0 },
	{ "mmGDS_OA_VMID12", REG_MMIO, 0x333c, &mmGDS_OA_VMID12[0], sizeof(mmGDS_OA_VMID12)/sizeof(mmGDS_OA_VMID12[0]), 0, 0 },
	{ "mmGDS_OA_VMID13", REG_MMIO, 0x333d, &mmGDS_OA_VMID13[0], sizeof(mmGDS_OA_VMID13)/sizeof(mmGDS_OA_VMID13[0]), 0, 0 },
	{ "mmGDS_OA_VMID14", REG_MMIO, 0x333e, &mmGDS_OA_VMID14[0], sizeof(mmGDS_OA_VMID14)/sizeof(mmGDS_OA_VMID14[0]), 0, 0 },
	{ "mmGDS_OA_VMID15", REG_MMIO, 0x333f, &mmGDS_OA_VMID15[0], sizeof(mmGDS_OA_VMID15)/sizeof(mmGDS_OA_VMID15[0]), 0, 0 },
	{ "mmGDS_GWS_RESET0", REG_MMIO, 0x3344, &mmGDS_GWS_RESET0[0], sizeof(mmGDS_GWS_RESET0)/sizeof(mmGDS_GWS_RESET0[0]), 0, 0 },
	{ "mmGDS_GWS_RESET1", REG_MMIO, 0x3345, &mmGDS_GWS_RESET1[0], sizeof(mmGDS_GWS_RESET1)/sizeof(mmGDS_GWS_RESET1[0]), 0, 0 },
	{ "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x3346, &mmGDS_GWS_RESOURCE_RESET[0], sizeof(mmGDS_GWS_RESOURCE_RESET)/sizeof(mmGDS_GWS_RESOURCE_RESET[0]), 0, 0 },
	{ "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x3348, &mmGDS_COMPUTE_MAX_WAVE_ID[0], sizeof(mmGDS_COMPUTE_MAX_WAVE_ID)/sizeof(mmGDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 },
	{ "mmGDS_OA_RESET_MASK", REG_MMIO, 0x3349, &mmGDS_OA_RESET_MASK[0], sizeof(mmGDS_OA_RESET_MASK)/sizeof(mmGDS_OA_RESET_MASK[0]), 0, 0 },
	{ "mmGDS_OA_RESET", REG_MMIO, 0x334a, &mmGDS_OA_RESET[0], sizeof(mmGDS_OA_RESET)/sizeof(mmGDS_OA_RESET[0]), 0, 0 },
	{ "mmGDS_ENHANCE", REG_MMIO, 0x334b, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 },
	{ "mmGDS_OA_CGPG_RESTORE", REG_MMIO, 0x334c, &mmGDS_OA_CGPG_RESTORE[0], sizeof(mmGDS_OA_CGPG_RESTORE)/sizeof(mmGDS_OA_CGPG_RESTORE[0]), 0, 0 },
	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 },
	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 },
	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 },
	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 },
	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 },
	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338b, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338c, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338d, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x338e, &mmRAS_SQ_SIGNATURE0[0], sizeof(mmRAS_SQ_SIGNATURE0)/sizeof(mmRAS_SQ_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338f, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 },
	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 },
	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 },
	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339a, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 },
	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339b, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339c, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339d, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339e, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 },
	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339f, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG04", REG_SMC, 0x4, &ixCLIPPER_DEBUG_REG04[0], sizeof(ixCLIPPER_DEBUG_REG04)/sizeof(ixCLIPPER_DEBUG_REG04[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG4", REG_SMC, 0x4, &ixGDS_DEBUG_REG4[0], sizeof(ixGDS_DEBUG_REG4)/sizeof(ixGDS_DEBUG_REG4[0]), 0, 0 },
	{ "ixWD_DEBUG_REG4", REG_SMC, 0x4, &ixWD_DEBUG_REG4[0], sizeof(ixWD_DEBUG_REG4)/sizeof(ixWD_DEBUG_REG4[0]), 0, 0 },
	{ "ixDIDT_TD_CTRL0", REG_SMC, 0x40, &ixDIDT_TD_CTRL0[0], sizeof(ixDIDT_TD_CTRL0)/sizeof(ixDIDT_TD_CTRL0[0]), 0, 0 },
	{ "ixDIDT_TD_CTRL1", REG_SMC, 0x41, &ixDIDT_TD_CTRL1[0], sizeof(ixDIDT_TD_CTRL1)/sizeof(ixDIDT_TD_CTRL1[0]), 0, 0 },
	{ "ixDIDT_TD_CTRL2", REG_SMC, 0x42, &ixDIDT_TD_CTRL2[0], sizeof(ixDIDT_TD_CTRL2)/sizeof(ixDIDT_TD_CTRL2[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG05", REG_SMC, 0x5, &ixCLIPPER_DEBUG_REG05[0], sizeof(ixCLIPPER_DEBUG_REG05)/sizeof(ixCLIPPER_DEBUG_REG05[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG5", REG_SMC, 0x5, &ixGDS_DEBUG_REG5[0], sizeof(ixGDS_DEBUG_REG5)/sizeof(ixGDS_DEBUG_REG5[0]), 0, 0 },
	{ "ixWD_DEBUG_REG5", REG_SMC, 0x5, &ixWD_DEBUG_REG5[0], sizeof(ixWD_DEBUG_REG5)/sizeof(ixWD_DEBUG_REG5[0]), 0, 0 },
	{ "ixDIDT_TD_WEIGHT0_3", REG_SMC, 0x50, &ixDIDT_TD_WEIGHT0_3[0], sizeof(ixDIDT_TD_WEIGHT0_3)/sizeof(ixDIDT_TD_WEIGHT0_3[0]), 0, 0 },
	{ "ixDIDT_TD_WEIGHT4_7", REG_SMC, 0x51, &ixDIDT_TD_WEIGHT4_7[0], sizeof(ixDIDT_TD_WEIGHT4_7)/sizeof(ixDIDT_TD_WEIGHT4_7[0]), 0, 0 },
	{ "ixDIDT_TD_WEIGHT8_11", REG_SMC, 0x52, &ixDIDT_TD_WEIGHT8_11[0], sizeof(ixDIDT_TD_WEIGHT8_11)/sizeof(ixDIDT_TD_WEIGHT8_11[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG06", REG_SMC, 0x6, &ixCLIPPER_DEBUG_REG06[0], sizeof(ixCLIPPER_DEBUG_REG06)/sizeof(ixCLIPPER_DEBUG_REG06[0]), 0, 0 },
	{ "ixGDS_DEBUG_REG6", REG_SMC, 0x6, &ixGDS_DEBUG_REG6[0], sizeof(ixGDS_DEBUG_REG6)/sizeof(ixGDS_DEBUG_REG6[0]), 0, 0 },
	{ "ixIA_DEBUG_REG6", REG_SMC, 0x6, &ixIA_DEBUG_REG6[0], sizeof(ixIA_DEBUG_REG6)/sizeof(ixIA_DEBUG_REG6[0]), 0, 0 },
	{ "ixDIDT_TCP_CTRL0", REG_SMC, 0x60, &ixDIDT_TCP_CTRL0[0], sizeof(ixDIDT_TCP_CTRL0)/sizeof(ixDIDT_TCP_CTRL0[0]), 0, 0 },
	{ "ixDIDT_TCP_CTRL1", REG_SMC, 0x61, &ixDIDT_TCP_CTRL1[0], sizeof(ixDIDT_TCP_CTRL1)/sizeof(ixDIDT_TCP_CTRL1[0]), 0, 0 },
	{ "ixDIDT_TCP_CTRL2", REG_SMC, 0x62, &ixDIDT_TCP_CTRL2[0], sizeof(ixDIDT_TCP_CTRL2)/sizeof(ixDIDT_TCP_CTRL2[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG07", REG_SMC, 0x7, &ixCLIPPER_DEBUG_REG07[0], sizeof(ixCLIPPER_DEBUG_REG07)/sizeof(ixCLIPPER_DEBUG_REG07[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG18", REG_SMC, 0x7, &ixVGT_DEBUG_REG18[0], sizeof(ixVGT_DEBUG_REG18)/sizeof(ixVGT_DEBUG_REG18[0]), 0, 0 },
	{ "ixIA_DEBUG_REG7", REG_SMC, 0x7, &ixIA_DEBUG_REG7[0], sizeof(ixIA_DEBUG_REG7)/sizeof(ixIA_DEBUG_REG7[0]), 0, 0 },
	{ "ixDIDT_TCP_WEIGHT0_3", REG_SMC, 0x70, &ixDIDT_TCP_WEIGHT0_3[0], sizeof(ixDIDT_TCP_WEIGHT0_3)/sizeof(ixDIDT_TCP_WEIGHT0_3[0]), 0, 0 },
	{ "ixDIDT_TCP_WEIGHT4_7", REG_SMC, 0x71, &ixDIDT_TCP_WEIGHT4_7[0], sizeof(ixDIDT_TCP_WEIGHT4_7)/sizeof(ixDIDT_TCP_WEIGHT4_7[0]), 0, 0 },
	{ "ixDIDT_TCP_WEIGHT8_11", REG_SMC, 0x72, &ixDIDT_TCP_WEIGHT8_11[0], sizeof(ixDIDT_TCP_WEIGHT8_11)/sizeof(ixDIDT_TCP_WEIGHT8_11[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG08", REG_SMC, 0x8, &ixCLIPPER_DEBUG_REG08[0], sizeof(ixCLIPPER_DEBUG_REG08)/sizeof(ixCLIPPER_DEBUG_REG08[0]), 0, 0 },
	{ "ixSQ_DEBUG_STS_LOCAL", REG_SMC, 0x8, &ixSQ_DEBUG_STS_LOCAL[0], sizeof(ixSQ_DEBUG_STS_LOCAL)/sizeof(ixSQ_DEBUG_STS_LOCAL[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG8", REG_SMC, 0x8, &ixVGT_DEBUG_REG8[0], sizeof(ixVGT_DEBUG_REG8)/sizeof(ixVGT_DEBUG_REG8[0]), 0, 0 },
	{ "ixIA_DEBUG_REG8", REG_SMC, 0x8, &ixIA_DEBUG_REG8[0], sizeof(ixIA_DEBUG_REG8)/sizeof(ixIA_DEBUG_REG8[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG09", REG_SMC, 0x9, &ixCLIPPER_DEBUG_REG09[0], sizeof(ixCLIPPER_DEBUG_REG09)/sizeof(ixCLIPPER_DEBUG_REG09[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG9", REG_SMC, 0x9, &ixVGT_DEBUG_REG9[0], sizeof(ixVGT_DEBUG_REG9)/sizeof(ixVGT_DEBUG_REG9[0]), 0, 0 },
	{ "ixIA_DEBUG_REG9", REG_SMC, 0x9, &ixIA_DEBUG_REG9[0], sizeof(ixIA_DEBUG_REG9)/sizeof(ixIA_DEBUG_REG9[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG10", REG_SMC, 0xa, &ixCLIPPER_DEBUG_REG10[0], sizeof(ixCLIPPER_DEBUG_REG10)/sizeof(ixCLIPPER_DEBUG_REG10[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG10", REG_SMC, 0xa, &ixVGT_DEBUG_REG10[0], sizeof(ixVGT_DEBUG_REG10)/sizeof(ixVGT_DEBUG_REG10[0]), 0, 0 },
	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xa000, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 },
	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xa001, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 },
	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xa002, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 },
	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xa003, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 },
	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xa004, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 },
	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xa005, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 },
	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xa008, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xa009, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xa00a, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 },
	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xa00b, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xa00c, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xa00d, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xa00f, &mmDB_DEPTH_INFO[0], sizeof(mmDB_DEPTH_INFO)/sizeof(mmDB_DEPTH_INFO[0]), 0, 0 },
	{ "mmDB_Z_INFO", REG_MMIO, 0xa010, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 },
	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xa011, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 },
	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xa012, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 },
	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xa013, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 },
	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xa014, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 },
	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xa015, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xa016, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 },
	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xa017, &mmDB_DEPTH_SLICE[0], sizeof(mmDB_DEPTH_SLICE)/sizeof(mmDB_DEPTH_SLICE[0]), 0, 0 },
	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xa020, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
	{ "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0xa021, &mmTA_BC_BASE_ADDR_HI[0], sizeof(mmTA_BC_BASE_ADDR_HI)/sizeof(mmTA_BC_BASE_ADDR_HI[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0xa07a, &mmCOHER_DEST_BASE_HI_0[0], sizeof(mmCOHER_DEST_BASE_HI_0)/sizeof(mmCOHER_DEST_BASE_HI_0[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0xa07b, &mmCOHER_DEST_BASE_HI_1[0], sizeof(mmCOHER_DEST_BASE_HI_1)/sizeof(mmCOHER_DEST_BASE_HI_1[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0xa07c, &mmCOHER_DEST_BASE_HI_2[0], sizeof(mmCOHER_DEST_BASE_HI_2)/sizeof(mmCOHER_DEST_BASE_HI_2[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0xa07d, &mmCOHER_DEST_BASE_HI_3[0], sizeof(mmCOHER_DEST_BASE_HI_3)/sizeof(mmCOHER_DEST_BASE_HI_3[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xa07e, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xa07f, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 },
	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xa080, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 },
	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xa081, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xa082, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xa083, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xa084, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xa085, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xa086, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xa087, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xa088, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xa089, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xa08a, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 },
	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xa08b, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 },
	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xa08c, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 },
	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xa08d, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
	{ "mmCB_TARGET_MASK", REG_MMIO, 0xa08e, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 },
	{ "mmCB_SHADER_MASK", REG_MMIO, 0xa08f, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 },
	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xa090, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xa091, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xa092, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 },
	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xa093, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xa094, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xa095, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xa096, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xa097, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xa098, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xa099, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xa09a, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xa09b, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xa09c, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xa09d, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xa09e, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xa09f, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xa0a0, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xa0a1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xa0a2, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xa0a3, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xa0a4, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xa0a5, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xa0a6, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xa0a7, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xa0a8, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xa0a9, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xa0aa, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xa0ab, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xa0ac, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xa0ad, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xa0ae, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xa0af, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xa0b0, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xa0b1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xa0b2, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xa0b3, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xa0b4, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xa0b5, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xa0b6, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xa0b7, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xa0b8, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xa0b9, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xa0ba, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xa0bb, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xa0bc, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xa0bd, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xa0be, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xa0bf, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xa0c0, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xa0c1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xa0c2, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xa0c3, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xa0c4, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xa0c5, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xa0c6, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xa0c7, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xa0c8, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xa0c9, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xa0ca, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xa0cb, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xa0cc, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xa0cd, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xa0ce, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xa0cf, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xa0d0, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xa0d1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xa0d2, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 },
	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xa0d3, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 },
	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xa0d4, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 },
	{ "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0xa0d5, &mmPA_SC_RASTER_CONFIG_1[0], sizeof(mmPA_SC_RASTER_CONFIG_1)/sizeof(mmPA_SC_RASTER_CONFIG_1[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0xa0d6, &mmPA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL)/sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 },
	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xa0d8, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 },
	{ "mmCP_RINGID", REG_MMIO, 0xa0d9, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 },
	{ "mmCP_VMID", REG_MMIO, 0xa0da, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 },
	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xa100, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 },
	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xa101, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 },
	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xa102, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 },
	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xa103, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
	{ "mmCB_BLEND_RED", REG_MMIO, 0xa105, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xa106, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xa107, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 },
	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xa108, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 },
	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xa10b, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 },
	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xa10c, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 },
	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xa10d, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xa10f, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xa110, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xa111, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xa112, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xa113, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xa114, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xa115, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xa116, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xa117, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xa118, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xa119, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xa11a, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xa11b, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xa11c, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xa11d, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xa11e, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xa11f, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xa120, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xa121, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xa122, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xa123, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xa124, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xa125, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xa126, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xa127, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xa128, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xa129, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xa12a, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xa12b, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xa12c, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xa12d, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xa12e, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xa12f, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xa130, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xa131, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xa132, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xa133, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xa134, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xa135, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xa136, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xa137, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xa138, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xa139, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xa13a, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xa13b, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xa13c, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xa13d, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xa13e, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xa13f, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xa140, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xa141, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xa142, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xa143, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xa144, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xa145, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xa146, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xa147, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xa148, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xa149, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xa14a, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xa14b, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xa14c, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xa14d, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xa14e, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xa14f, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xa150, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xa151, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xa152, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xa153, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xa154, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xa155, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xa156, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xa157, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xa158, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xa159, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xa15a, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xa15b, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xa15c, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xa15d, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xa15e, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xa15f, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xa160, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xa161, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xa162, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xa163, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xa164, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xa165, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xa166, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xa167, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xa168, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xa169, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 },
	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xa16a, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xa16b, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 },
	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xa16c, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xa16d, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xa16e, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xa16f, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xa170, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xa171, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xa172, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 },
	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xa173, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xa174, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xa175, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xa176, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 },
	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xa177, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xa178, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xa179, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xa17a, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 },
	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xa17b, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xa17c, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xa17d, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xa17e, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 },
	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xa17f, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xa180, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xa181, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xa182, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 },
	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xa183, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 },
	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xa184, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 },
	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xa185, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 },
	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xa186, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xa191, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xa192, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xa193, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xa194, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xa195, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xa196, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xa197, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xa198, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xa199, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xa19a, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xa19b, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xa19c, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xa19d, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xa19e, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xa19f, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xa1a0, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xa1a1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xa1a2, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xa1a3, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xa1a4, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xa1a5, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xa1a6, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xa1a7, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xa1a8, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xa1a9, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xa1aa, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xa1ab, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xa1ac, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xa1ad, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xa1ae, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xa1af, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xa1b0, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 },
	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xa1b1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xa1b3, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 },
	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xa1b4, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 },
	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xa1b5, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 },
	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xa1b6, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 },
	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xa1b8, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 },
	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xa1ba, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 },
	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xa1c3, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 },
	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xa1c4, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 },
	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xa1c5, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 },
	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xa1e0, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xa1e1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xa1e2, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xa1e3, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xa1e4, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xa1e5, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xa1e6, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 },
	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xa1e7, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 },
	{ "mmCS_COPY_STATE", REG_MMIO, 0xa1f3, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 },
	{ "mmGFX_COPY_STATE", REG_MMIO, 0xa1f4, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 },
	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xa1f5, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 },
	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xa1f6, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 },
	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xa1f7, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 },
	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xa1f8, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 },
	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xa1f9, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 },
	{ "mmVGT_DMA_BASE", REG_MMIO, 0xa1fa, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 },
	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xa1fc, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 },
	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xa1fd, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 },
	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xa1fe, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 },
	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xa200, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 },
	{ "mmDB_EQAA", REG_MMIO, 0xa201, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 },
	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xa202, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 },
	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xa203, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 },
	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xa204, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 },
	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xa205, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 },
	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xa206, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 },
	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xa207, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 },
	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xa208, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 },
	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xa209, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xa20a, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xa20b, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xa280, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 },
	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xa281, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 },
	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xa282, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 },
	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xa283, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 },
	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xa284, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xa285, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 },
	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xa286, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xa287, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xa288, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 },
	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xa289, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 },
	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xa28a, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 },
	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xa28b, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 },
	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xa28c, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xa28d, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xa28e, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xa28f, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
	{ "mmVGT_GS_MODE", REG_MMIO, 0xa290, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 },
	{ "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0xa291, &mmVGT_GS_ONCHIP_CNTL[0], sizeof(mmVGT_GS_ONCHIP_CNTL)/sizeof(mmVGT_GS_ONCHIP_CNTL[0]), 0, 0 },
	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xa292, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 },
	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xa293, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 },
	{ "mmVGT_ENHANCE", REG_MMIO, 0xa294, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 },
	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xa295, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 },
	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xa296, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 },
	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xa297, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 },
	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xa298, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xa299, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xa29a, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xa29b, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
	{ "mmIA_ENHANCE", REG_MMIO, 0xa29c, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 },
	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xa29d, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 },
	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xa29e, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 },
	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xa29f, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 },
	{ "mmWD_ENHANCE", REG_MMIO, 0xa2a0, &mmWD_ENHANCE[0], sizeof(mmWD_ENHANCE)/sizeof(mmWD_ENHANCE[0]), 0, 0 },
	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xa2a1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 },
	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xa2a2, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 },
	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xa2a3, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 },
	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xa2a4, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xa2a5, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xa2a8, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xa2a9, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xa2aa, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xa2ab, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xa2ac, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xa2ad, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 },
	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xa2ae, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 },
	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xa2af, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 },
	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xa2b0, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xa2b1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xa2b2, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xa2b4, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xa2b5, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xa2b7, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xa2b8, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xa2b9, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xa2bb, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xa2bc, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xa2bd, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xa2bf, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xa2c0, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xa2c1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xa2c3, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xa2ca, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xa2cb, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xa2cc, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xa2ce, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 },
	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xa2d5, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 },
	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xa2d6, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 },
	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xa2d7, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xa2d8, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xa2d9, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xa2da, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
	{ "mmVGT_TF_PARAM", REG_MMIO, 0xa2db, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 },
	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xa2dc, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 },
	{ "mmVGT_DISPATCH_DRAW_INDEX", REG_MMIO, 0xa2dd, &mmVGT_DISPATCH_DRAW_INDEX[0], sizeof(mmVGT_DISPATCH_DRAW_INDEX)/sizeof(mmVGT_DISPATCH_DRAW_INDEX[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xa2de, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xa2df, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xa2e0, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xa2e1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xa2e2, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xa2e3, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xa2e4, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 },
	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xa2e5, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xa2e6, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xa2f5, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xa2f6, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xa2f7, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 },
	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xa2f8, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 },
	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xa2f9, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 },
	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xa2fa, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xa2fb, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xa2fc, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xa2fd, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xa2fe, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xa2ff, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xa300, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xa301, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xa302, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xa303, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xa304, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xa305, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xa306, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xa307, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xa308, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xa309, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xa30a, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xa30b, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xa30c, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xa30d, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xa30e, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xa30f, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xa316, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xa317, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xa318, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 },
	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xa319, &mmCB_COLOR0_PITCH[0], sizeof(mmCB_COLOR0_PITCH)/sizeof(mmCB_COLOR0_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xa31a, &mmCB_COLOR0_SLICE[0], sizeof(mmCB_COLOR0_SLICE)/sizeof(mmCB_COLOR0_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xa31b, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xa31c, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 },
	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xa31d, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xa31f, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xa320, &mmCB_COLOR0_CMASK_SLICE[0], sizeof(mmCB_COLOR0_CMASK_SLICE)/sizeof(mmCB_COLOR0_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xa321, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xa322, &mmCB_COLOR0_FMASK_SLICE[0], sizeof(mmCB_COLOR0_FMASK_SLICE)/sizeof(mmCB_COLOR0_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xa323, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xa324, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xa327, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 },
	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xa328, &mmCB_COLOR1_PITCH[0], sizeof(mmCB_COLOR1_PITCH)/sizeof(mmCB_COLOR1_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xa329, &mmCB_COLOR1_SLICE[0], sizeof(mmCB_COLOR1_SLICE)/sizeof(mmCB_COLOR1_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xa32a, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xa32b, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 },
	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xa32c, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xa32e, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xa32f, &mmCB_COLOR1_CMASK_SLICE[0], sizeof(mmCB_COLOR1_CMASK_SLICE)/sizeof(mmCB_COLOR1_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xa330, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xa331, &mmCB_COLOR1_FMASK_SLICE[0], sizeof(mmCB_COLOR1_FMASK_SLICE)/sizeof(mmCB_COLOR1_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xa332, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xa333, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xa336, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 },
	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xa337, &mmCB_COLOR2_PITCH[0], sizeof(mmCB_COLOR2_PITCH)/sizeof(mmCB_COLOR2_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xa338, &mmCB_COLOR2_SLICE[0], sizeof(mmCB_COLOR2_SLICE)/sizeof(mmCB_COLOR2_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xa339, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xa33a, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 },
	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xa33b, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xa33d, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xa33e, &mmCB_COLOR2_CMASK_SLICE[0], sizeof(mmCB_COLOR2_CMASK_SLICE)/sizeof(mmCB_COLOR2_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xa33f, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xa340, &mmCB_COLOR2_FMASK_SLICE[0], sizeof(mmCB_COLOR2_FMASK_SLICE)/sizeof(mmCB_COLOR2_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xa341, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xa342, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xa345, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 },
	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xa346, &mmCB_COLOR3_PITCH[0], sizeof(mmCB_COLOR3_PITCH)/sizeof(mmCB_COLOR3_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xa347, &mmCB_COLOR3_SLICE[0], sizeof(mmCB_COLOR3_SLICE)/sizeof(mmCB_COLOR3_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xa348, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xa349, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 },
	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xa34a, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xa34c, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xa34d, &mmCB_COLOR3_CMASK_SLICE[0], sizeof(mmCB_COLOR3_CMASK_SLICE)/sizeof(mmCB_COLOR3_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xa34e, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xa34f, &mmCB_COLOR3_FMASK_SLICE[0], sizeof(mmCB_COLOR3_FMASK_SLICE)/sizeof(mmCB_COLOR3_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xa350, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xa351, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xa354, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 },
	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xa355, &mmCB_COLOR4_PITCH[0], sizeof(mmCB_COLOR4_PITCH)/sizeof(mmCB_COLOR4_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xa356, &mmCB_COLOR4_SLICE[0], sizeof(mmCB_COLOR4_SLICE)/sizeof(mmCB_COLOR4_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xa357, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xa358, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 },
	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xa359, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xa35b, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xa35c, &mmCB_COLOR4_CMASK_SLICE[0], sizeof(mmCB_COLOR4_CMASK_SLICE)/sizeof(mmCB_COLOR4_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xa35d, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xa35e, &mmCB_COLOR4_FMASK_SLICE[0], sizeof(mmCB_COLOR4_FMASK_SLICE)/sizeof(mmCB_COLOR4_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xa35f, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xa360, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xa363, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 },
	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xa364, &mmCB_COLOR5_PITCH[0], sizeof(mmCB_COLOR5_PITCH)/sizeof(mmCB_COLOR5_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xa365, &mmCB_COLOR5_SLICE[0], sizeof(mmCB_COLOR5_SLICE)/sizeof(mmCB_COLOR5_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xa366, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xa367, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 },
	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xa368, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xa36a, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xa36b, &mmCB_COLOR5_CMASK_SLICE[0], sizeof(mmCB_COLOR5_CMASK_SLICE)/sizeof(mmCB_COLOR5_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xa36c, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xa36d, &mmCB_COLOR5_FMASK_SLICE[0], sizeof(mmCB_COLOR5_FMASK_SLICE)/sizeof(mmCB_COLOR5_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xa36e, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xa36f, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xa372, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 },
	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xa373, &mmCB_COLOR6_PITCH[0], sizeof(mmCB_COLOR6_PITCH)/sizeof(mmCB_COLOR6_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xa374, &mmCB_COLOR6_SLICE[0], sizeof(mmCB_COLOR6_SLICE)/sizeof(mmCB_COLOR6_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xa375, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xa376, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 },
	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xa377, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xa379, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xa37a, &mmCB_COLOR6_CMASK_SLICE[0], sizeof(mmCB_COLOR6_CMASK_SLICE)/sizeof(mmCB_COLOR6_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xa37b, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xa37c, &mmCB_COLOR6_FMASK_SLICE[0], sizeof(mmCB_COLOR6_FMASK_SLICE)/sizeof(mmCB_COLOR6_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xa37d, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xa37e, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xa381, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 },
	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xa382, &mmCB_COLOR7_PITCH[0], sizeof(mmCB_COLOR7_PITCH)/sizeof(mmCB_COLOR7_PITCH[0]), 0, 0 },
	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xa383, &mmCB_COLOR7_SLICE[0], sizeof(mmCB_COLOR7_SLICE)/sizeof(mmCB_COLOR7_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xa384, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 },
	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xa385, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 },
	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xa386, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 },
	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xa388, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 },
	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xa389, &mmCB_COLOR7_CMASK_SLICE[0], sizeof(mmCB_COLOR7_CMASK_SLICE)/sizeof(mmCB_COLOR7_CMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xa38a, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 },
	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xa38b, &mmCB_COLOR7_FMASK_SLICE[0], sizeof(mmCB_COLOR7_FMASK_SLICE)/sizeof(mmCB_COLOR7_FMASK_SLICE[0]), 0, 0 },
	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xa38c, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xa38d, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG11", REG_SMC, 0xb, &ixCLIPPER_DEBUG_REG11[0], sizeof(ixCLIPPER_DEBUG_REG11)/sizeof(ixCLIPPER_DEBUG_REG11[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG11", REG_SMC, 0xb, &ixVGT_DEBUG_REG11[0], sizeof(ixVGT_DEBUG_REG11)/sizeof(ixVGT_DEBUG_REG11[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG12", REG_SMC, 0xc, &ixCLIPPER_DEBUG_REG12[0], sizeof(ixCLIPPER_DEBUG_REG12)/sizeof(ixCLIPPER_DEBUG_REG12[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG12", REG_SMC, 0xc, &ixVGT_DEBUG_REG12[0], sizeof(ixVGT_DEBUG_REG12)/sizeof(ixVGT_DEBUG_REG12[0]), 0, 0 },
	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0xc000, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 },
	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0xc001, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 },
	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0xc002, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 },
	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0xc003, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 },
	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0xc004, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 },
	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0xc005, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 },
	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0xc006, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0xc007, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0xc008, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0xc009, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0xc00a, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0xc00b, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0xc00c, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0xc00d, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0xc00e, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0xc00f, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0xc010, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0xc011, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0xc012, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0xc013, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0xc014, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0xc015, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0xc016, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0xc017, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0xc018, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0xc019, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0xc01a, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0xc01b, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0xc01c, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0xc01d, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0xc01e, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0xc01f, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0xc020, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0xc021, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0xc022, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0xc023, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0xc024, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0xc025, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0xc026, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0xc027, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0xc028, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0xc029, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0xc02a, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0xc02b, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0xc02c, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0xc02d, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0xc02e, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0xc02f, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0xc030, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0xc031, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0xc03f, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 },
	{ "mmSCRATCH_REG0", REG_MMIO, 0xc040, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 },
	{ "mmSCRATCH_REG1", REG_MMIO, 0xc041, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 },
	{ "mmSCRATCH_REG2", REG_MMIO, 0xc042, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 },
	{ "mmSCRATCH_REG3", REG_MMIO, 0xc043, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 },
	{ "mmSCRATCH_REG4", REG_MMIO, 0xc044, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 },
	{ "mmSCRATCH_REG5", REG_MMIO, 0xc045, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 },
	{ "mmSCRATCH_REG6", REG_MMIO, 0xc046, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 },
	{ "mmSCRATCH_REG7", REG_MMIO, 0xc047, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 },
	{ "mmSCRATCH_UMSK", REG_MMIO, 0xc050, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 },
	{ "mmSCRATCH_ADDR", REG_MMIO, 0xc051, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 },
	{ "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0xc052, &mmCP_PFP_ATOMIC_PREOP_LO[0], sizeof(mmCP_PFP_ATOMIC_PREOP_LO)/sizeof(mmCP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 },
	{ "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0xc053, &mmCP_PFP_ATOMIC_PREOP_HI[0], sizeof(mmCP_PFP_ATOMIC_PREOP_HI)/sizeof(mmCP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 },
	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc054, &mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc055, &mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc056, &mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc057, &mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0xc058, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 },
	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0xc059, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 },
	{ "mmCP_APPEND_DATA", REG_MMIO, 0xc05a, &mmCP_APPEND_DATA[0], sizeof(mmCP_APPEND_DATA)/sizeof(mmCP_APPEND_DATA[0]), 0, 0 },
	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0xc05b, &mmCP_APPEND_LAST_CS_FENCE[0], sizeof(mmCP_APPEND_LAST_CS_FENCE)/sizeof(mmCP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0xc05c, &mmCP_APPEND_LAST_PS_FENCE[0], sizeof(mmCP_APPEND_LAST_PS_FENCE)/sizeof(mmCP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
	{ "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ME_ATOMIC_PREOP_LO[0], sizeof(mmCP_ME_ATOMIC_PREOP_LO)/sizeof(mmCP_ME_ATOMIC_PREOP_LO[0]), 0, 0 },
	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 },
	{ "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ME_ATOMIC_PREOP_HI[0], sizeof(mmCP_ME_ATOMIC_PREOP_HI)/sizeof(mmCP_ME_ATOMIC_PREOP_HI[0]), 0, 0 },
	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 },
	{ "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
	{ "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
	{ "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
	{ "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0xc069, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 },
	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0xc06a, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 },
	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0xc06b, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 },
	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0xc06c, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 },
	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0xc06d, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 },
	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0xc06e, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 },
	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0xc06f, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 },
	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0xc070, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 },
	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0xc071, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 },
	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0xc074, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0xc075, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0xc076, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0xc077, &mmCP_DMA_PFP_CONTROL[0], sizeof(mmCP_DMA_PFP_CONTROL)/sizeof(mmCP_DMA_PFP_CONTROL[0]), 0, 0 },
	{ "mmCP_DMA_ME_CONTROL", REG_MMIO, 0xc078, &mmCP_DMA_ME_CONTROL[0], sizeof(mmCP_DMA_ME_CONTROL)/sizeof(mmCP_DMA_ME_CONTROL[0]), 0, 0 },
	{ "mmCP_COHER_BASE_HI", REG_MMIO, 0xc079, &mmCP_COHER_BASE_HI[0], sizeof(mmCP_COHER_BASE_HI)/sizeof(mmCP_COHER_BASE_HI[0]), 0, 0 },
	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0xc07b, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 },
	{ "mmCP_COHER_CNTL", REG_MMIO, 0xc07c, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 },
	{ "mmCP_COHER_SIZE", REG_MMIO, 0xc07d, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 },
	{ "mmCP_COHER_BASE", REG_MMIO, 0xc07e, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 },
	{ "mmCP_COHER_STATUS", REG_MMIO, 0xc07f, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 },
	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0xc080, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 },
	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0xc081, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0xc082, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 },
	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0xc083, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0xc084, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 },
	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0xc085, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0xc086, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0xc087, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 },
	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0xc088, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0xc089, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 },
	{ "mmCP_DMA_CNTL", REG_MMIO, 0xc08a, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 },
	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0xc08b, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 },
	{ "mmCP_COHER_SIZE_HI", REG_MMIO, 0xc08c, &mmCP_COHER_SIZE_HI[0], sizeof(mmCP_COHER_SIZE_HI)/sizeof(mmCP_COHER_SIZE_HI[0]), 0, 0 },
	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0xc08d, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 },
	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0xc08e, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 },
	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0xc08f, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 },
	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0xc090, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 },
	{ "mmCP_RB_OFFSET", REG_MMIO, 0xc091, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 },
	{ "mmCP_IB1_OFFSET", REG_MMIO, 0xc092, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 },
	{ "mmCP_IB2_OFFSET", REG_MMIO, 0xc093, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 },
	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0xc094, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0xc095, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 },
	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0xc096, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0xc097, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 },
	{ "mmCP_CE_IB1_OFFSET", REG_MMIO, 0xc098, &mmCP_CE_IB1_OFFSET[0], sizeof(mmCP_CE_IB1_OFFSET)/sizeof(mmCP_CE_IB1_OFFSET[0]), 0, 0 },
	{ "mmCP_CE_IB2_OFFSET", REG_MMIO, 0xc099, &mmCP_CE_IB2_OFFSET[0], sizeof(mmCP_CE_IB2_OFFSET)/sizeof(mmCP_CE_IB2_OFFSET[0]), 0, 0 },
	{ "mmCP_CE_COUNTER", REG_MMIO, 0xc09a, &mmCP_CE_COUNTER[0], sizeof(mmCP_CE_COUNTER)/sizeof(mmCP_CE_COUNTER[0]), 0, 0 },
	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0xc0c3, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 },
	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0xc0c4, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 },
	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0xc0c5, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 },
	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0xc0c6, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 },
	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0xc0c7, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 },
	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0xc0c8, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 },
	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0xc0c9, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 },
	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0xc0ca, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 },
	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0xc0cb, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 },
	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0xc0cc, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 },
	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0xc0cd, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 },
	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0xc0ce, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 },
	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0xc0cf, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 },
	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0xc0d0, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 },
	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0xc0d1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 },
	{ "mmCP_ST_BASE_LO", REG_MMIO, 0xc0d2, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 },
	{ "mmCP_ST_BASE_HI", REG_MMIO, 0xc0d3, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 },
	{ "mmCP_ST_BUFSZ", REG_MMIO, 0xc0d4, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 },
	{ "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0xc0d5, &mmCP_EOP_DONE_EVENT_CNTL[0], sizeof(mmCP_EOP_DONE_EVENT_CNTL)/sizeof(mmCP_EOP_DONE_EVENT_CNTL[0]), 0, 0 },
	{ "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0xc0d6, &mmCP_EOP_DONE_DATA_CNTL[0], sizeof(mmCP_EOP_DONE_DATA_CNTL)/sizeof(mmCP_EOP_DONE_DATA_CNTL[0]), 0, 0 },
	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0xc200, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 },
	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0xc240, &mmVGT_ESGS_RING_SIZE[0], sizeof(mmVGT_ESGS_RING_SIZE)/sizeof(mmVGT_ESGS_RING_SIZE[0]), 0, 0 },
	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0xc241, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 },
	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0xc242, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 },
	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0xc243, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0xc244, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0xc245, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0xc246, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0xc247, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
	{ "mmVGT_NUM_INDICES", REG_MMIO, 0xc24c, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 },
	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0xc24d, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 },
	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0xc24e, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 },
	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0xc24f, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0xc250, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 },
	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0xc280, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0xc281, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0xc284, &mmPA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0xc285, &mmPA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0xc286, &mmPA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 },
	{ "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0xc28b, &mmPA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a0, &mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a1, &mmPA_SC_P3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0xc2a2, &mmPA_SC_P3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2a3, &mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
	{ "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2a4, &mmPA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a8, &mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a9, &mmPA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0xc2aa, &mmPA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2ab, &mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
	{ "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2ac, &mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2b0, &mmPA_SC_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0xc2b1, &mmPA_SC_TRAP_SCREEN_H[0], sizeof(mmPA_SC_TRAP_SCREEN_H)/sizeof(mmPA_SC_TRAP_SCREEN_H[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0xc2b2, &mmPA_SC_TRAP_SCREEN_V[0], sizeof(mmPA_SC_TRAP_SCREEN_V)/sizeof(mmPA_SC_TRAP_SCREEN_V[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2b3, &mmPA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
	{ "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2b4, &mmPA_SC_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0xc340, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0xc341, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0xc342, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0xc343, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
	{ "mmSQC_CACHES", REG_MMIO, 0xc348, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 },
	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0xc380, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
	{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0xc381, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0xc3c0, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0xc3c1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0xc3c2, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0xc3c3, &mmDB_OCCLUSION_COUNT1_HI[0], sizeof(mmDB_OCCLUSION_COUNT1_HI)/sizeof(mmDB_OCCLUSION_COUNT1_HI[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0xc3c4, &mmDB_OCCLUSION_COUNT2_LOW[0], sizeof(mmDB_OCCLUSION_COUNT2_LOW)/sizeof(mmDB_OCCLUSION_COUNT2_LOW[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0xc3c5, &mmDB_OCCLUSION_COUNT2_HI[0], sizeof(mmDB_OCCLUSION_COUNT2_HI)/sizeof(mmDB_OCCLUSION_COUNT2_HI[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0xc3c6, &mmDB_OCCLUSION_COUNT3_LOW[0], sizeof(mmDB_OCCLUSION_COUNT3_LOW)/sizeof(mmDB_OCCLUSION_COUNT3_LOW[0]), 0, 0 },
	{ "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0xc3c7, &mmDB_OCCLUSION_COUNT3_HI[0], sizeof(mmDB_OCCLUSION_COUNT3_HI)/sizeof(mmDB_OCCLUSION_COUNT3_HI[0]), 0, 0 },
	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0xc3fe, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 },
	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0xc3ff, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 },
	{ "mmGDS_RD_ADDR", REG_MMIO, 0xc400, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 },
	{ "mmGDS_RD_DATA", REG_MMIO, 0xc401, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 },
	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0xc402, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 },
	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0xc403, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 },
	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0xc404, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 },
	{ "mmGDS_WR_ADDR", REG_MMIO, 0xc405, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 },
	{ "mmGDS_WR_DATA", REG_MMIO, 0xc406, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 },
	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0xc407, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 },
	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0xc408, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 },
	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0xc409, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 },
	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0xc40a, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 },
	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0xc40b, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 },
	{ "mmGDS_ATOM_BASE", REG_MMIO, 0xc40c, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 },
	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0xc40d, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 },
	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0xc40e, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 },
	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0xc40f, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 },
	{ "mmGDS_ATOM_DST", REG_MMIO, 0xc410, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 },
	{ "mmGDS_ATOM_OP", REG_MMIO, 0xc411, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 },
	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0xc412, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 },
	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0xc413, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 },
	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0xc414, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 },
	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0xc415, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 },
	{ "mmGDS_ATOM_READ0", REG_MMIO, 0xc416, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 },
	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0xc417, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 },
	{ "mmGDS_ATOM_READ1", REG_MMIO, 0xc418, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 },
	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0xc419, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 },
	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0xc41a, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0xc41b, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 },
	{ "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0xc41c, &mmGDS_GWS_RESOURCE_CNT[0], sizeof(mmGDS_GWS_RESOURCE_CNT)/sizeof(mmGDS_GWS_RESOURCE_CNT[0]), 0, 0 },
	{ "mmGDS_OA_CNTL", REG_MMIO, 0xc41d, &mmGDS_OA_CNTL[0], sizeof(mmGDS_OA_CNTL)/sizeof(mmGDS_OA_CNTL[0]), 0, 0 },
	{ "mmGDS_OA_COUNTER", REG_MMIO, 0xc41e, &mmGDS_OA_COUNTER[0], sizeof(mmGDS_OA_COUNTER)/sizeof(mmGDS_OA_COUNTER[0]), 0, 0 },
	{ "mmGDS_OA_ADDRESS", REG_MMIO, 0xc41f, &mmGDS_OA_ADDRESS[0], sizeof(mmGDS_OA_ADDRESS)/sizeof(mmGDS_OA_ADDRESS[0]), 0, 0 },
	{ "mmGDS_OA_INCDEC", REG_MMIO, 0xc420, &mmGDS_OA_INCDEC[0], sizeof(mmGDS_OA_INCDEC)/sizeof(mmGDS_OA_INCDEC[0]), 0, 0 },
	{ "mmGDS_OA_RING_SIZE", REG_MMIO, 0xc421, &mmGDS_OA_RING_SIZE[0], sizeof(mmGDS_OA_RING_SIZE)/sizeof(mmGDS_OA_RING_SIZE[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG13", REG_SMC, 0xd, &ixCLIPPER_DEBUG_REG13[0], sizeof(ixCLIPPER_DEBUG_REG13)/sizeof(ixCLIPPER_DEBUG_REG13[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG13", REG_SMC, 0xd, &ixVGT_DEBUG_REG13[0], sizeof(ixVGT_DEBUG_REG13)/sizeof(ixVGT_DEBUG_REG13[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0xd000, &mmCPG_PERFCOUNTER1_LO[0], sizeof(mmCPG_PERFCOUNTER1_LO)/sizeof(mmCPG_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0xd001, &mmCPG_PERFCOUNTER1_HI[0], sizeof(mmCPG_PERFCOUNTER1_HI)/sizeof(mmCPG_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0xd002, &mmCPG_PERFCOUNTER0_LO[0], sizeof(mmCPG_PERFCOUNTER0_LO)/sizeof(mmCPG_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0xd003, &mmCPG_PERFCOUNTER0_HI[0], sizeof(mmCPG_PERFCOUNTER0_HI)/sizeof(mmCPG_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0xd004, &mmCPC_PERFCOUNTER1_LO[0], sizeof(mmCPC_PERFCOUNTER1_LO)/sizeof(mmCPC_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0xd005, &mmCPC_PERFCOUNTER1_HI[0], sizeof(mmCPC_PERFCOUNTER1_HI)/sizeof(mmCPC_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0xd006, &mmCPC_PERFCOUNTER0_LO[0], sizeof(mmCPC_PERFCOUNTER0_LO)/sizeof(mmCPC_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0xd007, &mmCPC_PERFCOUNTER0_HI[0], sizeof(mmCPC_PERFCOUNTER0_HI)/sizeof(mmCPC_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0xd008, &mmCPF_PERFCOUNTER1_LO[0], sizeof(mmCPF_PERFCOUNTER1_LO)/sizeof(mmCPF_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0xd009, &mmCPF_PERFCOUNTER1_HI[0], sizeof(mmCPF_PERFCOUNTER1_HI)/sizeof(mmCPF_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0xd00a, &mmCPF_PERFCOUNTER0_LO[0], sizeof(mmCPF_PERFCOUNTER0_LO)/sizeof(mmCPF_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0xd00b, &mmCPF_PERFCOUNTER0_HI[0], sizeof(mmCPF_PERFCOUNTER0_HI)/sizeof(mmCPF_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0xd040, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0xd041, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0xd043, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0xd044, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0xd045, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0xd046, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0xd047, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0xd048, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
	{ "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0xd049, &mmGRBM_SE2_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE2_PERFCOUNTER_LO)/sizeof(mmGRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 },
	{ "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0xd04a, &mmGRBM_SE2_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE2_PERFCOUNTER_HI)/sizeof(mmGRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 },
	{ "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0xd04b, &mmGRBM_SE3_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE3_PERFCOUNTER_LO)/sizeof(mmGRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 },
	{ "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0xd04c, &mmGRBM_SE3_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE3_PERFCOUNTER_HI)/sizeof(mmGRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0xd080, &mmWD_PERFCOUNTER0_LO[0], sizeof(mmWD_PERFCOUNTER0_LO)/sizeof(mmWD_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0xd081, &mmWD_PERFCOUNTER0_HI[0], sizeof(mmWD_PERFCOUNTER0_HI)/sizeof(mmWD_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0xd082, &mmWD_PERFCOUNTER1_LO[0], sizeof(mmWD_PERFCOUNTER1_LO)/sizeof(mmWD_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0xd083, &mmWD_PERFCOUNTER1_HI[0], sizeof(mmWD_PERFCOUNTER1_HI)/sizeof(mmWD_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0xd084, &mmWD_PERFCOUNTER2_LO[0], sizeof(mmWD_PERFCOUNTER2_LO)/sizeof(mmWD_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0xd085, &mmWD_PERFCOUNTER2_HI[0], sizeof(mmWD_PERFCOUNTER2_HI)/sizeof(mmWD_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0xd086, &mmWD_PERFCOUNTER3_LO[0], sizeof(mmWD_PERFCOUNTER3_LO)/sizeof(mmWD_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0xd087, &mmWD_PERFCOUNTER3_HI[0], sizeof(mmWD_PERFCOUNTER3_HI)/sizeof(mmWD_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0xd088, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0xd089, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0xd08a, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0xd08b, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0xd08c, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0xd08d, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0xd08e, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0xd08f, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0xd090, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0xd091, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0xd092, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0xd093, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0xd094, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0xd095, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0xd096, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0xd097, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0xd100, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0xd101, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0xd102, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0xd103, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0xd104, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0xd105, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0xd106, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0xd107, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0xd140, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0xd141, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0xd142, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0xd143, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0xd144, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0xd145, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0xd146, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0xd147, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0xd148, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0xd149, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0xd14a, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0xd14b, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0xd14c, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0xd14d, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0xd14e, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0xd14f, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0xd180, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0xd181, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0xd182, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0xd183, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0xd184, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0xd185, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0xd186, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0xd187, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0xd188, &mmSPI_PERFCOUNTER4_HI[0], sizeof(mmSPI_PERFCOUNTER4_HI)/sizeof(mmSPI_PERFCOUNTER4_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0xd189, &mmSPI_PERFCOUNTER4_LO[0], sizeof(mmSPI_PERFCOUNTER4_LO)/sizeof(mmSPI_PERFCOUNTER4_LO[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0xd18a, &mmSPI_PERFCOUNTER5_HI[0], sizeof(mmSPI_PERFCOUNTER5_HI)/sizeof(mmSPI_PERFCOUNTER5_HI[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0xd18b, &mmSPI_PERFCOUNTER5_LO[0], sizeof(mmSPI_PERFCOUNTER5_LO)/sizeof(mmSPI_PERFCOUNTER5_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0xd1c0, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0xd1c1, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0xd1c2, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0xd1c3, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0xd1c4, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0xd1c5, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0xd1c6, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0xd1c7, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0xd1c8, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0xd1c9, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0xd1ca, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0xd1cb, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0xd1cc, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0xd1cd, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0xd1ce, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0xd1cf, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0xd1d0, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0xd1d1, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0xd1d2, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0xd1d3, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0xd1d4, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0xd1d5, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0xd1d6, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0xd1d7, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0xd1d8, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0xd1d9, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0xd1da, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0xd1db, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0xd1dc, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0xd1dd, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0xd1de, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0xd1df, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0xd240, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0xd241, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0xd242, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0xd243, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0xd244, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0xd245, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0xd246, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0xd247, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0xd280, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0xd281, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0xd282, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0xd283, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0xd284, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0xd285, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0xd286, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0xd287, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0xd2c0, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0xd2c1, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0xd2c2, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0xd2c3, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0xd300, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0xd301, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0xd302, &mmTD_PERFCOUNTER1_LO[0], sizeof(mmTD_PERFCOUNTER1_LO)/sizeof(mmTD_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0xd303, &mmTD_PERFCOUNTER1_HI[0], sizeof(mmTD_PERFCOUNTER1_HI)/sizeof(mmTD_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0xd340, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0xd341, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0xd342, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0xd343, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0xd344, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0xd345, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0xd346, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0xd347, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0xd380, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0xd381, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0xd382, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0xd383, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0xd384, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0xd385, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0xd386, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0xd387, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0xd390, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0xd391, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0xd392, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0xd393, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0xd394, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0xd395, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0xd396, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0xd397, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER0_LO", REG_MMIO, 0xd3a0, &mmTCS_PERFCOUNTER0_LO[0], sizeof(mmTCS_PERFCOUNTER0_LO)/sizeof(mmTCS_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER0_HI", REG_MMIO, 0xd3a1, &mmTCS_PERFCOUNTER0_HI[0], sizeof(mmTCS_PERFCOUNTER0_HI)/sizeof(mmTCS_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER1_LO", REG_MMIO, 0xd3a2, &mmTCS_PERFCOUNTER1_LO[0], sizeof(mmTCS_PERFCOUNTER1_LO)/sizeof(mmTCS_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER1_HI", REG_MMIO, 0xd3a3, &mmTCS_PERFCOUNTER1_HI[0], sizeof(mmTCS_PERFCOUNTER1_HI)/sizeof(mmTCS_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER2_LO", REG_MMIO, 0xd3a4, &mmTCS_PERFCOUNTER2_LO[0], sizeof(mmTCS_PERFCOUNTER2_LO)/sizeof(mmTCS_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER2_HI", REG_MMIO, 0xd3a5, &mmTCS_PERFCOUNTER2_HI[0], sizeof(mmTCS_PERFCOUNTER2_HI)/sizeof(mmTCS_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER3_LO", REG_MMIO, 0xd3a6, &mmTCS_PERFCOUNTER3_LO[0], sizeof(mmTCS_PERFCOUNTER3_LO)/sizeof(mmTCS_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER3_HI", REG_MMIO, 0xd3a7, &mmTCS_PERFCOUNTER3_HI[0], sizeof(mmTCS_PERFCOUNTER3_HI)/sizeof(mmTCS_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0xd406, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0xd407, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0xd408, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0xd409, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0xd40a, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0xd40b, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0xd40c, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0xd40d, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0xd440, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0xd441, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0xd442, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0xd443, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0xd444, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0xd445, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0xd446, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0xd447, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0xd480, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0xd481, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0xd482, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0xd483, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0xd800, &mmCPG_PERFCOUNTER1_SELECT[0], sizeof(mmCPG_PERFCOUNTER1_SELECT)/sizeof(mmCPG_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd801, &mmCPG_PERFCOUNTER0_SELECT1[0], sizeof(mmCPG_PERFCOUNTER0_SELECT1)/sizeof(mmCPG_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0xd802, &mmCPG_PERFCOUNTER0_SELECT[0], sizeof(mmCPG_PERFCOUNTER0_SELECT)/sizeof(mmCPG_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd803, &mmCPC_PERFCOUNTER1_SELECT[0], sizeof(mmCPC_PERFCOUNTER1_SELECT)/sizeof(mmCPC_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd804, &mmCPC_PERFCOUNTER0_SELECT1[0], sizeof(mmCPC_PERFCOUNTER0_SELECT1)/sizeof(mmCPC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0xd805, &mmCPF_PERFCOUNTER1_SELECT[0], sizeof(mmCPF_PERFCOUNTER1_SELECT)/sizeof(mmCPF_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd806, &mmCPF_PERFCOUNTER0_SELECT1[0], sizeof(mmCPF_PERFCOUNTER0_SELECT1)/sizeof(mmCPF_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0xd807, &mmCPF_PERFCOUNTER0_SELECT[0], sizeof(mmCPF_PERFCOUNTER0_SELECT)/sizeof(mmCPF_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0xd808, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 },
	{ "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd809, &mmCPC_PERFCOUNTER0_SELECT[0], sizeof(mmCPC_PERFCOUNTER0_SELECT)/sizeof(mmCPC_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmCP_DRAW_OBJECT", REG_MMIO, 0xd810, &mmCP_DRAW_OBJECT[0], sizeof(mmCP_DRAW_OBJECT)/sizeof(mmCP_DRAW_OBJECT[0]), 0, 0 },
	{ "mmCP_DRAW_OBJECT_COUNTER", REG_MMIO, 0xd811, &mmCP_DRAW_OBJECT_COUNTER[0], sizeof(mmCP_DRAW_OBJECT_COUNTER)/sizeof(mmCP_DRAW_OBJECT_COUNTER[0]), 0, 0 },
	{ "mmCP_DRAW_WINDOW_MASK_HI", REG_MMIO, 0xd812, &mmCP_DRAW_WINDOW_MASK_HI[0], sizeof(mmCP_DRAW_WINDOW_MASK_HI)/sizeof(mmCP_DRAW_WINDOW_MASK_HI[0]), 0, 0 },
	{ "mmCP_DRAW_WINDOW_HI", REG_MMIO, 0xd813, &mmCP_DRAW_WINDOW_HI[0], sizeof(mmCP_DRAW_WINDOW_HI)/sizeof(mmCP_DRAW_WINDOW_HI[0]), 0, 0 },
	{ "mmCP_DRAW_WINDOW_LO", REG_MMIO, 0xd814, &mmCP_DRAW_WINDOW_LO[0], sizeof(mmCP_DRAW_WINDOW_LO)/sizeof(mmCP_DRAW_WINDOW_LO[0]), 0, 0 },
	{ "mmCP_DRAW_WINDOW_CNTL", REG_MMIO, 0xd815, &mmCP_DRAW_WINDOW_CNTL[0], sizeof(mmCP_DRAW_WINDOW_CNTL)/sizeof(mmCP_DRAW_WINDOW_CNTL[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0xd840, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0xd841, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0xd842, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0xd843, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
	{ "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0xd844, &mmGRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 },
	{ "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0xd845, &mmGRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0xd880, &mmWD_PERFCOUNTER0_SELECT[0], sizeof(mmWD_PERFCOUNTER0_SELECT)/sizeof(mmWD_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0xd881, &mmWD_PERFCOUNTER1_SELECT[0], sizeof(mmWD_PERFCOUNTER1_SELECT)/sizeof(mmWD_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0xd882, &mmWD_PERFCOUNTER2_SELECT[0], sizeof(mmWD_PERFCOUNTER2_SELECT)/sizeof(mmWD_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0xd883, &mmWD_PERFCOUNTER3_SELECT[0], sizeof(mmWD_PERFCOUNTER3_SELECT)/sizeof(mmWD_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0xd884, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0xd885, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0xd886, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0xd887, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd888, &mmIA_PERFCOUNTER0_SELECT1[0], sizeof(mmIA_PERFCOUNTER0_SELECT1)/sizeof(mmIA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0xd88c, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0xd88d, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0xd88e, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0xd88f, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd890, &mmVGT_PERFCOUNTER0_SELECT1[0], sizeof(mmVGT_PERFCOUNTER0_SELECT1)/sizeof(mmVGT_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd891, &mmVGT_PERFCOUNTER1_SELECT1[0], sizeof(mmVGT_PERFCOUNTER1_SELECT1)/sizeof(mmVGT_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0xd894, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0xd900, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd901, &mmPA_SU_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0xd902, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd903, &mmPA_SU_PERFCOUNTER1_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0xd904, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0xd905, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd940, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd941, &mmPA_SC_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd942, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0xd943, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0xd944, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0xd945, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0xd946, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0xd947, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0xd948, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0xd980, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0xd981, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0xd982, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0xd983, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd984, &mmSPI_PERFCOUNTER0_SELECT1[0], sizeof(mmSPI_PERFCOUNTER0_SELECT1)/sizeof(mmSPI_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd985, &mmSPI_PERFCOUNTER1_SELECT1[0], sizeof(mmSPI_PERFCOUNTER1_SELECT1)/sizeof(mmSPI_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0xd986, &mmSPI_PERFCOUNTER2_SELECT1[0], sizeof(mmSPI_PERFCOUNTER2_SELECT1)/sizeof(mmSPI_PERFCOUNTER2_SELECT1[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0xd987, &mmSPI_PERFCOUNTER3_SELECT1[0], sizeof(mmSPI_PERFCOUNTER3_SELECT1)/sizeof(mmSPI_PERFCOUNTER3_SELECT1[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0xd988, &mmSPI_PERFCOUNTER4_SELECT[0], sizeof(mmSPI_PERFCOUNTER4_SELECT)/sizeof(mmSPI_PERFCOUNTER4_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0xd989, &mmSPI_PERFCOUNTER5_SELECT[0], sizeof(mmSPI_PERFCOUNTER5_SELECT)/sizeof(mmSPI_PERFCOUNTER5_SELECT[0]), 0, 0 },
	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0xd98a, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0xd9c0, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0xd9c1, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0xd9c2, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0xd9c3, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0xd9c4, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0xd9c5, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0xd9c6, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0xd9c7, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0xd9c8, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0xd9c9, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0xd9ca, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0xd9cb, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0xd9cc, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0xd9cd, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0xd9ce, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0xd9cf, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0xd9e0, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0xd9e1, &mmSQ_PERFCOUNTER_MASK[0], sizeof(mmSQ_PERFCOUNTER_MASK)/sizeof(mmSQ_PERFCOUNTER_MASK[0]), 0, 0 },
	{ "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0xd9e2, &mmSQ_PERFCOUNTER_CTRL2[0], sizeof(mmSQ_PERFCOUNTER_CTRL2)/sizeof(mmSQ_PERFCOUNTER_CTRL2[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0xda40, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0xda41, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0xda42, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0xda43, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda44, &mmSX_PERFCOUNTER0_SELECT1[0], sizeof(mmSX_PERFCOUNTER0_SELECT1)/sizeof(mmSX_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0xda45, &mmSX_PERFCOUNTER1_SELECT1[0], sizeof(mmSX_PERFCOUNTER1_SELECT1)/sizeof(mmSX_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0xda80, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0xda81, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0xda82, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0xda83, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda84, &mmGDS_PERFCOUNTER0_SELECT1[0], sizeof(mmGDS_PERFCOUNTER0_SELECT1)/sizeof(mmGDS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdac0, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdac1, &mmTA_PERFCOUNTER0_SELECT1[0], sizeof(mmTA_PERFCOUNTER0_SELECT1)/sizeof(mmTA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdac2, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb00, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb01, &mmTD_PERFCOUNTER0_SELECT1[0], sizeof(mmTD_PERFCOUNTER0_SELECT1)/sizeof(mmTD_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb02, &mmTD_PERFCOUNTER1_SELECT[0], sizeof(mmTD_PERFCOUNTER1_SELECT)/sizeof(mmTD_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb40, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb41, &mmTCP_PERFCOUNTER0_SELECT1[0], sizeof(mmTCP_PERFCOUNTER0_SELECT1)/sizeof(mmTCP_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb42, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb43, &mmTCP_PERFCOUNTER1_SELECT1[0], sizeof(mmTCP_PERFCOUNTER1_SELECT1)/sizeof(mmTCP_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb44, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb45, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb80, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb81, &mmTCC_PERFCOUNTER0_SELECT1[0], sizeof(mmTCC_PERFCOUNTER0_SELECT1)/sizeof(mmTCC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb82, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb83, &mmTCC_PERFCOUNTER1_SELECT1[0], sizeof(mmTCC_PERFCOUNTER1_SELECT1)/sizeof(mmTCC_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb84, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb85, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb90, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb91, &mmTCA_PERFCOUNTER0_SELECT1[0], sizeof(mmTCA_PERFCOUNTER0_SELECT1)/sizeof(mmTCA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb92, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb93, &mmTCA_PERFCOUNTER1_SELECT1[0], sizeof(mmTCA_PERFCOUNTER1_SELECT1)/sizeof(mmTCA_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb94, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb95, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER0_SELECT", REG_MMIO, 0xdba0, &mmTCS_PERFCOUNTER0_SELECT[0], sizeof(mmTCS_PERFCOUNTER0_SELECT)/sizeof(mmTCS_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdba1, &mmTCS_PERFCOUNTER0_SELECT1[0], sizeof(mmTCS_PERFCOUNTER0_SELECT1)/sizeof(mmTCS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER1_SELECT", REG_MMIO, 0xdba2, &mmTCS_PERFCOUNTER1_SELECT[0], sizeof(mmTCS_PERFCOUNTER1_SELECT)/sizeof(mmTCS_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER2_SELECT", REG_MMIO, 0xdba3, &mmTCS_PERFCOUNTER2_SELECT[0], sizeof(mmTCS_PERFCOUNTER2_SELECT)/sizeof(mmTCS_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmTCS_PERFCOUNTER3_SELECT", REG_MMIO, 0xdba4, &mmTCS_PERFCOUNTER3_SELECT[0], sizeof(mmTCS_PERFCOUNTER3_SELECT)/sizeof(mmTCS_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0xdc00, &mmCB_PERFCOUNTER_FILTER[0], sizeof(mmCB_PERFCOUNTER_FILTER)/sizeof(mmCB_PERFCOUNTER_FILTER[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc01, &mmCB_PERFCOUNTER0_SELECT[0], sizeof(mmCB_PERFCOUNTER0_SELECT)/sizeof(mmCB_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc02, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc03, &mmCB_PERFCOUNTER1_SELECT[0], sizeof(mmCB_PERFCOUNTER1_SELECT)/sizeof(mmCB_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc04, &mmCB_PERFCOUNTER2_SELECT[0], sizeof(mmCB_PERFCOUNTER2_SELECT)/sizeof(mmCB_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc05, &mmCB_PERFCOUNTER3_SELECT[0], sizeof(mmCB_PERFCOUNTER3_SELECT)/sizeof(mmCB_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc40, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc41, &mmDB_PERFCOUNTER0_SELECT1[0], sizeof(mmDB_PERFCOUNTER0_SELECT1)/sizeof(mmDB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc42, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdc43, &mmDB_PERFCOUNTER1_SELECT1[0], sizeof(mmDB_PERFCOUNTER1_SELECT1)/sizeof(mmDB_PERFCOUNTER1_SELECT1[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc44, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 },
	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc46, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 },
	{ "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0xdc80, &mmRLC_SPM_PERFMON_CNTL[0], sizeof(mmRLC_SPM_PERFMON_CNTL)/sizeof(mmRLC_SPM_PERFMON_CNTL[0]), 0, 0 },
	{ "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0xdc81, &mmRLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 },
	{ "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0xdc82, &mmRLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 },
	{ "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0xdc83, &mmRLC_SPM_PERFMON_RING_SIZE[0], sizeof(mmRLC_SPM_PERFMON_RING_SIZE)/sizeof(mmRLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 },
	{ "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0xdc84, &mmRLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 },
	{ "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0xdc85, &mmRLC_SPM_SE_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_SE_MUXSEL_ADDR)/sizeof(mmRLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 },
	{ "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0xdc86, &mmRLC_SPM_SE_MUXSEL_DATA[0], sizeof(mmRLC_SPM_SE_MUXSEL_DATA)/sizeof(mmRLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 },
	{ "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc87, &mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc88, &mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc89, &mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8a, &mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8b, &mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8c, &mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8d, &mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8e, &mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc90, &mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc91, &mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc92, &mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc93, &mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc94, &mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc95, &mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc96, &mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc97, &mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc98, &mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc99, &mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9a, &mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0xdc9b, &mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 },
	{ "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0xdc9c, &mmRLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 },
	{ "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0xdc9d, &mmRLC_SPM_RING_RDPTR[0], sizeof(mmRLC_SPM_RING_RDPTR)/sizeof(mmRLC_SPM_RING_RDPTR[0]), 0, 0 },
	{ "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0xdc9e, &mmRLC_SPM_SEGMENT_THRESHOLD[0], sizeof(mmRLC_SPM_SEGMENT_THRESHOLD)/sizeof(mmRLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 },
	{ "mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9f, &mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca0, &mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca1, &mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca2, &mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0xdcc0, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdcc1, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdcc2, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG14", REG_SMC, 0xe, &ixCLIPPER_DEBUG_REG14[0], sizeof(ixCLIPPER_DEBUG_REG14)/sizeof(ixCLIPPER_DEBUG_REG14[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG14", REG_SMC, 0xe, &ixVGT_DEBUG_REG14[0], sizeof(ixVGT_DEBUG_REG14)/sizeof(ixVGT_DEBUG_REG14[0]), 0, 0 },
	{ "ixCLIPPER_DEBUG_REG15", REG_SMC, 0xf, &ixCLIPPER_DEBUG_REG15[0], sizeof(ixCLIPPER_DEBUG_REG15)/sizeof(ixCLIPPER_DEBUG_REG15[0]), 0, 0 },
	{ "ixVGT_DEBUG_REG15", REG_SMC, 0xf, &ixVGT_DEBUG_REG15[0], sizeof(ixVGT_DEBUG_REG15)/sizeof(ixVGT_DEBUG_REG15[0]), 0, 0 },
	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0xf000, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0xf001, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_RD_REG", REG_MMIO, 0xf002, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 },
	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0xf003, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 },
	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0xf004, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 },
	{ "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0xf008, &mmCGTS_CU0_SP0_CTRL_REG[0], sizeof(mmCGTS_CU0_SP0_CTRL_REG)/sizeof(mmCGTS_CU0_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0xf009, &mmCGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0xf00a, &mmCGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0xf00b, &mmCGTS_CU0_SP1_CTRL_REG[0], sizeof(mmCGTS_CU0_SP1_CTRL_REG)/sizeof(mmCGTS_CU0_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0xf00c, &mmCGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0xf00d, &mmCGTS_CU1_SP0_CTRL_REG[0], sizeof(mmCGTS_CU1_SP0_CTRL_REG)/sizeof(mmCGTS_CU1_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0xf00e, &mmCGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU1_TA_CTRL_REG", REG_MMIO, 0xf00f, &mmCGTS_CU1_TA_CTRL_REG[0], sizeof(mmCGTS_CU1_TA_CTRL_REG)/sizeof(mmCGTS_CU1_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0xf010, &mmCGTS_CU1_SP1_CTRL_REG[0], sizeof(mmCGTS_CU1_SP1_CTRL_REG)/sizeof(mmCGTS_CU1_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0xf011, &mmCGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0xf012, &mmCGTS_CU2_SP0_CTRL_REG[0], sizeof(mmCGTS_CU2_SP0_CTRL_REG)/sizeof(mmCGTS_CU2_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0xf013, &mmCGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU2_TA_CTRL_REG", REG_MMIO, 0xf014, &mmCGTS_CU2_TA_CTRL_REG[0], sizeof(mmCGTS_CU2_TA_CTRL_REG)/sizeof(mmCGTS_CU2_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0xf015, &mmCGTS_CU2_SP1_CTRL_REG[0], sizeof(mmCGTS_CU2_SP1_CTRL_REG)/sizeof(mmCGTS_CU2_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0xf016, &mmCGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0xf017, &mmCGTS_CU3_SP0_CTRL_REG[0], sizeof(mmCGTS_CU3_SP0_CTRL_REG)/sizeof(mmCGTS_CU3_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0xf018, &mmCGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU3_TA_CTRL_REG", REG_MMIO, 0xf019, &mmCGTS_CU3_TA_CTRL_REG[0], sizeof(mmCGTS_CU3_TA_CTRL_REG)/sizeof(mmCGTS_CU3_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0xf01a, &mmCGTS_CU3_SP1_CTRL_REG[0], sizeof(mmCGTS_CU3_SP1_CTRL_REG)/sizeof(mmCGTS_CU3_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0xf01b, &mmCGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0xf01c, &mmCGTS_CU4_SP0_CTRL_REG[0], sizeof(mmCGTS_CU4_SP0_CTRL_REG)/sizeof(mmCGTS_CU4_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0xf01d, &mmCGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0xf01e, &mmCGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0xf01f, &mmCGTS_CU4_SP1_CTRL_REG[0], sizeof(mmCGTS_CU4_SP1_CTRL_REG)/sizeof(mmCGTS_CU4_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0xf020, &mmCGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0xf021, &mmCGTS_CU5_SP0_CTRL_REG[0], sizeof(mmCGTS_CU5_SP0_CTRL_REG)/sizeof(mmCGTS_CU5_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0xf022, &mmCGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU5_TA_CTRL_REG", REG_MMIO, 0xf023, &mmCGTS_CU5_TA_CTRL_REG[0], sizeof(mmCGTS_CU5_TA_CTRL_REG)/sizeof(mmCGTS_CU5_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0xf024, &mmCGTS_CU5_SP1_CTRL_REG[0], sizeof(mmCGTS_CU5_SP1_CTRL_REG)/sizeof(mmCGTS_CU5_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0xf025, &mmCGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0xf026, &mmCGTS_CU6_SP0_CTRL_REG[0], sizeof(mmCGTS_CU6_SP0_CTRL_REG)/sizeof(mmCGTS_CU6_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0xf027, &mmCGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU6_TA_CTRL_REG", REG_MMIO, 0xf028, &mmCGTS_CU6_TA_CTRL_REG[0], sizeof(mmCGTS_CU6_TA_CTRL_REG)/sizeof(mmCGTS_CU6_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0xf029, &mmCGTS_CU6_SP1_CTRL_REG[0], sizeof(mmCGTS_CU6_SP1_CTRL_REG)/sizeof(mmCGTS_CU6_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0xf02a, &mmCGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0xf02b, &mmCGTS_CU7_SP0_CTRL_REG[0], sizeof(mmCGTS_CU7_SP0_CTRL_REG)/sizeof(mmCGTS_CU7_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0xf02c, &mmCGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU7_TA_CTRL_REG", REG_MMIO, 0xf02d, &mmCGTS_CU7_TA_CTRL_REG[0], sizeof(mmCGTS_CU7_TA_CTRL_REG)/sizeof(mmCGTS_CU7_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0xf02e, &mmCGTS_CU7_SP1_CTRL_REG[0], sizeof(mmCGTS_CU7_SP1_CTRL_REG)/sizeof(mmCGTS_CU7_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0xf02f, &mmCGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0xf030, &mmCGTS_CU8_SP0_CTRL_REG[0], sizeof(mmCGTS_CU8_SP0_CTRL_REG)/sizeof(mmCGTS_CU8_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0xf031, &mmCGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0xf032, &mmCGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0xf033, &mmCGTS_CU8_SP1_CTRL_REG[0], sizeof(mmCGTS_CU8_SP1_CTRL_REG)/sizeof(mmCGTS_CU8_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0xf034, &mmCGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0xf035, &mmCGTS_CU9_SP0_CTRL_REG[0], sizeof(mmCGTS_CU9_SP0_CTRL_REG)/sizeof(mmCGTS_CU9_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0xf036, &mmCGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU9_TA_CTRL_REG", REG_MMIO, 0xf037, &mmCGTS_CU9_TA_CTRL_REG[0], sizeof(mmCGTS_CU9_TA_CTRL_REG)/sizeof(mmCGTS_CU9_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0xf038, &mmCGTS_CU9_SP1_CTRL_REG[0], sizeof(mmCGTS_CU9_SP1_CTRL_REG)/sizeof(mmCGTS_CU9_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0xf039, &mmCGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0xf03a, &mmCGTS_CU10_SP0_CTRL_REG[0], sizeof(mmCGTS_CU10_SP0_CTRL_REG)/sizeof(mmCGTS_CU10_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0xf03b, &mmCGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU10_TA_CTRL_REG", REG_MMIO, 0xf03c, &mmCGTS_CU10_TA_CTRL_REG[0], sizeof(mmCGTS_CU10_TA_CTRL_REG)/sizeof(mmCGTS_CU10_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0xf03d, &mmCGTS_CU10_SP1_CTRL_REG[0], sizeof(mmCGTS_CU10_SP1_CTRL_REG)/sizeof(mmCGTS_CU10_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0xf03e, &mmCGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0xf03f, &mmCGTS_CU11_SP0_CTRL_REG[0], sizeof(mmCGTS_CU11_SP0_CTRL_REG)/sizeof(mmCGTS_CU11_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0xf040, &mmCGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU11_TA_CTRL_REG", REG_MMIO, 0xf041, &mmCGTS_CU11_TA_CTRL_REG[0], sizeof(mmCGTS_CU11_TA_CTRL_REG)/sizeof(mmCGTS_CU11_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0xf042, &mmCGTS_CU11_SP1_CTRL_REG[0], sizeof(mmCGTS_CU11_SP1_CTRL_REG)/sizeof(mmCGTS_CU11_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0xf043, &mmCGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0xf044, &mmCGTS_CU12_SP0_CTRL_REG[0], sizeof(mmCGTS_CU12_SP0_CTRL_REG)/sizeof(mmCGTS_CU12_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0xf045, &mmCGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0xf046, &mmCGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0xf047, &mmCGTS_CU12_SP1_CTRL_REG[0], sizeof(mmCGTS_CU12_SP1_CTRL_REG)/sizeof(mmCGTS_CU12_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0xf048, &mmCGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0xf049, &mmCGTS_CU13_SP0_CTRL_REG[0], sizeof(mmCGTS_CU13_SP0_CTRL_REG)/sizeof(mmCGTS_CU13_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04a, &mmCGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU13_TA_CTRL_REG", REG_MMIO, 0xf04b, &mmCGTS_CU13_TA_CTRL_REG[0], sizeof(mmCGTS_CU13_TA_CTRL_REG)/sizeof(mmCGTS_CU13_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0xf04c, &mmCGTS_CU13_SP1_CTRL_REG[0], sizeof(mmCGTS_CU13_SP1_CTRL_REG)/sizeof(mmCGTS_CU13_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0xf04d, &mmCGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0xf04e, &mmCGTS_CU14_SP0_CTRL_REG[0], sizeof(mmCGTS_CU14_SP0_CTRL_REG)/sizeof(mmCGTS_CU14_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04f, &mmCGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU14_TA_CTRL_REG", REG_MMIO, 0xf050, &mmCGTS_CU14_TA_CTRL_REG[0], sizeof(mmCGTS_CU14_TA_CTRL_REG)/sizeof(mmCGTS_CU14_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0xf051, &mmCGTS_CU14_SP1_CTRL_REG[0], sizeof(mmCGTS_CU14_SP1_CTRL_REG)/sizeof(mmCGTS_CU14_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0xf052, &mmCGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0xf053, &mmCGTS_CU15_SP0_CTRL_REG[0], sizeof(mmCGTS_CU15_SP0_CTRL_REG)/sizeof(mmCGTS_CU15_SP0_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0xf054, &mmCGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU15_TA_CTRL_REG", REG_MMIO, 0xf055, &mmCGTS_CU15_TA_CTRL_REG[0], sizeof(mmCGTS_CU15_TA_CTRL_REG)/sizeof(mmCGTS_CU15_TA_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0xf056, &mmCGTS_CU15_SP1_CTRL_REG[0], sizeof(mmCGTS_CU15_SP1_CTRL_REG)/sizeof(mmCGTS_CU15_SP1_CTRL_REG[0]), 0, 0 },
	{ "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0xf057, &mmCGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 },
	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0xf080, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0xf081, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0xf082, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0xf084, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0xf085, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0xf086, &mmCGTT_WD_CLK_CTRL[0], sizeof(mmCGTT_WD_CLK_CTRL)/sizeof(mmCGTT_WD_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0xf088, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0xf089, &mmCGTT_SC_CLK_CTRL[0], sizeof(mmCGTT_SC_CLK_CTRL)/sizeof(mmCGTT_SC_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0xf08c, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0xf08d, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 },
	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0xf08e, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 },
	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0xf08f, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 },
	{ "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0xf090, &mmSQ_LDS_CLK_CTRL[0], sizeof(mmSQ_LDS_CLK_CTRL)/sizeof(mmSQ_LDS_CLK_CTRL[0]), 0, 0 },
	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0xf091, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 },
	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0xf092, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 },
	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0xf094, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 },
	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0xf095, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 },
	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0xf096, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 },
	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0xf097, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 },
	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0xf098, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 },
	{ "mmTD_CGTT_CTRL", REG_MMIO, 0xf09c, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 },
	{ "mmTA_CGTT_CTRL", REG_MMIO, 0xf09d, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 },
	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0xf09e, &mmCGTT_TCP_CLK_CTRL[0], sizeof(mmCGTT_TCP_CLK_CTRL)/sizeof(mmCGTT_TCP_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0xf09f, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0xf0a0, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 },
	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0xf0a4, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 },
	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0xf0a8, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 },
	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ac, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 },
	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ad, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 },
	{ "mmTCS_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ae, &mmTCS_CGTT_SCLK_CTRL[0], sizeof(mmTCS_CGTT_SCLK_CTRL)/sizeof(mmTCS_CGTT_SCLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0xf0b0, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0xf0b1, &mmCGTT_CPF_CLK_CTRL[0], sizeof(mmCGTT_CPF_CLK_CTRL)/sizeof(mmCGTT_CPF_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0xf0b2, &mmCGTT_CPC_CLK_CTRL[0], sizeof(mmCGTT_CPC_CLK_CTRL)/sizeof(mmCGTT_CPC_CLK_CTRL[0]), 0, 0 },
	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0xf0b8, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 },
	{ "mmSQ_HV_VMID_CTRL", REG_MMIO, 0xf840, &mmSQ_HV_VMID_CTRL[0], sizeof(mmSQ_HV_VMID_CTRL)/sizeof(mmSQ_HV_VMID_CTRL[0]), 0, 0 },
	{ "mmGFX_PIPE_PRIORITY", REG_MMIO, 0xf87f, &mmGFX_PIPE_PRIORITY[0], sizeof(mmGFX_PIPE_PRIORITY)/sizeof(mmGFX_PIPE_PRIORITY[0]), 0, 0 },