diff options
Diffstat (limited to 'src/lib/ip/vce20_regs.i')
| -rw-r--r-- | src/lib/ip/vce20_regs.i | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/lib/ip/vce20_regs.i b/src/lib/ip/vce20_regs.i new file mode 100644 index 0000000..508739f --- /dev/null +++ b/src/lib/ip/vce20_regs.i @@ -0,0 +1,40 @@ + { "mmVCE_STATUS", REG_MMIO, 0x8001, &mmVCE_STATUS[0], sizeof(mmVCE_STATUS)/sizeof(mmVCE_STATUS[0]), 0, 0 }, + { "mmVCE_VCPU_CNTL", REG_MMIO, 0x8005, &mmVCE_VCPU_CNTL[0], sizeof(mmVCE_VCPU_CNTL)/sizeof(mmVCE_VCPU_CNTL[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_OFFSET0", REG_MMIO, 0x8009, &mmVCE_VCPU_CACHE_OFFSET0[0], sizeof(mmVCE_VCPU_CACHE_OFFSET0)/sizeof(mmVCE_VCPU_CACHE_OFFSET0[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_SIZE0", REG_MMIO, 0x800a, &mmVCE_VCPU_CACHE_SIZE0[0], sizeof(mmVCE_VCPU_CACHE_SIZE0)/sizeof(mmVCE_VCPU_CACHE_SIZE0[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_OFFSET1", REG_MMIO, 0x800b, &mmVCE_VCPU_CACHE_OFFSET1[0], sizeof(mmVCE_VCPU_CACHE_OFFSET1)/sizeof(mmVCE_VCPU_CACHE_OFFSET1[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_SIZE1", REG_MMIO, 0x800c, &mmVCE_VCPU_CACHE_SIZE1[0], sizeof(mmVCE_VCPU_CACHE_SIZE1)/sizeof(mmVCE_VCPU_CACHE_SIZE1[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_OFFSET2", REG_MMIO, 0x800d, &mmVCE_VCPU_CACHE_OFFSET2[0], sizeof(mmVCE_VCPU_CACHE_OFFSET2)/sizeof(mmVCE_VCPU_CACHE_OFFSET2[0]), 0, 0 }, + { "mmVCE_VCPU_CACHE_SIZE2", REG_MMIO, 0x800e, &mmVCE_VCPU_CACHE_SIZE2[0], sizeof(mmVCE_VCPU_CACHE_SIZE2)/sizeof(mmVCE_VCPU_CACHE_SIZE2[0]), 0, 0 }, + { "mmVCE_SOFT_RESET", REG_MMIO, 0x8048, &mmVCE_SOFT_RESET[0], sizeof(mmVCE_SOFT_RESET)/sizeof(mmVCE_SOFT_RESET[0]), 0, 0 }, + { "mmVCE_RB_BASE_LO2", REG_MMIO, 0x805b, &mmVCE_RB_BASE_LO2[0], sizeof(mmVCE_RB_BASE_LO2)/sizeof(mmVCE_RB_BASE_LO2[0]), 0, 0 }, + { "mmVCE_RB_BASE_HI2", REG_MMIO, 0x805c, &mmVCE_RB_BASE_HI2[0], sizeof(mmVCE_RB_BASE_HI2)/sizeof(mmVCE_RB_BASE_HI2[0]), 0, 0 }, + { "mmVCE_RB_SIZE2", REG_MMIO, 0x805d, &mmVCE_RB_SIZE2[0], sizeof(mmVCE_RB_SIZE2)/sizeof(mmVCE_RB_SIZE2[0]), 0, 0 }, + { "mmVCE_RB_RPTR2", REG_MMIO, 0x805e, &mmVCE_RB_RPTR2[0], sizeof(mmVCE_RB_RPTR2)/sizeof(mmVCE_RB_RPTR2[0]), 0, 0 }, + { "mmVCE_RB_WPTR2", REG_MMIO, 0x805f, &mmVCE_RB_WPTR2[0], sizeof(mmVCE_RB_WPTR2)/sizeof(mmVCE_RB_WPTR2[0]), 0, 0 }, + { "mmVCE_RB_BASE_LO", REG_MMIO, 0x8060, &mmVCE_RB_BASE_LO[0], sizeof(mmVCE_RB_BASE_LO)/sizeof(mmVCE_RB_BASE_LO[0]), 0, 0 }, + { "mmVCE_RB_BASE_HI", REG_MMIO, 0x8061, &mmVCE_RB_BASE_HI[0], sizeof(mmVCE_RB_BASE_HI)/sizeof(mmVCE_RB_BASE_HI[0]), 0, 0 }, + { "mmVCE_RB_SIZE", REG_MMIO, 0x8062, &mmVCE_RB_SIZE[0], sizeof(mmVCE_RB_SIZE)/sizeof(mmVCE_RB_SIZE[0]), 0, 0 }, + { "mmVCE_RB_RPTR", REG_MMIO, 0x8063, &mmVCE_RB_RPTR[0], sizeof(mmVCE_RB_RPTR)/sizeof(mmVCE_RB_RPTR[0]), 0, 0 }, + { "mmVCE_RB_WPTR", REG_MMIO, 0x8064, &mmVCE_RB_WPTR[0], sizeof(mmVCE_RB_WPTR)/sizeof(mmVCE_RB_WPTR[0]), 0, 0 }, + { "mmVCE_RB_ARB_CTRL", REG_MMIO, 0x809f, NULL, 0, 0, 0 }, + { "mmVCE_CLOCK_GATING_A", REG_MMIO, 0x80be, NULL, 0, 0, 0 }, + { "mmVCE_CLOCK_GATING_B", REG_MMIO, 0x80bf, NULL, 0, 0, 0 }, + { "mmVCE_CGTT_CLK_OVERRIDE", REG_MMIO, 0x81e8, NULL, 0, 0, 0 }, + { "mmVCE_UENC_CLOCK_GATING", REG_MMIO, 0x81ef, NULL, 0, 0, 0 }, + { "mmVCE_UENC_REG_CLOCK_GATING", REG_MMIO, 0x81f0, NULL, 0, 0, 0 }, + { "mmVCE_UENC_DMA_DCLK_CTRL", REG_MMIO, 0x8390, &mmVCE_UENC_DMA_DCLK_CTRL[0], sizeof(mmVCE_UENC_DMA_DCLK_CTRL)/sizeof(mmVCE_UENC_DMA_DCLK_CTRL[0]), 0, 0 }, + { "mmVCE_SYS_INT_EN", REG_MMIO, 0x84c0, &mmVCE_SYS_INT_EN[0], sizeof(mmVCE_SYS_INT_EN)/sizeof(mmVCE_SYS_INT_EN[0]), 0, 0 }, + { "mmVCE_SYS_INT_STATUS", REG_MMIO, 0x84c1, &mmVCE_SYS_INT_STATUS[0], sizeof(mmVCE_SYS_INT_STATUS)/sizeof(mmVCE_SYS_INT_STATUS[0]), 0, 0 }, + { "mmVCE_SYS_INT_ACK", REG_MMIO, 0x84c1, &mmVCE_SYS_INT_ACK[0], sizeof(mmVCE_SYS_INT_ACK)/sizeof(mmVCE_SYS_INT_ACK[0]), 0, 0 }, + { "mmVCE_LMI_VCPU_CACHE_40BIT_BAR", REG_MMIO, 0x8517, &mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0], sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR)/sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0]), 0, 0 }, + { "mmVCE_LMI_CTRL2", REG_MMIO, 0x851d, &mmVCE_LMI_CTRL2[0], sizeof(mmVCE_LMI_CTRL2)/sizeof(mmVCE_LMI_CTRL2[0]), 0, 0 }, + { "mmVCE_LMI_SWAP_CNTL3", REG_MMIO, 0x851e, &mmVCE_LMI_SWAP_CNTL3[0], sizeof(mmVCE_LMI_SWAP_CNTL3)/sizeof(mmVCE_LMI_SWAP_CNTL3[0]), 0, 0 }, + { "mmVCE_LMI_CTRL", REG_MMIO, 0x8526, &mmVCE_LMI_CTRL[0], sizeof(mmVCE_LMI_CTRL)/sizeof(mmVCE_LMI_CTRL[0]), 0, 0 }, + { "mmVCE_LMI_STATUS", REG_MMIO, 0x8527, NULL, 0, 0, 0 }, + { "mmVCE_LMI_VM_CTRL", REG_MMIO, 0x8528, NULL, 0, 0, 0 }, + { "mmVCE_LMI_SWAP_CNTL", REG_MMIO, 0x852d, &mmVCE_LMI_SWAP_CNTL[0], sizeof(mmVCE_LMI_SWAP_CNTL)/sizeof(mmVCE_LMI_SWAP_CNTL[0]), 0, 0 }, + { "mmVCE_LMI_SWAP_CNTL1", REG_MMIO, 0x852e, &mmVCE_LMI_SWAP_CNTL1[0], sizeof(mmVCE_LMI_SWAP_CNTL1)/sizeof(mmVCE_LMI_SWAP_CNTL1[0]), 0, 0 }, + { "mmVCE_LMI_SWAP_CNTL2", REG_MMIO, 0x8533, &mmVCE_LMI_SWAP_CNTL2[0], sizeof(mmVCE_LMI_SWAP_CNTL2)/sizeof(mmVCE_LMI_SWAP_CNTL2[0]), 0, 0 }, + { "mmVCE_LMI_MISC_CTRL", REG_MMIO, 0x8535, NULL, 0, 0, 0 }, + { "mmVCE_LMI_CACHE_CTRL", REG_MMIO, 0x853d, &mmVCE_LMI_CACHE_CTRL[0], sizeof(mmVCE_LMI_CACHE_CTRL)/sizeof(mmVCE_LMI_CACHE_CTRL[0]), 0, 0 }, |