diff options
Diffstat (limited to 'src/lib/ip/uvd42_regs.i')
| -rw-r--r-- | src/lib/ip/uvd42_regs.i | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/lib/ip/uvd42_regs.i b/src/lib/ip/uvd42_regs.i new file mode 100644 index 0000000..82ad30c --- /dev/null +++ b/src/lib/ip/uvd42_regs.i @@ -0,0 +1,68 @@ + { "ixUVD_MIF_RECON1_ADDR_CONFIG", REG_SMC, 0x114, &ixUVD_MIF_RECON1_ADDR_CONFIG[0], sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG)/sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x38f8, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 }, + { "mmUVD_PGFSM_READ_TILE1", REG_MMIO, 0x38fa, &mmUVD_PGFSM_READ_TILE1[0], sizeof(mmUVD_PGFSM_READ_TILE1)/sizeof(mmUVD_PGFSM_READ_TILE1[0]), 0, 0 }, + { "mmUVD_PGFSM_READ_TILE2", REG_MMIO, 0x38fb, &mmUVD_PGFSM_READ_TILE2[0], sizeof(mmUVD_PGFSM_READ_TILE2)/sizeof(mmUVD_PGFSM_READ_TILE2[0]), 0, 0 }, + { "mmUVD_POWER_STATUS", REG_MMIO, 0x38fc, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 }, + { "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x3bc0, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 }, + { "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x3bc1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 }, + { "mmUVD_SEMA_CMD", REG_MMIO, 0x3bc2, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x3bc3, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x3bc4, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 }, + { "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x3bc5, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 }, + { "mmUVD_ENGINE_CNTL", REG_MMIO, 0x3bc6, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 }, + { "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x3bd3, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x3bd4, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x3bd5, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 }, + { "mmUVD_NO_OP", REG_MMIO, 0x3bff, NULL, 0, 0, 0 }, + { "mmUVD_SEMA_CNTL", REG_MMIO, 0x3d00, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 }, + { "mmUVD_LMI_EXT40_ADDR", REG_MMIO, 0x3d26, &mmUVD_LMI_EXT40_ADDR[0], sizeof(mmUVD_LMI_EXT40_ADDR)/sizeof(mmUVD_LMI_EXT40_ADDR[0]), 0, 0 }, + { "mmUVD_CTX_INDEX", REG_MMIO, 0x3d28, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 }, + { "mmUVD_CTX_DATA", REG_MMIO, 0x3d29, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 }, + { "mmUVD_CGC_GATE", REG_MMIO, 0x3d2a, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 }, + { "mmUVD_CGC_STATUS", REG_MMIO, 0x3d2b, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 }, + { "mmUVD_CGC_CTRL", REG_MMIO, 0x3d2c, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 }, + { "mmUVD_CGC_UDEC_STATUS", REG_MMIO, 0x3d2d, &mmUVD_CGC_UDEC_STATUS[0], sizeof(mmUVD_CGC_UDEC_STATUS)/sizeof(mmUVD_CGC_UDEC_STATUS[0]), 0, 0 }, + { "mmUVD_LMI_CTRL2", REG_MMIO, 0x3d3d, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 }, + { "mmUVD_MASTINT_EN", REG_MMIO, 0x3d40, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 }, + { "mmUVD_LMI_ADDR_EXT", REG_MMIO, 0x3d65, &mmUVD_LMI_ADDR_EXT[0], sizeof(mmUVD_LMI_ADDR_EXT)/sizeof(mmUVD_LMI_ADDR_EXT[0]), 0, 0 }, + { "mmUVD_LMI_CTRL", REG_MMIO, 0x3d66, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 }, + { "mmUVD_LMI_STATUS", REG_MMIO, 0x3d67, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 }, + { "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x3d6d, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 }, + { "mmUVD_MP_SWAP_CNTL", REG_MMIO, 0x3d6f, &mmUVD_MP_SWAP_CNTL[0], sizeof(mmUVD_MP_SWAP_CNTL)/sizeof(mmUVD_MP_SWAP_CNTL[0]), 0, 0 }, + { "mmUVD_MPC_CNTL", REG_MMIO, 0x3d77, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x3d79, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x3d7a, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x3d7b, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x3d7c, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 }, + { "mmUVD_MPC_SET_MUX", REG_MMIO, 0x3d7d, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 }, + { "mmUVD_MPC_SET_ALU", REG_MMIO, 0x3d7e, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x3d82, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x3d83, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x3d84, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x3d85, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x3d86, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 }, + { "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x3d87, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 }, + { "mmUVD_VCPU_CNTL", REG_MMIO, 0x3d98, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 }, + { "mmUVD_SOFT_RESET", REG_MMIO, 0x3da0, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 }, + { "mmUVD_RBC_IB_BASE", REG_MMIO, 0x3da1, &mmUVD_RBC_IB_BASE[0], sizeof(mmUVD_RBC_IB_BASE)/sizeof(mmUVD_RBC_IB_BASE[0]), 0, 0 }, + { "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x3da2, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 }, + { "mmUVD_RBC_RB_BASE", REG_MMIO, 0x3da3, &mmUVD_RBC_RB_BASE[0], sizeof(mmUVD_RBC_RB_BASE)/sizeof(mmUVD_RBC_RB_BASE[0]), 0, 0 }, + { "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x3da4, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 }, + { "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x3da5, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 }, + { "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x3da6, NULL, 0, 0, 0 }, + { "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x3da9, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 }, + { "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x3daa, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 }, + { "mmUVD_STATUS", REG_MMIO, 0x3daf, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 }, + { "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x3db0, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 }, + { "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x3db2, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db3, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 }, + { "mmUVD_CONTEXT_ID", REG_MMIO, 0x3dbd, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 }, + { "mmUVD_RBC_IB_SIZE_UPDATE", REG_MMIO, 0x3df1, NULL, 0, 0, 0 }, + { "ixUVD_MIF_CURR_ADDR_CONFIG", REG_SMC, 0x48, &ixUVD_MIF_CURR_ADDR_CONFIG[0], sizeof(ixUVD_MIF_CURR_ADDR_CONFIG)/sizeof(ixUVD_MIF_CURR_ADDR_CONFIG[0]), 0, 0 }, + { "ixUVD_MIF_REF_ADDR_CONFIG", REG_SMC, 0x4c, &ixUVD_MIF_REF_ADDR_CONFIG[0], sizeof(ixUVD_MIF_REF_ADDR_CONFIG)/sizeof(ixUVD_MIF_REF_ADDR_CONFIG[0]), 0, 0 }, + { "ixUVD_LMI_CACHE_CTRL", REG_SMC, 0x9b, &ixUVD_LMI_CACHE_CTRL[0], sizeof(ixUVD_LMI_CACHE_CTRL)/sizeof(ixUVD_LMI_CACHE_CTRL[0]), 0, 0 }, + { "ixUVD_LMI_SWAP_CNTL2", REG_SMC, 0xaa, &ixUVD_LMI_SWAP_CNTL2[0], sizeof(ixUVD_LMI_SWAP_CNTL2)/sizeof(ixUVD_LMI_SWAP_CNTL2[0]), 0, 0 }, + { "ixUVD_LMI_ADDR_EXT2", REG_SMC, 0xab, &ixUVD_LMI_ADDR_EXT2[0], sizeof(ixUVD_LMI_ADDR_EXT2)/sizeof(ixUVD_LMI_ADDR_EXT2[0]), 0, 0 }, + { "ixUVD_CGC_MEM_CTRL", REG_SMC, 0xc0, &ixUVD_CGC_MEM_CTRL[0], sizeof(ixUVD_CGC_MEM_CTRL)/sizeof(ixUVD_CGC_MEM_CTRL[0]), 0, 0 }, + { "ixUVD_CGC_CTRL2", REG_SMC, 0xc1, &ixUVD_CGC_CTRL2[0], sizeof(ixUVD_CGC_CTRL2)/sizeof(ixUVD_CGC_CTRL2[0]), 0, 0 }, |