diff options
Diffstat (limited to 'src/lib/ip/smu60_regs.i')
| -rw-r--r-- | src/lib/ip/smu60_regs.i | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/src/lib/ip/smu60_regs.i b/src/lib/ip/smu60_regs.i new file mode 100644 index 0000000..abc4922 --- /dev/null +++ b/src/lib/ip/smu60_regs.i @@ -0,0 +1,119 @@ + { "mmSMC_IND_INDEX_0", REG_MMIO, 0x0080, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 }, + { "mmSMC_IND_DATA_0", REG_MMIO, 0x0081, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 }, + { "mmSMC_IND_INDEX_1", REG_MMIO, 0x0082, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 }, + { "mmSMC_IND_DATA_1", REG_MMIO, 0x0083, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 }, + { "mmSMC_IND_INDEX_2", REG_MMIO, 0x0084, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 }, + { "mmSMC_IND_DATA_2", REG_MMIO, 0x0085, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 }, + { "mmSMC_IND_INDEX_3", REG_MMIO, 0x0086, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 }, + { "mmSMC_IND_DATA_3", REG_MMIO, 0x0087, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 }, + { "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x008A, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 }, + { "mmSMC_MESSAGE_0", REG_MMIO, 0x008B, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 }, + { "mmSMC_RESP_0", REG_MMIO, 0x008C, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 }, + { "mmSMC_MESSAGE_1", REG_MMIO, 0x008D, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 }, + { "mmSMC_RESP_1", REG_MMIO, 0x008E, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 }, + { "mmSMC_MESSAGE_2", REG_MMIO, 0x008F, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 }, + { "mmSMC_RESP_2", REG_MMIO, 0x0090, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 }, + { "ixLCAC_MC0_CNTL", REG_SMC, 0x011C, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 }, + { "ixLCAC_MC0_OVR_SEL", REG_SMC, 0x011D, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC0_OVR_VAL", REG_SMC, 0x011E, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 }, + { "ixLCAC_MC1_CNTL", REG_SMC, 0x011F, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 }, + { "ixLCAC_MC1_OVR_SEL", REG_SMC, 0x0120, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC1_OVR_VAL", REG_SMC, 0x0121, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 }, + { "ixLCAC_MC2_CNTL", REG_SMC, 0x0122, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 }, + { "ixLCAC_MC2_OVR_SEL", REG_SMC, 0x0123, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC2_OVR_VAL", REG_SMC, 0x0124, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 }, + { "ixLCAC_MC3_CNTL", REG_SMC, 0x0125, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 }, + { "ixLCAC_MC3_OVR_SEL", REG_SMC, 0x0126, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC3_OVR_VAL", REG_SMC, 0x0127, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 }, + { "ixLCAC_MC4_CNTL", REG_SMC, 0x0128, &ixLCAC_MC4_CNTL[0], sizeof(ixLCAC_MC4_CNTL)/sizeof(ixLCAC_MC4_CNTL[0]), 0, 0 }, + { "ixLCAC_MC4_OVR_SEL", REG_SMC, 0x0129, &ixLCAC_MC4_OVR_SEL[0], sizeof(ixLCAC_MC4_OVR_SEL)/sizeof(ixLCAC_MC4_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC4_OVR_VAL", REG_SMC, 0x012A, &ixLCAC_MC4_OVR_VAL[0], sizeof(ixLCAC_MC4_OVR_VAL)/sizeof(ixLCAC_MC4_OVR_VAL[0]), 0, 0 }, + { "ixLCAC_MC5_CNTL", REG_SMC, 0x012B, &ixLCAC_MC5_CNTL[0], sizeof(ixLCAC_MC5_CNTL)/sizeof(ixLCAC_MC5_CNTL[0]), 0, 0 }, + { "ixLCAC_MC5_OVR_SEL", REG_SMC, 0x012C, &ixLCAC_MC5_OVR_SEL[0], sizeof(ixLCAC_MC5_OVR_SEL)/sizeof(ixLCAC_MC5_OVR_SEL[0]), 0, 0 }, + { "ixLCAC_MC5_OVR_VAL", REG_SMC, 0x012D, &ixLCAC_MC5_OVR_VAL[0], sizeof(ixLCAC_MC5_OVR_VAL)/sizeof(ixLCAC_MC5_OVR_VAL[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0x0300, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0x0301, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0x0302, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0x0303, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0x0304, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0x0305, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0x0306, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0x0307, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0x0308, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0x0309, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0x030A, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0x030B, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0x030C, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0x030D, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0x030E, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0x030F, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0x0310, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0x0311, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0x0312, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0x0313, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0x0314, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0x0315, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0x0316, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0x0317, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0x0318, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0x0319, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0x031A, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0x031B, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0x031C, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0x031D, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0x031E, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0x031F, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL0_DATA", REG_SMC, 0x0320, &ixTHM_TMON1_RDIL0_DATA[0], sizeof(ixTHM_TMON1_RDIL0_DATA)/sizeof(ixTHM_TMON1_RDIL0_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL1_DATA", REG_SMC, 0x0321, &ixTHM_TMON1_RDIL1_DATA[0], sizeof(ixTHM_TMON1_RDIL1_DATA)/sizeof(ixTHM_TMON1_RDIL1_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL2_DATA", REG_SMC, 0x0322, &ixTHM_TMON1_RDIL2_DATA[0], sizeof(ixTHM_TMON1_RDIL2_DATA)/sizeof(ixTHM_TMON1_RDIL2_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL3_DATA", REG_SMC, 0x0323, &ixTHM_TMON1_RDIL3_DATA[0], sizeof(ixTHM_TMON1_RDIL3_DATA)/sizeof(ixTHM_TMON1_RDIL3_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL4_DATA", REG_SMC, 0x0324, &ixTHM_TMON1_RDIL4_DATA[0], sizeof(ixTHM_TMON1_RDIL4_DATA)/sizeof(ixTHM_TMON1_RDIL4_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL5_DATA", REG_SMC, 0x0325, &ixTHM_TMON1_RDIL5_DATA[0], sizeof(ixTHM_TMON1_RDIL5_DATA)/sizeof(ixTHM_TMON1_RDIL5_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL6_DATA", REG_SMC, 0x0326, &ixTHM_TMON1_RDIL6_DATA[0], sizeof(ixTHM_TMON1_RDIL6_DATA)/sizeof(ixTHM_TMON1_RDIL6_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL7_DATA", REG_SMC, 0x0327, &ixTHM_TMON1_RDIL7_DATA[0], sizeof(ixTHM_TMON1_RDIL7_DATA)/sizeof(ixTHM_TMON1_RDIL7_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL8_DATA", REG_SMC, 0x0328, &ixTHM_TMON1_RDIL8_DATA[0], sizeof(ixTHM_TMON1_RDIL8_DATA)/sizeof(ixTHM_TMON1_RDIL8_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL9_DATA", REG_SMC, 0x0329, &ixTHM_TMON1_RDIL9_DATA[0], sizeof(ixTHM_TMON1_RDIL9_DATA)/sizeof(ixTHM_TMON1_RDIL9_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL10_DATA", REG_SMC, 0x032A, &ixTHM_TMON1_RDIL10_DATA[0], sizeof(ixTHM_TMON1_RDIL10_DATA)/sizeof(ixTHM_TMON1_RDIL10_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL11_DATA", REG_SMC, 0x032B, &ixTHM_TMON1_RDIL11_DATA[0], sizeof(ixTHM_TMON1_RDIL11_DATA)/sizeof(ixTHM_TMON1_RDIL11_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL12_DATA", REG_SMC, 0x032C, &ixTHM_TMON1_RDIL12_DATA[0], sizeof(ixTHM_TMON1_RDIL12_DATA)/sizeof(ixTHM_TMON1_RDIL12_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL13_DATA", REG_SMC, 0x032D, &ixTHM_TMON1_RDIL13_DATA[0], sizeof(ixTHM_TMON1_RDIL13_DATA)/sizeof(ixTHM_TMON1_RDIL13_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL14_DATA", REG_SMC, 0x032E, &ixTHM_TMON1_RDIL14_DATA[0], sizeof(ixTHM_TMON1_RDIL14_DATA)/sizeof(ixTHM_TMON1_RDIL14_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIL15_DATA", REG_SMC, 0x032F, &ixTHM_TMON1_RDIL15_DATA[0], sizeof(ixTHM_TMON1_RDIL15_DATA)/sizeof(ixTHM_TMON1_RDIL15_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR0_DATA", REG_SMC, 0x0330, &ixTHM_TMON1_RDIR0_DATA[0], sizeof(ixTHM_TMON1_RDIR0_DATA)/sizeof(ixTHM_TMON1_RDIR0_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR1_DATA", REG_SMC, 0x0331, &ixTHM_TMON1_RDIR1_DATA[0], sizeof(ixTHM_TMON1_RDIR1_DATA)/sizeof(ixTHM_TMON1_RDIR1_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR2_DATA", REG_SMC, 0x0332, &ixTHM_TMON1_RDIR2_DATA[0], sizeof(ixTHM_TMON1_RDIR2_DATA)/sizeof(ixTHM_TMON1_RDIR2_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR3_DATA", REG_SMC, 0x0333, &ixTHM_TMON1_RDIR3_DATA[0], sizeof(ixTHM_TMON1_RDIR3_DATA)/sizeof(ixTHM_TMON1_RDIR3_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR4_DATA", REG_SMC, 0x0334, &ixTHM_TMON1_RDIR4_DATA[0], sizeof(ixTHM_TMON1_RDIR4_DATA)/sizeof(ixTHM_TMON1_RDIR4_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR5_DATA", REG_SMC, 0x0335, &ixTHM_TMON1_RDIR5_DATA[0], sizeof(ixTHM_TMON1_RDIR5_DATA)/sizeof(ixTHM_TMON1_RDIR5_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR6_DATA", REG_SMC, 0x0336, &ixTHM_TMON1_RDIR6_DATA[0], sizeof(ixTHM_TMON1_RDIR6_DATA)/sizeof(ixTHM_TMON1_RDIR6_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR7_DATA", REG_SMC, 0x0337, &ixTHM_TMON1_RDIR7_DATA[0], sizeof(ixTHM_TMON1_RDIR7_DATA)/sizeof(ixTHM_TMON1_RDIR7_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR8_DATA", REG_SMC, 0x0338, &ixTHM_TMON1_RDIR8_DATA[0], sizeof(ixTHM_TMON1_RDIR8_DATA)/sizeof(ixTHM_TMON1_RDIR8_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR9_DATA", REG_SMC, 0x0339, &ixTHM_TMON1_RDIR9_DATA[0], sizeof(ixTHM_TMON1_RDIR9_DATA)/sizeof(ixTHM_TMON1_RDIR9_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR10_DATA", REG_SMC, 0x033A, &ixTHM_TMON1_RDIR10_DATA[0], sizeof(ixTHM_TMON1_RDIR10_DATA)/sizeof(ixTHM_TMON1_RDIR10_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR11_DATA", REG_SMC, 0x033B, &ixTHM_TMON1_RDIR11_DATA[0], sizeof(ixTHM_TMON1_RDIR11_DATA)/sizeof(ixTHM_TMON1_RDIR11_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR12_DATA", REG_SMC, 0x033C, &ixTHM_TMON1_RDIR12_DATA[0], sizeof(ixTHM_TMON1_RDIR12_DATA)/sizeof(ixTHM_TMON1_RDIR12_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR13_DATA", REG_SMC, 0x033D, &ixTHM_TMON1_RDIR13_DATA[0], sizeof(ixTHM_TMON1_RDIR13_DATA)/sizeof(ixTHM_TMON1_RDIR13_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR14_DATA", REG_SMC, 0x033E, &ixTHM_TMON1_RDIR14_DATA[0], sizeof(ixTHM_TMON1_RDIR14_DATA)/sizeof(ixTHM_TMON1_RDIR14_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_RDIR15_DATA", REG_SMC, 0x033F, &ixTHM_TMON1_RDIR15_DATA[0], sizeof(ixTHM_TMON1_RDIR15_DATA)/sizeof(ixTHM_TMON1_RDIR15_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_INT_DATA", REG_SMC, 0x0380, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 }, + { "ixTHM_TMON1_INT_DATA", REG_SMC, 0x0381, &ixTHM_TMON1_INT_DATA[0], sizeof(ixTHM_TMON1_INT_DATA)/sizeof(ixTHM_TMON1_INT_DATA[0]), 0, 0 }, + { "ixTHM_TMON0_DEBUG", REG_SMC, 0x03F0, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 }, + { "ixTHM_TMON1_DEBUG", REG_SMC, 0x03F1, &ixTHM_TMON1_DEBUG[0], sizeof(ixTHM_TMON1_DEBUG)/sizeof(ixTHM_TMON1_DEBUG[0]), 0, 0 }, + { "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x05E4, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 }, + { "mmGPIOPAD_STRENGTH", REG_MMIO, 0x05E5, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 }, + { "mmGPIOPAD_MASK", REG_MMIO, 0x05E6, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 }, + { "mmGPIOPAD_A", REG_MMIO, 0x05E7, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 }, + { "mmGPIOPAD_EN", REG_MMIO, 0x05E8, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 }, + { "mmGPIOPAD_Y", REG_MMIO, 0x05E9, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 }, + { "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x05EA, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 }, + { "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x05EB, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 }, + { "mmGPIOPAD_INT_STAT", REG_MMIO, 0x05EC, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 }, + { "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x05ED, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 }, + { "mmGPIOPAD_INT_EN", REG_MMIO, 0x05EE, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 }, + { "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x05EF, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 }, + { "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x05F0, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 }, + { "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x05F1, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 }, + { "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x05F2, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 }, + { "mmGPIOPAD_PU_EN", REG_MMIO, 0x05F3, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 }, + { "mmGPIOPAD_PD_EN", REG_MMIO, 0x05F4, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 }, + { "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 }, |