diff options
Diffstat (limited to 'src/lib/ip/gmc70_regs.i')
| -rw-r--r-- | src/lib/ip/gmc70_regs.i | 629 |
1 files changed, 629 insertions, 0 deletions
diff --git a/src/lib/ip/gmc70_regs.i b/src/lib/ip/gmc70_regs.i new file mode 100644 index 0000000..bc1753b --- /dev/null +++ b/src/lib/ip/gmc70_regs.i @@ -0,0 +1,629 @@ + { "mmVM_L2_CNTL", REG_MMIO, 0x500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 }, + { "mmVM_L2_CNTL2", REG_MMIO, 0x501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 }, + { "mmVM_L2_CNTL3", REG_MMIO, 0x502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 }, + { "mmVM_L2_STATUS", REG_MMIO, 0x503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 }, + { "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 }, + { "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x50c, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 }, + { "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x50d, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 }, + { "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50e, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50f, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x51e, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 }, + { "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x51f, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 }, + { "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x52c, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x52d, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x52e, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x52f, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 }, + { "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 }, + { "mmVM_PRT_CNTL", REG_MMIO, 0x534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 }, + { "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 }, + { "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 }, + { "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 }, + { "mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x538, &mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 }, + { "mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x539, &mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 }, + { "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53e, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53f, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 }, + { "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x54e, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x54f, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x55f, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 }, + { "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 }, + { "mmVM_DEBUG", REG_MMIO, 0x56f, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 }, + { "mmVM_L2_CG", REG_MMIO, 0x570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 }, + { "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 }, + { "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 }, + { "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER_LO", REG_MMIO, 0x7a0, &mmMC_CITF_PERFCOUNTER_LO[0], sizeof(mmMC_CITF_PERFCOUNTER_LO)/sizeof(mmMC_CITF_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER_LO", REG_MMIO, 0x7a1, &mmMC_HUB_PERFCOUNTER_LO[0], sizeof(mmMC_HUB_PERFCOUNTER_LO)/sizeof(mmMC_HUB_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER_LO", REG_MMIO, 0x7a2, &mmMC_RPB_PERFCOUNTER_LO[0], sizeof(mmMC_RPB_PERFCOUNTER_LO)/sizeof(mmMC_RPB_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER_LO", REG_MMIO, 0x7a3, &mmMC_MCBVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCBVM_PERFCOUNTER_LO)/sizeof(mmMC_MCBVM_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER_LO", REG_MMIO, 0x7a4, &mmMC_MCDVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCDVM_PERFCOUNTER_LO)/sizeof(mmMC_MCDVM_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x7a5, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER_LO", REG_MMIO, 0x7a6, &mmMC_ARB_PERFCOUNTER_LO[0], sizeof(mmMC_ARB_PERFCOUNTER_LO)/sizeof(mmMC_ARB_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmATC_PERFCOUNTER_LO", REG_MMIO, 0x7a7, &mmATC_PERFCOUNTER_LO[0], sizeof(mmATC_PERFCOUNTER_LO)/sizeof(mmATC_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER_HI", REG_MMIO, 0x7a8, &mmMC_CITF_PERFCOUNTER_HI[0], sizeof(mmMC_CITF_PERFCOUNTER_HI)/sizeof(mmMC_CITF_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER_HI", REG_MMIO, 0x7a9, &mmMC_HUB_PERFCOUNTER_HI[0], sizeof(mmMC_HUB_PERFCOUNTER_HI)/sizeof(mmMC_HUB_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER_HI", REG_MMIO, 0x7aa, &mmMC_MCBVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCBVM_PERFCOUNTER_HI)/sizeof(mmMC_MCBVM_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER_HI", REG_MMIO, 0x7ab, &mmMC_MCDVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCDVM_PERFCOUNTER_HI)/sizeof(mmMC_MCDVM_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER_HI", REG_MMIO, 0x7ac, &mmMC_RPB_PERFCOUNTER_HI[0], sizeof(mmMC_RPB_PERFCOUNTER_HI)/sizeof(mmMC_RPB_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x7ad, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER_HI", REG_MMIO, 0x7ae, &mmMC_ARB_PERFCOUNTER_HI[0], sizeof(mmMC_ARB_PERFCOUNTER_HI)/sizeof(mmMC_ARB_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmATC_PERFCOUNTER_HI", REG_MMIO, 0x7af, &mmATC_PERFCOUNTER_HI[0], sizeof(mmATC_PERFCOUNTER_HI)/sizeof(mmATC_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER0_CFG", REG_MMIO, 0x7b0, &mmMC_CITF_PERFCOUNTER0_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER0_CFG)/sizeof(mmMC_CITF_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER1_CFG", REG_MMIO, 0x7b1, &mmMC_CITF_PERFCOUNTER1_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER1_CFG)/sizeof(mmMC_CITF_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER2_CFG", REG_MMIO, 0x7b2, &mmMC_CITF_PERFCOUNTER2_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER2_CFG)/sizeof(mmMC_CITF_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER3_CFG", REG_MMIO, 0x7b3, &mmMC_CITF_PERFCOUNTER3_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER3_CFG)/sizeof(mmMC_CITF_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b4, &mmMC_HUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER0_CFG)/sizeof(mmMC_HUB_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b5, &mmMC_HUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER1_CFG)/sizeof(mmMC_HUB_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER2_CFG", REG_MMIO, 0x7b6, &mmMC_HUB_PERFCOUNTER2_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER2_CFG)/sizeof(mmMC_HUB_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER3_CFG", REG_MMIO, 0x7b7, &mmMC_HUB_PERFCOUNTER3_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER3_CFG)/sizeof(mmMC_HUB_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b8, &mmMC_RPB_PERFCOUNTER0_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER0_CFG)/sizeof(mmMC_RPB_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b9, &mmMC_RPB_PERFCOUNTER1_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER1_CFG)/sizeof(mmMC_RPB_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER2_CFG", REG_MMIO, 0x7ba, &mmMC_RPB_PERFCOUNTER2_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER2_CFG)/sizeof(mmMC_RPB_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bb, &mmMC_RPB_PERFCOUNTER3_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER3_CFG)/sizeof(mmMC_RPB_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER0_CFG", REG_MMIO, 0x7bc, &mmMC_ARB_PERFCOUNTER0_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER0_CFG)/sizeof(mmMC_ARB_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER1_CFG", REG_MMIO, 0x7bd, &mmMC_ARB_PERFCOUNTER1_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER1_CFG)/sizeof(mmMC_ARB_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER2_CFG", REG_MMIO, 0x7be, &mmMC_ARB_PERFCOUNTER2_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER2_CFG)/sizeof(mmMC_ARB_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bf, &mmMC_ARB_PERFCOUNTER3_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER3_CFG)/sizeof(mmMC_ARB_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c0, &mmMC_MCBVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c1, &mmMC_MCBVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c2, &mmMC_MCBVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c3, &mmMC_MCBVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c4, &mmMC_MCDVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c5, &mmMC_MCDVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c6, &mmMC_MCDVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c7, &mmMC_MCDVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7c8, &mmATC_PERFCOUNTER0_CFG[0], sizeof(mmATC_PERFCOUNTER0_CFG)/sizeof(mmATC_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7c9, &mmATC_PERFCOUNTER1_CFG[0], sizeof(mmATC_PERFCOUNTER1_CFG)/sizeof(mmATC_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmATC_PERFCOUNTER2_CFG", REG_MMIO, 0x7ca, &mmATC_PERFCOUNTER2_CFG[0], sizeof(mmATC_PERFCOUNTER2_CFG)/sizeof(mmATC_PERFCOUNTER2_CFG[0]), 0, 0 }, + { "mmATC_PERFCOUNTER3_CFG", REG_MMIO, 0x7cb, &mmATC_PERFCOUNTER3_CFG[0], sizeof(mmATC_PERFCOUNTER3_CFG)/sizeof(mmATC_PERFCOUNTER3_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x7cc, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x7cd, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmMC_CITF_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7ce, &mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_HUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7cf, &mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_RPB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d0, &mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d1, &mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d2, &mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d3, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_ARB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d4, &mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d5, &mmATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmCHUB_ATC_PERFCOUNTER_LO", REG_MMIO, 0x7d6, &mmCHUB_ATC_PERFCOUNTER_LO[0], sizeof(mmCHUB_ATC_PERFCOUNTER_LO)/sizeof(mmCHUB_ATC_PERFCOUNTER_LO[0]), 0, 0 }, + { "mmCHUB_ATC_PERFCOUNTER_HI", REG_MMIO, 0x7d7, &mmCHUB_ATC_PERFCOUNTER_HI[0], sizeof(mmCHUB_ATC_PERFCOUNTER_HI)/sizeof(mmCHUB_ATC_PERFCOUNTER_HI[0]), 0, 0 }, + { "mmCHUB_ATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7d8, &mmCHUB_ATC_PERFCOUNTER0_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG[0]), 0, 0 }, + { "mmCHUB_ATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7d9, &mmCHUB_ATC_PERFCOUNTER1_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG[0]), 0, 0 }, + { "mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7da, &mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 }, + { "mmMC_ARB_PERF_MON_CNTL0_ECC", REG_MMIO, 0x7db, &mmMC_ARB_PERF_MON_CNTL0_ECC[0], sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC)/sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC[0]), 0, 0 }, + { "mmMC_CONFIG", REG_MMIO, 0x800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 }, + { "mmMC_SHARED_CHMAP", REG_MMIO, 0x801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 }, + { "mmMC_SHARED_CHREMAP", REG_MMIO, 0x802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 }, + { "mmMC_RD_GRP_GFX", REG_MMIO, 0x803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 }, + { "mmMC_WR_GRP_GFX", REG_MMIO, 0x804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 }, + { "mmMC_RD_GRP_SYS", REG_MMIO, 0x805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 }, + { "mmMC_WR_GRP_SYS", REG_MMIO, 0x806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 }, + { "mmMC_RD_GRP_OTH", REG_MMIO, 0x807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 }, + { "mmMC_WR_GRP_OTH", REG_MMIO, 0x808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 }, + { "mmMC_VM_FB_LOCATION", REG_MMIO, 0x809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 }, + { "mmMC_VM_AGP_TOP", REG_MMIO, 0x80a, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 }, + { "mmMC_VM_AGP_BOT", REG_MMIO, 0x80b, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 }, + { "mmMC_VM_AGP_BASE", REG_MMIO, 0x80c, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x80d, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x80e, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x80f, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 }, + { "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 }, + { "mmMC_VM_FB_OFFSET", REG_MMIO, 0x81a, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 }, + { "mmMC_VM_STEERING", REG_MMIO, 0x81b, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 }, + { "mmMC_CONFIG_MCD", REG_MMIO, 0x828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 }, + { "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 }, + { "mmMC_MEM_POWER_LS", REG_MMIO, 0x82a, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 }, + { "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x82b, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 }, + { "mmMC_HUB_MISC_POWER", REG_MMIO, 0x82d, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 }, + { "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x82e, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 }, + { "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x82f, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 }, + { "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 }, + { "mmMC_HUB_MISC_DBG", REG_MMIO, 0x831, &mmMC_HUB_MISC_DBG[0], sizeof(mmMC_HUB_MISC_DBG)/sizeof(mmMC_HUB_MISC_DBG[0]), 0, 0 }, + { "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 }, + { "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 }, + { "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 }, + { "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 }, + { "mmMC_HUB_WDP_ERR", REG_MMIO, 0x836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 }, + { "mmMC_HUB_WDP_BP", REG_MMIO, 0x837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 }, + { "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 }, + { "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x83a, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x83b, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 }, + { "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x83c, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x83d, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 }, + { "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x83e, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 }, + { "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x83f, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 }, + { "mmMC_HUB_WDP_MGPU2", REG_MMIO, 0x840, &mmMC_HUB_WDP_MGPU2[0], sizeof(mmMC_HUB_WDP_MGPU2)/sizeof(mmMC_HUB_WDP_MGPU2[0]), 0, 0 }, + { "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 }, + { "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 }, + { "mmMC_HUB_WDP_MGPU", REG_MMIO, 0x843, &mmMC_HUB_WDP_MGPU[0], sizeof(mmMC_HUB_WDP_MGPU)/sizeof(mmMC_HUB_WDP_MGPU[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 }, + { "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 }, + { "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_ACPG_LIMIT", REG_MMIO, 0x849, &mmMC_HUB_RDREQ_ACPG_LIMIT[0], sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT)/sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT[0]), 0, 0 }, + { "mmMC_HUB_WDP_SH2", REG_MMIO, 0x84d, &mmMC_HUB_WDP_SH2[0], sizeof(mmMC_HUB_WDP_SH2)/sizeof(mmMC_HUB_WDP_SH2[0]), 0, 0 }, + { "mmMC_HUB_WDP_SH3", REG_MMIO, 0x84e, &mmMC_HUB_WDP_SH3[0], sizeof(mmMC_HUB_WDP_SH3)/sizeof(mmMC_HUB_WDP_SH3[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_IA0", REG_MMIO, 0x84f, &mmMC_HUB_RDREQ_IA0[0], sizeof(mmMC_HUB_RDREQ_IA0)/sizeof(mmMC_HUB_RDREQ_IA0[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_IA1", REG_MMIO, 0x850, &mmMC_HUB_RDREQ_IA1[0], sizeof(mmMC_HUB_RDREQ_IA1)/sizeof(mmMC_HUB_RDREQ_IA1[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CPG", REG_MMIO, 0x859, &mmMC_HUB_RDREQ_CPG[0], sizeof(mmMC_HUB_RDREQ_CPG)/sizeof(mmMC_HUB_RDREQ_CPG[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SDMA0", REG_MMIO, 0x85a, &mmMC_HUB_RDREQ_SDMA0[0], sizeof(mmMC_HUB_RDREQ_SDMA0)/sizeof(mmMC_HUB_RDREQ_SDMA0[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x85b, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SDMA1", REG_MMIO, 0x85c, &mmMC_HUB_RDREQ_SDMA1[0], sizeof(mmMC_HUB_RDREQ_SDMA1)/sizeof(mmMC_HUB_RDREQ_SDMA1[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x85d, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x85e, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_VCE", REG_MMIO, 0x85f, &mmMC_HUB_RDREQ_VCE[0], sizeof(mmMC_HUB_RDREQ_VCE)/sizeof(mmMC_HUB_RDREQ_VCE[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x860, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x861, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_IA", REG_MMIO, 0x862, &mmMC_HUB_RDREQ_IA[0], sizeof(mmMC_HUB_RDREQ_IA)/sizeof(mmMC_HUB_RDREQ_IA[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x863, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x864, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x865, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_VCEU", REG_MMIO, 0x866, &mmMC_HUB_RDREQ_VCEU[0], sizeof(mmMC_HUB_RDREQ_VCEU)/sizeof(mmMC_HUB_RDREQ_VCEU[0]), 0, 0 }, + { "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x867, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 }, + { "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x868, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 }, + { "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x869, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 }, + { "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x86a, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 }, + { "mmMC_HUB_WDP_SIP", REG_MMIO, 0x86b, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 }, + { "mmMC_HUB_WDP_CPG", REG_MMIO, 0x86c, &mmMC_HUB_WDP_CPG[0], sizeof(mmMC_HUB_WDP_CPG)/sizeof(mmMC_HUB_WDP_CPG[0]), 0, 0 }, + { "mmMC_HUB_WDP_SDMA1", REG_MMIO, 0x86d, &mmMC_HUB_WDP_SDMA1[0], sizeof(mmMC_HUB_WDP_SDMA1)/sizeof(mmMC_HUB_WDP_SDMA1[0]), 0, 0 }, + { "mmMC_HUB_WDP_SH0", REG_MMIO, 0x86e, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 }, + { "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x86f, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 }, + { "mmMC_HUB_WDP_VCE", REG_MMIO, 0x870, &mmMC_HUB_WDP_VCE[0], sizeof(mmMC_HUB_WDP_VCE)/sizeof(mmMC_HUB_WDP_VCE[0]), 0, 0 }, + { "mmMC_HUB_WDP_XDP", REG_MMIO, 0x871, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 }, + { "mmMC_HUB_WDP_IH", REG_MMIO, 0x872, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 }, + { "mmMC_HUB_WDP_RLC", REG_MMIO, 0x873, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 }, + { "mmMC_HUB_WDP_SEM", REG_MMIO, 0x874, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 }, + { "mmMC_HUB_WDP_SMU", REG_MMIO, 0x875, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 }, + { "mmMC_HUB_WDP_SH1", REG_MMIO, 0x876, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 }, + { "mmMC_HUB_WDP_UMC", REG_MMIO, 0x877, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 }, + { "mmMC_HUB_WDP_UVD", REG_MMIO, 0x878, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 }, + { "mmMC_HUB_WDP_HDP", REG_MMIO, 0x879, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 }, + { "mmMC_HUB_WDP_SDMA0", REG_MMIO, 0x87a, &mmMC_HUB_WDP_SDMA0[0], sizeof(mmMC_HUB_WDP_SDMA0)/sizeof(mmMC_HUB_WDP_SDMA0[0]), 0, 0 }, + { "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x87b, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 }, + { "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x87c, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 }, + { "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x87d, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 }, + { "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x87e, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 }, + { "mmMC_HUB_WDP_VCEU", REG_MMIO, 0x87f, &mmMC_HUB_WDP_VCEU[0], sizeof(mmMC_HUB_WDP_VCEU)/sizeof(mmMC_HUB_WDP_VCEU[0]), 0, 0 }, + { "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x880, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 }, + { "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x881, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x882, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_ACPG", REG_MMIO, 0x883, &mmMC_HUB_RDREQ_ACPG[0], sizeof(mmMC_HUB_RDREQ_ACPG)/sizeof(mmMC_HUB_RDREQ_ACPG[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_ACPO", REG_MMIO, 0x884, &mmMC_HUB_RDREQ_ACPO[0], sizeof(mmMC_HUB_RDREQ_ACPO)/sizeof(mmMC_HUB_RDREQ_ACPO[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_SAM", REG_MMIO, 0x885, &mmMC_HUB_RDREQ_SAM[0], sizeof(mmMC_HUB_RDREQ_SAM)/sizeof(mmMC_HUB_RDREQ_SAM[0]), 0, 0 }, + { "mmMC_HUB_WDP_ACPG", REG_MMIO, 0x886, &mmMC_HUB_WDP_ACPG[0], sizeof(mmMC_HUB_WDP_ACPG)/sizeof(mmMC_HUB_WDP_ACPG[0]), 0, 0 }, + { "mmMC_HUB_WDP_ACPO", REG_MMIO, 0x887, &mmMC_HUB_WDP_ACPO[0], sizeof(mmMC_HUB_WDP_ACPO)/sizeof(mmMC_HUB_WDP_ACPO[0]), 0, 0 }, + { "mmMC_HUB_WDP_SAM", REG_MMIO, 0x888, &mmMC_HUB_WDP_SAM[0], sizeof(mmMC_HUB_WDP_SAM)/sizeof(mmMC_HUB_WDP_SAM[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CPC", REG_MMIO, 0x889, &mmMC_HUB_RDREQ_CPC[0], sizeof(mmMC_HUB_RDREQ_CPC)/sizeof(mmMC_HUB_RDREQ_CPC[0]), 0, 0 }, + { "mmMC_HUB_RDREQ_CPF", REG_MMIO, 0x88a, &mmMC_HUB_RDREQ_CPF[0], sizeof(mmMC_HUB_RDREQ_CPF)/sizeof(mmMC_HUB_RDREQ_CPF[0]), 0, 0 }, + { "mmMC_HUB_WDP_CPC", REG_MMIO, 0x88b, &mmMC_HUB_WDP_CPC[0], sizeof(mmMC_HUB_WDP_CPC)/sizeof(mmMC_HUB_WDP_CPC[0]), 0, 0 }, + { "mmMC_HUB_WDP_CPF", REG_MMIO, 0x88c, &mmMC_HUB_WDP_CPF[0], sizeof(mmMC_HUB_WDP_CPF)/sizeof(mmMC_HUB_WDP_CPF[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 }, + { "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x8a1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x8a5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x8a6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 }, + { "mmCHUB_ATC_L1_DEBUG_TLB", REG_MMIO, 0x8c00, &mmCHUB_ATC_L1_DEBUG_TLB[0], sizeof(mmCHUB_ATC_L1_DEBUG_TLB)/sizeof(mmCHUB_ATC_L1_DEBUG_TLB[0]), 0, 0 }, + { "mmCHUB_ATC_L1_STATUS", REG_MMIO, 0x8c01, &mmCHUB_ATC_L1_STATUS[0], sizeof(mmCHUB_ATC_L1_STATUS)/sizeof(mmCHUB_ATC_L1_STATUS[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x8cd, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x8ce, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x8cf, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x8d0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x8d1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x8d2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x8d3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x8d4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x8d5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 }, + { "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x8d6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x8d7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x8d8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x8d9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x8da, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x8db, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x8dc, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x8dd, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x8de, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x8df, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x8e0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x8e1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x8e2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x8e3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 }, + { "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x8e4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x8e5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x8e6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x8e7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 }, + { "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x8e8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x8e9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x8ea, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x8eb, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x8ec, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x8ed, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x8ee, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x8ef, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x8f0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x8f1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x8f2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x8f3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x8f4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x8f5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x8f6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x8f7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x8f8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x8f9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x8fa, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x8fb, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x8fc, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 }, + { "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x8fd, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 }, + { "mmMC_XPB_LB_ADDR", REG_MMIO, 0x8fe, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 }, + { "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x8ff, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 }, + { "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 }, + { "mmMC_XPB_WCB_STS", REG_MMIO, 0x901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 }, + { "mmMC_XPB_WCB_CFG", REG_MMIO, 0x902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x90a, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x90b, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x90c, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x90d, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x90e, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 }, + { "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x90f, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 }, + { "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 }, + { "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x91a, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 }, + { "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x91b, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 }, + { "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x91c, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 }, + { "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x91d, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 }, + { "mmMC_XPB_CLK_GAT", REG_MMIO, 0x91e, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 }, + { "mmMC_XPB_INTF_CFG", REG_MMIO, 0x91f, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 }, + { "mmMC_XPB_INTF_STS", REG_MMIO, 0x920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 }, + { "mmMC_XPB_PIPE_STS", REG_MMIO, 0x921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 }, + { "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 }, + { "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 }, + { "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 }, + { "mmMC_XPB_STICKY", REG_MMIO, 0x925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 }, + { "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 }, + { "mmMC_XPB_MISC_CFG", REG_MMIO, 0x927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x92a, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x92b, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x92c, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x92d, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x92e, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x92f, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 }, + { "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 }, + { "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 }, + { "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x93a, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 }, + { "mmMC_RPB_CONF", REG_MMIO, 0x94d, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 }, + { "mmMC_RPB_IF_CONF", REG_MMIO, 0x94e, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 }, + { "mmMC_RPB_DBG1", REG_MMIO, 0x94f, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 }, + { "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 }, + { "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 }, + { "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 }, + { "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 }, + { "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 }, + { "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 }, + { "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 }, + { "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 }, + { "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 }, + { "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 }, + { "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x95a, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 }, + { "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x95b, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 }, + { "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x96d, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 }, + { "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x96e, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 }, + { "mmMC_CG_CONFIG", REG_MMIO, 0x96f, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 }, + { "mmMC_CITF_CNTL", REG_MMIO, 0x970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 }, + { "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 }, + { "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 }, + { "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 }, + { "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 }, + { "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 }, + { "mmMC_CITF_RET_MODE", REG_MMIO, 0x976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 }, + { "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 }, + { "mmMC_RD_GRP_EXT", REG_MMIO, 0x978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 }, + { "mmMC_WR_GRP_EXT", REG_MMIO, 0x979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 }, + { "mmMC_CITF_REMREQ", REG_MMIO, 0x97a, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 }, + { "mmMC_WR_TC0", REG_MMIO, 0x97b, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 }, + { "mmMC_WR_TC1", REG_MMIO, 0x97c, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 }, + { "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x97d, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 }, + { "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x97f, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 }, + { "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 }, + { "mmMC_RD_CB", REG_MMIO, 0x981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 }, + { "mmMC_RD_DB", REG_MMIO, 0x982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 }, + { "mmMC_RD_TC0", REG_MMIO, 0x983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 }, + { "mmMC_RD_TC1", REG_MMIO, 0x984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 }, + { "mmMC_RD_HUB", REG_MMIO, 0x985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 }, + { "mmMC_WR_CB", REG_MMIO, 0x986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 }, + { "mmMC_WR_DB", REG_MMIO, 0x987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 }, + { "mmMC_WR_HUB", REG_MMIO, 0x988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 }, + { "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 }, + { "mmMC_RD_GRP_LCL", REG_MMIO, 0x98a, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 }, + { "mmMC_WR_GRP_LCL", REG_MMIO, 0x98b, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 }, + { "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x98e, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 }, + { "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 }, + { "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 }, + { "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 }, + { "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x99a, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x99b, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x99c, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x99d, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 }, + { "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x9a4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x9a7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 }, + { "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x9a8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 }, + { "mmMC_ARB_AGE_CNTL", REG_MMIO, 0x9bf, &mmMC_ARB_AGE_CNTL[0], sizeof(mmMC_ARB_AGE_CNTL)/sizeof(mmMC_ARB_AGE_CNTL[0]), 0, 0 }, + { "mmMC_ARB_RET_CREDITS2", REG_MMIO, 0x9c0, &mmMC_ARB_RET_CREDITS2[0], sizeof(mmMC_ARB_RET_CREDITS2)/sizeof(mmMC_ARB_RET_CREDITS2[0]), 0, 0 }, + { "mmMC_ARB_FED_CNTL", REG_MMIO, 0x9c1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 }, + { "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x9c2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 }, + { "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x9c3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 }, + { "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x9c4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 }, + { "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x9c5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 }, + { "mmMC_ARB_GECC2", REG_MMIO, 0x9c9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 }, + { "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x9ca, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 }, + { "mmMC_ARB_ADDR_SWIZ0", REG_MMIO, 0x9cb, &mmMC_ARB_ADDR_SWIZ0[0], sizeof(mmMC_ARB_ADDR_SWIZ0)/sizeof(mmMC_ARB_ADDR_SWIZ0[0]), 0, 0 }, + { "mmMC_ARB_ADDR_SWIZ1", REG_MMIO, 0x9cc, &mmMC_ARB_ADDR_SWIZ1[0], sizeof(mmMC_ARB_ADDR_SWIZ1)/sizeof(mmMC_ARB_ADDR_SWIZ1[0]), 0, 0 }, + { "mmMC_ARB_MISC3", REG_MMIO, 0x9cd, &mmMC_ARB_MISC3[0], sizeof(mmMC_ARB_MISC3)/sizeof(mmMC_ARB_MISC3[0]), 0, 0 }, + { "mmMC_ARB_WCDR_2", REG_MMIO, 0x9ce, &mmMC_ARB_WCDR_2[0], sizeof(mmMC_ARB_WCDR_2)/sizeof(mmMC_ARB_WCDR_2[0]), 0, 0 }, + { "mmMC_ARB_RTT_DATA", REG_MMIO, 0x9cf, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 }, + { "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x9d0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 }, + { "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x9d1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 }, + { "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x9d2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 }, + { "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x9d3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 }, + { "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x9d4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 }, + { "mmMC_ARB_MISC2", REG_MMIO, 0x9d5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 }, + { "mmMC_ARB_MISC", REG_MMIO, 0x9d6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 }, + { "mmMC_ARB_BANKMAP", REG_MMIO, 0x9d7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 }, + { "mmMC_ARB_RAMCFG", REG_MMIO, 0x9d8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 }, + { "mmMC_ARB_POP", REG_MMIO, 0x9d9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 }, + { "mmMC_ARB_MINCLKS", REG_MMIO, 0x9da, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 }, + { "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x9db, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 }, + { "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x9dc, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 }, + { "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x9dd, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 }, + { "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x9de, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 }, + { "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x9df, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 }, + { "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x9e0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 }, + { "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x9e1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 }, + { "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x9e2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 }, + { "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x9e3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 }, + { "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x9e4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 }, + { "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x9e5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 }, + { "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x9e6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 }, + { "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x9e7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 }, + { "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x9e8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 }, + { "mmMC_ARB_AGE_RD", REG_MMIO, 0x9e9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 }, + { "mmMC_ARB_AGE_WR", REG_MMIO, 0x9ea, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 }, + { "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x9eb, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 }, + { "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x9ec, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 }, + { "mmMC_ARB_PM_CNTL", REG_MMIO, 0x9ed, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 }, + { "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x9ee, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 }, + { "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x9ef, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 }, + { "mmMC_ARB_LM_RD", REG_MMIO, 0x9f0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 }, + { "mmMC_ARB_LM_WR", REG_MMIO, 0x9f1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 }, + { "mmMC_ARB_REMREQ", REG_MMIO, 0x9f2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 }, + { "mmMC_ARB_REPLAY", REG_MMIO, 0x9f3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 }, + { "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x9f4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 }, + { "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x9f5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 }, + { "mmMC_ARB_MAX_LAT_CID", REG_MMIO, 0x9f6, &mmMC_ARB_MAX_LAT_CID[0], sizeof(mmMC_ARB_MAX_LAT_CID)/sizeof(mmMC_ARB_MAX_LAT_CID[0]), 0, 0 }, + { "mmMC_ARB_MAX_LAT_RSLT0", REG_MMIO, 0x9f7, &mmMC_ARB_MAX_LAT_RSLT0[0], sizeof(mmMC_ARB_MAX_LAT_RSLT0)/sizeof(mmMC_ARB_MAX_LAT_RSLT0[0]), 0, 0 }, + { "mmMC_ARB_MAX_LAT_RSLT1", REG_MMIO, 0x9f8, &mmMC_ARB_MAX_LAT_RSLT1[0], sizeof(mmMC_ARB_MAX_LAT_RSLT1)/sizeof(mmMC_ARB_MAX_LAT_RSLT1[0]), 0, 0 }, + { "mmMC_ARB_SSM", REG_MMIO, 0x9f9, &mmMC_ARB_SSM[0], sizeof(mmMC_ARB_SSM)/sizeof(mmMC_ARB_SSM[0]), 0, 0 }, + { "mmMC_ARB_CG", REG_MMIO, 0x9fa, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 }, + { "mmMC_ARB_WCDR", REG_MMIO, 0x9fb, &mmMC_ARB_WCDR[0], sizeof(mmMC_ARB_WCDR)/sizeof(mmMC_ARB_WCDR[0]), 0, 0 }, + { "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x9fc, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 }, + { "mmMC_ARB_BUSY_STATUS", REG_MMIO, 0x9fd, &mmMC_ARB_BUSY_STATUS[0], sizeof(mmMC_ARB_BUSY_STATUS)/sizeof(mmMC_ARB_BUSY_STATUS[0]), 0, 0 }, + { "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x9ff, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 }, + { "mmMC_ARB_BURST_TIME", REG_MMIO, 0xa02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CS0_BASE", REG_MMIO, 0xa05, &mmMC_FUS_DRAM0_CS0_BASE[0], sizeof(mmMC_FUS_DRAM0_CS0_BASE)/sizeof(mmMC_FUS_DRAM0_CS0_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CS0_BASE", REG_MMIO, 0xa06, &mmMC_FUS_DRAM1_CS0_BASE[0], sizeof(mmMC_FUS_DRAM1_CS0_BASE)/sizeof(mmMC_FUS_DRAM1_CS0_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CS1_BASE", REG_MMIO, 0xa07, &mmMC_FUS_DRAM0_CS1_BASE[0], sizeof(mmMC_FUS_DRAM0_CS1_BASE)/sizeof(mmMC_FUS_DRAM0_CS1_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CS1_BASE", REG_MMIO, 0xa08, &mmMC_FUS_DRAM1_CS1_BASE[0], sizeof(mmMC_FUS_DRAM1_CS1_BASE)/sizeof(mmMC_FUS_DRAM1_CS1_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CS2_BASE", REG_MMIO, 0xa09, &mmMC_FUS_DRAM0_CS2_BASE[0], sizeof(mmMC_FUS_DRAM0_CS2_BASE)/sizeof(mmMC_FUS_DRAM0_CS2_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CS2_BASE", REG_MMIO, 0xa0a, &mmMC_FUS_DRAM1_CS2_BASE[0], sizeof(mmMC_FUS_DRAM1_CS2_BASE)/sizeof(mmMC_FUS_DRAM1_CS2_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CS3_BASE", REG_MMIO, 0xa0b, &mmMC_FUS_DRAM0_CS3_BASE[0], sizeof(mmMC_FUS_DRAM0_CS3_BASE)/sizeof(mmMC_FUS_DRAM0_CS3_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CS3_BASE", REG_MMIO, 0xa0c, &mmMC_FUS_DRAM1_CS3_BASE[0], sizeof(mmMC_FUS_DRAM1_CS3_BASE)/sizeof(mmMC_FUS_DRAM1_CS3_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CS01_MASK", REG_MMIO, 0xa0d, NULL, 0, 0, 0 }, + { "mmMC_FUS_DRAM1_CS01_MASK", REG_MMIO, 0xa0e, NULL, 0, 0, 0 }, + { "mmMC_FUS_DRAM0_CS23_MASK", REG_MMIO, 0xa0f, NULL, 0, 0, 0 }, + { "mmMC_FUS_DRAM1_CS23_MASK", REG_MMIO, 0xa10, NULL, 0, 0, 0 }, + { "mmMC_FUS_DRAM0_BANK_ADDR_MAPPING", REG_MMIO, 0xa11, &mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_BANK_ADDR_MAPPING", REG_MMIO, 0xa12, &mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CTL_BASE", REG_MMIO, 0xa13, &mmMC_FUS_DRAM0_CTL_BASE[0], sizeof(mmMC_FUS_DRAM0_CTL_BASE)/sizeof(mmMC_FUS_DRAM0_CTL_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CTL_BASE", REG_MMIO, 0xa14, &mmMC_FUS_DRAM1_CTL_BASE[0], sizeof(mmMC_FUS_DRAM1_CTL_BASE)/sizeof(mmMC_FUS_DRAM1_CTL_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM0_CTL_LIMIT", REG_MMIO, 0xa15, &mmMC_FUS_DRAM0_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM0_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM0_CTL_LIMIT[0]), 0, 0 }, + { "mmMC_FUS_DRAM1_CTL_LIMIT", REG_MMIO, 0xa16, &mmMC_FUS_DRAM1_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM1_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM1_CTL_LIMIT[0]), 0, 0 }, + { "mmMC_FUS_DRAM_CTL_HIGH_01", REG_MMIO, 0xa17, &mmMC_FUS_DRAM_CTL_HIGH_01[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_01)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_01[0]), 0, 0 }, + { "mmMC_FUS_DRAM_CTL_HIGH_23", REG_MMIO, 0xa18, &mmMC_FUS_DRAM_CTL_HIGH_23[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_23)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_23[0]), 0, 0 }, + { "mmMC_FUS_DRAM_MODE", REG_MMIO, 0xa19, &mmMC_FUS_DRAM_MODE[0], sizeof(mmMC_FUS_DRAM_MODE)/sizeof(mmMC_FUS_DRAM_MODE[0]), 0, 0 }, + { "mmMC_FUS_DRAM_APER_BASE", REG_MMIO, 0xa1a, &mmMC_FUS_DRAM_APER_BASE[0], sizeof(mmMC_FUS_DRAM_APER_BASE)/sizeof(mmMC_FUS_DRAM_APER_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM_APER_TOP", REG_MMIO, 0xa1b, &mmMC_FUS_DRAM_APER_TOP[0], sizeof(mmMC_FUS_DRAM_APER_TOP)/sizeof(mmMC_FUS_DRAM_APER_TOP[0]), 0, 0 }, + { "mmMC_FUS_DRAM_C6SAVE_APER_BASE", REG_MMIO, 0xa1c, &mmMC_FUS_DRAM_C6SAVE_APER_BASE[0], sizeof(mmMC_FUS_DRAM_C6SAVE_APER_BASE)/sizeof(mmMC_FUS_DRAM_C6SAVE_APER_BASE[0]), 0, 0 }, + { "mmMC_FUS_DRAM_C6SAVE_APER_TOP", REG_MMIO, 0xa1d, &mmMC_FUS_DRAM_C6SAVE_APER_TOP[0], sizeof(mmMC_FUS_DRAM_C6SAVE_APER_TOP)/sizeof(mmMC_FUS_DRAM_C6SAVE_APER_TOP[0]), 0, 0 }, + { "mmMC_FUS_DRAM_APER_DEF", REG_MMIO, 0xa1e, &mmMC_FUS_DRAM_APER_DEF[0], sizeof(mmMC_FUS_DRAM_APER_DEF)/sizeof(mmMC_FUS_DRAM_APER_DEF[0]), 0, 0 }, + { "mmMC_FUS_ARB_GARLIC_ISOC_PRI", REG_MMIO, 0xa1f, &mmMC_FUS_ARB_GARLIC_ISOC_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI[0]), 0, 0 }, + { "mmMC_FUS_ARB_GARLIC_CNTL", REG_MMIO, 0xa20, &mmMC_FUS_ARB_GARLIC_CNTL[0], sizeof(mmMC_FUS_ARB_GARLIC_CNTL)/sizeof(mmMC_FUS_ARB_GARLIC_CNTL[0]), 0, 0 }, + { "mmMC_FUS_ARB_GARLIC_WR_PRI", REG_MMIO, 0xa21, &mmMC_FUS_ARB_GARLIC_WR_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI[0]), 0, 0 }, + { "mmMC_FUS_ARB_GARLIC_WR_PRI2", REG_MMIO, 0xa22, &mmMC_FUS_ARB_GARLIC_WR_PRI2[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2[0]), 0, 0 }, + { "mmMC_CG_DATAPORT", REG_MMIO, 0xa32, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 }, + { "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0xc80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 }, + { "mmMC_XBAR_REMOTE", REG_MMIO, 0xc81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 }, + { "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0xc82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 }, + { "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0xc83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 }, + { "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0xc84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 }, + { "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0xc85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 }, + { "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0xc86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 }, + { "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0xc87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 }, + { "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0xc88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 }, + { "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0xc89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 }, + { "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0xc8a, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 }, + { "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0xc8b, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 }, + { "mmMC_XBAR_TWOCHAN", REG_MMIO, 0xc8c, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 }, + { "mmMC_XBAR_ARB", REG_MMIO, 0xc8d, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 }, + { "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0xc8e, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_CNTL0", REG_MMIO, 0xc8f, &mmMC_XBAR_PERF_MON_CNTL0[0], sizeof(mmMC_XBAR_PERF_MON_CNTL0)/sizeof(mmMC_XBAR_PERF_MON_CNTL0[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_CNTL1", REG_MMIO, 0xc90, &mmMC_XBAR_PERF_MON_CNTL1[0], sizeof(mmMC_XBAR_PERF_MON_CNTL1)/sizeof(mmMC_XBAR_PERF_MON_CNTL1[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_CNTL2", REG_MMIO, 0xc91, &mmMC_XBAR_PERF_MON_CNTL2[0], sizeof(mmMC_XBAR_PERF_MON_CNTL2)/sizeof(mmMC_XBAR_PERF_MON_CNTL2[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_RSLT0", REG_MMIO, 0xc92, &mmMC_XBAR_PERF_MON_RSLT0[0], sizeof(mmMC_XBAR_PERF_MON_RSLT0)/sizeof(mmMC_XBAR_PERF_MON_RSLT0[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_RSLT1", REG_MMIO, 0xc93, &mmMC_XBAR_PERF_MON_RSLT1[0], sizeof(mmMC_XBAR_PERF_MON_RSLT1)/sizeof(mmMC_XBAR_PERF_MON_RSLT1[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_RSLT2", REG_MMIO, 0xc94, &mmMC_XBAR_PERF_MON_RSLT2[0], sizeof(mmMC_XBAR_PERF_MON_RSLT2)/sizeof(mmMC_XBAR_PERF_MON_RSLT2[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_RSLT3", REG_MMIO, 0xc95, &mmMC_XBAR_PERF_MON_RSLT3[0], sizeof(mmMC_XBAR_PERF_MON_RSLT3)/sizeof(mmMC_XBAR_PERF_MON_RSLT3[0]), 0, 0 }, + { "mmMC_XBAR_PERF_MON_MAX_THSH", REG_MMIO, 0xc96, &mmMC_XBAR_PERF_MON_MAX_THSH[0], sizeof(mmMC_XBAR_PERF_MON_MAX_THSH)/sizeof(mmMC_XBAR_PERF_MON_MAX_THSH[0]), 0, 0 }, + { "mmMC_XBAR_SPARE0", REG_MMIO, 0xc97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 }, + { "mmMC_XBAR_SPARE1", REG_MMIO, 0xc98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 }, + { "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0xcc0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 }, + { "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0xcc1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 }, + { "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0xcc2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 }, + { "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0xcc3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 }, + { "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0xcc4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 }, + { "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0xcc5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 }, + { "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0xcc6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 }, + { "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0xcc7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 }, + { "mmATC_ATS_CNTL", REG_MMIO, 0xcc9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 }, + { "mmATC_ATS_DEBUG", REG_MMIO, 0xcca, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 }, + { "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0xccb, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 }, + { "mmATC_ATS_STATUS", REG_MMIO, 0xccc, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 }, + { "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0xccd, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 }, + { "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0xcce, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 }, + { "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0xccf, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 }, + { "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0xcd0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 }, + { "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0xcd1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 }, + { "mmATC_MISC_CG", REG_MMIO, 0xcd4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 }, + { "mmATC_L2_CNTL", REG_MMIO, 0xcd5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 }, + { "mmATC_L2_CNTL2", REG_MMIO, 0xcd6, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 }, + { "mmATC_L2_DEBUG", REG_MMIO, 0xcd7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 }, + { "mmATC_L2_DEBUG2", REG_MMIO, 0xcd8, &mmATC_L2_DEBUG2[0], sizeof(mmATC_L2_DEBUG2)/sizeof(mmATC_L2_DEBUG2[0]), 0, 0 }, + { "mmATC_L1_CNTL", REG_MMIO, 0xcdc, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 }, + { "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0xcdd, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 }, + { "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0xcde, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 }, + { "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0xcdf, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 }, + { "mmATC_L1RD_STATUS", REG_MMIO, 0xce0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 }, + { "mmATC_L1WR_STATUS", REG_MMIO, 0xce1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 }, + { "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0xce6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 }, + { "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0xce7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0xce8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0xce9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0xcea, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0xceb, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0xcec, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0xced, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0xcee, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0xcef, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0xcf0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0xcf1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0xcf2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0xcf3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0xcf4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0xcf5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 }, + { "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0xcf6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 }, + { "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0xd40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 }, + { "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0xd41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 }, + { "mmGMCON_RENG_EXECUTE", REG_MMIO, 0xd42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 }, + { "mmGMCON_MISC", REG_MMIO, 0xd43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 }, + { "mmGMCON_MISC2", REG_MMIO, 0xd44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 }, + { "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0xd45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 }, + { "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0xd46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 }, + { "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0xd47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 }, + { "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0xd48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 }, + { "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0xd49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 }, + { "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0xd4a, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 }, + { "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0xd4b, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 }, + { "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0xd4c, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 }, + { "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0xd4d, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 }, + { "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0xd4e, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 }, + { "mmGMCON_PGFSM_WRITE", REG_MMIO, 0xd4f, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 }, + { "mmGMCON_PGFSM_READ", REG_MMIO, 0xd50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 }, + { "mmGMCON_MISC3", REG_MMIO, 0xd51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 }, + { "mmGMCON_MASK", REG_MMIO, 0xd52, &mmGMCON_MASK[0], sizeof(mmGMCON_MASK)/sizeof(mmGMCON_MASK[0]), 0, 0 }, + { "mmGMCON_DEBUG", REG_MMIO, 0xd5f, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 }, + { "mmMC_ARB_HARSH_EN_RD", REG_MMIO, 0xdc0, &mmMC_ARB_HARSH_EN_RD[0], sizeof(mmMC_ARB_HARSH_EN_RD)/sizeof(mmMC_ARB_HARSH_EN_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_EN_WR", REG_MMIO, 0xdc1, &mmMC_ARB_HARSH_EN_WR[0], sizeof(mmMC_ARB_HARSH_EN_WR)/sizeof(mmMC_ARB_HARSH_EN_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_HI0_RD", REG_MMIO, 0xdc2, &mmMC_ARB_HARSH_TX_HI0_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI0_RD)/sizeof(mmMC_ARB_HARSH_TX_HI0_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_HI0_WR", REG_MMIO, 0xdc3, &mmMC_ARB_HARSH_TX_HI0_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI0_WR)/sizeof(mmMC_ARB_HARSH_TX_HI0_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_HI1_RD", REG_MMIO, 0xdc4, &mmMC_ARB_HARSH_TX_HI1_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI1_RD)/sizeof(mmMC_ARB_HARSH_TX_HI1_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_HI1_WR", REG_MMIO, 0xdc5, &mmMC_ARB_HARSH_TX_HI1_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI1_WR)/sizeof(mmMC_ARB_HARSH_TX_HI1_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_LO0_RD", REG_MMIO, 0xdc6, &mmMC_ARB_HARSH_TX_LO0_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO0_RD)/sizeof(mmMC_ARB_HARSH_TX_LO0_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_LO0_WR", REG_MMIO, 0xdc7, &mmMC_ARB_HARSH_TX_LO0_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO0_WR)/sizeof(mmMC_ARB_HARSH_TX_LO0_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_LO1_RD", REG_MMIO, 0xdc8, &mmMC_ARB_HARSH_TX_LO1_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO1_RD)/sizeof(mmMC_ARB_HARSH_TX_LO1_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_TX_LO1_WR", REG_MMIO, 0xdc9, &mmMC_ARB_HARSH_TX_LO1_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO1_WR)/sizeof(mmMC_ARB_HARSH_TX_LO1_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWPERIOD0_RD", REG_MMIO, 0xdca, &mmMC_ARB_HARSH_BWPERIOD0_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWPERIOD0_WR", REG_MMIO, 0xdcb, &mmMC_ARB_HARSH_BWPERIOD0_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWPERIOD1_RD", REG_MMIO, 0xdcc, &mmMC_ARB_HARSH_BWPERIOD1_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWPERIOD1_WR", REG_MMIO, 0xdcd, &mmMC_ARB_HARSH_BWPERIOD1_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWCNT0_RD", REG_MMIO, 0xdce, &mmMC_ARB_HARSH_BWCNT0_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT0_RD)/sizeof(mmMC_ARB_HARSH_BWCNT0_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWCNT0_WR", REG_MMIO, 0xdcf, &mmMC_ARB_HARSH_BWCNT0_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT0_WR)/sizeof(mmMC_ARB_HARSH_BWCNT0_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWCNT1_RD", REG_MMIO, 0xdd0, &mmMC_ARB_HARSH_BWCNT1_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT1_RD)/sizeof(mmMC_ARB_HARSH_BWCNT1_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_BWCNT1_WR", REG_MMIO, 0xdd1, &mmMC_ARB_HARSH_BWCNT1_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT1_WR)/sizeof(mmMC_ARB_HARSH_BWCNT1_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_SAT0_RD", REG_MMIO, 0xdd2, &mmMC_ARB_HARSH_SAT0_RD[0], sizeof(mmMC_ARB_HARSH_SAT0_RD)/sizeof(mmMC_ARB_HARSH_SAT0_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_SAT0_WR", REG_MMIO, 0xdd3, &mmMC_ARB_HARSH_SAT0_WR[0], sizeof(mmMC_ARB_HARSH_SAT0_WR)/sizeof(mmMC_ARB_HARSH_SAT0_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_SAT1_RD", REG_MMIO, 0xdd4, &mmMC_ARB_HARSH_SAT1_RD[0], sizeof(mmMC_ARB_HARSH_SAT1_RD)/sizeof(mmMC_ARB_HARSH_SAT1_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_SAT1_WR", REG_MMIO, 0xdd5, &mmMC_ARB_HARSH_SAT1_WR[0], sizeof(mmMC_ARB_HARSH_SAT1_WR)/sizeof(mmMC_ARB_HARSH_SAT1_WR[0]), 0, 0 }, + { "mmMC_ARB_HARSH_CTL_RD", REG_MMIO, 0xdd6, &mmMC_ARB_HARSH_CTL_RD[0], sizeof(mmMC_ARB_HARSH_CTL_RD)/sizeof(mmMC_ARB_HARSH_CTL_RD[0]), 0, 0 }, + { "mmMC_ARB_HARSH_CTL_WR", REG_MMIO, 0xdd7, &mmMC_ARB_HARSH_CTL_WR[0], sizeof(mmMC_ARB_HARSH_CTL_WR)/sizeof(mmMC_ARB_HARSH_CTL_WR[0]), 0, 0 }, |