diff options
Diffstat (limited to 'src/lib/ip/bif51_regs.i')
| -rw-r--r-- | src/lib/ip/bif51_regs.i | 2886 |
1 files changed, 2886 insertions, 0 deletions
diff --git a/src/lib/ip/bif51_regs.i b/src/lib/ip/bif51_regs.i new file mode 100644 index 0000000..3273295 --- /dev/null +++ b/src/lib/ip/bif51_regs.i @@ -0,0 +1,2886 @@ + { "ixD2F1_PCIEP_RESERVED", REG_SMC, 0x0, &ixD2F1_PCIEP_RESERVED[0], sizeof(ixD2F1_PCIEP_RESERVED)/sizeof(ixD2F1_PCIEP_RESERVED[0]), 0, 0 }, + { "mmVENDOR_ID", REG_MMIO, 0x0, &mmVENDOR_ID[0], sizeof(mmVENDOR_ID)/sizeof(mmVENDOR_ID[0]), 0, 0 }, + { "mmMM_INDEX", REG_MMIO, 0x0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 }, + { "ixD2F1_PCIEP_SCRATCH", REG_SMC, 0x1, &ixD2F1_PCIEP_SCRATCH[0], sizeof(ixD2F1_PCIEP_SCRATCH)/sizeof(ixD2F1_PCIEP_SCRATCH[0]), 0, 0 }, + { "mmMM_DATA", REG_MMIO, 0x1, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 }, + { "mmSTATUS", REG_MMIO, 0x1, &mmSTATUS[0], sizeof(mmSTATUS)/sizeof(mmSTATUS[0]), 0, 0 }, + { "ixD2F1_PCIEP_PORT_CNTL", REG_SMC, 0x10, &ixD2F1_PCIEP_PORT_CNTL[0], sizeof(ixD2F1_PCIEP_PORT_CNTL)/sizeof(ixD2F1_PCIEP_PORT_CNTL[0]), 0, 0 }, + { "ixPCIEP_RESERVED", REG_SMC, 0x10010000, &ixPCIEP_RESERVED[0], sizeof(ixPCIEP_RESERVED)/sizeof(ixPCIEP_RESERVED[0]), 0, 0 }, + { "ixPCIEP_SCRATCH", REG_SMC, 0x10010001, &ixPCIEP_SCRATCH[0], sizeof(ixPCIEP_SCRATCH)/sizeof(ixPCIEP_SCRATCH[0]), 0, 0 }, + { "ixPCIEP_HW_DEBUG", REG_SMC, 0x10010002, &ixPCIEP_HW_DEBUG[0], sizeof(ixPCIEP_HW_DEBUG)/sizeof(ixPCIEP_HW_DEBUG[0]), 0, 0 }, + { "ixPCIEP_PORT_CNTL", REG_SMC, 0x10010010, &ixPCIEP_PORT_CNTL[0], sizeof(ixPCIEP_PORT_CNTL)/sizeof(ixPCIEP_PORT_CNTL[0]), 0, 0 }, + { "ixPCIE_TX_CNTL", REG_SMC, 0x10010020, &ixPCIE_TX_CNTL[0], sizeof(ixPCIE_TX_CNTL)/sizeof(ixPCIE_TX_CNTL[0]), 0, 0 }, + { "ixPCIE_TX_REQUESTER_ID", REG_SMC, 0x10010021, &ixPCIE_TX_REQUESTER_ID[0], sizeof(ixPCIE_TX_REQUESTER_ID)/sizeof(ixPCIE_TX_REQUESTER_ID[0]), 0, 0 }, + { "ixPCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x10010022, &ixPCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_TX_VENDOR_SPECIFIC)/sizeof(ixPCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 }, + { "ixPCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x10010023, &ixPCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixPCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixPCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 }, + { "ixPCIE_TX_SEQ", REG_SMC, 0x10010024, &ixPCIE_TX_SEQ[0], sizeof(ixPCIE_TX_SEQ)/sizeof(ixPCIE_TX_SEQ[0]), 0, 0 }, + { "ixPCIE_TX_REPLAY", REG_SMC, 0x10010025, &ixPCIE_TX_REPLAY[0], sizeof(ixPCIE_TX_REPLAY)/sizeof(ixPCIE_TX_REPLAY[0]), 0, 0 }, + { "ixPCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x10010026, &ixPCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x10010030, &ixPCIE_TX_CREDITS_ADVT_P[0], sizeof(ixPCIE_TX_CREDITS_ADVT_P)/sizeof(ixPCIE_TX_CREDITS_ADVT_P[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x10010031, &ixPCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixPCIE_TX_CREDITS_ADVT_NP)/sizeof(ixPCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x10010032, &ixPCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixPCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixPCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_INIT_P", REG_SMC, 0x10010033, &ixPCIE_TX_CREDITS_INIT_P[0], sizeof(ixPCIE_TX_CREDITS_INIT_P)/sizeof(ixPCIE_TX_CREDITS_INIT_P[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x10010034, &ixPCIE_TX_CREDITS_INIT_NP[0], sizeof(ixPCIE_TX_CREDITS_INIT_NP)/sizeof(ixPCIE_TX_CREDITS_INIT_NP[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x10010035, &ixPCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixPCIE_TX_CREDITS_INIT_CPL)/sizeof(ixPCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_STATUS", REG_SMC, 0x10010036, &ixPCIE_TX_CREDITS_STATUS[0], sizeof(ixPCIE_TX_CREDITS_STATUS)/sizeof(ixPCIE_TX_CREDITS_STATUS[0]), 0, 0 }, + { "ixPCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x10010037, &ixPCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 }, + { "ixPCIE_P_PORT_LANE_STATUS", REG_SMC, 0x10010050, &ixPCIE_P_PORT_LANE_STATUS[0], sizeof(ixPCIE_P_PORT_LANE_STATUS)/sizeof(ixPCIE_P_PORT_LANE_STATUS[0]), 0, 0 }, + { "ixPCIE_FC_P", REG_SMC, 0x10010060, &ixPCIE_FC_P[0], sizeof(ixPCIE_FC_P)/sizeof(ixPCIE_FC_P[0]), 0, 0 }, + { "ixPCIE_FC_NP", REG_SMC, 0x10010061, &ixPCIE_FC_NP[0], sizeof(ixPCIE_FC_NP)/sizeof(ixPCIE_FC_NP[0]), 0, 0 }, + { "ixPCIE_FC_CPL", REG_SMC, 0x10010062, &ixPCIE_FC_CPL[0], sizeof(ixPCIE_FC_CPL)/sizeof(ixPCIE_FC_CPL[0]), 0, 0 }, + { "ixPCIE_ERR_CNTL", REG_SMC, 0x1001006a, &ixPCIE_ERR_CNTL[0], sizeof(ixPCIE_ERR_CNTL)/sizeof(ixPCIE_ERR_CNTL[0]), 0, 0 }, + { "ixPCIE_RX_CNTL", REG_SMC, 0x10010070, &ixPCIE_RX_CNTL[0], sizeof(ixPCIE_RX_CNTL)/sizeof(ixPCIE_RX_CNTL[0]), 0, 0 }, + { "ixPCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x10010071, &ixPCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixPCIE_RX_EXPECTED_SEQNUM)/sizeof(ixPCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 }, + { "ixPCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x10010072, &ixPCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_RX_VENDOR_SPECIFIC)/sizeof(ixPCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 }, + { "ixPCIE_RX_CNTL3", REG_SMC, 0x10010074, &ixPCIE_RX_CNTL3[0], sizeof(ixPCIE_RX_CNTL3)/sizeof(ixPCIE_RX_CNTL3[0]), 0, 0 }, + { "ixPCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x10010080, &ixPCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 }, + { "ixPCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x10010081, &ixPCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 }, + { "ixPCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x10010082, &ixPCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 }, + { "ixPCIE_LC_CNTL", REG_SMC, 0x100100a0, &ixPCIE_LC_CNTL[0], sizeof(ixPCIE_LC_CNTL)/sizeof(ixPCIE_LC_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_TRAINING_CNTL", REG_SMC, 0x100100a1, &ixPCIE_LC_TRAINING_CNTL[0], sizeof(ixPCIE_LC_TRAINING_CNTL)/sizeof(ixPCIE_LC_TRAINING_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0x100100a2, &ixPCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixPCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixPCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_N_FTS_CNTL", REG_SMC, 0x100100a3, &ixPCIE_LC_N_FTS_CNTL[0], sizeof(ixPCIE_LC_N_FTS_CNTL)/sizeof(ixPCIE_LC_N_FTS_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_SPEED_CNTL", REG_SMC, 0x100100a4, &ixPCIE_LC_SPEED_CNTL[0], sizeof(ixPCIE_LC_SPEED_CNTL)/sizeof(ixPCIE_LC_SPEED_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_STATE0", REG_SMC, 0x100100a5, &ixPCIE_LC_STATE0[0], sizeof(ixPCIE_LC_STATE0)/sizeof(ixPCIE_LC_STATE0[0]), 0, 0 }, + { "ixPCIE_LC_STATE1", REG_SMC, 0x100100a6, &ixPCIE_LC_STATE1[0], sizeof(ixPCIE_LC_STATE1)/sizeof(ixPCIE_LC_STATE1[0]), 0, 0 }, + { "ixPCIE_LC_STATE2", REG_SMC, 0x100100a7, &ixPCIE_LC_STATE2[0], sizeof(ixPCIE_LC_STATE2)/sizeof(ixPCIE_LC_STATE2[0]), 0, 0 }, + { "ixPCIE_LC_STATE3", REG_SMC, 0x100100a8, &ixPCIE_LC_STATE3[0], sizeof(ixPCIE_LC_STATE3)/sizeof(ixPCIE_LC_STATE3[0]), 0, 0 }, + { "ixPCIE_LC_STATE4", REG_SMC, 0x100100a9, &ixPCIE_LC_STATE4[0], sizeof(ixPCIE_LC_STATE4)/sizeof(ixPCIE_LC_STATE4[0]), 0, 0 }, + { "ixPCIE_LC_STATE5", REG_SMC, 0x100100aa, &ixPCIE_LC_STATE5[0], sizeof(ixPCIE_LC_STATE5)/sizeof(ixPCIE_LC_STATE5[0]), 0, 0 }, + { "ixPCIE_LC_CNTL2", REG_SMC, 0x100100b1, &ixPCIE_LC_CNTL2[0], sizeof(ixPCIE_LC_CNTL2)/sizeof(ixPCIE_LC_CNTL2[0]), 0, 0 }, + { "ixPCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0x100100b2, &ixPCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixPCIE_LC_BW_CHANGE_CNTL)/sizeof(ixPCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_CDR_CNTL", REG_SMC, 0x100100b3, &ixPCIE_LC_CDR_CNTL[0], sizeof(ixPCIE_LC_CDR_CNTL)/sizeof(ixPCIE_LC_CDR_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_LANE_CNTL", REG_SMC, 0x100100b4, &ixPCIE_LC_LANE_CNTL[0], sizeof(ixPCIE_LC_LANE_CNTL)/sizeof(ixPCIE_LC_LANE_CNTL[0]), 0, 0 }, + { "ixPCIE_LC_CNTL3", REG_SMC, 0x100100b5, &ixPCIE_LC_CNTL3[0], sizeof(ixPCIE_LC_CNTL3)/sizeof(ixPCIE_LC_CNTL3[0]), 0, 0 }, + { "ixPCIE_LC_CNTL4", REG_SMC, 0x100100b6, &ixPCIE_LC_CNTL4[0], sizeof(ixPCIE_LC_CNTL4)/sizeof(ixPCIE_LC_CNTL4[0]), 0, 0 }, + { "ixPCIE_LC_CNTL5", REG_SMC, 0x100100b7, &ixPCIE_LC_CNTL5[0], sizeof(ixPCIE_LC_CNTL5)/sizeof(ixPCIE_LC_CNTL5[0]), 0, 0 }, + { "ixPCIE_LC_FORCE_COEFF", REG_SMC, 0x100100b8, &ixPCIE_LC_FORCE_COEFF[0], sizeof(ixPCIE_LC_FORCE_COEFF)/sizeof(ixPCIE_LC_FORCE_COEFF[0]), 0, 0 }, + { "ixPCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0x100100b9, &ixPCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixPCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixPCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 }, + { "ixPCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0x100100ba, &ixPCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 }, + { "ixPCIEP_STRAP_LC", REG_SMC, 0x100100c0, &ixPCIEP_STRAP_LC[0], sizeof(ixPCIEP_STRAP_LC)/sizeof(ixPCIEP_STRAP_LC[0]), 0, 0 }, + { "ixPCIEP_STRAP_MISC", REG_SMC, 0x100100c1, &ixPCIEP_STRAP_MISC[0], sizeof(ixPCIEP_STRAP_MISC)/sizeof(ixPCIEP_STRAP_MISC[0]), 0, 0 }, + { "ixPCIEP_BCH_ECC_CNTL", REG_SMC, 0x100100d0, &ixPCIEP_BCH_ECC_CNTL[0], sizeof(ixPCIEP_BCH_ECC_CNTL)/sizeof(ixPCIEP_BCH_ECC_CNTL[0]), 0, 0 }, + { "ixRFE_SOFTRST_CNTL", REG_SMC, 0x1080001, &ixRFE_SOFTRST_CNTL[0], sizeof(ixRFE_SOFTRST_CNTL)/sizeof(ixRFE_SOFTRST_CNTL[0]), 0, 0 }, + { "ixRFE_CLIENT_SOFTRST_TRIGGER", REG_SMC, 0x1080004, &ixRFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(ixRFE_CLIENT_SOFTRST_TRIGGER)/sizeof(ixRFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 }, + { "ixRFE_MASTER_SOFTRST_TRIGGER", REG_SMC, 0x1080005, &ixRFE_MASTER_SOFTRST_TRIGGER[0], sizeof(ixRFE_MASTER_SOFTRST_TRIGGER)/sizeof(ixRFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 }, + { "ixRFE_PWDN_COMMAND", REG_SMC, 0x1080010, &ixRFE_PWDN_COMMAND[0], sizeof(ixRFE_PWDN_COMMAND)/sizeof(ixRFE_PWDN_COMMAND[0]), 0, 0 }, + { "ixRFE_PWDN_STATUS", REG_SMC, 0x1080011, &ixRFE_PWDN_STATUS[0], sizeof(ixRFE_PWDN_STATUS)/sizeof(ixRFE_PWDN_STATUS[0]), 0, 0 }, + { "ixRFE_MST_PCIEW0_CMDSTATUS", REG_SMC, 0x1080020, &ixRFE_MST_PCIEW0_CMDSTATUS[0], sizeof(ixRFE_MST_PCIEW0_CMDSTATUS)/sizeof(ixRFE_MST_PCIEW0_CMDSTATUS[0]), 0, 0 }, + { "ixRFE_MST_PCIEW1_CMDSTATUS", REG_SMC, 0x1080021, &ixRFE_MST_PCIEW1_CMDSTATUS[0], sizeof(ixRFE_MST_PCIEW1_CMDSTATUS)/sizeof(ixRFE_MST_PCIEW1_CMDSTATUS[0]), 0, 0 }, + { "ixRFE_MST_RWREG_RFEWRC_CMDSTATUS", REG_SMC, 0x1080022, &ixRFE_MST_RWREG_RFEWRC_CMDSTATUS[0], sizeof(ixRFE_MST_RWREG_RFEWRC_CMDSTATUS)/sizeof(ixRFE_MST_RWREG_RFEWRC_CMDSTATUS[0]), 0, 0 }, + { "ixRFE_MST_TMOUT_STATUS", REG_SMC, 0x108003f, &ixRFE_MST_TMOUT_STATUS[0], sizeof(ixRFE_MST_TMOUT_STATUS)/sizeof(ixRFE_MST_TMOUT_STATUS[0]), 0, 0 }, + { "ixRFE_IMPARBH_CONTROL", REG_SMC, 0x1080083, &ixRFE_IMPARBH_CONTROL[0], sizeof(ixRFE_IMPARBH_CONTROL)/sizeof(ixRFE_IMPARBH_CONTROL[0]), 0, 0 }, + { "ixRFE_IMPARBH_STATUS", REG_SMC, 0x1085140, &ixRFE_IMPARBH_STATUS[0], sizeof(ixRFE_IMPARBH_STATUS)/sizeof(ixRFE_IMPARBH_STATUS[0]), 0, 0 }, + { "ixRFE_IMPRST_CNTL", REG_SMC, 0x1085160, &ixRFE_IMPRST_CNTL[0], sizeof(ixRFE_IMPRST_CNTL)/sizeof(ixRFE_IMPRST_CNTL[0]), 0, 0 }, + { "ixRFE_WARMRST_CNTL", REG_SMC, 0x1085164, &ixRFE_WARMRST_CNTL[0], sizeof(ixRFE_WARMRST_CNTL)/sizeof(ixRFE_WARMRST_CNTL[0]), 0, 0 }, + { "ixMM_INDEX_IND", REG_SMC, 0x1090000, &ixMM_INDEX_IND[0], sizeof(ixMM_INDEX_IND)/sizeof(ixMM_INDEX_IND[0]), 0, 0 }, + { "ixMM_DATA_IND", REG_SMC, 0x1090001, &ixMM_DATA_IND[0], sizeof(ixMM_DATA_IND)/sizeof(ixMM_DATA_IND[0]), 0, 0 }, + { "ixMM_INDEX_HI_IND", REG_SMC, 0x1090006, &ixMM_INDEX_HI_IND[0], sizeof(ixMM_INDEX_HI_IND)/sizeof(ixMM_INDEX_HI_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_0_IND", REG_SMC, 0x10905c9, &ixBIOS_SCRATCH_0_IND[0], sizeof(ixBIOS_SCRATCH_0_IND)/sizeof(ixBIOS_SCRATCH_0_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_1_IND", REG_SMC, 0x10905ca, &ixBIOS_SCRATCH_1_IND[0], sizeof(ixBIOS_SCRATCH_1_IND)/sizeof(ixBIOS_SCRATCH_1_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_2_IND", REG_SMC, 0x10905cb, &ixBIOS_SCRATCH_2_IND[0], sizeof(ixBIOS_SCRATCH_2_IND)/sizeof(ixBIOS_SCRATCH_2_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_3_IND", REG_SMC, 0x10905cc, &ixBIOS_SCRATCH_3_IND[0], sizeof(ixBIOS_SCRATCH_3_IND)/sizeof(ixBIOS_SCRATCH_3_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_4_IND", REG_SMC, 0x10905cd, &ixBIOS_SCRATCH_4_IND[0], sizeof(ixBIOS_SCRATCH_4_IND)/sizeof(ixBIOS_SCRATCH_4_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_5_IND", REG_SMC, 0x10905ce, &ixBIOS_SCRATCH_5_IND[0], sizeof(ixBIOS_SCRATCH_5_IND)/sizeof(ixBIOS_SCRATCH_5_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_6_IND", REG_SMC, 0x10905cf, &ixBIOS_SCRATCH_6_IND[0], sizeof(ixBIOS_SCRATCH_6_IND)/sizeof(ixBIOS_SCRATCH_6_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_7_IND", REG_SMC, 0x10905d0, &ixBIOS_SCRATCH_7_IND[0], sizeof(ixBIOS_SCRATCH_7_IND)/sizeof(ixBIOS_SCRATCH_7_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_8_IND", REG_SMC, 0x10905d1, &ixBIOS_SCRATCH_8_IND[0], sizeof(ixBIOS_SCRATCH_8_IND)/sizeof(ixBIOS_SCRATCH_8_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_9_IND", REG_SMC, 0x10905d2, &ixBIOS_SCRATCH_9_IND[0], sizeof(ixBIOS_SCRATCH_9_IND)/sizeof(ixBIOS_SCRATCH_9_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_10_IND", REG_SMC, 0x10905d3, &ixBIOS_SCRATCH_10_IND[0], sizeof(ixBIOS_SCRATCH_10_IND)/sizeof(ixBIOS_SCRATCH_10_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_11_IND", REG_SMC, 0x10905d4, &ixBIOS_SCRATCH_11_IND[0], sizeof(ixBIOS_SCRATCH_11_IND)/sizeof(ixBIOS_SCRATCH_11_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_12_IND", REG_SMC, 0x10905d5, &ixBIOS_SCRATCH_12_IND[0], sizeof(ixBIOS_SCRATCH_12_IND)/sizeof(ixBIOS_SCRATCH_12_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_13_IND", REG_SMC, 0x10905d6, &ixBIOS_SCRATCH_13_IND[0], sizeof(ixBIOS_SCRATCH_13_IND)/sizeof(ixBIOS_SCRATCH_13_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_14_IND", REG_SMC, 0x10905d7, &ixBIOS_SCRATCH_14_IND[0], sizeof(ixBIOS_SCRATCH_14_IND)/sizeof(ixBIOS_SCRATCH_14_IND[0]), 0, 0 }, + { "ixBIOS_SCRATCH_15_IND", REG_SMC, 0x10905d8, &ixBIOS_SCRATCH_15_IND[0], sizeof(ixBIOS_SCRATCH_15_IND)/sizeof(ixBIOS_SCRATCH_15_IND[0]), 0, 0 }, + { "ixGARLIC_FLUSH_CNTL_IND", REG_SMC, 0x1091401, &ixGARLIC_FLUSH_CNTL_IND[0], sizeof(ixGARLIC_FLUSH_CNTL_IND)/sizeof(ixGARLIC_FLUSH_CNTL_IND[0]), 0, 0 }, + { "ixGARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091412, &ixGARLIC_FLUSH_REQ_IND[0], sizeof(ixGARLIC_FLUSH_REQ_IND)/sizeof(ixGARLIC_FLUSH_REQ_IND[0]), 0, 0 }, + { "ixGPU_GARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091413, &ixGPU_GARLIC_FLUSH_REQ_IND[0], sizeof(ixGPU_GARLIC_FLUSH_REQ_IND)/sizeof(ixGPU_GARLIC_FLUSH_REQ_IND[0]), 0, 0 }, + { "ixGPU_GARLIC_FLUSH_DONE_IND", REG_SMC, 0x1091414, &ixGPU_GARLIC_FLUSH_DONE_IND[0], sizeof(ixGPU_GARLIC_FLUSH_DONE_IND)/sizeof(ixGPU_GARLIC_FLUSH_DONE_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_RB0_WPTR_IND", REG_SMC, 0x1091415, &ixGARLIC_COHE_CP_RB0_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB0_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB0_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_RB1_WPTR_IND", REG_SMC, 0x1091416, &ixGARLIC_COHE_CP_RB1_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB1_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB1_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_RB2_WPTR_IND", REG_SMC, 0x1091417, &ixGARLIC_COHE_CP_RB2_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB2_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB2_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND", REG_SMC, 0x1091418, &ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND", REG_SMC, 0x1091419, &ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND", REG_SMC, 0x109141a, &ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND", REG_SMC, 0x109141b, &ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND", REG_SMC, 0x109141c, &ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND", REG_SMC, 0x109141d, &ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND[0], sizeof(ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND)/sizeof(ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND", REG_SMC, 0x109141e, &ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND[0], sizeof(ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND)/sizeof(ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND", REG_SMC, 0x109141f, &ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_VCE_RB_WPTR2_IND", REG_SMC, 0x1091420, &ixGARLIC_COHE_VCE_RB_WPTR2_IND[0], sizeof(ixGARLIC_COHE_VCE_RB_WPTR2_IND)/sizeof(ixGARLIC_COHE_VCE_RB_WPTR2_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_VCE_RB_WPTR_IND", REG_SMC, 0x1091421, &ixGARLIC_COHE_VCE_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_VCE_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_VCE_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND", REG_SMC, 0x1091422, &ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND", REG_SMC, 0x1091423, &ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND", REG_SMC, 0x1091424, &ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND[0]), 0, 0 }, + { "ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091425, &ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND[0], sizeof(ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND)/sizeof(ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND[0]), 0, 0 }, + { "ixREMAP_HDP_MEM_FLUSH_CNTL_IND", REG_SMC, 0x1091426, &ixREMAP_HDP_MEM_FLUSH_CNTL_IND[0], sizeof(ixREMAP_HDP_MEM_FLUSH_CNTL_IND)/sizeof(ixREMAP_HDP_MEM_FLUSH_CNTL_IND[0]), 0, 0 }, + { "ixREMAP_HDP_REG_FLUSH_CNTL_IND", REG_SMC, 0x1091427, &ixREMAP_HDP_REG_FLUSH_CNTL_IND[0], sizeof(ixREMAP_HDP_REG_FLUSH_CNTL_IND)/sizeof(ixREMAP_HDP_REG_FLUSH_CNTL_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX0_LOWER_IND", REG_SMC, 0x1091428, &ixBIF_VDDGFX_GFX0_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX0_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX0_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX0_UPPER_IND", REG_SMC, 0x1091429, &ixBIF_VDDGFX_GFX0_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX0_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX0_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX1_LOWER_IND", REG_SMC, 0x109142a, &ixBIF_VDDGFX_GFX1_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX1_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX1_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX1_UPPER_IND", REG_SMC, 0x109142b, &ixBIF_VDDGFX_GFX1_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX1_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX1_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX2_LOWER_IND", REG_SMC, 0x109142c, &ixBIF_VDDGFX_GFX2_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX2_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX2_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX2_UPPER_IND", REG_SMC, 0x109142d, &ixBIF_VDDGFX_GFX2_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX2_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX2_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX3_LOWER_IND", REG_SMC, 0x109142e, &ixBIF_VDDGFX_GFX3_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX3_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX3_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX3_UPPER_IND", REG_SMC, 0x109142f, &ixBIF_VDDGFX_GFX3_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX3_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX3_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX4_LOWER_IND", REG_SMC, 0x1091430, &ixBIF_VDDGFX_GFX4_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX4_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX4_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX4_UPPER_IND", REG_SMC, 0x1091431, &ixBIF_VDDGFX_GFX4_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX4_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX4_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX5_LOWER_IND", REG_SMC, 0x1091432, &ixBIF_VDDGFX_GFX5_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX5_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX5_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_GFX5_UPPER_IND", REG_SMC, 0x1091433, &ixBIF_VDDGFX_GFX5_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX5_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX5_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV1_LOWER_IND", REG_SMC, 0x1091434, &ixBIF_VDDGFX_RSV1_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV1_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV1_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV1_UPPER_IND", REG_SMC, 0x1091435, &ixBIF_VDDGFX_RSV1_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV1_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV1_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV2_LOWER_IND", REG_SMC, 0x1091436, &ixBIF_VDDGFX_RSV2_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV2_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV2_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV2_UPPER_IND", REG_SMC, 0x1091437, &ixBIF_VDDGFX_RSV2_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV2_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV2_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV3_LOWER_IND", REG_SMC, 0x1091438, &ixBIF_VDDGFX_RSV3_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV3_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV3_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV3_UPPER_IND", REG_SMC, 0x1091439, &ixBIF_VDDGFX_RSV3_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV3_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV3_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV4_LOWER_IND", REG_SMC, 0x109143a, &ixBIF_VDDGFX_RSV4_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV4_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV4_LOWER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_RSV4_UPPER_IND", REG_SMC, 0x109143b, &ixBIF_VDDGFX_RSV4_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV4_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV4_UPPER_IND[0]), 0, 0 }, + { "ixBIF_VDDGFX_FB_CMP_IND", REG_SMC, 0x109143c, &ixBIF_VDDGFX_FB_CMP_IND[0], sizeof(ixBIF_VDDGFX_FB_CMP_IND)/sizeof(ixBIF_VDDGFX_FB_CMP_IND[0]), 0, 0 }, + { "ixBIF_SMU_INDEX_IND", REG_SMC, 0x109143d, &ixBIF_SMU_INDEX_IND[0], sizeof(ixBIF_SMU_INDEX_IND)/sizeof(ixBIF_SMU_INDEX_IND[0]), 0, 0 }, + { "ixBIF_SMU_DATA_IND", REG_SMC, 0x109143e, &ixBIF_SMU_DATA_IND[0], sizeof(ixBIF_SMU_DATA_IND)/sizeof(ixBIF_SMU_DATA_IND[0]), 0, 0 }, + { "ixBIF_XDMA_LO_IND", REG_SMC, 0x10914c0, &ixBIF_XDMA_LO_IND[0], sizeof(ixBIF_XDMA_LO_IND)/sizeof(ixBIF_XDMA_LO_IND[0]), 0, 0 }, + { "ixBIF_XDMA_HI_IND", REG_SMC, 0x10914c1, &ixBIF_XDMA_HI_IND[0], sizeof(ixBIF_XDMA_HI_IND)/sizeof(ixBIF_XDMA_HI_IND[0]), 0, 0 }, + { "ixBIF_FEATURES_CONTROL_MISC_IND", REG_SMC, 0x10914c2, &ixBIF_FEATURES_CONTROL_MISC_IND[0], sizeof(ixBIF_FEATURES_CONTROL_MISC_IND)/sizeof(ixBIF_FEATURES_CONTROL_MISC_IND[0]), 0, 0 }, + { "ixBIF_DOORBELL_CNTL_IND", REG_SMC, 0x10914c3, &ixBIF_DOORBELL_CNTL_IND[0], sizeof(ixBIF_DOORBELL_CNTL_IND)/sizeof(ixBIF_DOORBELL_CNTL_IND[0]), 0, 0 }, + { "ixBIF_SLVARB_MODE_IND", REG_SMC, 0x10914c4, &ixBIF_SLVARB_MODE_IND[0], sizeof(ixBIF_SLVARB_MODE_IND)/sizeof(ixBIF_SLVARB_MODE_IND[0]), 0, 0 }, + { "ixSMBUS_BACO_DUMMY_IND", REG_SMC, 0x10914c6, &ixSMBUS_BACO_DUMMY_IND[0], sizeof(ixSMBUS_BACO_DUMMY_IND)/sizeof(ixSMBUS_BACO_DUMMY_IND[0]), 0, 0 }, + { "ixBF_ANA_ISO_CNTL_IND", REG_SMC, 0x10914c7, &ixBF_ANA_ISO_CNTL_IND[0], sizeof(ixBF_ANA_ISO_CNTL_IND)/sizeof(ixBF_ANA_ISO_CNTL_IND[0]), 0, 0 }, + { "ixBACO_CNTL_MISC_IND", REG_SMC, 0x10914db, &ixBACO_CNTL_MISC_IND[0], sizeof(ixBACO_CNTL_MISC_IND)/sizeof(ixBACO_CNTL_MISC_IND[0]), 0, 0 }, + { "ixBIF_BACO_DEBUG_LATCH_IND", REG_SMC, 0x10914dc, &ixBIF_BACO_DEBUG_LATCH_IND[0], sizeof(ixBIF_BACO_DEBUG_LATCH_IND)/sizeof(ixBIF_BACO_DEBUG_LATCH_IND[0]), 0, 0 }, + { "ixBIF_BACO_DEBUG_IND", REG_SMC, 0x10914df, &ixBIF_BACO_DEBUG_IND[0], sizeof(ixBIF_BACO_DEBUG_IND)/sizeof(ixBIF_BACO_DEBUG_IND[0]), 0, 0 }, + { "ixMEM_TYPE_CNTL_IND", REG_SMC, 0x10914e4, &ixMEM_TYPE_CNTL_IND[0], sizeof(ixMEM_TYPE_CNTL_IND)/sizeof(ixMEM_TYPE_CNTL_IND[0]), 0, 0 }, + { "ixBACO_CNTL_IND", REG_SMC, 0x10914e5, &ixBACO_CNTL_IND[0], sizeof(ixBACO_CNTL_IND)/sizeof(ixBACO_CNTL_IND[0]), 0, 0 }, + { "ixBIF_DEVFUNCNUM_LIST1_IND", REG_SMC, 0x10914e7, &ixBIF_DEVFUNCNUM_LIST1_IND[0], sizeof(ixBIF_DEVFUNCNUM_LIST1_IND)/sizeof(ixBIF_DEVFUNCNUM_LIST1_IND[0]), 0, 0 }, + { "ixBIF_DEVFUNCNUM_LIST0_IND", REG_SMC, 0x10914e8, &ixBIF_DEVFUNCNUM_LIST0_IND[0], sizeof(ixBIF_DEVFUNCNUM_LIST0_IND)/sizeof(ixBIF_DEVFUNCNUM_LIST0_IND[0]), 0, 0 }, + { "ixDBG_BYPASS_SRBM_ACCESS_IND", REG_SMC, 0x10914eb, &ixDBG_BYPASS_SRBM_ACCESS_IND[0], sizeof(ixDBG_BYPASS_SRBM_ACCESS_IND)/sizeof(ixDBG_BYPASS_SRBM_ACCESS_IND[0]), 0, 0 }, + { "ixPEER3_FB_OFFSET_LO_IND", REG_SMC, 0x10914ec, &ixPEER3_FB_OFFSET_LO_IND[0], sizeof(ixPEER3_FB_OFFSET_LO_IND)/sizeof(ixPEER3_FB_OFFSET_LO_IND[0]), 0, 0 }, + { "ixPEER3_FB_OFFSET_HI_IND", REG_SMC, 0x10914ed, &ixPEER3_FB_OFFSET_HI_IND[0], sizeof(ixPEER3_FB_OFFSET_HI_IND)/sizeof(ixPEER3_FB_OFFSET_HI_IND[0]), 0, 0 }, + { "ixPEER2_FB_OFFSET_LO_IND", REG_SMC, 0x10914ee, &ixPEER2_FB_OFFSET_LO_IND[0], sizeof(ixPEER2_FB_OFFSET_LO_IND)/sizeof(ixPEER2_FB_OFFSET_LO_IND[0]), 0, 0 }, + { "ixPEER2_FB_OFFSET_HI_IND", REG_SMC, 0x10914ef, &ixPEER2_FB_OFFSET_HI_IND[0], sizeof(ixPEER2_FB_OFFSET_HI_IND)/sizeof(ixPEER2_FB_OFFSET_HI_IND[0]), 0, 0 }, + { "ixPEER1_FB_OFFSET_LO_IND", REG_SMC, 0x10914f0, &ixPEER1_FB_OFFSET_LO_IND[0], sizeof(ixPEER1_FB_OFFSET_LO_IND)/sizeof(ixPEER1_FB_OFFSET_LO_IND[0]), 0, 0 }, + { "ixPEER1_FB_OFFSET_HI_IND", REG_SMC, 0x10914f1, &ixPEER1_FB_OFFSET_HI_IND[0], sizeof(ixPEER1_FB_OFFSET_HI_IND)/sizeof(ixPEER1_FB_OFFSET_HI_IND[0]), 0, 0 }, + { "ixPEER0_FB_OFFSET_LO_IND", REG_SMC, 0x10914f2, &ixPEER0_FB_OFFSET_LO_IND[0], sizeof(ixPEER0_FB_OFFSET_LO_IND)/sizeof(ixPEER0_FB_OFFSET_LO_IND[0]), 0, 0 }, + { "ixPEER0_FB_OFFSET_HI_IND", REG_SMC, 0x10914f3, &ixPEER0_FB_OFFSET_HI_IND[0], sizeof(ixPEER0_FB_OFFSET_HI_IND)/sizeof(ixPEER0_FB_OFFSET_HI_IND[0]), 0, 0 }, + { "ixIMPCTL_RESET_IND", REG_SMC, 0x10914f5, &ixIMPCTL_RESET_IND[0], sizeof(ixIMPCTL_RESET_IND)/sizeof(ixIMPCTL_RESET_IND[0]), 0, 0 }, + { "ixSMU_BIF_VDDGFX_PWR_STATUS_IND", REG_SMC, 0x10914f8, &ixSMU_BIF_VDDGFX_PWR_STATUS_IND[0], sizeof(ixSMU_BIF_VDDGFX_PWR_STATUS_IND)/sizeof(ixSMU_BIF_VDDGFX_PWR_STATUS_IND[0]), 0, 0 }, + { "ixBIF_DOORBELL_GBLAPER1_LOWER_IND", REG_SMC, 0x10914fc, &ixBIF_DOORBELL_GBLAPER1_LOWER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER1_LOWER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER1_LOWER_IND[0]), 0, 0 }, + { "ixBIF_DOORBELL_GBLAPER1_UPPER_IND", REG_SMC, 0x10914fd, &ixBIF_DOORBELL_GBLAPER1_UPPER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER1_UPPER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER1_UPPER_IND[0]), 0, 0 }, + { "ixBIF_DOORBELL_GBLAPER2_LOWER_IND", REG_SMC, 0x10914fe, &ixBIF_DOORBELL_GBLAPER2_LOWER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER2_LOWER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER2_LOWER_IND[0]), 0, 0 }, + { "ixBIF_DOORBELL_GBLAPER2_UPPER_IND", REG_SMC, 0x10914ff, &ixBIF_DOORBELL_GBLAPER2_UPPER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER2_UPPER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER2_UPPER_IND[0]), 0, 0 }, + { "ixBIF_MM_INDACCESS_CNTL_IND", REG_SMC, 0x1091500, &ixBIF_MM_INDACCESS_CNTL_IND[0], sizeof(ixBIF_MM_INDACCESS_CNTL_IND)/sizeof(ixBIF_MM_INDACCESS_CNTL_IND[0]), 0, 0 }, + { "ixBUS_CNTL_IND", REG_SMC, 0x1091508, &ixBUS_CNTL_IND[0], sizeof(ixBUS_CNTL_IND)/sizeof(ixBUS_CNTL_IND[0]), 0, 0 }, + { "ixCONFIG_CNTL_IND", REG_SMC, 0x1091509, &ixCONFIG_CNTL_IND[0], sizeof(ixCONFIG_CNTL_IND)/sizeof(ixCONFIG_CNTL_IND[0]), 0, 0 }, + { "ixCONFIG_MEMSIZE_IND", REG_SMC, 0x109150a, &ixCONFIG_MEMSIZE_IND[0], sizeof(ixCONFIG_MEMSIZE_IND)/sizeof(ixCONFIG_MEMSIZE_IND[0]), 0, 0 }, + { "ixCONFIG_F0_BASE_IND", REG_SMC, 0x109150b, &ixCONFIG_F0_BASE_IND[0], sizeof(ixCONFIG_F0_BASE_IND)/sizeof(ixCONFIG_F0_BASE_IND[0]), 0, 0 }, + { "ixCONFIG_APER_SIZE_IND", REG_SMC, 0x109150c, &ixCONFIG_APER_SIZE_IND[0], sizeof(ixCONFIG_APER_SIZE_IND)/sizeof(ixCONFIG_APER_SIZE_IND[0]), 0, 0 }, + { "ixCONFIG_REG_APER_SIZE_IND", REG_SMC, 0x109150d, &ixCONFIG_REG_APER_SIZE_IND[0], sizeof(ixCONFIG_REG_APER_SIZE_IND)/sizeof(ixCONFIG_REG_APER_SIZE_IND[0]), 0, 0 }, + { "ixBIF_SCRATCH0_IND", REG_SMC, 0x109150e, &ixBIF_SCRATCH0_IND[0], sizeof(ixBIF_SCRATCH0_IND)/sizeof(ixBIF_SCRATCH0_IND[0]), 0, 0 }, + { "ixBIF_SCRATCH1_IND", REG_SMC, 0x109150f, &ixBIF_SCRATCH1_IND[0], sizeof(ixBIF_SCRATCH1_IND)/sizeof(ixBIF_SCRATCH1_IND[0]), 0, 0 }, + { "ixMM_CFGREGS_CNTL_IND", REG_SMC, 0x1091513, &ixMM_CFGREGS_CNTL_IND[0], sizeof(ixMM_CFGREGS_CNTL_IND)/sizeof(ixMM_CFGREGS_CNTL_IND[0]), 0, 0 }, + { "ixBX_RESET_EN_IND", REG_SMC, 0x1091514, &ixBX_RESET_EN_IND[0], sizeof(ixBX_RESET_EN_IND)/sizeof(ixBX_RESET_EN_IND[0]), 0, 0 }, + { "ixHW_DEBUG_IND", REG_SMC, 0x1091515, &ixHW_DEBUG_IND[0], sizeof(ixHW_DEBUG_IND)/sizeof(ixHW_DEBUG_IND[0]), 0, 0 }, + { "ixMASTER_CREDIT_CNTL_IND", REG_SMC, 0x1091516, &ixMASTER_CREDIT_CNTL_IND[0], sizeof(ixMASTER_CREDIT_CNTL_IND)/sizeof(ixMASTER_CREDIT_CNTL_IND[0]), 0, 0 }, + { "ixSLAVE_REQ_CREDIT_CNTL_IND", REG_SMC, 0x1091517, &ixSLAVE_REQ_CREDIT_CNTL_IND[0], sizeof(ixSLAVE_REQ_CREDIT_CNTL_IND)/sizeof(ixSLAVE_REQ_CREDIT_CNTL_IND[0]), 0, 0 }, + { "ixBX_RESET_CNTL_IND", REG_SMC, 0x1091518, &ixBX_RESET_CNTL_IND[0], sizeof(ixBX_RESET_CNTL_IND)/sizeof(ixBX_RESET_CNTL_IND[0]), 0, 0 }, + { "ixINTERRUPT_CNTL_IND", REG_SMC, 0x109151a, &ixINTERRUPT_CNTL_IND[0], sizeof(ixINTERRUPT_CNTL_IND)/sizeof(ixINTERRUPT_CNTL_IND[0]), 0, 0 }, + { "ixINTERRUPT_CNTL2_IND", REG_SMC, 0x109151b, &ixINTERRUPT_CNTL2_IND[0], sizeof(ixINTERRUPT_CNTL2_IND)/sizeof(ixINTERRUPT_CNTL2_IND[0]), 0, 0 }, + { "ixBIF_DEBUG_CNTL_IND", REG_SMC, 0x109151c, &ixBIF_DEBUG_CNTL_IND[0], sizeof(ixBIF_DEBUG_CNTL_IND)/sizeof(ixBIF_DEBUG_CNTL_IND[0]), 0, 0 }, + { "ixBIF_DEBUG_MUX_IND", REG_SMC, 0x109151d, &ixBIF_DEBUG_MUX_IND[0], sizeof(ixBIF_DEBUG_MUX_IND)/sizeof(ixBIF_DEBUG_MUX_IND[0]), 0, 0 }, + { "ixBIF_DEBUG_OUT_IND", REG_SMC, 0x109151e, &ixBIF_DEBUG_OUT_IND[0], sizeof(ixBIF_DEBUG_OUT_IND)/sizeof(ixBIF_DEBUG_OUT_IND[0]), 0, 0 }, + { "ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND", REG_SMC, 0x1091520, &ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND[0], sizeof(ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND)/sizeof(ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND[0]), 0, 0 }, + { "ixCLKREQB_PAD_CNTL_IND", REG_SMC, 0x1091521, &ixCLKREQB_PAD_CNTL_IND[0], sizeof(ixCLKREQB_PAD_CNTL_IND)/sizeof(ixCLKREQB_PAD_CNTL_IND[0]), 0, 0 }, + { "ixSMBDAT_PAD_CNTL_IND", REG_SMC, 0x1091522, &ixSMBDAT_PAD_CNTL_IND[0], sizeof(ixSMBDAT_PAD_CNTL_IND)/sizeof(ixSMBDAT_PAD_CNTL_IND[0]), 0, 0 }, + { "ixSMBCLK_PAD_CNTL_IND", REG_SMC, 0x1091523, &ixSMBCLK_PAD_CNTL_IND[0], sizeof(ixSMBCLK_PAD_CNTL_IND)/sizeof(ixSMBCLK_PAD_CNTL_IND[0]), 0, 0 }, + { "ixBIF_FB_EN_IND", REG_SMC, 0x1091524, &ixBIF_FB_EN_IND[0], sizeof(ixBIF_FB_EN_IND)/sizeof(ixBIF_FB_EN_IND[0]), 0, 0 }, + { "ixBIF_BUSNUM_CNTL1_IND", REG_SMC, 0x1091525, &ixBIF_BUSNUM_CNTL1_IND[0], sizeof(ixBIF_BUSNUM_CNTL1_IND)/sizeof(ixBIF_BUSNUM_CNTL1_IND[0]), 0, 0 }, + { "ixBIF_BUSNUM_LIST0_IND", REG_SMC, 0x1091526, &ixBIF_BUSNUM_LIST0_IND[0], sizeof(ixBIF_BUSNUM_LIST0_IND)/sizeof(ixBIF_BUSNUM_LIST0_IND[0]), 0, 0 }, + { "ixBIF_BUSNUM_LIST1_IND", REG_SMC, 0x1091527, &ixBIF_BUSNUM_LIST1_IND[0], sizeof(ixBIF_BUSNUM_LIST1_IND)/sizeof(ixBIF_BUSNUM_LIST1_IND[0]), 0, 0 }, + { "ixHDP_REG_COHERENCY_FLUSH_CNTL_IND", REG_SMC, 0x1091528, &ixHDP_REG_COHERENCY_FLUSH_CNTL_IND[0], sizeof(ixHDP_REG_COHERENCY_FLUSH_CNTL_IND)/sizeof(ixHDP_REG_COHERENCY_FLUSH_CNTL_IND[0]), 0, 0 }, + { "ixBIF_BUSY_DELAY_CNTR_IND", REG_SMC, 0x1091529, &ixBIF_BUSY_DELAY_CNTR_IND[0], sizeof(ixBIF_BUSY_DELAY_CNTR_IND)/sizeof(ixBIF_BUSY_DELAY_CNTR_IND[0]), 0, 0 }, + { "ixBIF_BUSNUM_CNTL2_IND", REG_SMC, 0x109152b, &ixBIF_BUSNUM_CNTL2_IND[0], sizeof(ixBIF_BUSNUM_CNTL2_IND)/sizeof(ixBIF_BUSNUM_CNTL2_IND[0]), 0, 0 }, + { "ixBIF_PERFMON_CNTL_IND", REG_SMC, 0x109152c, &ixBIF_PERFMON_CNTL_IND[0], sizeof(ixBIF_PERFMON_CNTL_IND)/sizeof(ixBIF_PERFMON_CNTL_IND[0]), 0, 0 }, + { "ixBIF_PERFCOUNTER0_RESULT_IND", REG_SMC, 0x109152d, &ixBIF_PERFCOUNTER0_RESULT_IND[0], sizeof(ixBIF_PERFCOUNTER0_RESULT_IND)/sizeof(ixBIF_PERFCOUNTER0_RESULT_IND[0]), 0, 0 }, + { "ixBIF_PERFCOUNTER1_RESULT_IND", REG_SMC, 0x109152e, &ixBIF_PERFCOUNTER1_RESULT_IND[0], sizeof(ixBIF_PERFCOUNTER1_RESULT_IND)/sizeof(ixBIF_PERFCOUNTER1_RESULT_IND[0]), 0, 0 }, + { "ixBIF_RB_CNTL_IND", REG_SMC, 0x1091530, &ixBIF_RB_CNTL_IND[0], sizeof(ixBIF_RB_CNTL_IND)/sizeof(ixBIF_RB_CNTL_IND[0]), 0, 0 }, + { "ixBIF_RB_BASE_IND", REG_SMC, 0x1091531, &ixBIF_RB_BASE_IND[0], sizeof(ixBIF_RB_BASE_IND)/sizeof(ixBIF_RB_BASE_IND[0]), 0, 0 }, + { "ixBIF_RB_RPTR_IND", REG_SMC, 0x1091532, &ixBIF_RB_RPTR_IND[0], sizeof(ixBIF_RB_RPTR_IND)/sizeof(ixBIF_RB_RPTR_IND[0]), 0, 0 }, + { "ixBIF_RB_WPTR_IND", REG_SMC, 0x1091533, &ixBIF_RB_WPTR_IND[0], sizeof(ixBIF_RB_WPTR_IND)/sizeof(ixBIF_RB_WPTR_IND[0]), 0, 0 }, + { "ixBIF_RB_WPTR_ADDR_HI_IND", REG_SMC, 0x1091534, &ixBIF_RB_WPTR_ADDR_HI_IND[0], sizeof(ixBIF_RB_WPTR_ADDR_HI_IND)/sizeof(ixBIF_RB_WPTR_ADDR_HI_IND[0]), 0, 0 }, + { "ixBIF_RB_WPTR_ADDR_LO_IND", REG_SMC, 0x1091535, &ixBIF_RB_WPTR_ADDR_LO_IND[0], sizeof(ixBIF_RB_WPTR_ADDR_LO_IND)/sizeof(ixBIF_RB_WPTR_ADDR_LO_IND[0]), 0, 0 }, + { "ixSLAVE_HANG_PROTECTION_CNTL_IND", REG_SMC, 0x1091536, &ixSLAVE_HANG_PROTECTION_CNTL_IND[0], sizeof(ixSLAVE_HANG_PROTECTION_CNTL_IND)/sizeof(ixSLAVE_HANG_PROTECTION_CNTL_IND[0]), 0, 0 }, + { "ixGPU_HDP_FLUSH_REQ_IND", REG_SMC, 0x1091537, &ixGPU_HDP_FLUSH_REQ_IND[0], sizeof(ixGPU_HDP_FLUSH_REQ_IND)/sizeof(ixGPU_HDP_FLUSH_REQ_IND[0]), 0, 0 }, + { "ixGPU_HDP_FLUSH_DONE_IND", REG_SMC, 0x1091538, &ixGPU_HDP_FLUSH_DONE_IND[0], sizeof(ixGPU_HDP_FLUSH_DONE_IND)/sizeof(ixGPU_HDP_FLUSH_DONE_IND[0]), 0, 0 }, + { "ixSLAVE_HANG_ERROR_IND", REG_SMC, 0x109153b, &ixSLAVE_HANG_ERROR_IND[0], sizeof(ixSLAVE_HANG_ERROR_IND)/sizeof(ixSLAVE_HANG_ERROR_IND[0]), 0, 0 }, + { "ixCAPTURE_HOST_BUSNUM_IND", REG_SMC, 0x109153c, &ixCAPTURE_HOST_BUSNUM_IND[0], sizeof(ixCAPTURE_HOST_BUSNUM_IND)/sizeof(ixCAPTURE_HOST_BUSNUM_IND[0]), 0, 0 }, + { "ixHOST_BUSNUM_IND", REG_SMC, 0x109153d, &ixHOST_BUSNUM_IND[0], sizeof(ixHOST_BUSNUM_IND)/sizeof(ixHOST_BUSNUM_IND[0]), 0, 0 }, + { "ixPEER_REG_RANGE0_IND", REG_SMC, 0x109153e, &ixPEER_REG_RANGE0_IND[0], sizeof(ixPEER_REG_RANGE0_IND)/sizeof(ixPEER_REG_RANGE0_IND[0]), 0, 0 }, + { "ixPEER_REG_RANGE1_IND", REG_SMC, 0x109153f, &ixPEER_REG_RANGE1_IND[0], sizeof(ixPEER_REG_RANGE1_IND)/sizeof(ixPEER_REG_RANGE1_IND[0]), 0, 0 }, + { "ixPSX80_PIF0_SCRATCH", REG_SMC, 0x1100001, &ixPSX80_PIF0_SCRATCH[0], sizeof(ixPSX80_PIF0_SCRATCH)/sizeof(ixPSX80_PIF0_SCRATCH[0]), 0, 0 }, + { "ixPSX80_PIF0_HW_DEBUG", REG_SMC, 0x1100002, &ixPSX80_PIF0_HW_DEBUG[0], sizeof(ixPSX80_PIF0_HW_DEBUG)/sizeof(ixPSX80_PIF0_HW_DEBUG[0]), 0, 0 }, + { "ixPSX80_PIF0_STRAP_0", REG_SMC, 0x1100003, &ixPSX80_PIF0_STRAP_0[0], sizeof(ixPSX80_PIF0_STRAP_0)/sizeof(ixPSX80_PIF0_STRAP_0[0]), 0, 0 }, + { "ixPSX80_PIF0_CTRL", REG_SMC, 0x1100004, &ixPSX80_PIF0_CTRL[0], sizeof(ixPSX80_PIF0_CTRL)/sizeof(ixPSX80_PIF0_CTRL[0]), 0, 0 }, + { "ixPSX80_PIF0_TX_CTRL", REG_SMC, 0x1100008, &ixPSX80_PIF0_TX_CTRL[0], sizeof(ixPSX80_PIF0_TX_CTRL)/sizeof(ixPSX80_PIF0_TX_CTRL[0]), 0, 0 }, + { "ixPSX80_PIF0_TX_CTRL2", REG_SMC, 0x1100009, &ixPSX80_PIF0_TX_CTRL2[0], sizeof(ixPSX80_PIF0_TX_CTRL2)/sizeof(ixPSX80_PIF0_TX_CTRL2[0]), 0, 0 }, + { "ixPSX80_PIF0_RX_CTRL", REG_SMC, 0x110000a, &ixPSX80_PIF0_RX_CTRL[0], sizeof(ixPSX80_PIF0_RX_CTRL)/sizeof(ixPSX80_PIF0_RX_CTRL[0]), 0, 0 }, + { "ixPSX80_PIF0_RX_CTRL2", REG_SMC, 0x110000b, &ixPSX80_PIF0_RX_CTRL2[0], sizeof(ixPSX80_PIF0_RX_CTRL2)/sizeof(ixPSX80_PIF0_RX_CTRL2[0]), 0, 0 }, + { "ixPSX80_PIF0_GLB_OVRD", REG_SMC, 0x110000c, &ixPSX80_PIF0_GLB_OVRD[0], sizeof(ixPSX80_PIF0_GLB_OVRD)/sizeof(ixPSX80_PIF0_GLB_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_GLB_OVRD2", REG_SMC, 0x110000d, &ixPSX80_PIF0_GLB_OVRD2[0], sizeof(ixPSX80_PIF0_GLB_OVRD2)/sizeof(ixPSX80_PIF0_GLB_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_BIF_CMD_STATUS", REG_SMC, 0x1100010, &ixPSX80_PIF0_BIF_CMD_STATUS[0], sizeof(ixPSX80_PIF0_BIF_CMD_STATUS)/sizeof(ixPSX80_PIF0_BIF_CMD_STATUS[0]), 0, 0 }, + { "ixPSX80_PIF0_CMD_BUS_CTRL", REG_SMC, 0x1100011, &ixPSX80_PIF0_CMD_BUS_CTRL[0], sizeof(ixPSX80_PIF0_CMD_BUS_CTRL)/sizeof(ixPSX80_PIF0_CMD_BUS_CTRL[0]), 0, 0 }, + { "ixPSX80_PIF0_CMD_BUS_GLB_OVRD", REG_SMC, 0x1100013, &ixPSX80_PIF0_CMD_BUS_GLB_OVRD[0], sizeof(ixPSX80_PIF0_CMD_BUS_GLB_OVRD)/sizeof(ixPSX80_PIF0_CMD_BUS_GLB_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE0_OVRD", REG_SMC, 0x1100014, &ixPSX80_PIF0_LANE0_OVRD[0], sizeof(ixPSX80_PIF0_LANE0_OVRD)/sizeof(ixPSX80_PIF0_LANE0_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE0_OVRD2", REG_SMC, 0x1100015, &ixPSX80_PIF0_LANE0_OVRD2[0], sizeof(ixPSX80_PIF0_LANE0_OVRD2)/sizeof(ixPSX80_PIF0_LANE0_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE1_OVRD", REG_SMC, 0x1100016, &ixPSX80_PIF0_LANE1_OVRD[0], sizeof(ixPSX80_PIF0_LANE1_OVRD)/sizeof(ixPSX80_PIF0_LANE1_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE1_OVRD2", REG_SMC, 0x1100017, &ixPSX80_PIF0_LANE1_OVRD2[0], sizeof(ixPSX80_PIF0_LANE1_OVRD2)/sizeof(ixPSX80_PIF0_LANE1_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE2_OVRD", REG_SMC, 0x1100018, &ixPSX80_PIF0_LANE2_OVRD[0], sizeof(ixPSX80_PIF0_LANE2_OVRD)/sizeof(ixPSX80_PIF0_LANE2_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE2_OVRD2", REG_SMC, 0x1100019, &ixPSX80_PIF0_LANE2_OVRD2[0], sizeof(ixPSX80_PIF0_LANE2_OVRD2)/sizeof(ixPSX80_PIF0_LANE2_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE3_OVRD", REG_SMC, 0x110001a, &ixPSX80_PIF0_LANE3_OVRD[0], sizeof(ixPSX80_PIF0_LANE3_OVRD)/sizeof(ixPSX80_PIF0_LANE3_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE3_OVRD2", REG_SMC, 0x110001b, &ixPSX80_PIF0_LANE3_OVRD2[0], sizeof(ixPSX80_PIF0_LANE3_OVRD2)/sizeof(ixPSX80_PIF0_LANE3_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE4_OVRD", REG_SMC, 0x110001c, &ixPSX80_PIF0_LANE4_OVRD[0], sizeof(ixPSX80_PIF0_LANE4_OVRD)/sizeof(ixPSX80_PIF0_LANE4_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE4_OVRD2", REG_SMC, 0x110001d, &ixPSX80_PIF0_LANE4_OVRD2[0], sizeof(ixPSX80_PIF0_LANE4_OVRD2)/sizeof(ixPSX80_PIF0_LANE4_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE5_OVRD", REG_SMC, 0x110001e, &ixPSX80_PIF0_LANE5_OVRD[0], sizeof(ixPSX80_PIF0_LANE5_OVRD)/sizeof(ixPSX80_PIF0_LANE5_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE5_OVRD2", REG_SMC, 0x110001f, &ixPSX80_PIF0_LANE5_OVRD2[0], sizeof(ixPSX80_PIF0_LANE5_OVRD2)/sizeof(ixPSX80_PIF0_LANE5_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE6_OVRD", REG_SMC, 0x1100020, &ixPSX80_PIF0_LANE6_OVRD[0], sizeof(ixPSX80_PIF0_LANE6_OVRD)/sizeof(ixPSX80_PIF0_LANE6_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE6_OVRD2", REG_SMC, 0x1100021, &ixPSX80_PIF0_LANE6_OVRD2[0], sizeof(ixPSX80_PIF0_LANE6_OVRD2)/sizeof(ixPSX80_PIF0_LANE6_OVRD2[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE7_OVRD", REG_SMC, 0x1100022, &ixPSX80_PIF0_LANE7_OVRD[0], sizeof(ixPSX80_PIF0_LANE7_OVRD)/sizeof(ixPSX80_PIF0_LANE7_OVRD[0]), 0, 0 }, + { "ixPSX80_PIF0_LANE7_OVRD2", REG_SMC, 0x1100023, &ixPSX80_PIF0_LANE7_OVRD2[0], sizeof(ixPSX80_PIF0_LANE7_OVRD2)/sizeof(ixPSX80_PIF0_LANE7_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_SCRATCH", REG_SMC, 0x1110001, &ixPSX81_PIF0_SCRATCH[0], sizeof(ixPSX81_PIF0_SCRATCH)/sizeof(ixPSX81_PIF0_SCRATCH[0]), 0, 0 }, + { "ixPSX81_PIF0_HW_DEBUG", REG_SMC, 0x1110002, &ixPSX81_PIF0_HW_DEBUG[0], sizeof(ixPSX81_PIF0_HW_DEBUG)/sizeof(ixPSX81_PIF0_HW_DEBUG[0]), 0, 0 }, + { "ixPSX81_PIF0_STRAP_0", REG_SMC, 0x1110003, &ixPSX81_PIF0_STRAP_0[0], sizeof(ixPSX81_PIF0_STRAP_0)/sizeof(ixPSX81_PIF0_STRAP_0[0]), 0, 0 }, + { "ixPSX81_PIF0_CTRL", REG_SMC, 0x1110004, &ixPSX81_PIF0_CTRL[0], sizeof(ixPSX81_PIF0_CTRL)/sizeof(ixPSX81_PIF0_CTRL[0]), 0, 0 }, + { "ixPSX81_PIF0_TX_CTRL", REG_SMC, 0x1110008, &ixPSX81_PIF0_TX_CTRL[0], sizeof(ixPSX81_PIF0_TX_CTRL)/sizeof(ixPSX81_PIF0_TX_CTRL[0]), 0, 0 }, + { "ixPSX81_PIF0_TX_CTRL2", REG_SMC, 0x1110009, &ixPSX81_PIF0_TX_CTRL2[0], sizeof(ixPSX81_PIF0_TX_CTRL2)/sizeof(ixPSX81_PIF0_TX_CTRL2[0]), 0, 0 }, + { "ixPSX81_PIF0_RX_CTRL", REG_SMC, 0x111000a, &ixPSX81_PIF0_RX_CTRL[0], sizeof(ixPSX81_PIF0_RX_CTRL)/sizeof(ixPSX81_PIF0_RX_CTRL[0]), 0, 0 }, + { "ixPSX81_PIF0_RX_CTRL2", REG_SMC, 0x111000b, &ixPSX81_PIF0_RX_CTRL2[0], sizeof(ixPSX81_PIF0_RX_CTRL2)/sizeof(ixPSX81_PIF0_RX_CTRL2[0]), 0, 0 }, + { "ixPSX81_PIF0_GLB_OVRD", REG_SMC, 0x111000c, &ixPSX81_PIF0_GLB_OVRD[0], sizeof(ixPSX81_PIF0_GLB_OVRD)/sizeof(ixPSX81_PIF0_GLB_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_GLB_OVRD2", REG_SMC, 0x111000d, &ixPSX81_PIF0_GLB_OVRD2[0], sizeof(ixPSX81_PIF0_GLB_OVRD2)/sizeof(ixPSX81_PIF0_GLB_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_BIF_CMD_STATUS", REG_SMC, 0x1110010, &ixPSX81_PIF0_BIF_CMD_STATUS[0], sizeof(ixPSX81_PIF0_BIF_CMD_STATUS)/sizeof(ixPSX81_PIF0_BIF_CMD_STATUS[0]), 0, 0 }, + { "ixPSX81_PIF0_CMD_BUS_CTRL", REG_SMC, 0x1110011, &ixPSX81_PIF0_CMD_BUS_CTRL[0], sizeof(ixPSX81_PIF0_CMD_BUS_CTRL)/sizeof(ixPSX81_PIF0_CMD_BUS_CTRL[0]), 0, 0 }, + { "ixPSX81_PIF0_CMD_BUS_GLB_OVRD", REG_SMC, 0x1110013, &ixPSX81_PIF0_CMD_BUS_GLB_OVRD[0], sizeof(ixPSX81_PIF0_CMD_BUS_GLB_OVRD)/sizeof(ixPSX81_PIF0_CMD_BUS_GLB_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE0_OVRD", REG_SMC, 0x1110014, &ixPSX81_PIF0_LANE0_OVRD[0], sizeof(ixPSX81_PIF0_LANE0_OVRD)/sizeof(ixPSX81_PIF0_LANE0_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE0_OVRD2", REG_SMC, 0x1110015, &ixPSX81_PIF0_LANE0_OVRD2[0], sizeof(ixPSX81_PIF0_LANE0_OVRD2)/sizeof(ixPSX81_PIF0_LANE0_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE1_OVRD", REG_SMC, 0x1110016, &ixPSX81_PIF0_LANE1_OVRD[0], sizeof(ixPSX81_PIF0_LANE1_OVRD)/sizeof(ixPSX81_PIF0_LANE1_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE1_OVRD2", REG_SMC, 0x1110017, &ixPSX81_PIF0_LANE1_OVRD2[0], sizeof(ixPSX81_PIF0_LANE1_OVRD2)/sizeof(ixPSX81_PIF0_LANE1_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE2_OVRD", REG_SMC, 0x1110018, &ixPSX81_PIF0_LANE2_OVRD[0], sizeof(ixPSX81_PIF0_LANE2_OVRD)/sizeof(ixPSX81_PIF0_LANE2_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE2_OVRD2", REG_SMC, 0x1110019, &ixPSX81_PIF0_LANE2_OVRD2[0], sizeof(ixPSX81_PIF0_LANE2_OVRD2)/sizeof(ixPSX81_PIF0_LANE2_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE3_OVRD", REG_SMC, 0x111001a, &ixPSX81_PIF0_LANE3_OVRD[0], sizeof(ixPSX81_PIF0_LANE3_OVRD)/sizeof(ixPSX81_PIF0_LANE3_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE3_OVRD2", REG_SMC, 0x111001b, &ixPSX81_PIF0_LANE3_OVRD2[0], sizeof(ixPSX81_PIF0_LANE3_OVRD2)/sizeof(ixPSX81_PIF0_LANE3_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE4_OVRD", REG_SMC, 0x111001c, &ixPSX81_PIF0_LANE4_OVRD[0], sizeof(ixPSX81_PIF0_LANE4_OVRD)/sizeof(ixPSX81_PIF0_LANE4_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE4_OVRD2", REG_SMC, 0x111001d, &ixPSX81_PIF0_LANE4_OVRD2[0], sizeof(ixPSX81_PIF0_LANE4_OVRD2)/sizeof(ixPSX81_PIF0_LANE4_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE5_OVRD", REG_SMC, 0x111001e, &ixPSX81_PIF0_LANE5_OVRD[0], sizeof(ixPSX81_PIF0_LANE5_OVRD)/sizeof(ixPSX81_PIF0_LANE5_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE5_OVRD2", REG_SMC, 0x111001f, &ixPSX81_PIF0_LANE5_OVRD2[0], sizeof(ixPSX81_PIF0_LANE5_OVRD2)/sizeof(ixPSX81_PIF0_LANE5_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE6_OVRD", REG_SMC, 0x1110020, &ixPSX81_PIF0_LANE6_OVRD[0], sizeof(ixPSX81_PIF0_LANE6_OVRD)/sizeof(ixPSX81_PIF0_LANE6_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE6_OVRD2", REG_SMC, 0x1110021, &ixPSX81_PIF0_LANE6_OVRD2[0], sizeof(ixPSX81_PIF0_LANE6_OVRD2)/sizeof(ixPSX81_PIF0_LANE6_OVRD2[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE7_OVRD", REG_SMC, 0x1110022, &ixPSX81_PIF0_LANE7_OVRD[0], sizeof(ixPSX81_PIF0_LANE7_OVRD)/sizeof(ixPSX81_PIF0_LANE7_OVRD[0]), 0, 0 }, + { "ixPSX81_PIF0_LANE7_OVRD2", REG_SMC, 0x1110023, &ixPSX81_PIF0_LANE7_OVRD2[0], sizeof(ixPSX81_PIF0_LANE7_OVRD2)/sizeof(ixPSX81_PIF0_LANE7_OVRD2[0]), 0, 0 }, + { "mmVENDOR_CAP_LIST", REG_MMIO, 0x12, &mmVENDOR_CAP_LIST[0], sizeof(mmVENDOR_CAP_LIST)/sizeof(mmVENDOR_CAP_LIST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0", REG_SMC, 0x1200000, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0", REG_SMC, 0x1200001, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE0", REG_SMC, 0x1200002, &ixPSX80_PHY0_RX_RX_CTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE0)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE0", REG_SMC, 0x1200003, &ixPSX80_PHY0_RX_DLL_CTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE0)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE0", REG_SMC, 0x1200004, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE0[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE0)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0", REG_SMC, 0x1200005, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE0", REG_SMC, 0x120000a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE0", REG_SMC, 0x120000b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE0)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0", REG_SMC, 0x120000c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0", REG_SMC, 0x120000d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE0", REG_SMC, 0x120000e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1", REG_SMC, 0x1200100, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1", REG_SMC, 0x1200101, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE1", REG_SMC, 0x1200102, &ixPSX80_PHY0_RX_RX_CTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE1)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE1", REG_SMC, 0x1200103, &ixPSX80_PHY0_RX_DLL_CTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE1)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE1", REG_SMC, 0x1200104, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE1[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE1)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1", REG_SMC, 0x1200105, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE1", REG_SMC, 0x120010a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE1", REG_SMC, 0x120010b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE1)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1", REG_SMC, 0x120010c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1", REG_SMC, 0x120010d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE1", REG_SMC, 0x120010e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2", REG_SMC, 0x1200200, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2", REG_SMC, 0x1200201, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE2", REG_SMC, 0x1200202, &ixPSX80_PHY0_RX_RX_CTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE2)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE2", REG_SMC, 0x1200203, &ixPSX80_PHY0_RX_DLL_CTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE2)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE2", REG_SMC, 0x1200204, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE2[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE2)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2", REG_SMC, 0x1200205, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE2", REG_SMC, 0x120020a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE2", REG_SMC, 0x120020b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE2)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2", REG_SMC, 0x120020c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2", REG_SMC, 0x120020d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE2", REG_SMC, 0x120020e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3", REG_SMC, 0x1200300, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3", REG_SMC, 0x1200301, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE3", REG_SMC, 0x1200302, &ixPSX80_PHY0_RX_RX_CTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE3)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE3", REG_SMC, 0x1200303, &ixPSX80_PHY0_RX_DLL_CTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE3)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE3", REG_SMC, 0x1200304, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE3[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE3)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3", REG_SMC, 0x1200305, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE3", REG_SMC, 0x120030a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE3", REG_SMC, 0x120030b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE3)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3", REG_SMC, 0x120030c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3", REG_SMC, 0x120030d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE3", REG_SMC, 0x120030e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4", REG_SMC, 0x1200400, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4", REG_SMC, 0x1200401, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE4", REG_SMC, 0x1200402, &ixPSX80_PHY0_RX_RX_CTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE4)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE4", REG_SMC, 0x1200403, &ixPSX80_PHY0_RX_DLL_CTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE4)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE4", REG_SMC, 0x1200404, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE4[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE4)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4", REG_SMC, 0x1200405, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE4", REG_SMC, 0x120040a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE4", REG_SMC, 0x120040b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE4)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4", REG_SMC, 0x120040c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4", REG_SMC, 0x120040d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE4", REG_SMC, 0x120040e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5", REG_SMC, 0x1200500, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5", REG_SMC, 0x1200501, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE5", REG_SMC, 0x1200502, &ixPSX80_PHY0_RX_RX_CTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE5)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE5", REG_SMC, 0x1200503, &ixPSX80_PHY0_RX_DLL_CTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE5)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE5", REG_SMC, 0x1200504, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE5[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE5)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5", REG_SMC, 0x1200505, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE5", REG_SMC, 0x120050a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE5", REG_SMC, 0x120050b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE5)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5", REG_SMC, 0x120050c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5", REG_SMC, 0x120050d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE5", REG_SMC, 0x120050e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6", REG_SMC, 0x1200600, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6", REG_SMC, 0x1200601, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE6", REG_SMC, 0x1200602, &ixPSX80_PHY0_RX_RX_CTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE6)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE6", REG_SMC, 0x1200603, &ixPSX80_PHY0_RX_DLL_CTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE6)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE6", REG_SMC, 0x1200604, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE6[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE6)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6", REG_SMC, 0x1200605, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE6", REG_SMC, 0x120060a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE6", REG_SMC, 0x120060b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE6)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6", REG_SMC, 0x120060c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6", REG_SMC, 0x120060d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE6", REG_SMC, 0x120060e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7", REG_SMC, 0x1200700, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7", REG_SMC, 0x1200701, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_LANE7", REG_SMC, 0x1200702, &ixPSX80_PHY0_RX_RX_CTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE7)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_LANE7", REG_SMC, 0x1200703, &ixPSX80_PHY0_RX_DLL_CTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE7)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_LANE7", REG_SMC, 0x1200704, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE7[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE7)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7", REG_SMC, 0x1200705, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_LANE7", REG_SMC, 0x120070a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_LANE7", REG_SMC, 0x120070b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE7)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7", REG_SMC, 0x120070c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7", REG_SMC, 0x120070d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_LANE7", REG_SMC, 0x120070e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0", REG_SMC, 0x1202000, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE0", REG_SMC, 0x1202001, &ixPSX80_PHY0_TX_DFX_LANE0[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE0)/sizeof(ixPSX80_PHY0_TX_DFX_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE0", REG_SMC, 0x1202002, &ixPSX80_PHY0_TX_DEEMPH_LANE0[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE0)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0", REG_SMC, 0x1202003, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0", REG_SMC, 0x1202004, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE0", REG_SMC, 0x1202006, &ixPSX80_PHY0_TX_TXCNTRL_LANE0[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE0)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_SMC, 0x1202007, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1", REG_SMC, 0x1202100, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE1", REG_SMC, 0x1202101, &ixPSX80_PHY0_TX_DFX_LANE1[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE1)/sizeof(ixPSX80_PHY0_TX_DFX_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE1", REG_SMC, 0x1202102, &ixPSX80_PHY0_TX_DEEMPH_LANE1[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE1)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1", REG_SMC, 0x1202103, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1", REG_SMC, 0x1202104, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE1", REG_SMC, 0x1202106, &ixPSX80_PHY0_TX_TXCNTRL_LANE1[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE1)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_SMC, 0x1202107, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2", REG_SMC, 0x1202200, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE2", REG_SMC, 0x1202201, &ixPSX80_PHY0_TX_DFX_LANE2[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE2)/sizeof(ixPSX80_PHY0_TX_DFX_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE2", REG_SMC, 0x1202202, &ixPSX80_PHY0_TX_DEEMPH_LANE2[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE2)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2", REG_SMC, 0x1202203, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2", REG_SMC, 0x1202204, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE2", REG_SMC, 0x1202206, &ixPSX80_PHY0_TX_TXCNTRL_LANE2[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE2)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_SMC, 0x1202207, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3", REG_SMC, 0x1202300, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE3", REG_SMC, 0x1202301, &ixPSX80_PHY0_TX_DFX_LANE3[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE3)/sizeof(ixPSX80_PHY0_TX_DFX_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE3", REG_SMC, 0x1202302, &ixPSX80_PHY0_TX_DEEMPH_LANE3[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE3)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3", REG_SMC, 0x1202303, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3", REG_SMC, 0x1202304, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE3", REG_SMC, 0x1202306, &ixPSX80_PHY0_TX_TXCNTRL_LANE3[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE3)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_SMC, 0x1202307, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4", REG_SMC, 0x1202400, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE4", REG_SMC, 0x1202401, &ixPSX80_PHY0_TX_DFX_LANE4[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE4)/sizeof(ixPSX80_PHY0_TX_DFX_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE4", REG_SMC, 0x1202402, &ixPSX80_PHY0_TX_DEEMPH_LANE4[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE4)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4", REG_SMC, 0x1202403, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4", REG_SMC, 0x1202404, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE4", REG_SMC, 0x1202406, &ixPSX80_PHY0_TX_TXCNTRL_LANE4[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE4)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4", REG_SMC, 0x1202407, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5", REG_SMC, 0x1202500, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE5", REG_SMC, 0x1202501, &ixPSX80_PHY0_TX_DFX_LANE5[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE5)/sizeof(ixPSX80_PHY0_TX_DFX_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE5", REG_SMC, 0x1202502, &ixPSX80_PHY0_TX_DEEMPH_LANE5[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE5)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5", REG_SMC, 0x1202503, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5", REG_SMC, 0x1202504, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE5", REG_SMC, 0x1202506, &ixPSX80_PHY0_TX_TXCNTRL_LANE5[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE5)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5", REG_SMC, 0x1202507, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6", REG_SMC, 0x1202600, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE6", REG_SMC, 0x1202601, &ixPSX80_PHY0_TX_DFX_LANE6[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE6)/sizeof(ixPSX80_PHY0_TX_DFX_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE6", REG_SMC, 0x1202602, &ixPSX80_PHY0_TX_DEEMPH_LANE6[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE6)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6", REG_SMC, 0x1202603, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6", REG_SMC, 0x1202604, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE6", REG_SMC, 0x1202606, &ixPSX80_PHY0_TX_TXCNTRL_LANE6[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE6)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6", REG_SMC, 0x1202607, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7", REG_SMC, 0x1202700, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_LANE7", REG_SMC, 0x1202701, &ixPSX80_PHY0_TX_DFX_LANE7[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE7)/sizeof(ixPSX80_PHY0_TX_DFX_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_LANE7", REG_SMC, 0x1202702, &ixPSX80_PHY0_TX_DEEMPH_LANE7[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE7)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7", REG_SMC, 0x1202703, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7", REG_SMC, 0x1202704, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_LANE7", REG_SMC, 0x1202706, &ixPSX80_PHY0_TX_TXCNTRL_LANE7[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE7)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7", REG_SMC, 0x1202707, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt", REG_SMC, 0x1204001, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl", REG_SMC, 0x1204002, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1", REG_SMC, 0x1204003, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2", REG_SMC, 0x1204004, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode", REG_SMC, 0x1204005, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl", REG_SMC, 0x1204007, &ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl", REG_SMC, 0x1204008, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3", REG_SMC, 0x1204009, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4", REG_SMC, 0x120400b, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5", REG_SMC, 0x120400c, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0]), 0, 0 }, + { "ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn", REG_SMC, 0x1204080, &ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt", REG_SMC, 0x1204101, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl", REG_SMC, 0x1204102, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1", REG_SMC, 0x1204103, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2", REG_SMC, 0x1204104, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode", REG_SMC, 0x1204105, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl", REG_SMC, 0x1204108, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3", REG_SMC, 0x1204109, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess", REG_SMC, 0x120410a, &ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4", REG_SMC, 0x120410b, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5", REG_SMC, 0x120410c, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0]), 0, 0 }, + { "ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn", REG_SMC, 0x1204180, &ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_FUSE1", REG_SMC, 0x1206200, &ixPSX80_PHY0_COM_COMMON_FUSE1[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE1)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE1[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_FUSE2", REG_SMC, 0x1206201, &ixPSX80_PHY0_COM_COMMON_FUSE2[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE2)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE2[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_FUSE3", REG_SMC, 0x1206202, &ixPSX80_PHY0_COM_COMMON_FUSE3[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE3)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE3[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ELECIDLE", REG_SMC, 0x1206204, &ixPSX80_PHY0_COM_COMMON_ELECIDLE[0], sizeof(ixPSX80_PHY0_COM_COMMON_ELECIDLE)/sizeof(ixPSX80_PHY0_COM_COMMON_ELECIDLE[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_DFX", REG_SMC, 0x1206205, &ixPSX80_PHY0_COM_COMMON_DFX[0], sizeof(ixPSX80_PHY0_COM_COMMON_DFX)/sizeof(ixPSX80_PHY0_COM_COMMON_DFX[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM", REG_SMC, 0x1206206, &ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0], sizeof(ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM)/sizeof(ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_SELDEEMPH35", REG_SMC, 0x1206207, &ixPSX80_PHY0_COM_COMMON_SELDEEMPH35[0], sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH35)/sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH35[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_SELDEEMPH60", REG_SMC, 0x1206208, &ixPSX80_PHY0_COM_COMMON_SELDEEMPH60[0], sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH60)/sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH60[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT", REG_SMC, 0x1206209, &ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT[0], sizeof(ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT)/sizeof(ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPTCTL1", REG_SMC, 0x120620a, &ixPSX80_PHY0_COM_COMMON_ADAPTCTL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL1[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPTCTL2", REG_SMC, 0x120620b, &ixPSX80_PHY0_COM_COMMON_ADAPTCTL2[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL2)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL2[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL", REG_SMC, 0x120620c, &ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1", REG_SMC, 0x120620d, &ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL", REG_SMC, 0x120620e, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1", REG_SMC, 0x120620f, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1", REG_SMC, 0x1206210, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_LNCNTRL", REG_SMC, 0x1206211, &ixPSX80_PHY0_COM_COMMON_LNCNTRL[0], sizeof(ixPSX80_PHY0_COM_COMMON_LNCNTRL)/sizeof(ixPSX80_PHY0_COM_COMMON_LNCNTRL[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG", REG_SMC, 0x1206212, &ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG[0], sizeof(ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG)/sizeof(ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG", REG_SMC, 0x1206213, &ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG[0], sizeof(ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG)/sizeof(ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_CDR_PHCTL", REG_SMC, 0x1206214, &ixPSX80_PHY0_COM_COMMON_CDR_PHCTL[0], sizeof(ixPSX80_PHY0_COM_COMMON_CDR_PHCTL)/sizeof(ixPSX80_PHY0_COM_COMMON_CDR_PHCTL[0]), 0, 0 }, + { "ixPSX80_PHY0_COM_COMMON_CDR_FRCTL", REG_SMC, 0x1206215, &ixPSX80_PHY0_COM_COMMON_CDR_FRCTL[0], sizeof(ixPSX80_PHY0_COM_COMMON_CDR_FRCTL)/sizeof(ixPSX80_PHY0_COM_COMMON_CDR_FRCTL[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST", REG_SMC, 0x120fe00, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST", REG_SMC, 0x120fe01, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RX_CTL_BROADCAST", REG_SMC, 0x120fe02, &ixPSX80_PHY0_RX_RX_CTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_RX_CTL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DLL_CTL_BROADCAST", REG_SMC, 0x120fe03, &ixPSX80_PHY0_RX_DLL_CTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST", REG_SMC, 0x120fe04, &ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST", REG_SMC, 0x120fe05, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST", REG_SMC, 0x120fe0a, &ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST", REG_SMC, 0x120fe0b, &ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST", REG_SMC, 0x120fe0c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST", REG_SMC, 0x120fe0d, &ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST", REG_SMC, 0x120fe0e, &ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST", REG_SMC, 0x120ff00, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DFX_BROADCAST", REG_SMC, 0x120ff01, &ixPSX80_PHY0_TX_DFX_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_DFX_BROADCAST)/sizeof(ixPSX80_PHY0_TX_DFX_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_DEEMPH_BROADCAST", REG_SMC, 0x120ff02, &ixPSX80_PHY0_TX_DEEMPH_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_BROADCAST)/sizeof(ixPSX80_PHY0_TX_DEEMPH_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST", REG_SMC, 0x120ff03, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST", REG_SMC, 0x120ff04, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_TXCNTRL_BROADCAST", REG_SMC, 0x120ff06, &ixPSX80_PHY0_TX_TXCNTRL_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_BROADCAST)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_BROADCAST[0]), 0, 0 }, + { "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST", REG_SMC, 0x120ff07, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0", REG_SMC, 0x1210000, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0", REG_SMC, 0x1210001, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE0", REG_SMC, 0x1210002, &ixPSX81_PHY0_RX_RX_CTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE0)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE0", REG_SMC, 0x1210003, &ixPSX81_PHY0_RX_DLL_CTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE0)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE0", REG_SMC, 0x1210004, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE0[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE0)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0", REG_SMC, 0x1210005, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE0", REG_SMC, 0x121000a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE0", REG_SMC, 0x121000b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE0)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0", REG_SMC, 0x121000c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0", REG_SMC, 0x121000d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE0", REG_SMC, 0x121000e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1", REG_SMC, 0x1210100, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1", REG_SMC, 0x1210101, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE1", REG_SMC, 0x1210102, &ixPSX81_PHY0_RX_RX_CTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE1)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE1", REG_SMC, 0x1210103, &ixPSX81_PHY0_RX_DLL_CTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE1)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE1", REG_SMC, 0x1210104, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE1[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE1)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1", REG_SMC, 0x1210105, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE1", REG_SMC, 0x121010a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE1", REG_SMC, 0x121010b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE1)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1", REG_SMC, 0x121010c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1", REG_SMC, 0x121010d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE1", REG_SMC, 0x121010e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2", REG_SMC, 0x1210200, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2", REG_SMC, 0x1210201, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE2", REG_SMC, 0x1210202, &ixPSX81_PHY0_RX_RX_CTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE2)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE2", REG_SMC, 0x1210203, &ixPSX81_PHY0_RX_DLL_CTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE2)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE2", REG_SMC, 0x1210204, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE2[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE2)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2", REG_SMC, 0x1210205, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE2", REG_SMC, 0x121020a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE2", REG_SMC, 0x121020b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE2)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2", REG_SMC, 0x121020c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2", REG_SMC, 0x121020d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE2", REG_SMC, 0x121020e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3", REG_SMC, 0x1210300, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3", REG_SMC, 0x1210301, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE3", REG_SMC, 0x1210302, &ixPSX81_PHY0_RX_RX_CTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE3)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE3", REG_SMC, 0x1210303, &ixPSX81_PHY0_RX_DLL_CTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE3)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE3", REG_SMC, 0x1210304, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE3[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE3)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3", REG_SMC, 0x1210305, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE3", REG_SMC, 0x121030a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE3", REG_SMC, 0x121030b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE3)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3", REG_SMC, 0x121030c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3", REG_SMC, 0x121030d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE3", REG_SMC, 0x121030e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4", REG_SMC, 0x1210400, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4", REG_SMC, 0x1210401, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE4", REG_SMC, 0x1210402, &ixPSX81_PHY0_RX_RX_CTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE4)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE4", REG_SMC, 0x1210403, &ixPSX81_PHY0_RX_DLL_CTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE4)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE4", REG_SMC, 0x1210404, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE4[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE4)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4", REG_SMC, 0x1210405, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE4", REG_SMC, 0x121040a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE4", REG_SMC, 0x121040b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE4)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4", REG_SMC, 0x121040c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4", REG_SMC, 0x121040d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE4", REG_SMC, 0x121040e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5", REG_SMC, 0x1210500, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5", REG_SMC, 0x1210501, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE5", REG_SMC, 0x1210502, &ixPSX81_PHY0_RX_RX_CTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE5)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE5", REG_SMC, 0x1210503, &ixPSX81_PHY0_RX_DLL_CTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE5)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE5", REG_SMC, 0x1210504, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE5[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE5)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5", REG_SMC, 0x1210505, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE5", REG_SMC, 0x121050a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE5", REG_SMC, 0x121050b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE5)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5", REG_SMC, 0x121050c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5", REG_SMC, 0x121050d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE5", REG_SMC, 0x121050e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6", REG_SMC, 0x1210600, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6", REG_SMC, 0x1210601, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE6", REG_SMC, 0x1210602, &ixPSX81_PHY0_RX_RX_CTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE6)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE6", REG_SMC, 0x1210603, &ixPSX81_PHY0_RX_DLL_CTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE6)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE6", REG_SMC, 0x1210604, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE6[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE6)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6", REG_SMC, 0x1210605, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE6", REG_SMC, 0x121060a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE6", REG_SMC, 0x121060b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE6)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6", REG_SMC, 0x121060c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6", REG_SMC, 0x121060d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE6", REG_SMC, 0x121060e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7", REG_SMC, 0x1210700, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7", REG_SMC, 0x1210701, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_LANE7", REG_SMC, 0x1210702, &ixPSX81_PHY0_RX_RX_CTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE7)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_LANE7", REG_SMC, 0x1210703, &ixPSX81_PHY0_RX_DLL_CTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE7)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_LANE7", REG_SMC, 0x1210704, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE7[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE7)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7", REG_SMC, 0x1210705, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_LANE7", REG_SMC, 0x121070a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_LANE7", REG_SMC, 0x121070b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE7)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7", REG_SMC, 0x121070c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7", REG_SMC, 0x121070d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_LANE7", REG_SMC, 0x121070e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0", REG_SMC, 0x1212000, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE0", REG_SMC, 0x1212001, &ixPSX81_PHY0_TX_DFX_LANE0[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE0)/sizeof(ixPSX81_PHY0_TX_DFX_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE0", REG_SMC, 0x1212002, &ixPSX81_PHY0_TX_DEEMPH_LANE0[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE0)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0", REG_SMC, 0x1212003, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0", REG_SMC, 0x1212004, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE0", REG_SMC, 0x1212006, &ixPSX81_PHY0_TX_TXCNTRL_LANE0[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE0)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_SMC, 0x1212007, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1", REG_SMC, 0x1212100, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE1", REG_SMC, 0x1212101, &ixPSX81_PHY0_TX_DFX_LANE1[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE1)/sizeof(ixPSX81_PHY0_TX_DFX_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE1", REG_SMC, 0x1212102, &ixPSX81_PHY0_TX_DEEMPH_LANE1[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE1)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1", REG_SMC, 0x1212103, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1", REG_SMC, 0x1212104, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE1", REG_SMC, 0x1212106, &ixPSX81_PHY0_TX_TXCNTRL_LANE1[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE1)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_SMC, 0x1212107, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2", REG_SMC, 0x1212200, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE2", REG_SMC, 0x1212201, &ixPSX81_PHY0_TX_DFX_LANE2[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE2)/sizeof(ixPSX81_PHY0_TX_DFX_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE2", REG_SMC, 0x1212202, &ixPSX81_PHY0_TX_DEEMPH_LANE2[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE2)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2", REG_SMC, 0x1212203, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2", REG_SMC, 0x1212204, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE2", REG_SMC, 0x1212206, &ixPSX81_PHY0_TX_TXCNTRL_LANE2[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE2)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_SMC, 0x1212207, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3", REG_SMC, 0x1212300, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE3", REG_SMC, 0x1212301, &ixPSX81_PHY0_TX_DFX_LANE3[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE3)/sizeof(ixPSX81_PHY0_TX_DFX_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE3", REG_SMC, 0x1212302, &ixPSX81_PHY0_TX_DEEMPH_LANE3[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE3)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3", REG_SMC, 0x1212303, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3", REG_SMC, 0x1212304, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE3", REG_SMC, 0x1212306, &ixPSX81_PHY0_TX_TXCNTRL_LANE3[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE3)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_SMC, 0x1212307, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4", REG_SMC, 0x1212400, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE4", REG_SMC, 0x1212401, &ixPSX81_PHY0_TX_DFX_LANE4[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE4)/sizeof(ixPSX81_PHY0_TX_DFX_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE4", REG_SMC, 0x1212402, &ixPSX81_PHY0_TX_DEEMPH_LANE4[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE4)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4", REG_SMC, 0x1212403, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4", REG_SMC, 0x1212404, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE4", REG_SMC, 0x1212406, &ixPSX81_PHY0_TX_TXCNTRL_LANE4[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE4)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4", REG_SMC, 0x1212407, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5", REG_SMC, 0x1212500, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE5", REG_SMC, 0x1212501, &ixPSX81_PHY0_TX_DFX_LANE5[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE5)/sizeof(ixPSX81_PHY0_TX_DFX_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE5", REG_SMC, 0x1212502, &ixPSX81_PHY0_TX_DEEMPH_LANE5[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE5)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5", REG_SMC, 0x1212503, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5", REG_SMC, 0x1212504, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE5", REG_SMC, 0x1212506, &ixPSX81_PHY0_TX_TXCNTRL_LANE5[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE5)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5", REG_SMC, 0x1212507, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6", REG_SMC, 0x1212600, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE6", REG_SMC, 0x1212601, &ixPSX81_PHY0_TX_DFX_LANE6[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE6)/sizeof(ixPSX81_PHY0_TX_DFX_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE6", REG_SMC, 0x1212602, &ixPSX81_PHY0_TX_DEEMPH_LANE6[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE6)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6", REG_SMC, 0x1212603, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6", REG_SMC, 0x1212604, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE6", REG_SMC, 0x1212606, &ixPSX81_PHY0_TX_TXCNTRL_LANE6[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE6)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6", REG_SMC, 0x1212607, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7", REG_SMC, 0x1212700, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_LANE7", REG_SMC, 0x1212701, &ixPSX81_PHY0_TX_DFX_LANE7[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE7)/sizeof(ixPSX81_PHY0_TX_DFX_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_LANE7", REG_SMC, 0x1212702, &ixPSX81_PHY0_TX_DEEMPH_LANE7[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE7)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7", REG_SMC, 0x1212703, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7", REG_SMC, 0x1212704, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_LANE7", REG_SMC, 0x1212706, &ixPSX81_PHY0_TX_TXCNTRL_LANE7[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE7)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7", REG_SMC, 0x1212707, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt", REG_SMC, 0x1214001, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl", REG_SMC, 0x1214002, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1", REG_SMC, 0x1214003, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2", REG_SMC, 0x1214004, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode", REG_SMC, 0x1214005, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl", REG_SMC, 0x1214007, &ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl", REG_SMC, 0x1214008, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3", REG_SMC, 0x1214009, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4", REG_SMC, 0x121400b, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5", REG_SMC, 0x121400c, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0]), 0, 0 }, + { "ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn", REG_SMC, 0x1214080, &ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt", REG_SMC, 0x1214101, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl", REG_SMC, 0x1214102, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1", REG_SMC, 0x1214103, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2", REG_SMC, 0x1214104, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode", REG_SMC, 0x1214105, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl", REG_SMC, 0x1214108, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3", REG_SMC, 0x1214109, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess", REG_SMC, 0x121410a, &ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4", REG_SMC, 0x121410b, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5", REG_SMC, 0x121410c, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0]), 0, 0 }, + { "ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn", REG_SMC, 0x1214180, &ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_FUSE1", REG_SMC, 0x1216200, &ixPSX81_PHY0_COM_COMMON_FUSE1[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE1)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE1[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_FUSE2", REG_SMC, 0x1216201, &ixPSX81_PHY0_COM_COMMON_FUSE2[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE2)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE2[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_FUSE3", REG_SMC, 0x1216202, &ixPSX81_PHY0_COM_COMMON_FUSE3[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE3)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE3[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ELECIDLE", REG_SMC, 0x1216204, &ixPSX81_PHY0_COM_COMMON_ELECIDLE[0], sizeof(ixPSX81_PHY0_COM_COMMON_ELECIDLE)/sizeof(ixPSX81_PHY0_COM_COMMON_ELECIDLE[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_DFX", REG_SMC, 0x1216205, &ixPSX81_PHY0_COM_COMMON_DFX[0], sizeof(ixPSX81_PHY0_COM_COMMON_DFX)/sizeof(ixPSX81_PHY0_COM_COMMON_DFX[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM", REG_SMC, 0x1216206, &ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0], sizeof(ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM)/sizeof(ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_SELDEEMPH35", REG_SMC, 0x1216207, &ixPSX81_PHY0_COM_COMMON_SELDEEMPH35[0], sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH35)/sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH35[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_SELDEEMPH60", REG_SMC, 0x1216208, &ixPSX81_PHY0_COM_COMMON_SELDEEMPH60[0], sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH60)/sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH60[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT", REG_SMC, 0x1216209, &ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT[0], sizeof(ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT)/sizeof(ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPTCTL1", REG_SMC, 0x121620a, &ixPSX81_PHY0_COM_COMMON_ADAPTCTL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL1[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPTCTL2", REG_SMC, 0x121620b, &ixPSX81_PHY0_COM_COMMON_ADAPTCTL2[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL2)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL2[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL", REG_SMC, 0x121620c, &ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1", REG_SMC, 0x121620d, &ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL", REG_SMC, 0x121620e, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1", REG_SMC, 0x121620f, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1", REG_SMC, 0x1216210, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_LNCNTRL", REG_SMC, 0x1216211, &ixPSX81_PHY0_COM_COMMON_LNCNTRL[0], sizeof(ixPSX81_PHY0_COM_COMMON_LNCNTRL)/sizeof(ixPSX81_PHY0_COM_COMMON_LNCNTRL[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG", REG_SMC, 0x1216212, &ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG[0], sizeof(ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG)/sizeof(ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG", REG_SMC, 0x1216213, &ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG[0], sizeof(ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG)/sizeof(ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_CDR_PHCTL", REG_SMC, 0x1216214, &ixPSX81_PHY0_COM_COMMON_CDR_PHCTL[0], sizeof(ixPSX81_PHY0_COM_COMMON_CDR_PHCTL)/sizeof(ixPSX81_PHY0_COM_COMMON_CDR_PHCTL[0]), 0, 0 }, + { "ixPSX81_PHY0_COM_COMMON_CDR_FRCTL", REG_SMC, 0x1216215, &ixPSX81_PHY0_COM_COMMON_CDR_FRCTL[0], sizeof(ixPSX81_PHY0_COM_COMMON_CDR_FRCTL)/sizeof(ixPSX81_PHY0_COM_COMMON_CDR_FRCTL[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST", REG_SMC, 0x121fe00, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST", REG_SMC, 0x121fe01, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RX_CTL_BROADCAST", REG_SMC, 0x121fe02, &ixPSX81_PHY0_RX_RX_CTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_RX_CTL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DLL_CTL_BROADCAST", REG_SMC, 0x121fe03, &ixPSX81_PHY0_RX_DLL_CTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST", REG_SMC, 0x121fe04, &ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST", REG_SMC, 0x121fe05, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST", REG_SMC, 0x121fe0a, &ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST", REG_SMC, 0x121fe0b, &ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST", REG_SMC, 0x121fe0c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST", REG_SMC, 0x121fe0d, &ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST", REG_SMC, 0x121fe0e, &ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST", REG_SMC, 0x121ff00, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DFX_BROADCAST", REG_SMC, 0x121ff01, &ixPSX81_PHY0_TX_DFX_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_DFX_BROADCAST)/sizeof(ixPSX81_PHY0_TX_DFX_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_DEEMPH_BROADCAST", REG_SMC, 0x121ff02, &ixPSX81_PHY0_TX_DEEMPH_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_BROADCAST)/sizeof(ixPSX81_PHY0_TX_DEEMPH_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST", REG_SMC, 0x121ff03, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST", REG_SMC, 0x121ff04, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_TXCNTRL_BROADCAST", REG_SMC, 0x121ff06, &ixPSX81_PHY0_TX_TXCNTRL_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_BROADCAST)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_BROADCAST[0]), 0, 0 }, + { "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST", REG_SMC, 0x121ff07, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0]), 0, 0 }, + { "mmADAPTER_ID_W", REG_MMIO, 0x13, &mmADAPTER_ID_W[0], sizeof(mmADAPTER_ID_W)/sizeof(mmADAPTER_ID_W[0]), 0, 0 }, + { "ixBIF_BACO_MSIC_IND", REG_SMC, 0x1301480, &ixBIF_BACO_MSIC_IND[0], sizeof(ixBIF_BACO_MSIC_IND)/sizeof(ixBIF_BACO_MSIC_IND[0]), 0, 0 }, + { "ixBIF_PIF_TXCLK_SWITCH_TIMER_IND", REG_SMC, 0x1301481, &ixBIF_PIF_TXCLK_SWITCH_TIMER_IND[0], sizeof(ixBIF_PIF_TXCLK_SWITCH_TIMER_IND)/sizeof(ixBIF_PIF_TXCLK_SWITCH_TIMER_IND[0]), 0, 0 }, + { "ixBIF_RESET_EN_IND", REG_SMC, 0x1301482, &ixBIF_RESET_EN_IND[0], sizeof(ixBIF_RESET_EN_IND)/sizeof(ixBIF_RESET_EN_IND[0]), 0, 0 }, + { "ixBIF_CLK_PDWN_DELAY_TIMER_IND", REG_SMC, 0x1301483, &ixBIF_CLK_PDWN_DELAY_TIMER_IND[0], sizeof(ixBIF_CLK_PDWN_DELAY_TIMER_IND)/sizeof(ixBIF_CLK_PDWN_DELAY_TIMER_IND[0]), 0, 0 }, + { "ixNEW_REFCLKB_TIMER_1_IND", REG_SMC, 0x1301484, &ixNEW_REFCLKB_TIMER_1_IND[0], sizeof(ixNEW_REFCLKB_TIMER_1_IND)/sizeof(ixNEW_REFCLKB_TIMER_1_IND[0]), 0, 0 }, + { "ixNEW_REFCLKB_TIMER_IND", REG_SMC, 0x1301485, &ixNEW_REFCLKB_TIMER_IND[0], sizeof(ixNEW_REFCLKB_TIMER_IND)/sizeof(ixNEW_REFCLKB_TIMER_IND[0]), 0, 0 }, + { "ixBIF_RESET_CNTL_IND", REG_SMC, 0x1301486, &ixBIF_RESET_CNTL_IND[0], sizeof(ixBIF_RESET_CNTL_IND)/sizeof(ixBIF_RESET_CNTL_IND[0]), 0, 0 }, + { "ixLNCNT_CONTROL_IND", REG_SMC, 0x1301487, &ixLNCNT_CONTROL_IND[0], sizeof(ixLNCNT_CONTROL_IND)/sizeof(ixLNCNT_CONTROL_IND[0]), 0, 0 }, + { "ixBIF_LNCNT_RESET_IND", REG_SMC, 0x1301488, &ixBIF_LNCNT_RESET_IND[0], sizeof(ixBIF_LNCNT_RESET_IND)/sizeof(ixBIF_LNCNT_RESET_IND[0]), 0, 0 }, + { "ixBIF_CLOCKS_BITS_IND", REG_SMC, 0x1301489, &ixBIF_CLOCKS_BITS_IND[0], sizeof(ixBIF_CLOCKS_BITS_IND)/sizeof(ixBIF_CLOCKS_BITS_IND[0]), 0, 0 }, + { "ixBIF_MEM_PG_CNTL_IND", REG_SMC, 0x130148a, &ixBIF_MEM_PG_CNTL_IND[0], sizeof(ixBIF_MEM_PG_CNTL_IND)/sizeof(ixBIF_MEM_PG_CNTL_IND[0]), 0, 0 }, + { "ixBIF_RFE_CNTL_MISC_IND", REG_SMC, 0x130148c, &ixBIF_RFE_CNTL_MISC_IND[0], sizeof(ixBIF_RFE_CNTL_MISC_IND)/sizeof(ixBIF_RFE_CNTL_MISC_IND[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_SCRATCH1", REG_SMC, 0x1308001, &ixPSX80_WRP_PCIE_WRAP_SCRATCH1[0], sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH1)/sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH1[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_SCRATCH2", REG_SMC, 0x1308002, &ixPSX80_WRP_PCIE_WRAP_SCRATCH2[0], sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH2)/sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH2[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC", REG_SMC, 0x1308005, &ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_DTM_MISC", REG_SMC, 0x1308006, &ixPSX80_WRP_PCIE_WRAP_DTM_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_DTM_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_DTM_MISC[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN", REG_SMC, 0x1308007, &ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0], sizeof(ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN)/sizeof(ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_MISC", REG_SMC, 0x1308008, &ixPSX80_WRP_PCIE_WRAP_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_MISC[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_WRAP_PIF_MISC", REG_SMC, 0x1308009, &ixPSX80_WRP_PCIE_WRAP_PIF_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_PIF_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_PIF_MISC[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_RXDET_OVERRIDE", REG_SMC, 0x130800a, &ixPSX80_WRP_PCIE_RXDET_OVERRIDE[0], sizeof(ixPSX80_WRP_PCIE_RXDET_OVERRIDE)/sizeof(ixPSX80_WRP_PCIE_RXDET_OVERRIDE[0]), 0, 0 }, + { "ixPSX80_WRP_IMPCTL_CNTL_PIF0", REG_SMC, 0x1308070, &ixPSX80_WRP_IMPCTL_CNTL_PIF0[0], sizeof(ixPSX80_WRP_IMPCTL_CNTL_PIF0)/sizeof(ixPSX80_WRP_IMPCTL_CNTL_PIF0[0]), 0, 0 }, + { "ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL", REG_SMC, 0x1308090, &ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL[0]), 0, 0 }, + { "ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL", REG_SMC, 0x1308096, &ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL[0]), 0, 0 }, + { "ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL", REG_SMC, 0x1308097, &ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL[0]), 0, 0 }, + { "ixPSX80_WRP_REG_ADAPT_pif0_CONTROL", REG_SMC, 0x1308098, &ixPSX80_WRP_REG_ADAPT_pif0_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pif0_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pif0_CONTROL[0]), 0, 0 }, + { "ixPSX80_WRP_BIOSTIMER_CMD", REG_SMC, 0x13080f0, &ixPSX80_WRP_BIOSTIMER_CMD[0], sizeof(ixPSX80_WRP_BIOSTIMER_CMD)/sizeof(ixPSX80_WRP_BIOSTIMER_CMD[0]), 0, 0 }, + { "ixPSX80_WRP_BIOSTIMER_CNTL", REG_SMC, 0x13080f1, &ixPSX80_WRP_BIOSTIMER_CNTL[0], sizeof(ixPSX80_WRP_BIOSTIMER_CNTL)/sizeof(ixPSX80_WRP_BIOSTIMER_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_BIOSTIMER_DEBUG", REG_SMC, 0x13080f2, &ixPSX80_WRP_BIOSTIMER_DEBUG[0], sizeof(ixPSX80_WRP_BIOSTIMER_DEBUG)/sizeof(ixPSX80_WRP_BIOSTIMER_DEBUG[0]), 0, 0 }, + { "ixPSX80_WRP_DELAYLINE_COMMAND", REG_SMC, 0x130ffd0, &ixPSX80_WRP_DELAYLINE_COMMAND[0], sizeof(ixPSX80_WRP_DELAYLINE_COMMAND)/sizeof(ixPSX80_WRP_DELAYLINE_COMMAND[0]), 0, 0 }, + { "ixPSX80_WRP_DELAYLINE_STATUS", REG_SMC, 0x130ffd1, &ixPSX80_WRP_DELAYLINE_STATUS[0], sizeof(ixPSX80_WRP_DELAYLINE_STATUS)/sizeof(ixPSX80_WRP_DELAYLINE_STATUS[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_RX_BP_CNTL", REG_SMC, 0x130ffe0, &ixPSX80_WRP_DTM_RX_BP_CNTL[0], sizeof(ixPSX80_WRP_DTM_RX_BP_CNTL)/sizeof(ixPSX80_WRP_DTM_RX_BP_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_CNTL", REG_SMC, 0x130ffe1, &ixPSX80_WRP_DTM_CNTL[0], sizeof(ixPSX80_WRP_DTM_CNTL)/sizeof(ixPSX80_WRP_DTM_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_CNTL_LEGACY", REG_SMC, 0x130ffe2, &ixPSX80_WRP_DTM_CNTL_LEGACY[0], sizeof(ixPSX80_WRP_DTM_CNTL_LEGACY)/sizeof(ixPSX80_WRP_DTM_CNTL_LEGACY[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_STI_LCLK_CTRL", REG_SMC, 0x130ffe3, &ixPSX80_WRP_DTM_STI_LCLK_CTRL[0], sizeof(ixPSX80_WRP_DTM_STI_LCLK_CTRL)/sizeof(ixPSX80_WRP_DTM_STI_LCLK_CTRL[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x", REG_SMC, 0x130ffe4, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt", REG_SMC, 0x130ffe5, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x", REG_SMC, 0x130ffe6, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0]), 0, 0 }, + { "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt", REG_SMC, 0x130ffe7, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_SCRATCH1", REG_SMC, 0x1318001, &ixPSX81_WRP_PCIE_WRAP_SCRATCH1[0], sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH1)/sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH1[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_SCRATCH2", REG_SMC, 0x1318002, &ixPSX81_WRP_PCIE_WRAP_SCRATCH2[0], sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH2)/sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH2[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC", REG_SMC, 0x1318005, &ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_DTM_MISC", REG_SMC, 0x1318006, &ixPSX81_WRP_PCIE_WRAP_DTM_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_DTM_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_DTM_MISC[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN", REG_SMC, 0x1318007, &ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0], sizeof(ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN)/sizeof(ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_MISC", REG_SMC, 0x1318008, &ixPSX81_WRP_PCIE_WRAP_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_MISC[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_WRAP_PIF_MISC", REG_SMC, 0x1318009, &ixPSX81_WRP_PCIE_WRAP_PIF_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_PIF_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_PIF_MISC[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_RXDET_OVERRIDE", REG_SMC, 0x131800a, &ixPSX81_WRP_PCIE_RXDET_OVERRIDE[0], sizeof(ixPSX81_WRP_PCIE_RXDET_OVERRIDE)/sizeof(ixPSX81_WRP_PCIE_RXDET_OVERRIDE[0]), 0, 0 }, + { "ixPSX81_WRP_IMPCTL_CNTL_PIF0", REG_SMC, 0x1318070, &ixPSX81_WRP_IMPCTL_CNTL_PIF0[0], sizeof(ixPSX81_WRP_IMPCTL_CNTL_PIF0)/sizeof(ixPSX81_WRP_IMPCTL_CNTL_PIF0[0]), 0, 0 }, + { "ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL", REG_SMC, 0x1318090, &ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL[0]), 0, 0 }, + { "ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL", REG_SMC, 0x1318096, &ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL[0]), 0, 0 }, + { "ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL", REG_SMC, 0x1318097, &ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL[0]), 0, 0 }, + { "ixPSX81_WRP_REG_ADAPT_pif0_CONTROL", REG_SMC, 0x1318098, &ixPSX81_WRP_REG_ADAPT_pif0_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pif0_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pif0_CONTROL[0]), 0, 0 }, + { "ixPSX81_WRP_BIOSTIMER_CMD", REG_SMC, 0x13180f0, &ixPSX81_WRP_BIOSTIMER_CMD[0], sizeof(ixPSX81_WRP_BIOSTIMER_CMD)/sizeof(ixPSX81_WRP_BIOSTIMER_CMD[0]), 0, 0 }, + { "ixPSX81_WRP_BIOSTIMER_CNTL", REG_SMC, 0x13180f1, &ixPSX81_WRP_BIOSTIMER_CNTL[0], sizeof(ixPSX81_WRP_BIOSTIMER_CNTL)/sizeof(ixPSX81_WRP_BIOSTIMER_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_BIOSTIMER_DEBUG", REG_SMC, 0x13180f2, &ixPSX81_WRP_BIOSTIMER_DEBUG[0], sizeof(ixPSX81_WRP_BIOSTIMER_DEBUG)/sizeof(ixPSX81_WRP_BIOSTIMER_DEBUG[0]), 0, 0 }, + { "ixPSX81_WRP_DELAYLINE_COMMAND", REG_SMC, 0x131ffd0, &ixPSX81_WRP_DELAYLINE_COMMAND[0], sizeof(ixPSX81_WRP_DELAYLINE_COMMAND)/sizeof(ixPSX81_WRP_DELAYLINE_COMMAND[0]), 0, 0 }, + { "ixPSX81_WRP_DELAYLINE_STATUS", REG_SMC, 0x131ffd1, &ixPSX81_WRP_DELAYLINE_STATUS[0], sizeof(ixPSX81_WRP_DELAYLINE_STATUS)/sizeof(ixPSX81_WRP_DELAYLINE_STATUS[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_RX_BP_CNTL", REG_SMC, 0x131ffe0, &ixPSX81_WRP_DTM_RX_BP_CNTL[0], sizeof(ixPSX81_WRP_DTM_RX_BP_CNTL)/sizeof(ixPSX81_WRP_DTM_RX_BP_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_CNTL", REG_SMC, 0x131ffe1, &ixPSX81_WRP_DTM_CNTL[0], sizeof(ixPSX81_WRP_DTM_CNTL)/sizeof(ixPSX81_WRP_DTM_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_CNTL_LEGACY", REG_SMC, 0x131ffe2, &ixPSX81_WRP_DTM_CNTL_LEGACY[0], sizeof(ixPSX81_WRP_DTM_CNTL_LEGACY)/sizeof(ixPSX81_WRP_DTM_CNTL_LEGACY[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_STI_LCLK_CTRL", REG_SMC, 0x131ffe3, &ixPSX81_WRP_DTM_STI_LCLK_CTRL[0], sizeof(ixPSX81_WRP_DTM_STI_LCLK_CTRL)/sizeof(ixPSX81_WRP_DTM_STI_LCLK_CTRL[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x", REG_SMC, 0x131ffe4, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt", REG_SMC, 0x131ffe5, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x", REG_SMC, 0x131ffe6, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0]), 0, 0 }, + { "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt", REG_SMC, 0x131ffe7, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0]), 0, 0 }, + { "mmPMI_CAP_LIST", REG_MMIO, 0x14, &mmPMI_CAP_LIST[0], sizeof(mmPMI_CAP_LIST)/sizeof(mmPMI_CAP_LIST[0]), 0, 0 }, + { "mmPMI_CAP", REG_MMIO, 0x14, &mmPMI_CAP[0], sizeof(mmPMI_CAP)/sizeof(mmPMI_CAP[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RESERVED", REG_SMC, 0x1400000, &ixPSX80_BIF_PCIE_RESERVED[0], sizeof(ixPSX80_BIF_PCIE_RESERVED)/sizeof(ixPSX80_BIF_PCIE_RESERVED[0]), 0, 0 }, + { "ixPCIE_RESERVED", REG_SMC, 0x1400000, &ixPCIE_RESERVED[0], sizeof(ixPCIE_RESERVED)/sizeof(ixPCIE_RESERVED[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_SCRATCH", REG_SMC, 0x1400001, &ixPSX80_BIF_PCIE_SCRATCH[0], sizeof(ixPSX80_BIF_PCIE_SCRATCH)/sizeof(ixPSX80_BIF_PCIE_SCRATCH[0]), 0, 0 }, + { "ixPCIE_SCRATCH", REG_SMC, 0x1400001, &ixPCIE_SCRATCH[0], sizeof(ixPCIE_SCRATCH)/sizeof(ixPCIE_SCRATCH[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPSX80_BIF_PCIE_HW_DEBUG[0], sizeof(ixPSX80_BIF_PCIE_HW_DEBUG)/sizeof(ixPSX80_BIF_PCIE_HW_DEBUG[0]), 0, 0 }, + { "ixPCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPCIE_HW_DEBUG[0], sizeof(ixPCIE_HW_DEBUG)/sizeof(ixPCIE_HW_DEBUG[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPSX80_BIF_PCIE_RX_NUM_NAK[0], sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK)/sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK[0]), 0, 0 }, + { "ixPCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPCIE_RX_NUM_NAK[0], sizeof(ixPCIE_RX_NUM_NAK)/sizeof(ixPCIE_RX_NUM_NAK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 }, + { "ixPCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_CNTL", REG_SMC, 0x1400010, &ixPSX80_BIF_PCIE_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CNTL)/sizeof(ixPSX80_BIF_PCIE_CNTL[0]), 0, 0 }, + { "ixPCIE_CNTL", REG_SMC, 0x1400010, &ixPCIE_CNTL[0], sizeof(ixPCIE_CNTL)/sizeof(ixPCIE_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPSX80_BIF_PCIE_CONFIG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CONFIG_CNTL)/sizeof(ixPSX80_BIF_PCIE_CONFIG_CNTL[0]), 0, 0 }, + { "ixPCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPCIE_CONFIG_CNTL[0], sizeof(ixPCIE_CONFIG_CNTL)/sizeof(ixPCIE_CONFIG_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPSX80_BIF_PCIE_DEBUG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_DEBUG_CNTL)/sizeof(ixPSX80_BIF_PCIE_DEBUG_CNTL[0]), 0, 0 }, + { "ixPCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPCIE_DEBUG_CNTL[0], sizeof(ixPCIE_DEBUG_CNTL)/sizeof(ixPCIE_DEBUG_CNTL[0]), 0, 0 }, + { "ixPCIE_INT_CNTL", REG_SMC, 0x140001a, &ixPCIE_INT_CNTL[0], sizeof(ixPCIE_INT_CNTL)/sizeof(ixPCIE_INT_CNTL[0]), 0, 0 }, + { "ixPCIE_INT_STATUS", REG_SMC, 0x140001b, &ixPCIE_INT_STATUS[0], sizeof(ixPCIE_INT_STATUS)/sizeof(ixPCIE_INT_STATUS[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_CNTL2", REG_SMC, 0x140001c, &ixPSX80_BIF_PCIE_CNTL2[0], sizeof(ixPSX80_BIF_PCIE_CNTL2)/sizeof(ixPSX80_BIF_PCIE_CNTL2[0]), 0, 0 }, + { "ixPCIE_CNTL2", REG_SMC, 0x140001c, &ixPCIE_CNTL2[0], sizeof(ixPCIE_CNTL2)/sizeof(ixPCIE_CNTL2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPSX80_BIF_PCIE_RX_CNTL2[0], sizeof(ixPSX80_BIF_PCIE_RX_CNTL2)/sizeof(ixPSX80_BIF_PCIE_RX_CNTL2[0]), 0, 0 }, + { "ixPCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPCIE_RX_CNTL2[0], sizeof(ixPCIE_RX_CNTL2)/sizeof(ixPCIE_RX_CNTL2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL)/sizeof(ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL[0]), 0, 0 }, + { "ixPCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPCIE_TX_F0_ATTR_CNTL)/sizeof(ixPCIE_TX_F0_ATTR_CNTL[0]), 0, 0 }, + { "ixPCIE_TX_F1_F2_ATTR_CNTL", REG_SMC, 0x140001f, &ixPCIE_TX_F1_F2_ATTR_CNTL[0], sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL)/sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPSX80_BIF_PCIE_CI_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CI_CNTL)/sizeof(ixPSX80_BIF_PCIE_CI_CNTL[0]), 0, 0 }, + { "ixPCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPCIE_CI_CNTL[0], sizeof(ixPCIE_CI_CNTL)/sizeof(ixPCIE_CI_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPSX80_BIF_PCIE_BUS_CNTL[0], sizeof(ixPSX80_BIF_PCIE_BUS_CNTL)/sizeof(ixPSX80_BIF_PCIE_BUS_CNTL[0]), 0, 0 }, + { "ixPCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPCIE_BUS_CNTL[0], sizeof(ixPCIE_BUS_CNTL)/sizeof(ixPCIE_BUS_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPSX80_BIF_PCIE_LC_STATE6[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE6)/sizeof(ixPSX80_BIF_PCIE_LC_STATE6[0]), 0, 0 }, + { "ixPCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPCIE_LC_STATE6[0], sizeof(ixPCIE_LC_STATE6)/sizeof(ixPCIE_LC_STATE6[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPSX80_BIF_PCIE_LC_STATE7[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE7)/sizeof(ixPSX80_BIF_PCIE_LC_STATE7[0]), 0, 0 }, + { "ixPCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPCIE_LC_STATE7[0], sizeof(ixPCIE_LC_STATE7)/sizeof(ixPCIE_LC_STATE7[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPSX80_BIF_PCIE_LC_STATE8[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE8)/sizeof(ixPSX80_BIF_PCIE_LC_STATE8[0]), 0, 0 }, + { "ixPCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPCIE_LC_STATE8[0], sizeof(ixPCIE_LC_STATE8)/sizeof(ixPCIE_LC_STATE8[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPSX80_BIF_PCIE_LC_STATE9[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE9)/sizeof(ixPSX80_BIF_PCIE_LC_STATE9[0]), 0, 0 }, + { "ixPCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPCIE_LC_STATE9[0], sizeof(ixPCIE_LC_STATE9)/sizeof(ixPCIE_LC_STATE9[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPSX80_BIF_PCIE_LC_STATE10[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE10)/sizeof(ixPSX80_BIF_PCIE_LC_STATE10[0]), 0, 0 }, + { "ixPCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPCIE_LC_STATE10[0], sizeof(ixPCIE_LC_STATE10)/sizeof(ixPCIE_LC_STATE10[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPSX80_BIF_PCIE_LC_STATE11[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE11)/sizeof(ixPSX80_BIF_PCIE_LC_STATE11[0]), 0, 0 }, + { "ixPCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPCIE_LC_STATE11[0], sizeof(ixPCIE_LC_STATE11)/sizeof(ixPCIE_LC_STATE11[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPSX80_BIF_PCIE_LC_STATUS1[0], sizeof(ixPSX80_BIF_PCIE_LC_STATUS1)/sizeof(ixPSX80_BIF_PCIE_LC_STATUS1[0]), 0, 0 }, + { "ixPCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPCIE_LC_STATUS1[0], sizeof(ixPCIE_LC_STATUS1)/sizeof(ixPCIE_LC_STATUS1[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPSX80_BIF_PCIE_LC_STATUS2[0], sizeof(ixPSX80_BIF_PCIE_LC_STATUS2)/sizeof(ixPSX80_BIF_PCIE_LC_STATUS2[0]), 0, 0 }, + { "ixPCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPCIE_LC_STATUS2[0], sizeof(ixPCIE_LC_STATUS2)/sizeof(ixPCIE_LC_STATUS2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPSX80_BIF_PCIE_WPR_CNTL[0], sizeof(ixPSX80_BIF_PCIE_WPR_CNTL)/sizeof(ixPSX80_BIF_PCIE_WPR_CNTL[0]), 0, 0 }, + { "ixPCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPCIE_WPR_CNTL[0], sizeof(ixPCIE_WPR_CNTL)/sizeof(ixPCIE_WPR_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPSX80_BIF_PCIE_RX_LAST_TLP0[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP0)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP0[0]), 0, 0 }, + { "ixPCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPCIE_RX_LAST_TLP0[0], sizeof(ixPCIE_RX_LAST_TLP0)/sizeof(ixPCIE_RX_LAST_TLP0[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPSX80_BIF_PCIE_RX_LAST_TLP1[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP1)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP1[0]), 0, 0 }, + { "ixPCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPCIE_RX_LAST_TLP1[0], sizeof(ixPCIE_RX_LAST_TLP1)/sizeof(ixPCIE_RX_LAST_TLP1[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPSX80_BIF_PCIE_RX_LAST_TLP2[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP2)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP2[0]), 0, 0 }, + { "ixPCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPCIE_RX_LAST_TLP2[0], sizeof(ixPCIE_RX_LAST_TLP2)/sizeof(ixPCIE_RX_LAST_TLP2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPSX80_BIF_PCIE_RX_LAST_TLP3[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP3)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP3[0]), 0, 0 }, + { "ixPCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPCIE_RX_LAST_TLP3[0], sizeof(ixPCIE_RX_LAST_TLP3)/sizeof(ixPCIE_RX_LAST_TLP3[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPSX80_BIF_PCIE_TX_LAST_TLP0[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP0)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP0[0]), 0, 0 }, + { "ixPCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPCIE_TX_LAST_TLP0[0], sizeof(ixPCIE_TX_LAST_TLP0)/sizeof(ixPCIE_TX_LAST_TLP0[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPSX80_BIF_PCIE_TX_LAST_TLP1[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP1)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP1[0]), 0, 0 }, + { "ixPCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPCIE_TX_LAST_TLP1[0], sizeof(ixPCIE_TX_LAST_TLP1)/sizeof(ixPCIE_TX_LAST_TLP1[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPSX80_BIF_PCIE_TX_LAST_TLP2[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP2)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP2[0]), 0, 0 }, + { "ixPCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPCIE_TX_LAST_TLP2[0], sizeof(ixPCIE_TX_LAST_TLP2)/sizeof(ixPCIE_TX_LAST_TLP2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPSX80_BIF_PCIE_TX_LAST_TLP3[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP3)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP3[0]), 0, 0 }, + { "ixPCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPCIE_TX_LAST_TLP3[0], sizeof(ixPCIE_TX_LAST_TLP3)/sizeof(ixPCIE_TX_LAST_TLP3[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 }, + { "ixPCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPSX80_BIF_PCIE_I2C_REG_DATA[0], sizeof(ixPSX80_BIF_PCIE_I2C_REG_DATA)/sizeof(ixPSX80_BIF_PCIE_I2C_REG_DATA[0]), 0, 0 }, + { "ixPCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPCIE_I2C_REG_DATA[0], sizeof(ixPCIE_I2C_REG_DATA)/sizeof(ixPCIE_I2C_REG_DATA[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPSX80_BIF_PCIE_CFG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CFG_CNTL)/sizeof(ixPSX80_BIF_PCIE_CFG_CNTL[0]), 0, 0 }, + { "ixPCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPCIE_CFG_CNTL[0], sizeof(ixPCIE_CFG_CNTL)/sizeof(ixPCIE_CFG_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_LC_PM_CNTL", REG_SMC, 0x140003d, &ixPSX80_BIF_PCIE_LC_PM_CNTL[0], sizeof(ixPSX80_BIF_PCIE_LC_PM_CNTL)/sizeof(ixPSX80_BIF_PCIE_LC_PM_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_P_CNTL", REG_SMC, 0x1400040, &ixPSX80_BIF_PCIE_P_CNTL[0], sizeof(ixPSX80_BIF_PCIE_P_CNTL)/sizeof(ixPSX80_BIF_PCIE_P_CNTL[0]), 0, 0 }, + { "ixPCIE_P_CNTL", REG_SMC, 0x1400040, &ixPCIE_P_CNTL[0], sizeof(ixPCIE_P_CNTL)/sizeof(ixPCIE_P_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPSX80_BIF_PCIE_P_BUF_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_BUF_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_BUF_STATUS[0]), 0, 0 }, + { "ixPCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPCIE_P_BUF_STATUS[0], sizeof(ixPCIE_P_BUF_STATUS)/sizeof(ixPCIE_P_BUF_STATUS[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPSX80_BIF_PCIE_P_DECODER_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_DECODER_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_DECODER_STATUS[0]), 0, 0 }, + { "ixPCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPCIE_P_DECODER_STATUS[0], sizeof(ixPCIE_P_DECODER_STATUS)/sizeof(ixPCIE_P_DECODER_STATUS[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPSX80_BIF_PCIE_P_MISC_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_MISC_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_MISC_STATUS[0]), 0, 0 }, + { "ixPCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPCIE_P_MISC_STATUS[0], sizeof(ixPCIE_P_MISC_STATUS)/sizeof(ixPCIE_P_MISC_STATUS[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 }, + { "ixPCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 }, + { "ixPCIE_TX_LTR_CNTL", REG_SMC, 0x1400060, &ixPCIE_TX_LTR_CNTL[0], sizeof(ixPCIE_TX_LTR_CNTL)/sizeof(ixPCIE_TX_LTR_CNTL[0]), 0, 0 }, + { "ixPCIE_OBFF_CNTL", REG_SMC, 0x1400061, &ixPCIE_OBFF_CNTL[0], sizeof(ixPCIE_OBFF_CNTL)/sizeof(ixPCIE_OBFF_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPSX80_BIF_PCIE_PERF_COUNT_CNTL[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT_CNTL)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT_CNTL[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPCIE_PERF_COUNT_CNTL[0], sizeof(ixPCIE_PERF_COUNT_CNTL)/sizeof(ixPCIE_PERF_COUNT_CNTL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPCIE_PERF_CNTL_TXCLK[0], sizeof(ixPCIE_PERF_CNTL_TXCLK)/sizeof(ixPCIE_PERF_CNTL_TXCLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK)/sizeof(ixPCIE_PERF_COUNT0_TXCLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK)/sizeof(ixPCIE_PERF_COUNT1_TXCLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2[0]), 0, 0 }, + { "ixPCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPCIE_PERF_CNTL_TXCLK2)/sizeof(ixPCIE_PERF_CNTL_TXCLK2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 }, + { "ixPCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPSX80_BIF_PCIE_STRAP_F0[0], sizeof(ixPSX80_BIF_PCIE_STRAP_F0)/sizeof(ixPSX80_BIF_PCIE_STRAP_F0[0]), 0, 0 }, + { "ixPCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPCIE_STRAP_F0[0], sizeof(ixPCIE_STRAP_F0)/sizeof(ixPCIE_STRAP_F0[0]), 0, 0 }, + { "ixPCIE_STRAP_F1", REG_SMC, 0x14000b1, &ixPCIE_STRAP_F1[0], sizeof(ixPCIE_STRAP_F1)/sizeof(ixPCIE_STRAP_F1[0]), 0, 0 }, + { "ixPCIE_STRAP_F2", REG_SMC, 0x14000b2, &ixPCIE_STRAP_F2[0], sizeof(ixPCIE_STRAP_F2)/sizeof(ixPCIE_STRAP_F2[0]), 0, 0 }, + { "ixPCIE_STRAP_F3", REG_SMC, 0x14000b3, &ixPCIE_STRAP_F3[0], sizeof(ixPCIE_STRAP_F3)/sizeof(ixPCIE_STRAP_F3[0]), 0, 0 }, + { "ixPCIE_STRAP_F4", REG_SMC, 0x14000b4, &ixPCIE_STRAP_F4[0], sizeof(ixPCIE_STRAP_F4)/sizeof(ixPCIE_STRAP_F4[0]), 0, 0 }, + { "ixPCIE_STRAP_F5", REG_SMC, 0x14000b5, &ixPCIE_STRAP_F5[0], sizeof(ixPCIE_STRAP_F5)/sizeof(ixPCIE_STRAP_F5[0]), 0, 0 }, + { "ixPCIE_STRAP_F6", REG_SMC, 0x14000b6, &ixPCIE_STRAP_F6[0], sizeof(ixPCIE_STRAP_F6)/sizeof(ixPCIE_STRAP_F6[0]), 0, 0 }, + { "ixPCIE_STRAP_F7", REG_SMC, 0x14000b7, &ixPCIE_STRAP_F7[0], sizeof(ixPCIE_STRAP_F7)/sizeof(ixPCIE_STRAP_F7[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPSX80_BIF_PCIE_STRAP_MISC[0], sizeof(ixPSX80_BIF_PCIE_STRAP_MISC)/sizeof(ixPSX80_BIF_PCIE_STRAP_MISC[0]), 0, 0 }, + { "ixPCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPCIE_STRAP_MISC[0], sizeof(ixPCIE_STRAP_MISC)/sizeof(ixPCIE_STRAP_MISC[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPSX80_BIF_PCIE_STRAP_MISC2[0], sizeof(ixPSX80_BIF_PCIE_STRAP_MISC2)/sizeof(ixPSX80_BIF_PCIE_STRAP_MISC2[0]), 0, 0 }, + { "ixPCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPCIE_STRAP_MISC2[0], sizeof(ixPCIE_STRAP_MISC2)/sizeof(ixPCIE_STRAP_MISC2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPSX80_BIF_PCIE_STRAP_PI[0], sizeof(ixPSX80_BIF_PCIE_STRAP_PI)/sizeof(ixPSX80_BIF_PCIE_STRAP_PI[0]), 0, 0 }, + { "ixPCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPCIE_STRAP_PI[0], sizeof(ixPCIE_STRAP_PI)/sizeof(ixPCIE_STRAP_PI[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPSX80_BIF_PCIE_STRAP_I2C_BD[0], sizeof(ixPSX80_BIF_PCIE_STRAP_I2C_BD)/sizeof(ixPSX80_BIF_PCIE_STRAP_I2C_BD[0]), 0, 0 }, + { "ixPCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPCIE_STRAP_I2C_BD[0], sizeof(ixPCIE_STRAP_I2C_BD)/sizeof(ixPCIE_STRAP_I2C_BD[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPSX80_BIF_PCIE_PRBS_CLR[0], sizeof(ixPSX80_BIF_PCIE_PRBS_CLR)/sizeof(ixPSX80_BIF_PCIE_PRBS_CLR[0]), 0, 0 }, + { "ixPCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPCIE_PRBS_CLR[0], sizeof(ixPCIE_PRBS_CLR)/sizeof(ixPCIE_PRBS_CLR[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPSX80_BIF_PCIE_PRBS_STATUS1[0], sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS1)/sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS1[0]), 0, 0 }, + { "ixPCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPCIE_PRBS_STATUS1[0], sizeof(ixPCIE_PRBS_STATUS1)/sizeof(ixPCIE_PRBS_STATUS1[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPSX80_BIF_PCIE_PRBS_STATUS2[0], sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS2)/sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS2[0]), 0, 0 }, + { "ixPCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPCIE_PRBS_STATUS2[0], sizeof(ixPCIE_PRBS_STATUS2)/sizeof(ixPCIE_PRBS_STATUS2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPSX80_BIF_PCIE_PRBS_FREERUN[0], sizeof(ixPSX80_BIF_PCIE_PRBS_FREERUN)/sizeof(ixPSX80_BIF_PCIE_PRBS_FREERUN[0]), 0, 0 }, + { "ixPCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPCIE_PRBS_FREERUN[0], sizeof(ixPCIE_PRBS_FREERUN)/sizeof(ixPCIE_PRBS_FREERUN[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPSX80_BIF_PCIE_PRBS_MISC[0], sizeof(ixPSX80_BIF_PCIE_PRBS_MISC)/sizeof(ixPSX80_BIF_PCIE_PRBS_MISC[0]), 0, 0 }, + { "ixPCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPCIE_PRBS_MISC[0], sizeof(ixPCIE_PRBS_MISC)/sizeof(ixPCIE_PRBS_MISC[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPSX80_BIF_PCIE_PRBS_USER_PATTERN[0], sizeof(ixPSX80_BIF_PCIE_PRBS_USER_PATTERN)/sizeof(ixPSX80_BIF_PCIE_PRBS_USER_PATTERN[0]), 0, 0 }, + { "ixPCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPCIE_PRBS_USER_PATTERN[0], sizeof(ixPCIE_PRBS_USER_PATTERN)/sizeof(ixPCIE_PRBS_USER_PATTERN[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPSX80_BIF_PCIE_PRBS_LO_BITCNT[0], sizeof(ixPSX80_BIF_PCIE_PRBS_LO_BITCNT)/sizeof(ixPSX80_BIF_PCIE_PRBS_LO_BITCNT[0]), 0, 0 }, + { "ixPCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPCIE_PRBS_LO_BITCNT[0], sizeof(ixPCIE_PRBS_LO_BITCNT)/sizeof(ixPCIE_PRBS_LO_BITCNT[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPSX80_BIF_PCIE_PRBS_HI_BITCNT[0], sizeof(ixPSX80_BIF_PCIE_PRBS_HI_BITCNT)/sizeof(ixPSX80_BIF_PCIE_PRBS_HI_BITCNT[0]), 0, 0 }, + { "ixPCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPCIE_PRBS_HI_BITCNT[0], sizeof(ixPCIE_PRBS_HI_BITCNT)/sizeof(ixPCIE_PRBS_HI_BITCNT[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_0[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_0)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_0[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPCIE_PRBS_ERRCNT_0[0], sizeof(ixPCIE_PRBS_ERRCNT_0)/sizeof(ixPCIE_PRBS_ERRCNT_0[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_1[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_1)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_1[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPCIE_PRBS_ERRCNT_1[0], sizeof(ixPCIE_PRBS_ERRCNT_1)/sizeof(ixPCIE_PRBS_ERRCNT_1[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_2[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_2)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_2[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPCIE_PRBS_ERRCNT_2[0], sizeof(ixPCIE_PRBS_ERRCNT_2)/sizeof(ixPCIE_PRBS_ERRCNT_2[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_3[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_3)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_3[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPCIE_PRBS_ERRCNT_3[0], sizeof(ixPCIE_PRBS_ERRCNT_3)/sizeof(ixPCIE_PRBS_ERRCNT_3[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_4[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_4)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_4[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPCIE_PRBS_ERRCNT_4[0], sizeof(ixPCIE_PRBS_ERRCNT_4)/sizeof(ixPCIE_PRBS_ERRCNT_4[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_5[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_5)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_5[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPCIE_PRBS_ERRCNT_5[0], sizeof(ixPCIE_PRBS_ERRCNT_5)/sizeof(ixPCIE_PRBS_ERRCNT_5[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_6[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_6)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_6[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPCIE_PRBS_ERRCNT_6[0], sizeof(ixPCIE_PRBS_ERRCNT_6)/sizeof(ixPCIE_PRBS_ERRCNT_6[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_7[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_7)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_7[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPCIE_PRBS_ERRCNT_7[0], sizeof(ixPCIE_PRBS_ERRCNT_7)/sizeof(ixPCIE_PRBS_ERRCNT_7[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_8[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_8)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_8[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPCIE_PRBS_ERRCNT_8[0], sizeof(ixPCIE_PRBS_ERRCNT_8)/sizeof(ixPCIE_PRBS_ERRCNT_8[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_9[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_9)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_9[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPCIE_PRBS_ERRCNT_9[0], sizeof(ixPCIE_PRBS_ERRCNT_9)/sizeof(ixPCIE_PRBS_ERRCNT_9[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_10[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_10)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_10[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPCIE_PRBS_ERRCNT_10[0], sizeof(ixPCIE_PRBS_ERRCNT_10)/sizeof(ixPCIE_PRBS_ERRCNT_10[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_11[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_11)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_11[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPCIE_PRBS_ERRCNT_11[0], sizeof(ixPCIE_PRBS_ERRCNT_11)/sizeof(ixPCIE_PRBS_ERRCNT_11[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_12[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_12)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_12[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPCIE_PRBS_ERRCNT_12[0], sizeof(ixPCIE_PRBS_ERRCNT_12)/sizeof(ixPCIE_PRBS_ERRCNT_12[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_13[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_13)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_13[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPCIE_PRBS_ERRCNT_13[0], sizeof(ixPCIE_PRBS_ERRCNT_13)/sizeof(ixPCIE_PRBS_ERRCNT_13[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_14[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_14)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_14[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPCIE_PRBS_ERRCNT_14[0], sizeof(ixPCIE_PRBS_ERRCNT_14)/sizeof(ixPCIE_PRBS_ERRCNT_14[0]), 0, 0 }, + { "ixPSX80_BIF_PCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_15[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_15)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_15[0]), 0, 0 }, + { "ixPCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPCIE_PRBS_ERRCNT_15[0], sizeof(ixPCIE_PRBS_ERRCNT_15)/sizeof(ixPCIE_PRBS_ERRCNT_15[0]), 0, 0 }, + { "ixPCIE_F0_DPA_CAP", REG_SMC, 0x14000e0, &ixPCIE_F0_DPA_CAP[0], sizeof(ixPCIE_F0_DPA_CAP)/sizeof(ixPCIE_F0_DPA_CAP[0]), 0, 0 }, + { "ixPCIE_F0_DPA_LATENCY_INDICATOR", REG_SMC, 0x14000e4, &ixPCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 }, + { "ixPCIE_F0_DPA_CNTL", REG_SMC, 0x14000e5, &ixPCIE_F0_DPA_CNTL[0], sizeof(ixPCIE_F0_DPA_CNTL)/sizeof(ixPCIE_F0_DPA_CNTL[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_SMC, 0x14000e7, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_SMC, 0x14000e8, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_SMC, 0x14000e9, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_SMC, 0x14000ea, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_SMC, 0x14000eb, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_SMC, 0x14000ec, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_SMC, 0x14000ed, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 }, + { "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_SMC, 0x14000ee, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_COMMAND_STATUS", REG_SMC, 0x1400100, &ixPSX80_BIF_SWRST_COMMAND_STATUS[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_STATUS)/sizeof(ixPSX80_BIF_SWRST_COMMAND_STATUS[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_GENERAL_CONTROL", REG_SMC, 0x1400101, &ixPSX80_BIF_SWRST_GENERAL_CONTROL[0], sizeof(ixPSX80_BIF_SWRST_GENERAL_CONTROL)/sizeof(ixPSX80_BIF_SWRST_GENERAL_CONTROL[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_COMMAND_0", REG_SMC, 0x1400102, &ixPSX80_BIF_SWRST_COMMAND_0[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_0)/sizeof(ixPSX80_BIF_SWRST_COMMAND_0[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_COMMAND_1", REG_SMC, 0x1400103, &ixPSX80_BIF_SWRST_COMMAND_1[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_1)/sizeof(ixPSX80_BIF_SWRST_COMMAND_1[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_0", REG_SMC, 0x1400104, &ixPSX80_BIF_SWRST_CONTROL_0[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_0)/sizeof(ixPSX80_BIF_SWRST_CONTROL_0[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_1", REG_SMC, 0x1400105, &ixPSX80_BIF_SWRST_CONTROL_1[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_1)/sizeof(ixPSX80_BIF_SWRST_CONTROL_1[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_2", REG_SMC, 0x1400106, &ixPSX80_BIF_SWRST_CONTROL_2[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_2)/sizeof(ixPSX80_BIF_SWRST_CONTROL_2[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_3", REG_SMC, 0x1400107, &ixPSX80_BIF_SWRST_CONTROL_3[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_3)/sizeof(ixPSX80_BIF_SWRST_CONTROL_3[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_4", REG_SMC, 0x1400108, &ixPSX80_BIF_SWRST_CONTROL_4[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_4)/sizeof(ixPSX80_BIF_SWRST_CONTROL_4[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_5", REG_SMC, 0x1400109, &ixPSX80_BIF_SWRST_CONTROL_5[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_5)/sizeof(ixPSX80_BIF_SWRST_CONTROL_5[0]), 0, 0 }, + { "ixPSX80_BIF_SWRST_CONTROL_6", REG_SMC, 0x140010a, &ixPSX80_BIF_SWRST_CONTROL_6[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_6)/sizeof(ixPSX80_BIF_SWRST_CONTROL_6[0]), 0, 0 }, + { "ixPSX80_BIF_CPM_CONTROL", REG_SMC, 0x1400118, &ixPSX80_BIF_CPM_CONTROL[0], sizeof(ixPSX80_BIF_CPM_CONTROL)/sizeof(ixPSX80_BIF_CPM_CONTROL[0]), 0, 0 }, + { "ixPSX80_BIF_LM_CONTROL", REG_SMC, 0x1400120, &ixPSX80_BIF_LM_CONTROL[0], sizeof(ixPSX80_BIF_LM_CONTROL)/sizeof(ixPSX80_BIF_LM_CONTROL[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIETXMUX0", REG_SMC, 0x1400121, &ixPSX80_BIF_LM_PCIETXMUX0[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX0)/sizeof(ixPSX80_BIF_LM_PCIETXMUX0[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIETXMUX1", REG_SMC, 0x1400122, &ixPSX80_BIF_LM_PCIETXMUX1[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX1)/sizeof(ixPSX80_BIF_LM_PCIETXMUX1[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIETXMUX2", REG_SMC, 0x1400123, &ixPSX80_BIF_LM_PCIETXMUX2[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX2)/sizeof(ixPSX80_BIF_LM_PCIETXMUX2[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIETXMUX3", REG_SMC, 0x1400124, &ixPSX80_BIF_LM_PCIETXMUX3[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX3)/sizeof(ixPSX80_BIF_LM_PCIETXMUX3[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIERXMUX0", REG_SMC, 0x1400125, &ixPSX80_BIF_LM_PCIERXMUX0[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX0)/sizeof(ixPSX80_BIF_LM_PCIERXMUX0[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIERXMUX1", REG_SMC, 0x1400126, &ixPSX80_BIF_LM_PCIERXMUX1[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX1)/sizeof(ixPSX80_BIF_LM_PCIERXMUX1[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIERXMUX2", REG_SMC, 0x1400127, &ixPSX80_BIF_LM_PCIERXMUX2[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX2)/sizeof(ixPSX80_BIF_LM_PCIERXMUX2[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PCIERXMUX3", REG_SMC, 0x1400128, &ixPSX80_BIF_LM_PCIERXMUX3[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX3)/sizeof(ixPSX80_BIF_LM_PCIERXMUX3[0]), 0, 0 }, + { "ixPSX80_BIF_LM_LANEENABLE", REG_SMC, 0x1400129, &ixPSX80_BIF_LM_LANEENABLE[0], sizeof(ixPSX80_BIF_LM_LANEENABLE)/sizeof(ixPSX80_BIF_LM_LANEENABLE[0]), 0, 0 }, + { "ixPSX80_BIF_LM_PRBSCONTROL", REG_SMC, 0x140012a, &ixPSX80_BIF_LM_PRBSCONTROL[0], sizeof(ixPSX80_BIF_LM_PRBSCONTROL)/sizeof(ixPSX80_BIF_LM_PRBSCONTROL[0]), 0, 0 }, + { "ixPSX80_BIF_LM_POWERCONTROL", REG_SMC, 0x140012b, &ixPSX80_BIF_LM_POWERCONTROL[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL)/sizeof(ixPSX80_BIF_LM_POWERCONTROL[0]), 0, 0 }, + { "ixPSX80_BIF_LM_POWERCONTROL1", REG_SMC, 0x140012c, &ixPSX80_BIF_LM_POWERCONTROL1[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL1)/sizeof(ixPSX80_BIF_LM_POWERCONTROL1[0]), 0, 0 }, + { "ixPSX80_BIF_LM_POWERCONTROL2", REG_SMC, 0x140012d, &ixPSX80_BIF_LM_POWERCONTROL2[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL2)/sizeof(ixPSX80_BIF_LM_POWERCONTROL2[0]), 0, 0 }, + { "ixPSX80_BIF_LM_POWERCONTROL3", REG_SMC, 0x140012e, &ixPSX80_BIF_LM_POWERCONTROL3[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL3)/sizeof(ixPSX80_BIF_LM_POWERCONTROL3[0]), 0, 0 }, + { "ixPSX80_BIF_LM_POWERCONTROL4", REG_SMC, 0x140012f, &ixPSX80_BIF_LM_POWERCONTROL4[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL4)/sizeof(ixPSX80_BIF_LM_POWERCONTROL4[0]), 0, 0 }, + { "mmGARLIC_FLUSH_CNTL", REG_MMIO, 0x1401, &mmGARLIC_FLUSH_CNTL[0], sizeof(mmGARLIC_FLUSH_CNTL)/sizeof(mmGARLIC_FLUSH_CNTL[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_0", REG_MMIO, 0x1402, &mmGARLIC_FLUSH_ADDR_START_0[0], sizeof(mmGARLIC_FLUSH_ADDR_START_0)/sizeof(mmGARLIC_FLUSH_ADDR_START_0[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_0", REG_MMIO, 0x1403, &mmGARLIC_FLUSH_ADDR_END_0[0], sizeof(mmGARLIC_FLUSH_ADDR_END_0)/sizeof(mmGARLIC_FLUSH_ADDR_END_0[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_1", REG_MMIO, 0x1404, &mmGARLIC_FLUSH_ADDR_START_1[0], sizeof(mmGARLIC_FLUSH_ADDR_START_1)/sizeof(mmGARLIC_FLUSH_ADDR_START_1[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_1", REG_MMIO, 0x1405, &mmGARLIC_FLUSH_ADDR_END_1[0], sizeof(mmGARLIC_FLUSH_ADDR_END_1)/sizeof(mmGARLIC_FLUSH_ADDR_END_1[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_2", REG_MMIO, 0x1406, &mmGARLIC_FLUSH_ADDR_START_2[0], sizeof(mmGARLIC_FLUSH_ADDR_START_2)/sizeof(mmGARLIC_FLUSH_ADDR_START_2[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_2", REG_MMIO, 0x1407, &mmGARLIC_FLUSH_ADDR_END_2[0], sizeof(mmGARLIC_FLUSH_ADDR_END_2)/sizeof(mmGARLIC_FLUSH_ADDR_END_2[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_3", REG_MMIO, 0x1408, &mmGARLIC_FLUSH_ADDR_START_3[0], sizeof(mmGARLIC_FLUSH_ADDR_START_3)/sizeof(mmGARLIC_FLUSH_ADDR_START_3[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_3", REG_MMIO, 0x1409, &mmGARLIC_FLUSH_ADDR_END_3[0], sizeof(mmGARLIC_FLUSH_ADDR_END_3)/sizeof(mmGARLIC_FLUSH_ADDR_END_3[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_4", REG_MMIO, 0x140a, &mmGARLIC_FLUSH_ADDR_START_4[0], sizeof(mmGARLIC_FLUSH_ADDR_START_4)/sizeof(mmGARLIC_FLUSH_ADDR_START_4[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_4", REG_MMIO, 0x140b, &mmGARLIC_FLUSH_ADDR_END_4[0], sizeof(mmGARLIC_FLUSH_ADDR_END_4)/sizeof(mmGARLIC_FLUSH_ADDR_END_4[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_5", REG_MMIO, 0x140c, &mmGARLIC_FLUSH_ADDR_START_5[0], sizeof(mmGARLIC_FLUSH_ADDR_START_5)/sizeof(mmGARLIC_FLUSH_ADDR_START_5[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_5", REG_MMIO, 0x140d, &mmGARLIC_FLUSH_ADDR_END_5[0], sizeof(mmGARLIC_FLUSH_ADDR_END_5)/sizeof(mmGARLIC_FLUSH_ADDR_END_5[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_6", REG_MMIO, 0x140e, &mmGARLIC_FLUSH_ADDR_START_6[0], sizeof(mmGARLIC_FLUSH_ADDR_START_6)/sizeof(mmGARLIC_FLUSH_ADDR_START_6[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_6", REG_MMIO, 0x140f, &mmGARLIC_FLUSH_ADDR_END_6[0], sizeof(mmGARLIC_FLUSH_ADDR_END_6)/sizeof(mmGARLIC_FLUSH_ADDR_END_6[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_START_7", REG_MMIO, 0x1410, &mmGARLIC_FLUSH_ADDR_START_7[0], sizeof(mmGARLIC_FLUSH_ADDR_START_7)/sizeof(mmGARLIC_FLUSH_ADDR_START_7[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RESERVED", REG_SMC, 0x1410000, &ixPSX81_BIF_PCIE_RESERVED[0], sizeof(ixPSX81_BIF_PCIE_RESERVED)/sizeof(ixPSX81_BIF_PCIE_RESERVED[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_SCRATCH", REG_SMC, 0x1410001, &ixPSX81_BIF_PCIE_SCRATCH[0], sizeof(ixPSX81_BIF_PCIE_SCRATCH)/sizeof(ixPSX81_BIF_PCIE_SCRATCH[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_HW_DEBUG", REG_SMC, 0x1410002, &ixPSX81_BIF_PCIE_HW_DEBUG[0], sizeof(ixPSX81_BIF_PCIE_HW_DEBUG)/sizeof(ixPSX81_BIF_PCIE_HW_DEBUG[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_NUM_NAK", REG_SMC, 0x141000e, &ixPSX81_BIF_PCIE_RX_NUM_NAK[0], sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK)/sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x141000f, &ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_CNTL", REG_SMC, 0x1410010, &ixPSX81_BIF_PCIE_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CNTL)/sizeof(ixPSX81_BIF_PCIE_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_CONFIG_CNTL", REG_SMC, 0x1410011, &ixPSX81_BIF_PCIE_CONFIG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CONFIG_CNTL)/sizeof(ixPSX81_BIF_PCIE_CONFIG_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_DEBUG_CNTL", REG_SMC, 0x1410012, &ixPSX81_BIF_PCIE_DEBUG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_DEBUG_CNTL)/sizeof(ixPSX81_BIF_PCIE_DEBUG_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_CNTL2", REG_SMC, 0x141001c, &ixPSX81_BIF_PCIE_CNTL2[0], sizeof(ixPSX81_BIF_PCIE_CNTL2)/sizeof(ixPSX81_BIF_PCIE_CNTL2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_CNTL2", REG_SMC, 0x141001d, &ixPSX81_BIF_PCIE_RX_CNTL2[0], sizeof(ixPSX81_BIF_PCIE_RX_CNTL2)/sizeof(ixPSX81_BIF_PCIE_RX_CNTL2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x141001e, &ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL)/sizeof(ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_CI_CNTL", REG_SMC, 0x1410020, &ixPSX81_BIF_PCIE_CI_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CI_CNTL)/sizeof(ixPSX81_BIF_PCIE_CI_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_BUS_CNTL", REG_SMC, 0x1410021, &ixPSX81_BIF_PCIE_BUS_CNTL[0], sizeof(ixPSX81_BIF_PCIE_BUS_CNTL)/sizeof(ixPSX81_BIF_PCIE_BUS_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE6", REG_SMC, 0x1410022, &ixPSX81_BIF_PCIE_LC_STATE6[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE6)/sizeof(ixPSX81_BIF_PCIE_LC_STATE6[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE7", REG_SMC, 0x1410023, &ixPSX81_BIF_PCIE_LC_STATE7[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE7)/sizeof(ixPSX81_BIF_PCIE_LC_STATE7[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE8", REG_SMC, 0x1410024, &ixPSX81_BIF_PCIE_LC_STATE8[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE8)/sizeof(ixPSX81_BIF_PCIE_LC_STATE8[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE9", REG_SMC, 0x1410025, &ixPSX81_BIF_PCIE_LC_STATE9[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE9)/sizeof(ixPSX81_BIF_PCIE_LC_STATE9[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE10", REG_SMC, 0x1410026, &ixPSX81_BIF_PCIE_LC_STATE10[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE10)/sizeof(ixPSX81_BIF_PCIE_LC_STATE10[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATE11", REG_SMC, 0x1410027, &ixPSX81_BIF_PCIE_LC_STATE11[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE11)/sizeof(ixPSX81_BIF_PCIE_LC_STATE11[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATUS1", REG_SMC, 0x1410028, &ixPSX81_BIF_PCIE_LC_STATUS1[0], sizeof(ixPSX81_BIF_PCIE_LC_STATUS1)/sizeof(ixPSX81_BIF_PCIE_LC_STATUS1[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_STATUS2", REG_SMC, 0x1410029, &ixPSX81_BIF_PCIE_LC_STATUS2[0], sizeof(ixPSX81_BIF_PCIE_LC_STATUS2)/sizeof(ixPSX81_BIF_PCIE_LC_STATUS2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_WPR_CNTL", REG_SMC, 0x1410030, &ixPSX81_BIF_PCIE_WPR_CNTL[0], sizeof(ixPSX81_BIF_PCIE_WPR_CNTL)/sizeof(ixPSX81_BIF_PCIE_WPR_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_LAST_TLP0", REG_SMC, 0x1410031, &ixPSX81_BIF_PCIE_RX_LAST_TLP0[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP0)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP0[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_LAST_TLP1", REG_SMC, 0x1410032, &ixPSX81_BIF_PCIE_RX_LAST_TLP1[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP1)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP1[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_LAST_TLP2", REG_SMC, 0x1410033, &ixPSX81_BIF_PCIE_RX_LAST_TLP2[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP2)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_RX_LAST_TLP3", REG_SMC, 0x1410034, &ixPSX81_BIF_PCIE_RX_LAST_TLP3[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP3)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP3[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_TX_LAST_TLP0", REG_SMC, 0x1410035, &ixPSX81_BIF_PCIE_TX_LAST_TLP0[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP0)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP0[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_TX_LAST_TLP1", REG_SMC, 0x1410036, &ixPSX81_BIF_PCIE_TX_LAST_TLP1[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP1)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP1[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_TX_LAST_TLP2", REG_SMC, 0x1410037, &ixPSX81_BIF_PCIE_TX_LAST_TLP2[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP2)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_TX_LAST_TLP3", REG_SMC, 0x1410038, &ixPSX81_BIF_PCIE_TX_LAST_TLP3[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP3)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP3[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x141003a, &ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_I2C_REG_DATA", REG_SMC, 0x141003b, &ixPSX81_BIF_PCIE_I2C_REG_DATA[0], sizeof(ixPSX81_BIF_PCIE_I2C_REG_DATA)/sizeof(ixPSX81_BIF_PCIE_I2C_REG_DATA[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_CFG_CNTL", REG_SMC, 0x141003c, &ixPSX81_BIF_PCIE_CFG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CFG_CNTL)/sizeof(ixPSX81_BIF_PCIE_CFG_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_LC_PM_CNTL", REG_SMC, 0x141003d, &ixPSX81_BIF_PCIE_LC_PM_CNTL[0], sizeof(ixPSX81_BIF_PCIE_LC_PM_CNTL)/sizeof(ixPSX81_BIF_PCIE_LC_PM_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_P_CNTL", REG_SMC, 0x1410040, &ixPSX81_BIF_PCIE_P_CNTL[0], sizeof(ixPSX81_BIF_PCIE_P_CNTL)/sizeof(ixPSX81_BIF_PCIE_P_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_P_BUF_STATUS", REG_SMC, 0x1410041, &ixPSX81_BIF_PCIE_P_BUF_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_BUF_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_BUF_STATUS[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_P_DECODER_STATUS", REG_SMC, 0x1410042, &ixPSX81_BIF_PCIE_P_DECODER_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_DECODER_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_DECODER_STATUS[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_P_MISC_STATUS", REG_SMC, 0x1410043, &ixPSX81_BIF_PCIE_P_MISC_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_MISC_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_MISC_STATUS[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1410050, &ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT_CNTL", REG_SMC, 0x1410080, &ixPSX81_BIF_PCIE_PERF_COUNT_CNTL[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT_CNTL)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT_CNTL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1410081, &ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1410082, &ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1410083, &ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1410084, &ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1410085, &ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1410086, &ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1410087, &ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1410088, &ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1410089, &ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x141008a, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x141008b, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x141008c, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x141008d, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x141008e, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x141008f, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1410090, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1410091, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1410092, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1410093, &ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1410094, &ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1410095, &ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1410096, &ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1410097, &ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_STRAP_F0", REG_SMC, 0x14100b0, &ixPSX81_BIF_PCIE_STRAP_F0[0], sizeof(ixPSX81_BIF_PCIE_STRAP_F0)/sizeof(ixPSX81_BIF_PCIE_STRAP_F0[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_STRAP_MISC", REG_SMC, 0x14100c0, &ixPSX81_BIF_PCIE_STRAP_MISC[0], sizeof(ixPSX81_BIF_PCIE_STRAP_MISC)/sizeof(ixPSX81_BIF_PCIE_STRAP_MISC[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_STRAP_MISC2", REG_SMC, 0x14100c1, &ixPSX81_BIF_PCIE_STRAP_MISC2[0], sizeof(ixPSX81_BIF_PCIE_STRAP_MISC2)/sizeof(ixPSX81_BIF_PCIE_STRAP_MISC2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_STRAP_PI", REG_SMC, 0x14100c2, &ixPSX81_BIF_PCIE_STRAP_PI[0], sizeof(ixPSX81_BIF_PCIE_STRAP_PI)/sizeof(ixPSX81_BIF_PCIE_STRAP_PI[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_STRAP_I2C_BD", REG_SMC, 0x14100c4, &ixPSX81_BIF_PCIE_STRAP_I2C_BD[0], sizeof(ixPSX81_BIF_PCIE_STRAP_I2C_BD)/sizeof(ixPSX81_BIF_PCIE_STRAP_I2C_BD[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_CLR", REG_SMC, 0x14100c8, &ixPSX81_BIF_PCIE_PRBS_CLR[0], sizeof(ixPSX81_BIF_PCIE_PRBS_CLR)/sizeof(ixPSX81_BIF_PCIE_PRBS_CLR[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_STATUS1", REG_SMC, 0x14100c9, &ixPSX81_BIF_PCIE_PRBS_STATUS1[0], sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS1)/sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS1[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_STATUS2", REG_SMC, 0x14100ca, &ixPSX81_BIF_PCIE_PRBS_STATUS2[0], sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS2)/sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_FREERUN", REG_SMC, 0x14100cb, &ixPSX81_BIF_PCIE_PRBS_FREERUN[0], sizeof(ixPSX81_BIF_PCIE_PRBS_FREERUN)/sizeof(ixPSX81_BIF_PCIE_PRBS_FREERUN[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_MISC", REG_SMC, 0x14100cc, &ixPSX81_BIF_PCIE_PRBS_MISC[0], sizeof(ixPSX81_BIF_PCIE_PRBS_MISC)/sizeof(ixPSX81_BIF_PCIE_PRBS_MISC[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_USER_PATTERN", REG_SMC, 0x14100cd, &ixPSX81_BIF_PCIE_PRBS_USER_PATTERN[0], sizeof(ixPSX81_BIF_PCIE_PRBS_USER_PATTERN)/sizeof(ixPSX81_BIF_PCIE_PRBS_USER_PATTERN[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_LO_BITCNT", REG_SMC, 0x14100ce, &ixPSX81_BIF_PCIE_PRBS_LO_BITCNT[0], sizeof(ixPSX81_BIF_PCIE_PRBS_LO_BITCNT)/sizeof(ixPSX81_BIF_PCIE_PRBS_LO_BITCNT[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_HI_BITCNT", REG_SMC, 0x14100cf, &ixPSX81_BIF_PCIE_PRBS_HI_BITCNT[0], sizeof(ixPSX81_BIF_PCIE_PRBS_HI_BITCNT)/sizeof(ixPSX81_BIF_PCIE_PRBS_HI_BITCNT[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_0", REG_SMC, 0x14100d0, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_0[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_0)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_0[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_1", REG_SMC, 0x14100d1, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_1[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_1)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_1[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_2", REG_SMC, 0x14100d2, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_2[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_2)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_2[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_3", REG_SMC, 0x14100d3, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_3[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_3)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_3[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_4", REG_SMC, 0x14100d4, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_4[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_4)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_4[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_5", REG_SMC, 0x14100d5, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_5[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_5)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_5[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_6", REG_SMC, 0x14100d6, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_6[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_6)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_6[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_7", REG_SMC, 0x14100d7, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_7[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_7)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_7[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_8", REG_SMC, 0x14100d8, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_8[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_8)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_8[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_9", REG_SMC, 0x14100d9, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_9[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_9)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_9[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_10", REG_SMC, 0x14100da, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_10[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_10)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_10[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_11", REG_SMC, 0x14100db, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_11[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_11)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_11[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_12", REG_SMC, 0x14100dc, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_12[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_12)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_12[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_13", REG_SMC, 0x14100dd, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_13[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_13)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_13[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_14", REG_SMC, 0x14100de, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_14[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_14)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_14[0]), 0, 0 }, + { "ixPSX81_BIF_PCIE_PRBS_ERRCNT_15", REG_SMC, 0x14100df, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_15[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_15)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_15[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_COMMAND_STATUS", REG_SMC, 0x1410100, &ixPSX81_BIF_SWRST_COMMAND_STATUS[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_STATUS)/sizeof(ixPSX81_BIF_SWRST_COMMAND_STATUS[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_GENERAL_CONTROL", REG_SMC, 0x1410101, &ixPSX81_BIF_SWRST_GENERAL_CONTROL[0], sizeof(ixPSX81_BIF_SWRST_GENERAL_CONTROL)/sizeof(ixPSX81_BIF_SWRST_GENERAL_CONTROL[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_COMMAND_0", REG_SMC, 0x1410102, &ixPSX81_BIF_SWRST_COMMAND_0[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_0)/sizeof(ixPSX81_BIF_SWRST_COMMAND_0[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_COMMAND_1", REG_SMC, 0x1410103, &ixPSX81_BIF_SWRST_COMMAND_1[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_1)/sizeof(ixPSX81_BIF_SWRST_COMMAND_1[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_0", REG_SMC, 0x1410104, &ixPSX81_BIF_SWRST_CONTROL_0[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_0)/sizeof(ixPSX81_BIF_SWRST_CONTROL_0[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_1", REG_SMC, 0x1410105, &ixPSX81_BIF_SWRST_CONTROL_1[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_1)/sizeof(ixPSX81_BIF_SWRST_CONTROL_1[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_2", REG_SMC, 0x1410106, &ixPSX81_BIF_SWRST_CONTROL_2[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_2)/sizeof(ixPSX81_BIF_SWRST_CONTROL_2[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_3", REG_SMC, 0x1410107, &ixPSX81_BIF_SWRST_CONTROL_3[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_3)/sizeof(ixPSX81_BIF_SWRST_CONTROL_3[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_4", REG_SMC, 0x1410108, &ixPSX81_BIF_SWRST_CONTROL_4[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_4)/sizeof(ixPSX81_BIF_SWRST_CONTROL_4[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_5", REG_SMC, 0x1410109, &ixPSX81_BIF_SWRST_CONTROL_5[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_5)/sizeof(ixPSX81_BIF_SWRST_CONTROL_5[0]), 0, 0 }, + { "ixPSX81_BIF_SWRST_CONTROL_6", REG_SMC, 0x141010a, &ixPSX81_BIF_SWRST_CONTROL_6[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_6)/sizeof(ixPSX81_BIF_SWRST_CONTROL_6[0]), 0, 0 }, + { "ixPSX81_BIF_CPM_CONTROL", REG_SMC, 0x1410118, &ixPSX81_BIF_CPM_CONTROL[0], sizeof(ixPSX81_BIF_CPM_CONTROL)/sizeof(ixPSX81_BIF_CPM_CONTROL[0]), 0, 0 }, + { "ixPSX81_BIF_LM_CONTROL", REG_SMC, 0x1410120, &ixPSX81_BIF_LM_CONTROL[0], sizeof(ixPSX81_BIF_LM_CONTROL)/sizeof(ixPSX81_BIF_LM_CONTROL[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIETXMUX0", REG_SMC, 0x1410121, &ixPSX81_BIF_LM_PCIETXMUX0[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX0)/sizeof(ixPSX81_BIF_LM_PCIETXMUX0[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIETXMUX1", REG_SMC, 0x1410122, &ixPSX81_BIF_LM_PCIETXMUX1[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX1)/sizeof(ixPSX81_BIF_LM_PCIETXMUX1[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIETXMUX2", REG_SMC, 0x1410123, &ixPSX81_BIF_LM_PCIETXMUX2[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX2)/sizeof(ixPSX81_BIF_LM_PCIETXMUX2[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIETXMUX3", REG_SMC, 0x1410124, &ixPSX81_BIF_LM_PCIETXMUX3[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX3)/sizeof(ixPSX81_BIF_LM_PCIETXMUX3[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIERXMUX0", REG_SMC, 0x1410125, &ixPSX81_BIF_LM_PCIERXMUX0[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX0)/sizeof(ixPSX81_BIF_LM_PCIERXMUX0[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIERXMUX1", REG_SMC, 0x1410126, &ixPSX81_BIF_LM_PCIERXMUX1[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX1)/sizeof(ixPSX81_BIF_LM_PCIERXMUX1[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIERXMUX2", REG_SMC, 0x1410127, &ixPSX81_BIF_LM_PCIERXMUX2[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX2)/sizeof(ixPSX81_BIF_LM_PCIERXMUX2[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PCIERXMUX3", REG_SMC, 0x1410128, &ixPSX81_BIF_LM_PCIERXMUX3[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX3)/sizeof(ixPSX81_BIF_LM_PCIERXMUX3[0]), 0, 0 }, + { "ixPSX81_BIF_LM_LANEENABLE", REG_SMC, 0x1410129, &ixPSX81_BIF_LM_LANEENABLE[0], sizeof(ixPSX81_BIF_LM_LANEENABLE)/sizeof(ixPSX81_BIF_LM_LANEENABLE[0]), 0, 0 }, + { "ixPSX81_BIF_LM_PRBSCONTROL", REG_SMC, 0x141012a, &ixPSX81_BIF_LM_PRBSCONTROL[0], sizeof(ixPSX81_BIF_LM_PRBSCONTROL)/sizeof(ixPSX81_BIF_LM_PRBSCONTROL[0]), 0, 0 }, + { "ixPSX81_BIF_LM_POWERCONTROL", REG_SMC, 0x141012b, &ixPSX81_BIF_LM_POWERCONTROL[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL)/sizeof(ixPSX81_BIF_LM_POWERCONTROL[0]), 0, 0 }, + { "ixPSX81_BIF_LM_POWERCONTROL1", REG_SMC, 0x141012c, &ixPSX81_BIF_LM_POWERCONTROL1[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL1)/sizeof(ixPSX81_BIF_LM_POWERCONTROL1[0]), 0, 0 }, + { "ixPSX81_BIF_LM_POWERCONTROL2", REG_SMC, 0x141012d, &ixPSX81_BIF_LM_POWERCONTROL2[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL2)/sizeof(ixPSX81_BIF_LM_POWERCONTROL2[0]), 0, 0 }, + { "ixPSX81_BIF_LM_POWERCONTROL3", REG_SMC, 0x141012e, &ixPSX81_BIF_LM_POWERCONTROL3[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL3)/sizeof(ixPSX81_BIF_LM_POWERCONTROL3[0]), 0, 0 }, + { "ixPSX81_BIF_LM_POWERCONTROL4", REG_SMC, 0x141012f, &ixPSX81_BIF_LM_POWERCONTROL4[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL4)/sizeof(ixPSX81_BIF_LM_POWERCONTROL4[0]), 0, 0 }, + { "mmGARLIC_FLUSH_ADDR_END_7", REG_MMIO, 0x1411, &mmGARLIC_FLUSH_ADDR_END_7[0], sizeof(mmGARLIC_FLUSH_ADDR_END_7)/sizeof(mmGARLIC_FLUSH_ADDR_END_7[0]), 0, 0 }, + { "mmGARLIC_FLUSH_REQ", REG_MMIO, 0x1412, &mmGARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_FLUSH_REQ)/sizeof(mmGARLIC_FLUSH_REQ[0]), 0, 0 }, + { "mmGPU_GARLIC_FLUSH_REQ", REG_MMIO, 0x1413, &mmGPU_GARLIC_FLUSH_REQ[0], sizeof(mmGPU_GARLIC_FLUSH_REQ)/sizeof(mmGPU_GARLIC_FLUSH_REQ[0]), 0, 0 }, + { "mmGPU_GARLIC_FLUSH_DONE", REG_MMIO, 0x1414, &mmGPU_GARLIC_FLUSH_DONE[0], sizeof(mmGPU_GARLIC_FLUSH_DONE)/sizeof(mmGPU_GARLIC_FLUSH_DONE[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_RB0_WPTR", REG_MMIO, 0x1415, &mmGARLIC_COHE_CP_RB0_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB0_WPTR)/sizeof(mmGARLIC_COHE_CP_RB0_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_RB1_WPTR", REG_MMIO, 0x1416, &mmGARLIC_COHE_CP_RB1_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB1_WPTR)/sizeof(mmGARLIC_COHE_CP_RB1_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_RB2_WPTR", REG_MMIO, 0x1417, &mmGARLIC_COHE_CP_RB2_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB2_WPTR)/sizeof(mmGARLIC_COHE_CP_RB2_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_UVD_RBC_RB_WPTR", REG_MMIO, 0x1418, &mmGARLIC_COHE_UVD_RBC_RB_WPTR[0], sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR)/sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_SDMA0_GFX_RB_WPTR", REG_MMIO, 0x1419, &mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_SDMA1_GFX_RB_WPTR", REG_MMIO, 0x141a, &mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_DMA_ME_COMMAND", REG_MMIO, 0x141b, &mmGARLIC_COHE_CP_DMA_ME_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_DMA_PFP_COMMAND", REG_MMIO, 0x141c, &mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0]), 0, 0 }, + { "mmGARLIC_COHE_SAM_SAB_RBI_WPTR", REG_MMIO, 0x141d, &mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_SAM_SAB_RBO_WPTR", REG_MMIO, 0x141e, &mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_VCE_OUT_RB_WPTR", REG_MMIO, 0x141f, &mmGARLIC_COHE_VCE_OUT_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_VCE_RB_WPTR2", REG_MMIO, 0x1420, &mmGARLIC_COHE_VCE_RB_WPTR2[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR2)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR2[0]), 0, 0 }, + { "mmGARLIC_COHE_VCE_RB_WPTR", REG_MMIO, 0x1421, &mmGARLIC_COHE_VCE_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_SDMA2_GFX_RB_WPTR", REG_MMIO, 0x1422, &mmGARLIC_COHE_SDMA2_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA2_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA2_GFX_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_SDMA3_GFX_RB_WPTR", REG_MMIO, 0x1423, &mmGARLIC_COHE_SDMA3_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA3_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA3_GFX_RB_WPTR[0]), 0, 0 }, + { "mmGARLIC_COHE_CP_DMA_PIO_COMMAND", REG_MMIO, 0x1424, &mmGARLIC_COHE_CP_DMA_PIO_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_PIO_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_PIO_COMMAND[0]), 0, 0 }, + { "mmGARLIC_COHE_GARLIC_FLUSH_REQ", REG_MMIO, 0x1425, &mmGARLIC_COHE_GARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_COHE_GARLIC_FLUSH_REQ)/sizeof(mmGARLIC_COHE_GARLIC_FLUSH_REQ[0]), 0, 0 }, + { "mmREMAP_HDP_MEM_FLUSH_CNTL", REG_MMIO, 0x1426, &mmREMAP_HDP_MEM_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL)/sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL[0]), 0, 0 }, + { "mmREMAP_HDP_REG_FLUSH_CNTL", REG_MMIO, 0x1427, &mmREMAP_HDP_REG_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_REG_FLUSH_CNTL)/sizeof(mmREMAP_HDP_REG_FLUSH_CNTL[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX0_LOWER", REG_MMIO, 0x1428, &mmBIF_VDDGFX_GFX0_LOWER[0], sizeof(mmBIF_VDDGFX_GFX0_LOWER)/sizeof(mmBIF_VDDGFX_GFX0_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX0_UPPER", REG_MMIO, 0x1429, &mmBIF_VDDGFX_GFX0_UPPER[0], sizeof(mmBIF_VDDGFX_GFX0_UPPER)/sizeof(mmBIF_VDDGFX_GFX0_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX1_LOWER", REG_MMIO, 0x142a, &mmBIF_VDDGFX_GFX1_LOWER[0], sizeof(mmBIF_VDDGFX_GFX1_LOWER)/sizeof(mmBIF_VDDGFX_GFX1_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX1_UPPER", REG_MMIO, 0x142b, &mmBIF_VDDGFX_GFX1_UPPER[0], sizeof(mmBIF_VDDGFX_GFX1_UPPER)/sizeof(mmBIF_VDDGFX_GFX1_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX2_LOWER", REG_MMIO, 0x142c, &mmBIF_VDDGFX_GFX2_LOWER[0], sizeof(mmBIF_VDDGFX_GFX2_LOWER)/sizeof(mmBIF_VDDGFX_GFX2_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX2_UPPER", REG_MMIO, 0x142d, &mmBIF_VDDGFX_GFX2_UPPER[0], sizeof(mmBIF_VDDGFX_GFX2_UPPER)/sizeof(mmBIF_VDDGFX_GFX2_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX3_LOWER", REG_MMIO, 0x142e, &mmBIF_VDDGFX_GFX3_LOWER[0], sizeof(mmBIF_VDDGFX_GFX3_LOWER)/sizeof(mmBIF_VDDGFX_GFX3_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX3_UPPER", REG_MMIO, 0x142f, &mmBIF_VDDGFX_GFX3_UPPER[0], sizeof(mmBIF_VDDGFX_GFX3_UPPER)/sizeof(mmBIF_VDDGFX_GFX3_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX4_LOWER", REG_MMIO, 0x1430, &mmBIF_VDDGFX_GFX4_LOWER[0], sizeof(mmBIF_VDDGFX_GFX4_LOWER)/sizeof(mmBIF_VDDGFX_GFX4_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX4_UPPER", REG_MMIO, 0x1431, &mmBIF_VDDGFX_GFX4_UPPER[0], sizeof(mmBIF_VDDGFX_GFX4_UPPER)/sizeof(mmBIF_VDDGFX_GFX4_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX5_LOWER", REG_MMIO, 0x1432, &mmBIF_VDDGFX_GFX5_LOWER[0], sizeof(mmBIF_VDDGFX_GFX5_LOWER)/sizeof(mmBIF_VDDGFX_GFX5_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_GFX5_UPPER", REG_MMIO, 0x1433, &mmBIF_VDDGFX_GFX5_UPPER[0], sizeof(mmBIF_VDDGFX_GFX5_UPPER)/sizeof(mmBIF_VDDGFX_GFX5_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV1_LOWER", REG_MMIO, 0x1434, &mmBIF_VDDGFX_RSV1_LOWER[0], sizeof(mmBIF_VDDGFX_RSV1_LOWER)/sizeof(mmBIF_VDDGFX_RSV1_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV1_UPPER", REG_MMIO, 0x1435, &mmBIF_VDDGFX_RSV1_UPPER[0], sizeof(mmBIF_VDDGFX_RSV1_UPPER)/sizeof(mmBIF_VDDGFX_RSV1_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV2_LOWER", REG_MMIO, 0x1436, &mmBIF_VDDGFX_RSV2_LOWER[0], sizeof(mmBIF_VDDGFX_RSV2_LOWER)/sizeof(mmBIF_VDDGFX_RSV2_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV2_UPPER", REG_MMIO, 0x1437, &mmBIF_VDDGFX_RSV2_UPPER[0], sizeof(mmBIF_VDDGFX_RSV2_UPPER)/sizeof(mmBIF_VDDGFX_RSV2_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV3_LOWER", REG_MMIO, 0x1438, &mmBIF_VDDGFX_RSV3_LOWER[0], sizeof(mmBIF_VDDGFX_RSV3_LOWER)/sizeof(mmBIF_VDDGFX_RSV3_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV3_UPPER", REG_MMIO, 0x1439, &mmBIF_VDDGFX_RSV3_UPPER[0], sizeof(mmBIF_VDDGFX_RSV3_UPPER)/sizeof(mmBIF_VDDGFX_RSV3_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV4_LOWER", REG_MMIO, 0x143a, &mmBIF_VDDGFX_RSV4_LOWER[0], sizeof(mmBIF_VDDGFX_RSV4_LOWER)/sizeof(mmBIF_VDDGFX_RSV4_LOWER[0]), 0, 0 }, + { "mmBIF_VDDGFX_RSV4_UPPER", REG_MMIO, 0x143b, &mmBIF_VDDGFX_RSV4_UPPER[0], sizeof(mmBIF_VDDGFX_RSV4_UPPER)/sizeof(mmBIF_VDDGFX_RSV4_UPPER[0]), 0, 0 }, + { "mmBIF_VDDGFX_FB_CMP", REG_MMIO, 0x143c, &mmBIF_VDDGFX_FB_CMP[0], sizeof(mmBIF_VDDGFX_FB_CMP)/sizeof(mmBIF_VDDGFX_FB_CMP[0]), 0, 0 }, + { "mmBIF_SMU_INDEX", REG_MMIO, 0x143d, &mmBIF_SMU_INDEX[0], sizeof(mmBIF_SMU_INDEX)/sizeof(mmBIF_SMU_INDEX[0]), 0, 0 }, + { "mmBIF_SMU_DATA", REG_MMIO, 0x143e, &mmBIF_SMU_DATA[0], sizeof(mmBIF_SMU_DATA)/sizeof(mmBIF_SMU_DATA[0]), 0, 0 }, + { "mmBIF_RFE_SOFTRST_CNTL", REG_MMIO, 0x1441, &mmBIF_RFE_SOFTRST_CNTL[0], sizeof(mmBIF_RFE_SOFTRST_CNTL)/sizeof(mmBIF_RFE_SOFTRST_CNTL[0]), 0, 0 }, + { "mmBIF_RFE_CLIENT_SOFTRST_TRIGGER", REG_MMIO, 0x1442, &mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 }, + { "mmBIF_RFE_MASTER_SOFTRST_TRIGGER", REG_MMIO, 0x1443, &mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 }, + { "mmBIF_PWDN_COMMAND", REG_MMIO, 0x1444, &mmBIF_PWDN_COMMAND[0], sizeof(mmBIF_PWDN_COMMAND)/sizeof(mmBIF_PWDN_COMMAND[0]), 0, 0 }, + { "mmBIF_PWDN_STATUS", REG_MMIO, 0x1445, &mmBIF_PWDN_STATUS[0], sizeof(mmBIF_PWDN_STATUS)/sizeof(mmBIF_PWDN_STATUS[0]), 0, 0 }, + { "mmBIF_RFE_MST_FBU_CMDSTATUS", REG_MMIO, 0x1446, &mmBIF_RFE_MST_FBU_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_FBU_CMDSTATUS)/sizeof(mmBIF_RFE_MST_FBU_CMDSTATUS[0]), 0, 0 }, + { "mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS", REG_MMIO, 0x1447, &mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS)/sizeof(mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS[0]), 0, 0 }, + { "mmBIF_RFE_MST_BX_CMDSTATUS", REG_MMIO, 0x1448, &mmBIF_RFE_MST_BX_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BX_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BX_CMDSTATUS[0]), 0, 0 }, + { "mmBIF_RFE_MST_TMOUT_STATUS", REG_MMIO, 0x144b, &mmBIF_RFE_MST_TMOUT_STATUS[0], sizeof(mmBIF_RFE_MST_TMOUT_STATUS)/sizeof(mmBIF_RFE_MST_TMOUT_STATUS[0]), 0, 0 }, + { "mmBIF_RFE_MMCFG_CNTL", REG_MMIO, 0x144c, &mmBIF_RFE_MMCFG_CNTL[0], sizeof(mmBIF_RFE_MMCFG_CNTL)/sizeof(mmBIF_RFE_MMCFG_CNTL[0]), 0, 0 }, + { "mmBIF_RFE_WARMRST_CNTL", REG_MMIO, 0x1459, &mmBIF_RFE_WARMRST_CNTL[0], sizeof(mmBIF_RFE_WARMRST_CNTL)/sizeof(mmBIF_RFE_WARMRST_CNTL[0]), 0, 0 }, + { "mmBIF_BACO_MSIC", REG_MMIO, 0x1480, &mmBIF_BACO_MSIC[0], sizeof(mmBIF_BACO_MSIC)/sizeof(mmBIF_BACO_MSIC[0]), 0, 0 }, + { "mmBIF_PIF_TXCLK_SWITCH_TIMER", REG_MMIO, 0x1481, &mmBIF_PIF_TXCLK_SWITCH_TIMER[0], sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER)/sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER[0]), 0, 0 }, + { "mmBIF_RESET_EN", REG_MMIO, 0x1482, &mmBIF_RESET_EN[0], sizeof(mmBIF_RESET_EN)/sizeof(mmBIF_RESET_EN[0]), 0, 0 }, + { "mmBIF_CLK_PDWN_DELAY_TIMER", REG_MMIO, 0x1483, &mmBIF_CLK_PDWN_DELAY_TIMER[0], sizeof(mmBIF_CLK_PDWN_DELAY_TIMER)/sizeof(mmBIF_CLK_PDWN_DELAY_TIMER[0]), 0, 0 }, + { "mmNEW_REFCLKB_TIMER_1", REG_MMIO, 0x1484, &mmNEW_REFCLKB_TIMER_1[0], sizeof(mmNEW_REFCLKB_TIMER_1)/sizeof(mmNEW_REFCLKB_TIMER_1[0]), 0, 0 }, + { "mmNEW_REFCLKB_TIMER", REG_MMIO, 0x1485, &mmNEW_REFCLKB_TIMER[0], sizeof(mmNEW_REFCLKB_TIMER)/sizeof(mmNEW_REFCLKB_TIMER[0]), 0, 0 }, + { "mmBIF_RESET_CNTL", REG_MMIO, 0x1486, &mmBIF_RESET_CNTL[0], sizeof(mmBIF_RESET_CNTL)/sizeof(mmBIF_RESET_CNTL[0]), 0, 0 }, + { "mmLNCNT_CONTROL", REG_MMIO, 0x1487, &mmLNCNT_CONTROL[0], sizeof(mmLNCNT_CONTROL)/sizeof(mmLNCNT_CONTROL[0]), 0, 0 }, + { "mmBIF_LNCNT_RESET", REG_MMIO, 0x1488, &mmBIF_LNCNT_RESET[0], sizeof(mmBIF_LNCNT_RESET)/sizeof(mmBIF_LNCNT_RESET[0]), 0, 0 }, + { "mmBIF_CLOCKS_BITS", REG_MMIO, 0x1489, &mmBIF_CLOCKS_BITS[0], sizeof(mmBIF_CLOCKS_BITS)/sizeof(mmBIF_CLOCKS_BITS[0]), 0, 0 }, + { "mmBIF_MEM_PG_CNTL", REG_MMIO, 0x148a, &mmBIF_MEM_PG_CNTL[0], sizeof(mmBIF_MEM_PG_CNTL)/sizeof(mmBIF_MEM_PG_CNTL[0]), 0, 0 }, + { "mmBIF_RFE_CNTL_MISC", REG_MMIO, 0x148c, &mmBIF_RFE_CNTL_MISC[0], sizeof(mmBIF_RFE_CNTL_MISC)/sizeof(mmBIF_RFE_CNTL_MISC[0]), 0, 0 }, + { "mmBIF_XDMA_LO", REG_MMIO, 0x14c0, &mmBIF_XDMA_LO[0], sizeof(mmBIF_XDMA_LO)/sizeof(mmBIF_XDMA_LO[0]), 0, 0 }, + { "mmBIF_XDMA_HI", REG_MMIO, 0x14c1, &mmBIF_XDMA_HI[0], sizeof(mmBIF_XDMA_HI)/sizeof(mmBIF_XDMA_HI[0]), 0, 0 }, + { "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x14c2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 }, + { "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x14c3, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 }, + { "mmBIF_SLVARB_MODE", REG_MMIO, 0x14c4, &mmBIF_SLVARB_MODE[0], sizeof(mmBIF_SLVARB_MODE)/sizeof(mmBIF_SLVARB_MODE[0]), 0, 0 }, + { "mmSMBUS_BACO_DUMMY", REG_MMIO, 0x14c6, &mmSMBUS_BACO_DUMMY[0], sizeof(mmSMBUS_BACO_DUMMY)/sizeof(mmSMBUS_BACO_DUMMY[0]), 0, 0 }, + { "mmBF_ANA_ISO_CNTL", REG_MMIO, 0x14c7, &mmBF_ANA_ISO_CNTL[0], sizeof(mmBF_ANA_ISO_CNTL)/sizeof(mmBF_ANA_ISO_CNTL[0]), 0, 0 }, + { "mmBACO_CNTL_MISC", REG_MMIO, 0x14db, &mmBACO_CNTL_MISC[0], sizeof(mmBACO_CNTL_MISC)/sizeof(mmBACO_CNTL_MISC[0]), 0, 0 }, + { "mmBIF_BACO_DEBUG_LATCH", REG_MMIO, 0x14dc, &mmBIF_BACO_DEBUG_LATCH[0], sizeof(mmBIF_BACO_DEBUG_LATCH)/sizeof(mmBIF_BACO_DEBUG_LATCH[0]), 0, 0 }, + { "mmBIF_BACO_DEBUG", REG_MMIO, 0x14df, &mmBIF_BACO_DEBUG[0], sizeof(mmBIF_BACO_DEBUG)/sizeof(mmBIF_BACO_DEBUG[0]), 0, 0 }, + { "mmMEM_TYPE_CNTL", REG_MMIO, 0x14e4, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 }, + { "mmBACO_CNTL", REG_MMIO, 0x14e5, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 }, + { "mmBIF_DEVFUNCNUM_LIST1", REG_MMIO, 0x14e7, &mmBIF_DEVFUNCNUM_LIST1[0], sizeof(mmBIF_DEVFUNCNUM_LIST1)/sizeof(mmBIF_DEVFUNCNUM_LIST1[0]), 0, 0 }, + { "mmBIF_DEVFUNCNUM_LIST0", REG_MMIO, 0x14e8, &mmBIF_DEVFUNCNUM_LIST0[0], sizeof(mmBIF_DEVFUNCNUM_LIST0)/sizeof(mmBIF_DEVFUNCNUM_LIST0[0]), 0, 0 }, + { "mmDBG_BYPASS_SRBM_ACCESS", REG_MMIO, 0x14eb, &mmDBG_BYPASS_SRBM_ACCESS[0], sizeof(mmDBG_BYPASS_SRBM_ACCESS)/sizeof(mmDBG_BYPASS_SRBM_ACCESS[0]), 0, 0 }, + { "mmPEER3_FB_OFFSET_LO", REG_MMIO, 0x14ec, &mmPEER3_FB_OFFSET_LO[0], sizeof(mmPEER3_FB_OFFSET_LO)/sizeof(mmPEER3_FB_OFFSET_LO[0]), 0, 0 }, + { "mmPEER3_FB_OFFSET_HI", REG_MMIO, 0x14ed, &mmPEER3_FB_OFFSET_HI[0], sizeof(mmPEER3_FB_OFFSET_HI)/sizeof(mmPEER3_FB_OFFSET_HI[0]), 0, 0 }, + { "mmPEER2_FB_OFFSET_LO", REG_MMIO, 0x14ee, &mmPEER2_FB_OFFSET_LO[0], sizeof(mmPEER2_FB_OFFSET_LO)/sizeof(mmPEER2_FB_OFFSET_LO[0]), 0, 0 }, + { "mmPEER2_FB_OFFSET_HI", REG_MMIO, 0x14ef, &mmPEER2_FB_OFFSET_HI[0], sizeof(mmPEER2_FB_OFFSET_HI)/sizeof(mmPEER2_FB_OFFSET_HI[0]), 0, 0 }, + { "mmPEER1_FB_OFFSET_LO", REG_MMIO, 0x14f0, &mmPEER1_FB_OFFSET_LO[0], sizeof(mmPEER1_FB_OFFSET_LO)/sizeof(mmPEER1_FB_OFFSET_LO[0]), 0, 0 }, + { "mmPEER1_FB_OFFSET_HI", REG_MMIO, 0x14f1, &mmPEER1_FB_OFFSET_HI[0], sizeof(mmPEER1_FB_OFFSET_HI)/sizeof(mmPEER1_FB_OFFSET_HI[0]), 0, 0 }, + { "mmPEER0_FB_OFFSET_LO", REG_MMIO, 0x14f2, &mmPEER0_FB_OFFSET_LO[0], sizeof(mmPEER0_FB_OFFSET_LO)/sizeof(mmPEER0_FB_OFFSET_LO[0]), 0, 0 }, + { "mmPEER0_FB_OFFSET_HI", REG_MMIO, 0x14f3, &mmPEER0_FB_OFFSET_HI[0], sizeof(mmPEER0_FB_OFFSET_HI)/sizeof(mmPEER0_FB_OFFSET_HI[0]), 0, 0 }, + { "mmIMPCTL_RESET", REG_MMIO, 0x14f5, &mmIMPCTL_RESET[0], sizeof(mmIMPCTL_RESET)/sizeof(mmIMPCTL_RESET[0]), 0, 0 }, + { "mmSMU_BIF_VDDGFX_PWR_STATUS", REG_MMIO, 0x14f8, &mmSMU_BIF_VDDGFX_PWR_STATUS[0], sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS)/sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER1_LOWER", REG_MMIO, 0x14fc, &mmBIF_DOORBELL_GBLAPER1_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER1_UPPER", REG_MMIO, 0x14fd, &mmBIF_DOORBELL_GBLAPER1_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER2_LOWER", REG_MMIO, 0x14fe, &mmBIF_DOORBELL_GBLAPER2_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER[0]), 0, 0 }, + { "mmBIF_DOORBELL_GBLAPER2_UPPER", REG_MMIO, 0x14ff, &mmBIF_DOORBELL_GBLAPER2_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER[0]), 0, 0 }, + { "mmPMI_STATUS_CNTL", REG_MMIO, 0x15, &mmPMI_STATUS_CNTL[0], sizeof(mmPMI_STATUS_CNTL)/sizeof(mmPMI_STATUS_CNTL[0]), 0, 0 }, + { "mmBIF_MM_INDACCESS_CNTL", REG_MMIO, 0x1500, &mmBIF_MM_INDACCESS_CNTL[0], sizeof(mmBIF_MM_INDACCESS_CNTL)/sizeof(mmBIF_MM_INDACCESS_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1", REG_SMC, 0x1500000, &ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1[0], sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1)/sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_PI_CNTL", REG_SMC, 0x1500001, &ixPSX80_WRP_BIF_STRAP_PI_CNTL[0], sizeof(ixPSX80_WRP_BIF_STRAP_PI_CNTL)/sizeof(ixPSX80_WRP_BIF_STRAP_PI_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE", REG_SMC, 0x1500002, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE", REG_SMC, 0x1500003, &ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE", REG_SMC, 0x1500004, &ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE)/sizeof(ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_TEST_DFT", REG_SMC, 0x1500005, &ixPSX80_WRP_BIF_STRAP_TEST_DFT[0], sizeof(ixPSX80_WRP_BIF_STRAP_TEST_DFT)/sizeof(ixPSX80_WRP_BIF_STRAP_TEST_DFT[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ID", REG_SMC, 0x1500006, NULL, 0, 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_REV_ID", REG_SMC, 0x1500007, NULL, 0, 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_I2C_CNTL", REG_SMC, 0x1500008, NULL, 0, 0, 0 }, + { "ixPSX80_WRP_BIF_INT_CNTL", REG_SMC, 0x1500009, &ixPSX80_WRP_BIF_INT_CNTL[0], sizeof(ixPSX80_WRP_BIF_INT_CNTL)/sizeof(ixPSX80_WRP_BIF_INT_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ACS", REG_SMC, 0x150000a, &ixPSX80_WRP_BIF_STRAP_ACS[0], sizeof(ixPSX80_WRP_BIF_STRAP_ACS)/sizeof(ixPSX80_WRP_BIF_STRAP_ACS[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_PM", REG_SMC, 0x150000b, NULL, 0, 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2", REG_SMC, 0x150000c, &ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2[0], sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2)/sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_SERIAL_NUM", REG_SMC, 0x1500045, NULL, 0, 0, 0 }, + { "ixPSX80_WRP_BIF_SSID", REG_SMC, 0x1500046, &ixPSX80_WRP_BIF_SSID[0], sizeof(ixPSX80_WRP_BIF_SSID)/sizeof(ixPSX80_WRP_BIF_SSID[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL", REG_SMC, 0x1500050, &ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL[0], sizeof(ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL)/sizeof(ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_LINK_CONFIG", REG_SMC, 0x1500080, &ixPSX80_WRP_PCIE_LINK_CONFIG[0], sizeof(ixPSX80_WRP_PCIE_LINK_CONFIG)/sizeof(ixPSX80_WRP_PCIE_LINK_CONFIG[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_HOLD_TRAINING_A", REG_SMC, 0x1500800, &ixPSX80_WRP_PCIE_HOLD_TRAINING_A[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_A)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_A[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A", REG_SMC, 0x1500801, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ASPM_A", REG_SMC, 0x1500802, &ixPSX80_WRP_BIF_STRAP_ASPM_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_A)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_A[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A", REG_SMC, 0x1500803, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_MISC_PORT_A", REG_SMC, 0x1500804, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_A[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A", REG_SMC, 0x1500805, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_PORT_IS_SB_A", REG_SMC, 0x1500813, &ixPSX80_WRP_PCIE_PORT_IS_SB_A[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_A)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_A[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_HOLD_TRAINING_B", REG_SMC, 0x1500900, &ixPSX80_WRP_PCIE_HOLD_TRAINING_B[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_B)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_B[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B", REG_SMC, 0x1500901, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ASPM_B", REG_SMC, 0x1500902, &ixPSX80_WRP_BIF_STRAP_ASPM_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_B)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_B[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B", REG_SMC, 0x1500903, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_MISC_PORT_B", REG_SMC, 0x1500904, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_B[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B", REG_SMC, 0x1500905, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_PORT_IS_SB_B", REG_SMC, 0x1500913, &ixPSX80_WRP_PCIE_PORT_IS_SB_B[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_B)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_B[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_HOLD_TRAINING_C", REG_SMC, 0x1500a00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_C[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_C)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_C[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C", REG_SMC, 0x1500a01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ASPM_C", REG_SMC, 0x1500a02, &ixPSX80_WRP_BIF_STRAP_ASPM_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_C)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_C[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C", REG_SMC, 0x1500a03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_MISC_PORT_C", REG_SMC, 0x1500a04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_C[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C", REG_SMC, 0x1500a05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_PORT_IS_SB_C", REG_SMC, 0x1500a13, &ixPSX80_WRP_PCIE_PORT_IS_SB_C[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_C)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_C[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_HOLD_TRAINING_D", REG_SMC, 0x1500b00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_D[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_D)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_D[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D", REG_SMC, 0x1500b01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ASPM_D", REG_SMC, 0x1500b02, &ixPSX80_WRP_BIF_STRAP_ASPM_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_D)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_D[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D", REG_SMC, 0x1500b03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_MISC_PORT_D", REG_SMC, 0x1500b04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_D[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D", REG_SMC, 0x1500b05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_PORT_IS_SB_D", REG_SMC, 0x1500b13, &ixPSX80_WRP_PCIE_PORT_IS_SB_D[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_D)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_D[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_HOLD_TRAINING_E", REG_SMC, 0x1500c00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_E[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_E)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_E[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E", REG_SMC, 0x1500c01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_ASPM_E", REG_SMC, 0x1500c02, &ixPSX80_WRP_BIF_STRAP_ASPM_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_E)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_E[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E", REG_SMC, 0x1500c03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_MISC_PORT_E", REG_SMC, 0x1500c04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_E[0]), 0, 0 }, + { "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E", REG_SMC, 0x1500c05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_PORT_IS_SB_E", REG_SMC, 0x1500c13, &ixPSX80_WRP_PCIE_PORT_IS_SB_E[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_E)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_E[0]), 0, 0 }, + { "mmBUS_CNTL", REG_MMIO, 0x1508, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 }, + { "ixPSX80_WRP_LNCNT_CONTROL", REG_SMC, 0x1508030, &ixPSX80_WRP_LNCNT_CONTROL[0], sizeof(ixPSX80_WRP_LNCNT_CONTROL)/sizeof(ixPSX80_WRP_LNCNT_CONTROL[0]), 0, 0 }, + { "ixPSX80_WRP_CFG_LNC_WINDOW", REG_SMC, 0x1508031, &ixPSX80_WRP_CFG_LNC_WINDOW[0], sizeof(ixPSX80_WRP_CFG_LNC_WINDOW)/sizeof(ixPSX80_WRP_CFG_LNC_WINDOW[0]), 0, 0 }, + { "ixPSX80_WRP_LNCNT_QUAN_THRD", REG_SMC, 0x1508032, &ixPSX80_WRP_LNCNT_QUAN_THRD[0], sizeof(ixPSX80_WRP_LNCNT_QUAN_THRD)/sizeof(ixPSX80_WRP_LNCNT_QUAN_THRD[0]), 0, 0 }, + { "ixPSX80_WRP_LNCNT_WEIGHT", REG_SMC, 0x1508033, &ixPSX80_WRP_LNCNT_WEIGHT[0], sizeof(ixPSX80_WRP_LNCNT_WEIGHT)/sizeof(ixPSX80_WRP_LNCNT_WEIGHT[0]), 0, 0 }, + { "ixPSX80_WRP_LNC_TOTAL_WACC", REG_SMC, 0x1508034, &ixPSX80_WRP_LNC_TOTAL_WACC[0], sizeof(ixPSX80_WRP_LNC_TOTAL_WACC)/sizeof(ixPSX80_WRP_LNC_TOTAL_WACC[0]), 0, 0 }, + { "ixPSX80_WRP_LNC_BW_WACC", REG_SMC, 0x1508035, &ixPSX80_WRP_LNC_BW_WACC[0], sizeof(ixPSX80_WRP_LNC_BW_WACC)/sizeof(ixPSX80_WRP_LNC_BW_WACC[0]), 0, 0 }, + { "ixPSX80_WRP_LNC_CMN_WACC", REG_SMC, 0x1508036, &ixPSX80_WRP_LNC_CMN_WACC[0], sizeof(ixPSX80_WRP_LNC_CMN_WACC)/sizeof(ixPSX80_WRP_LNC_CMN_WACC[0]), 0, 0 }, + { "mmCONFIG_CNTL", REG_MMIO, 0x1509, &mmCONFIG_CNTL[0], sizeof(mmCONFIG_CNTL)/sizeof(mmCONFIG_CNTL[0]), 0, 0 }, + { "mmCONFIG_MEMSIZE", REG_MMIO, 0x150a, &mmCONFIG_MEMSIZE[0], sizeof(mmCONFIG_MEMSIZE)/sizeof(mmCONFIG_MEMSIZE[0]), 0, 0 }, + { "mmCONFIG_F0_BASE", REG_MMIO, 0x150b, &mmCONFIG_F0_BASE[0], sizeof(mmCONFIG_F0_BASE)/sizeof(mmCONFIG_F0_BASE[0]), 0, 0 }, + { "mmCONFIG_APER_SIZE", REG_MMIO, 0x150c, &mmCONFIG_APER_SIZE[0], sizeof(mmCONFIG_APER_SIZE)/sizeof(mmCONFIG_APER_SIZE[0]), 0, 0 }, + { "mmCONFIG_REG_APER_SIZE", REG_MMIO, 0x150d, &mmCONFIG_REG_APER_SIZE[0], sizeof(mmCONFIG_REG_APER_SIZE)/sizeof(mmCONFIG_REG_APER_SIZE[0]), 0, 0 }, + { "mmBIF_SCRATCH0", REG_MMIO, 0x150e, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 }, + { "mmBIF_SCRATCH1", REG_MMIO, 0x150f, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE", REG_SMC, 0x150fff0, &ixPSX80_WRP_PCIE_EFUSE[0], sizeof(ixPSX80_WRP_PCIE_EFUSE)/sizeof(ixPSX80_WRP_PCIE_EFUSE[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE2", REG_SMC, 0x150fff1, &ixPSX80_WRP_PCIE_EFUSE2[0], sizeof(ixPSX80_WRP_PCIE_EFUSE2)/sizeof(ixPSX80_WRP_PCIE_EFUSE2[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE3", REG_SMC, 0x150fff2, &ixPSX80_WRP_PCIE_EFUSE3[0], sizeof(ixPSX80_WRP_PCIE_EFUSE3)/sizeof(ixPSX80_WRP_PCIE_EFUSE3[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE4", REG_SMC, 0x150fff3, &ixPSX80_WRP_PCIE_EFUSE4[0], sizeof(ixPSX80_WRP_PCIE_EFUSE4)/sizeof(ixPSX80_WRP_PCIE_EFUSE4[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE5", REG_SMC, 0x150fff4, &ixPSX80_WRP_PCIE_EFUSE5[0], sizeof(ixPSX80_WRP_PCIE_EFUSE5)/sizeof(ixPSX80_WRP_PCIE_EFUSE5[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE6", REG_SMC, 0x150fff5, &ixPSX80_WRP_PCIE_EFUSE6[0], sizeof(ixPSX80_WRP_PCIE_EFUSE6)/sizeof(ixPSX80_WRP_PCIE_EFUSE6[0]), 0, 0 }, + { "ixPSX80_WRP_PCIE_EFUSE7", REG_SMC, 0x150fff6, &ixPSX80_WRP_PCIE_EFUSE7[0], sizeof(ixPSX80_WRP_PCIE_EFUSE7)/sizeof(ixPSX80_WRP_PCIE_EFUSE7[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1", REG_SMC, 0x1510000, &ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1[0], sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1)/sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_PI_CNTL", REG_SMC, 0x1510001, &ixPSX81_WRP_BIF_STRAP_PI_CNTL[0], sizeof(ixPSX81_WRP_BIF_STRAP_PI_CNTL)/sizeof(ixPSX81_WRP_BIF_STRAP_PI_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE", REG_SMC, 0x1510002, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE", REG_SMC, 0x1510003, &ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE", REG_SMC, 0x1510004, &ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE)/sizeof(ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_TEST_DFT", REG_SMC, 0x1510005, &ixPSX81_WRP_BIF_STRAP_TEST_DFT[0], sizeof(ixPSX81_WRP_BIF_STRAP_TEST_DFT)/sizeof(ixPSX81_WRP_BIF_STRAP_TEST_DFT[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ID", REG_SMC, 0x1510006, NULL, 0, 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_REV_ID", REG_SMC, 0x1510007, NULL, 0, 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_I2C_CNTL", REG_SMC, 0x1510008, NULL, 0, 0, 0 }, + { "ixPSX81_WRP_BIF_INT_CNTL", REG_SMC, 0x1510009, &ixPSX81_WRP_BIF_INT_CNTL[0], sizeof(ixPSX81_WRP_BIF_INT_CNTL)/sizeof(ixPSX81_WRP_BIF_INT_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ACS", REG_SMC, 0x151000a, &ixPSX81_WRP_BIF_STRAP_ACS[0], sizeof(ixPSX81_WRP_BIF_STRAP_ACS)/sizeof(ixPSX81_WRP_BIF_STRAP_ACS[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_PM", REG_SMC, 0x151000b, NULL, 0, 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2", REG_SMC, 0x151000c, &ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2[0], sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2)/sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_SERIAL_NUM", REG_SMC, 0x1510045, NULL, 0, 0, 0 }, + { "ixPSX81_WRP_BIF_SSID", REG_SMC, 0x1510046, &ixPSX81_WRP_BIF_SSID[0], sizeof(ixPSX81_WRP_BIF_SSID)/sizeof(ixPSX81_WRP_BIF_SSID[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL", REG_SMC, 0x1510050, &ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL[0], sizeof(ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL)/sizeof(ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_LINK_CONFIG", REG_SMC, 0x1510080, &ixPSX81_WRP_PCIE_LINK_CONFIG[0], sizeof(ixPSX81_WRP_PCIE_LINK_CONFIG)/sizeof(ixPSX81_WRP_PCIE_LINK_CONFIG[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_HOLD_TRAINING_A", REG_SMC, 0x1510800, &ixPSX81_WRP_PCIE_HOLD_TRAINING_A[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_A)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_A[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A", REG_SMC, 0x1510801, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ASPM_A", REG_SMC, 0x1510802, &ixPSX81_WRP_BIF_STRAP_ASPM_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_A)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_A[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A", REG_SMC, 0x1510803, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_MISC_PORT_A", REG_SMC, 0x1510804, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_A[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A", REG_SMC, 0x1510805, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_PORT_IS_SB_A", REG_SMC, 0x1510813, &ixPSX81_WRP_PCIE_PORT_IS_SB_A[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_A)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_A[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_HOLD_TRAINING_B", REG_SMC, 0x1510900, &ixPSX81_WRP_PCIE_HOLD_TRAINING_B[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_B)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_B[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B", REG_SMC, 0x1510901, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ASPM_B", REG_SMC, 0x1510902, &ixPSX81_WRP_BIF_STRAP_ASPM_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_B)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_B[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B", REG_SMC, 0x1510903, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_MISC_PORT_B", REG_SMC, 0x1510904, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_B[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B", REG_SMC, 0x1510905, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_PORT_IS_SB_B", REG_SMC, 0x1510913, &ixPSX81_WRP_PCIE_PORT_IS_SB_B[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_B)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_B[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_HOLD_TRAINING_C", REG_SMC, 0x1510a00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_C[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_C)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_C[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C", REG_SMC, 0x1510a01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ASPM_C", REG_SMC, 0x1510a02, &ixPSX81_WRP_BIF_STRAP_ASPM_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_C)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_C[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C", REG_SMC, 0x1510a03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_MISC_PORT_C", REG_SMC, 0x1510a04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_C[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C", REG_SMC, 0x1510a05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_PORT_IS_SB_C", REG_SMC, 0x1510a13, &ixPSX81_WRP_PCIE_PORT_IS_SB_C[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_C)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_C[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_HOLD_TRAINING_D", REG_SMC, 0x1510b00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_D[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_D)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_D[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D", REG_SMC, 0x1510b01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ASPM_D", REG_SMC, 0x1510b02, &ixPSX81_WRP_BIF_STRAP_ASPM_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_D)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_D[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D", REG_SMC, 0x1510b03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_MISC_PORT_D", REG_SMC, 0x1510b04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_D[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D", REG_SMC, 0x1510b05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_PORT_IS_SB_D", REG_SMC, 0x1510b13, &ixPSX81_WRP_PCIE_PORT_IS_SB_D[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_D)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_D[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_HOLD_TRAINING_E", REG_SMC, 0x1510c00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_E[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_E)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_E[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E", REG_SMC, 0x1510c01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_ASPM_E", REG_SMC, 0x1510c02, &ixPSX81_WRP_BIF_STRAP_ASPM_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_E)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_E[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E", REG_SMC, 0x1510c03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_MISC_PORT_E", REG_SMC, 0x1510c04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_E[0]), 0, 0 }, + { "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E", REG_SMC, 0x1510c05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_PORT_IS_SB_E", REG_SMC, 0x1510c13, &ixPSX81_WRP_PCIE_PORT_IS_SB_E[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_E)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_E[0]), 0, 0 }, + { "mmMM_CFGREGS_CNTL", REG_MMIO, 0x1513, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 }, + { "mmBX_RESET_EN", REG_MMIO, 0x1514, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 }, + { "mmHW_DEBUG", REG_MMIO, 0x1515, &mmHW_DEBUG[0], sizeof(mmHW_DEBUG)/sizeof(mmHW_DEBUG[0]), 0, 0 }, + { "mmMASTER_CREDIT_CNTL", REG_MMIO, 0x1516, &mmMASTER_CREDIT_CNTL[0], sizeof(mmMASTER_CREDIT_CNTL)/sizeof(mmMASTER_CREDIT_CNTL[0]), 0, 0 }, + { "mmSLAVE_REQ_CREDIT_CNTL", REG_MMIO, 0x1517, &mmSLAVE_REQ_CREDIT_CNTL[0], sizeof(mmSLAVE_REQ_CREDIT_CNTL)/sizeof(mmSLAVE_REQ_CREDIT_CNTL[0]), 0, 0 }, + { "mmBX_RESET_CNTL", REG_MMIO, 0x1518, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 }, + { "ixPSX81_WRP_LNCNT_CONTROL", REG_SMC, 0x1518030, &ixPSX81_WRP_LNCNT_CONTROL[0], sizeof(ixPSX81_WRP_LNCNT_CONTROL)/sizeof(ixPSX81_WRP_LNCNT_CONTROL[0]), 0, 0 }, + { "ixPSX81_WRP_CFG_LNC_WINDOW", REG_SMC, 0x1518031, &ixPSX81_WRP_CFG_LNC_WINDOW[0], sizeof(ixPSX81_WRP_CFG_LNC_WINDOW)/sizeof(ixPSX81_WRP_CFG_LNC_WINDOW[0]), 0, 0 }, + { "ixPSX81_WRP_LNCNT_QUAN_THRD", REG_SMC, 0x1518032, &ixPSX81_WRP_LNCNT_QUAN_THRD[0], sizeof(ixPSX81_WRP_LNCNT_QUAN_THRD)/sizeof(ixPSX81_WRP_LNCNT_QUAN_THRD[0]), 0, 0 }, + { "ixPSX81_WRP_LNCNT_WEIGHT", REG_SMC, 0x1518033, &ixPSX81_WRP_LNCNT_WEIGHT[0], sizeof(ixPSX81_WRP_LNCNT_WEIGHT)/sizeof(ixPSX81_WRP_LNCNT_WEIGHT[0]), 0, 0 }, + { "ixPSX81_WRP_LNC_TOTAL_WACC", REG_SMC, 0x1518034, &ixPSX81_WRP_LNC_TOTAL_WACC[0], sizeof(ixPSX81_WRP_LNC_TOTAL_WACC)/sizeof(ixPSX81_WRP_LNC_TOTAL_WACC[0]), 0, 0 }, + { "ixPSX81_WRP_LNC_BW_WACC", REG_SMC, 0x1518035, &ixPSX81_WRP_LNC_BW_WACC[0], sizeof(ixPSX81_WRP_LNC_BW_WACC)/sizeof(ixPSX81_WRP_LNC_BW_WACC[0]), 0, 0 }, + { "ixPSX81_WRP_LNC_CMN_WACC", REG_SMC, 0x1518036, &ixPSX81_WRP_LNC_CMN_WACC[0], sizeof(ixPSX81_WRP_LNC_CMN_WACC)/sizeof(ixPSX81_WRP_LNC_CMN_WACC[0]), 0, 0 }, + { "mmINTERRUPT_CNTL", REG_MMIO, 0x151a, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 }, + { "mmINTERRUPT_CNTL2", REG_MMIO, 0x151b, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 }, + { "mmBIF_DEBUG_CNTL", REG_MMIO, 0x151c, &mmBIF_DEBUG_CNTL[0], sizeof(mmBIF_DEBUG_CNTL)/sizeof(mmBIF_DEBUG_CNTL[0]), 0, 0 }, + { "mmBIF_DEBUG_MUX", REG_MMIO, 0x151d, &mmBIF_DEBUG_MUX[0], sizeof(mmBIF_DEBUG_MUX)/sizeof(mmBIF_DEBUG_MUX[0]), 0, 0 }, + { "mmBIF_DEBUG_OUT", REG_MMIO, 0x151e, &mmBIF_DEBUG_OUT[0], sizeof(mmBIF_DEBUG_OUT)/sizeof(mmBIF_DEBUG_OUT[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE", REG_SMC, 0x151fff0, &ixPSX81_WRP_PCIE_EFUSE[0], sizeof(ixPSX81_WRP_PCIE_EFUSE)/sizeof(ixPSX81_WRP_PCIE_EFUSE[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE2", REG_SMC, 0x151fff1, &ixPSX81_WRP_PCIE_EFUSE2[0], sizeof(ixPSX81_WRP_PCIE_EFUSE2)/sizeof(ixPSX81_WRP_PCIE_EFUSE2[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE3", REG_SMC, 0x151fff2, &ixPSX81_WRP_PCIE_EFUSE3[0], sizeof(ixPSX81_WRP_PCIE_EFUSE3)/sizeof(ixPSX81_WRP_PCIE_EFUSE3[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE4", REG_SMC, 0x151fff3, &ixPSX81_WRP_PCIE_EFUSE4[0], sizeof(ixPSX81_WRP_PCIE_EFUSE4)/sizeof(ixPSX81_WRP_PCIE_EFUSE4[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE5", REG_SMC, 0x151fff4, &ixPSX81_WRP_PCIE_EFUSE5[0], sizeof(ixPSX81_WRP_PCIE_EFUSE5)/sizeof(ixPSX81_WRP_PCIE_EFUSE5[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE6", REG_SMC, 0x151fff5, &ixPSX81_WRP_PCIE_EFUSE6[0], sizeof(ixPSX81_WRP_PCIE_EFUSE6)/sizeof(ixPSX81_WRP_PCIE_EFUSE6[0]), 0, 0 }, + { "ixPSX81_WRP_PCIE_EFUSE7", REG_SMC, 0x151fff6, &ixPSX81_WRP_PCIE_EFUSE7[0], sizeof(ixPSX81_WRP_PCIE_EFUSE7)/sizeof(ixPSX81_WRP_PCIE_EFUSE7[0]), 0, 0 }, + { "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1520, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, + { "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x1521, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 }, + { "mmSMBDAT_PAD_CNTL", REG_MMIO, 0x1522, &mmSMBDAT_PAD_CNTL[0], sizeof(mmSMBDAT_PAD_CNTL)/sizeof(mmSMBDAT_PAD_CNTL[0]), 0, 0 }, + { "mmSMBCLK_PAD_CNTL", REG_MMIO, 0x1523, &mmSMBCLK_PAD_CNTL[0], sizeof(mmSMBCLK_PAD_CNTL)/sizeof(mmSMBCLK_PAD_CNTL[0]), 0, 0 }, + { "mmBIF_FB_EN", REG_MMIO, 0x1524, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 }, + { "mmBIF_BUSNUM_CNTL1", REG_MMIO, 0x1525, &mmBIF_BUSNUM_CNTL1[0], sizeof(mmBIF_BUSNUM_CNTL1)/sizeof(mmBIF_BUSNUM_CNTL1[0]), 0, 0 }, + { "mmBIF_BUSNUM_LIST0", REG_MMIO, 0x1526, &mmBIF_BUSNUM_LIST0[0], sizeof(mmBIF_BUSNUM_LIST0)/sizeof(mmBIF_BUSNUM_LIST0[0]), 0, 0 }, + { "mmBIF_BUSNUM_LIST1", REG_MMIO, 0x1527, &mmBIF_BUSNUM_LIST1[0], sizeof(mmBIF_BUSNUM_LIST1)/sizeof(mmBIF_BUSNUM_LIST1[0]), 0, 0 }, + { "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1528, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 }, + { "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x1529, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 }, + { "mmBIF_BUSNUM_CNTL2", REG_MMIO, 0x152b, &mmBIF_BUSNUM_CNTL2[0], sizeof(mmBIF_BUSNUM_CNTL2)/sizeof(mmBIF_BUSNUM_CNTL2[0]), 0, 0 }, + { "mmBIF_PERFMON_CNTL", REG_MMIO, 0x152c, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 }, + { "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x152d, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 }, + { "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x152e, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 }, + { "mmBIF_RB_CNTL", REG_MMIO, 0x1530, &mmBIF_RB_CNTL[0], sizeof(mmBIF_RB_CNTL)/sizeof(mmBIF_RB_CNTL[0]), 0, 0 }, + { "mmBIF_RB_BASE", REG_MMIO, 0x1531, &mmBIF_RB_BASE[0], sizeof(mmBIF_RB_BASE)/sizeof(mmBIF_RB_BASE[0]), 0, 0 }, + { "mmBIF_RB_RPTR", REG_MMIO, 0x1532, &mmBIF_RB_RPTR[0], sizeof(mmBIF_RB_RPTR)/sizeof(mmBIF_RB_RPTR[0]), 0, 0 }, + { "mmBIF_RB_WPTR", REG_MMIO, 0x1533, &mmBIF_RB_WPTR[0], sizeof(mmBIF_RB_WPTR)/sizeof(mmBIF_RB_WPTR[0]), 0, 0 }, + { "mmBIF_RB_WPTR_ADDR_HI", REG_MMIO, 0x1534, &mmBIF_RB_WPTR_ADDR_HI[0], sizeof(mmBIF_RB_WPTR_ADDR_HI)/sizeof(mmBIF_RB_WPTR_ADDR_HI[0]), 0, 0 }, + { "mmBIF_RB_WPTR_ADDR_LO", REG_MMIO, 0x1535, &mmBIF_RB_WPTR_ADDR_LO[0], sizeof(mmBIF_RB_WPTR_ADDR_LO)/sizeof(mmBIF_RB_WPTR_ADDR_LO[0]), 0, 0 }, + { "mmSLAVE_HANG_PROTECTION_CNTL", REG_MMIO, 0x1536, &mmSLAVE_HANG_PROTECTION_CNTL[0], sizeof(mmSLAVE_HANG_PROTECTION_CNTL)/sizeof(mmSLAVE_HANG_PROTECTION_CNTL[0]), 0, 0 }, + { "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x1537, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 }, + { "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x1538, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 }, + { "mmSLAVE_HANG_ERROR", REG_MMIO, 0x153b, &mmSLAVE_HANG_ERROR[0], sizeof(mmSLAVE_HANG_ERROR)/sizeof(mmSLAVE_HANG_ERROR[0]), 0, 0 }, + { "mmCAPTURE_HOST_BUSNUM", REG_MMIO, 0x153c, &mmCAPTURE_HOST_BUSNUM[0], sizeof(mmCAPTURE_HOST_BUSNUM)/sizeof(mmCAPTURE_HOST_BUSNUM[0]), 0, 0 }, + { "mmHOST_BUSNUM", REG_MMIO, 0x153d, &mmHOST_BUSNUM[0], sizeof(mmHOST_BUSNUM)/sizeof(mmHOST_BUSNUM[0]), 0, 0 }, + { "mmPEER_REG_RANGE0", REG_MMIO, 0x153e, &mmPEER_REG_RANGE0[0], sizeof(mmPEER_REG_RANGE0)/sizeof(mmPEER_REG_RANGE0[0]), 0, 0 }, + { "mmPEER_REG_RANGE1", REG_MMIO, 0x153f, &mmPEER_REG_RANGE1[0], sizeof(mmPEER_REG_RANGE1)/sizeof(mmPEER_REG_RANGE1[0]), 0, 0 }, + { "mmPCIE_CAP_LIST", REG_MMIO, 0x16, &mmPCIE_CAP_LIST[0], sizeof(mmPCIE_CAP_LIST)/sizeof(mmPCIE_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_CAP", REG_MMIO, 0x16, &mmPCIE_CAP[0], sizeof(mmPCIE_CAP)/sizeof(mmPCIE_CAP[0]), 0, 0 }, + { "mmDEVICE_CAP", REG_MMIO, 0x17, &mmDEVICE_CAP[0], sizeof(mmDEVICE_CAP)/sizeof(mmDEVICE_CAP[0]), 0, 0 }, + { "mmDEVICE_STATUS", REG_MMIO, 0x18, &mmDEVICE_STATUS[0], sizeof(mmDEVICE_STATUS)/sizeof(mmDEVICE_STATUS[0]), 0, 0 }, + { "mmDEVICE_CNTL", REG_MMIO, 0x18, &mmDEVICE_CNTL[0], sizeof(mmDEVICE_CNTL)/sizeof(mmDEVICE_CNTL[0]), 0, 0 }, + { "mmLINK_CAP", REG_MMIO, 0x19, &mmLINK_CAP[0], sizeof(mmLINK_CAP)/sizeof(mmLINK_CAP[0]), 0, 0 }, + { "mmLINK_STATUS", REG_MMIO, 0x1a, &mmLINK_STATUS[0], sizeof(mmLINK_STATUS)/sizeof(mmLINK_STATUS[0]), 0, 0 }, + { "mmLINK_CNTL", REG_MMIO, 0x1a, &mmLINK_CNTL[0], sizeof(mmLINK_CNTL)/sizeof(mmLINK_CNTL[0]), 0, 0 }, + { "mmDEVICE_CAP2", REG_MMIO, 0x1f, &mmDEVICE_CAP2[0], sizeof(mmDEVICE_CAP2)/sizeof(mmDEVICE_CAP2[0]), 0, 0 }, + { "ixD2F1_PCIEP_HW_DEBUG", REG_SMC, 0x2, &ixD2F1_PCIEP_HW_DEBUG[0], sizeof(ixD2F1_PCIEP_HW_DEBUG)/sizeof(ixD2F1_PCIEP_HW_DEBUG[0]), 0, 0 }, + { "mmPROG_INTERFACE", REG_MMIO, 0x2, &mmPROG_INTERFACE[0], sizeof(mmPROG_INTERFACE)/sizeof(mmPROG_INTERFACE[0]), 0, 0 }, + { "mmREVISION_ID", REG_MMIO, 0x2, &mmREVISION_ID[0], sizeof(mmREVISION_ID)/sizeof(mmREVISION_ID[0]), 0, 0 }, + { "mmBASE_CLASS", REG_MMIO, 0x2, &mmBASE_CLASS[0], sizeof(mmBASE_CLASS)/sizeof(mmBASE_CLASS[0]), 0, 0 }, + { "mmSUB_CLASS", REG_MMIO, 0x2, &mmSUB_CLASS[0], sizeof(mmSUB_CLASS)/sizeof(mmSUB_CLASS[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CNTL", REG_SMC, 0x20, &ixD2F1_PCIE_TX_CNTL[0], sizeof(ixD2F1_PCIE_TX_CNTL)/sizeof(ixD2F1_PCIE_TX_CNTL[0]), 0, 0 }, + { "mmDEVICE_STATUS2", REG_MMIO, 0x20, &mmDEVICE_STATUS2[0], sizeof(mmDEVICE_STATUS2)/sizeof(mmDEVICE_STATUS2[0]), 0, 0 }, + { "mmDEVICE_CNTL2", REG_MMIO, 0x20, &mmDEVICE_CNTL2[0], sizeof(mmDEVICE_CNTL2)/sizeof(mmDEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F1_VENDOR_ID", REG_SMC, 0x2000000, &ixD2F1_VENDOR_ID[0], sizeof(ixD2F1_VENDOR_ID)/sizeof(ixD2F1_VENDOR_ID[0]), 0, 0 }, + { "ixD2F1_COMMAND", REG_SMC, 0x2000001, &ixD2F1_COMMAND[0], sizeof(ixD2F1_COMMAND)/sizeof(ixD2F1_COMMAND[0]), 0, 0 }, + { "ixD2F1_STATUS", REG_SMC, 0x2000001, &ixD2F1_STATUS[0], sizeof(ixD2F1_STATUS)/sizeof(ixD2F1_STATUS[0]), 0, 0 }, + { "ixD2F1_PROG_INTERFACE", REG_SMC, 0x2000002, &ixD2F1_PROG_INTERFACE[0], sizeof(ixD2F1_PROG_INTERFACE)/sizeof(ixD2F1_PROG_INTERFACE[0]), 0, 0 }, + { "ixD2F1_REVISION_ID", REG_SMC, 0x2000002, &ixD2F1_REVISION_ID[0], sizeof(ixD2F1_REVISION_ID)/sizeof(ixD2F1_REVISION_ID[0]), 0, 0 }, + { "ixD2F1_BASE_CLASS", REG_SMC, 0x2000002, &ixD2F1_BASE_CLASS[0], sizeof(ixD2F1_BASE_CLASS)/sizeof(ixD2F1_BASE_CLASS[0]), 0, 0 }, + { "ixD2F1_SUB_CLASS", REG_SMC, 0x2000002, &ixD2F1_SUB_CLASS[0], sizeof(ixD2F1_SUB_CLASS)/sizeof(ixD2F1_SUB_CLASS[0]), 0, 0 }, + { "ixD2F1_CACHE_LINE", REG_SMC, 0x2000003, &ixD2F1_CACHE_LINE[0], sizeof(ixD2F1_CACHE_LINE)/sizeof(ixD2F1_CACHE_LINE[0]), 0, 0 }, + { "ixD2F1_LATENCY", REG_SMC, 0x2000003, &ixD2F1_LATENCY[0], sizeof(ixD2F1_LATENCY)/sizeof(ixD2F1_LATENCY[0]), 0, 0 }, + { "ixD2F1_HEADER", REG_SMC, 0x2000003, &ixD2F1_HEADER[0], sizeof(ixD2F1_HEADER)/sizeof(ixD2F1_HEADER[0]), 0, 0 }, + { "ixD2F1_BIST", REG_SMC, 0x2000003, &ixD2F1_BIST[0], sizeof(ixD2F1_BIST)/sizeof(ixD2F1_BIST[0]), 0, 0 }, + { "ixD2F1_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x2000006, &ixD2F1_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F1_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F1_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD2F1_SECONDARY_STATUS", REG_SMC, 0x2000007, &ixD2F1_SECONDARY_STATUS[0], sizeof(ixD2F1_SECONDARY_STATUS)/sizeof(ixD2F1_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD2F1_IO_BASE_LIMIT", REG_SMC, 0x2000007, &ixD2F1_IO_BASE_LIMIT[0], sizeof(ixD2F1_IO_BASE_LIMIT)/sizeof(ixD2F1_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F1_MEM_BASE_LIMIT", REG_SMC, 0x2000008, &ixD2F1_MEM_BASE_LIMIT[0], sizeof(ixD2F1_MEM_BASE_LIMIT)/sizeof(ixD2F1_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F1_PREF_BASE_LIMIT", REG_SMC, 0x2000009, &ixD2F1_PREF_BASE_LIMIT[0], sizeof(ixD2F1_PREF_BASE_LIMIT)/sizeof(ixD2F1_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F1_PREF_BASE_UPPER", REG_SMC, 0x200000a, &ixD2F1_PREF_BASE_UPPER[0], sizeof(ixD2F1_PREF_BASE_UPPER)/sizeof(ixD2F1_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD2F1_PREF_LIMIT_UPPER", REG_SMC, 0x200000b, &ixD2F1_PREF_LIMIT_UPPER[0], sizeof(ixD2F1_PREF_LIMIT_UPPER)/sizeof(ixD2F1_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD2F1_IO_BASE_LIMIT_HI", REG_SMC, 0x200000c, &ixD2F1_IO_BASE_LIMIT_HI[0], sizeof(ixD2F1_IO_BASE_LIMIT_HI)/sizeof(ixD2F1_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD2F1_CAP_PTR", REG_SMC, 0x200000d, &ixD2F1_CAP_PTR[0], sizeof(ixD2F1_CAP_PTR)/sizeof(ixD2F1_CAP_PTR[0]), 0, 0 }, + { "ixD2F1_IRQ_BRIDGE_CNTL", REG_SMC, 0x200000f, &ixD2F1_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F1_IRQ_BRIDGE_CNTL)/sizeof(ixD2F1_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F1_INTERRUPT_LINE", REG_SMC, 0x200000f, &ixD2F1_INTERRUPT_LINE[0], sizeof(ixD2F1_INTERRUPT_LINE)/sizeof(ixD2F1_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD2F1_INTERRUPT_PIN", REG_SMC, 0x200000f, &ixD2F1_INTERRUPT_PIN[0], sizeof(ixD2F1_INTERRUPT_PIN)/sizeof(ixD2F1_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD2F1_EXT_BRIDGE_CNTL", REG_SMC, 0x2000010, &ixD2F1_EXT_BRIDGE_CNTL[0], sizeof(ixD2F1_EXT_BRIDGE_CNTL)/sizeof(ixD2F1_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F1_PMI_CAP_LIST", REG_SMC, 0x2000014, &ixD2F1_PMI_CAP_LIST[0], sizeof(ixD2F1_PMI_CAP_LIST)/sizeof(ixD2F1_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PMI_CAP", REG_SMC, 0x2000014, &ixD2F1_PMI_CAP[0], sizeof(ixD2F1_PMI_CAP)/sizeof(ixD2F1_PMI_CAP[0]), 0, 0 }, + { "ixD2F1_PMI_STATUS_CNTL", REG_SMC, 0x2000015, &ixD2F1_PMI_STATUS_CNTL[0], sizeof(ixD2F1_PMI_STATUS_CNTL)/sizeof(ixD2F1_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_CAP_LIST", REG_SMC, 0x2000016, &ixD2F1_PCIE_CAP_LIST[0], sizeof(ixD2F1_PCIE_CAP_LIST)/sizeof(ixD2F1_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_CAP", REG_SMC, 0x2000016, &ixD2F1_PCIE_CAP[0], sizeof(ixD2F1_PCIE_CAP)/sizeof(ixD2F1_PCIE_CAP[0]), 0, 0 }, + { "ixD2F1_DEVICE_CAP", REG_SMC, 0x2000017, &ixD2F1_DEVICE_CAP[0], sizeof(ixD2F1_DEVICE_CAP)/sizeof(ixD2F1_DEVICE_CAP[0]), 0, 0 }, + { "ixD2F1_DEVICE_STATUS", REG_SMC, 0x2000018, &ixD2F1_DEVICE_STATUS[0], sizeof(ixD2F1_DEVICE_STATUS)/sizeof(ixD2F1_DEVICE_STATUS[0]), 0, 0 }, + { "ixD2F1_DEVICE_CNTL", REG_SMC, 0x2000018, &ixD2F1_DEVICE_CNTL[0], sizeof(ixD2F1_DEVICE_CNTL)/sizeof(ixD2F1_DEVICE_CNTL[0]), 0, 0 }, + { "ixD2F1_LINK_CAP", REG_SMC, 0x2000019, &ixD2F1_LINK_CAP[0], sizeof(ixD2F1_LINK_CAP)/sizeof(ixD2F1_LINK_CAP[0]), 0, 0 }, + { "ixD2F1_LINK_STATUS", REG_SMC, 0x200001a, &ixD2F1_LINK_STATUS[0], sizeof(ixD2F1_LINK_STATUS)/sizeof(ixD2F1_LINK_STATUS[0]), 0, 0 }, + { "ixD2F1_LINK_CNTL", REG_SMC, 0x200001a, &ixD2F1_LINK_CNTL[0], sizeof(ixD2F1_LINK_CNTL)/sizeof(ixD2F1_LINK_CNTL[0]), 0, 0 }, + { "ixD2F1_SLOT_CAP", REG_SMC, 0x200001b, &ixD2F1_SLOT_CAP[0], sizeof(ixD2F1_SLOT_CAP)/sizeof(ixD2F1_SLOT_CAP[0]), 0, 0 }, + { "ixD2F1_SLOT_STATUS", REG_SMC, 0x200001c, &ixD2F1_SLOT_STATUS[0], sizeof(ixD2F1_SLOT_STATUS)/sizeof(ixD2F1_SLOT_STATUS[0]), 0, 0 }, + { "ixD2F1_SLOT_CNTL", REG_SMC, 0x200001c, &ixD2F1_SLOT_CNTL[0], sizeof(ixD2F1_SLOT_CNTL)/sizeof(ixD2F1_SLOT_CNTL[0]), 0, 0 }, + { "ixD2F1_ROOT_CNTL", REG_SMC, 0x200001d, &ixD2F1_ROOT_CNTL[0], sizeof(ixD2F1_ROOT_CNTL)/sizeof(ixD2F1_ROOT_CNTL[0]), 0, 0 }, + { "ixD2F1_ROOT_CAP", REG_SMC, 0x200001d, &ixD2F1_ROOT_CAP[0], sizeof(ixD2F1_ROOT_CAP)/sizeof(ixD2F1_ROOT_CAP[0]), 0, 0 }, + { "ixD2F1_ROOT_STATUS", REG_SMC, 0x200001e, &ixD2F1_ROOT_STATUS[0], sizeof(ixD2F1_ROOT_STATUS)/sizeof(ixD2F1_ROOT_STATUS[0]), 0, 0 }, + { "ixD2F1_DEVICE_CAP2", REG_SMC, 0x200001f, &ixD2F1_DEVICE_CAP2[0], sizeof(ixD2F1_DEVICE_CAP2)/sizeof(ixD2F1_DEVICE_CAP2[0]), 0, 0 }, + { "ixD2F1_DEVICE_STATUS2", REG_SMC, 0x2000020, &ixD2F1_DEVICE_STATUS2[0], sizeof(ixD2F1_DEVICE_STATUS2)/sizeof(ixD2F1_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD2F1_DEVICE_CNTL2", REG_SMC, 0x2000020, &ixD2F1_DEVICE_CNTL2[0], sizeof(ixD2F1_DEVICE_CNTL2)/sizeof(ixD2F1_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F1_LINK_CAP2", REG_SMC, 0x2000021, &ixD2F1_LINK_CAP2[0], sizeof(ixD2F1_LINK_CAP2)/sizeof(ixD2F1_LINK_CAP2[0]), 0, 0 }, + { "ixD2F1_LINK_STATUS2", REG_SMC, 0x2000022, &ixD2F1_LINK_STATUS2[0], sizeof(ixD2F1_LINK_STATUS2)/sizeof(ixD2F1_LINK_STATUS2[0]), 0, 0 }, + { "ixD2F1_LINK_CNTL2", REG_SMC, 0x2000022, &ixD2F1_LINK_CNTL2[0], sizeof(ixD2F1_LINK_CNTL2)/sizeof(ixD2F1_LINK_CNTL2[0]), 0, 0 }, + { "ixD2F1_SLOT_CAP2", REG_SMC, 0x2000023, &ixD2F1_SLOT_CAP2[0], sizeof(ixD2F1_SLOT_CAP2)/sizeof(ixD2F1_SLOT_CAP2[0]), 0, 0 }, + { "ixD2F1_SLOT_STATUS2", REG_SMC, 0x2000024, &ixD2F1_SLOT_STATUS2[0], sizeof(ixD2F1_SLOT_STATUS2)/sizeof(ixD2F1_SLOT_STATUS2[0]), 0, 0 }, + { "ixD2F1_SLOT_CNTL2", REG_SMC, 0x2000024, &ixD2F1_SLOT_CNTL2[0], sizeof(ixD2F1_SLOT_CNTL2)/sizeof(ixD2F1_SLOT_CNTL2[0]), 0, 0 }, + { "ixD2F1_MSI_CAP_LIST", REG_SMC, 0x2000028, &ixD2F1_MSI_CAP_LIST[0], sizeof(ixD2F1_MSI_CAP_LIST)/sizeof(ixD2F1_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_MSI_MSG_ADDR_LO", REG_SMC, 0x2000029, &ixD2F1_MSI_MSG_ADDR_LO[0], sizeof(ixD2F1_MSI_MSG_ADDR_LO)/sizeof(ixD2F1_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD2F1_MSI_MSG_ADDR_HI", REG_SMC, 0x200002a, &ixD2F1_MSI_MSG_ADDR_HI[0], sizeof(ixD2F1_MSI_MSG_ADDR_HI)/sizeof(ixD2F1_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD2F1_MSI_MSG_DATA", REG_SMC, 0x200002a, &ixD2F1_MSI_MSG_DATA[0], sizeof(ixD2F1_MSI_MSG_DATA)/sizeof(ixD2F1_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD2F1_MSI_MSG_DATA_64", REG_SMC, 0x200002b, &ixD2F1_MSI_MSG_DATA_64[0], sizeof(ixD2F1_MSI_MSG_DATA_64)/sizeof(ixD2F1_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD2F1_SSID_CAP_LIST", REG_SMC, 0x2000030, &ixD2F1_SSID_CAP_LIST[0], sizeof(ixD2F1_SSID_CAP_LIST)/sizeof(ixD2F1_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_SSID_CAP", REG_SMC, 0x2000031, &ixD2F1_SSID_CAP[0], sizeof(ixD2F1_SSID_CAP)/sizeof(ixD2F1_SSID_CAP[0]), 0, 0 }, + { "ixD2F1_MSI_MAP_CAP_LIST", REG_SMC, 0x2000032, &ixD2F1_MSI_MAP_CAP_LIST[0], sizeof(ixD2F1_MSI_MAP_CAP_LIST)/sizeof(ixD2F1_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_MSI_MAP_CAP", REG_SMC, 0x2000032, &ixD2F1_MSI_MAP_CAP[0], sizeof(ixD2F1_MSI_MAP_CAP)/sizeof(ixD2F1_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD2F1_MSI_MAP_ADDR_LO", REG_SMC, 0x2000033, &ixD2F1_MSI_MAP_ADDR_LO[0], sizeof(ixD2F1_MSI_MAP_ADDR_LO)/sizeof(ixD2F1_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD2F1_MSI_MAP_ADDR_HI", REG_SMC, 0x2000034, &ixD2F1_MSI_MAP_ADDR_HI[0], sizeof(ixD2F1_MSI_MAP_ADDR_HI)/sizeof(ixD2F1_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_INDEX", REG_SMC, 0x2000038, &ixD2F1_PCIE_PORT_INDEX[0], sizeof(ixD2F1_PCIE_PORT_INDEX)/sizeof(ixD2F1_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_DATA", REG_SMC, 0x2000039, &ixD2F1_PCIE_PORT_DATA[0], sizeof(ixD2F1_PCIE_PORT_DATA)/sizeof(ixD2F1_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x2000040, &ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x2000041, &ixD2F1_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD2F1_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x2000042, &ixD2F1_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD2F1_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x2000043, &ixD2F1_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD2F1_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x2000044, &ixD2F1_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x2000045, &ixD2F1_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x2000046, &ixD2F1_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_VC_STATUS", REG_SMC, 0x2000047, &ixD2F1_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F1_PCIE_PORT_VC_STATUS)/sizeof(ixD2F1_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_PORT_VC_CNTL", REG_SMC, 0x2000047, &ixD2F1_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F1_PCIE_PORT_VC_CNTL)/sizeof(ixD2F1_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x2000048, &ixD2F1_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x2000049, &ixD2F1_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x200004a, &ixD2F1_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x200004b, &ixD2F1_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x200004c, &ixD2F1_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x200004d, &ixD2F1_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x2000050, &ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x2000051, &ixD2F1_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD2F1_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x2000052, &ixD2F1_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x2000054, &ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x2000055, &ixD2F1_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F1_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x2000056, &ixD2F1_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F1_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F1_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x2000057, &ixD2F1_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F1_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD2F1_PCIE_CORR_ERR_STATUS", REG_SMC, 0x2000058, &ixD2F1_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F1_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F1_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_CORR_ERR_MASK", REG_SMC, 0x2000059, &ixD2F1_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F1_PCIE_CORR_ERR_MASK)/sizeof(ixD2F1_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F1_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x200005a, &ixD2F1_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F1_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F1_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_HDR_LOG0", REG_SMC, 0x200005b, &ixD2F1_PCIE_HDR_LOG0[0], sizeof(ixD2F1_PCIE_HDR_LOG0)/sizeof(ixD2F1_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD2F1_PCIE_HDR_LOG1", REG_SMC, 0x200005c, &ixD2F1_PCIE_HDR_LOG1[0], sizeof(ixD2F1_PCIE_HDR_LOG1)/sizeof(ixD2F1_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD2F1_PCIE_HDR_LOG2", REG_SMC, 0x200005d, &ixD2F1_PCIE_HDR_LOG2[0], sizeof(ixD2F1_PCIE_HDR_LOG2)/sizeof(ixD2F1_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD2F1_PCIE_HDR_LOG3", REG_SMC, 0x200005e, &ixD2F1_PCIE_HDR_LOG3[0], sizeof(ixD2F1_PCIE_HDR_LOG3)/sizeof(ixD2F1_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD2F1_PCIE_ROOT_ERR_CMD", REG_SMC, 0x200005f, &ixD2F1_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F1_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F1_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD2F1_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x2000060, &ixD2F1_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F1_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F1_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_ERR_SRC_ID", REG_SMC, 0x2000061, &ixD2F1_PCIE_ERR_SRC_ID[0], sizeof(ixD2F1_PCIE_ERR_SRC_ID)/sizeof(ixD2F1_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD2F1_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x2000062, &ixD2F1_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F1_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x2000063, &ixD2F1_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD2F1_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x2000064, &ixD2F1_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD2F1_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x2000065, &ixD2F1_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x200009c, &ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_LINK_CNTL3", REG_SMC, 0x200009d, &ixD2F1_PCIE_LINK_CNTL3[0], sizeof(ixD2F1_PCIE_LINK_CNTL3)/sizeof(ixD2F1_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x200009e, &ixD2F1_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F1_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F1_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x200009f, &ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x20000a0, &ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x20000a1, &ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x20000a2, &ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x20000a3, &ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x20000a4, &ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x20000a5, &ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x20000a6, &ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x20000a8, &ixD2F1_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_ACS_CNTL", REG_SMC, 0x20000a9, &ixD2F1_PCIE_ACS_CNTL[0], sizeof(ixD2F1_PCIE_ACS_CNTL)/sizeof(ixD2F1_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_ACS_CAP", REG_SMC, 0x20000a9, &ixD2F1_PCIE_ACS_CAP[0], sizeof(ixD2F1_PCIE_ACS_CAP)/sizeof(ixD2F1_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x20000bc, &ixD2F1_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_CNTL", REG_SMC, 0x20000bd, &ixD2F1_PCIE_MC_CNTL[0], sizeof(ixD2F1_PCIE_MC_CNTL)/sizeof(ixD2F1_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_CAP", REG_SMC, 0x20000bd, &ixD2F1_PCIE_MC_CAP[0], sizeof(ixD2F1_PCIE_MC_CAP)/sizeof(ixD2F1_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_ADDR0", REG_SMC, 0x20000be, &ixD2F1_PCIE_MC_ADDR0[0], sizeof(ixD2F1_PCIE_MC_ADDR0)/sizeof(ixD2F1_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_ADDR1", REG_SMC, 0x20000bf, &ixD2F1_PCIE_MC_ADDR1[0], sizeof(ixD2F1_PCIE_MC_ADDR1)/sizeof(ixD2F1_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_RCV0", REG_SMC, 0x20000c0, &ixD2F1_PCIE_MC_RCV0[0], sizeof(ixD2F1_PCIE_MC_RCV0)/sizeof(ixD2F1_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_RCV1", REG_SMC, 0x20000c1, &ixD2F1_PCIE_MC_RCV1[0], sizeof(ixD2F1_PCIE_MC_RCV1)/sizeof(ixD2F1_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x20000c2, &ixD2F1_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F1_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F1_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x20000c3, &ixD2F1_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F1_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F1_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x20000c4, &ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x20000c5, &ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x20000c6, &ixD2F1_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD2F1_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x20000c7, &ixD2F1_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_REQUESTER_ID", REG_SMC, 0x21, &ixD2F1_PCIE_TX_REQUESTER_ID[0], sizeof(ixD2F1_PCIE_TX_REQUESTER_ID)/sizeof(ixD2F1_PCIE_TX_REQUESTER_ID[0]), 0, 0 }, + { "mmLINK_CAP2", REG_MMIO, 0x21, &mmLINK_CAP2[0], sizeof(mmLINK_CAP2)/sizeof(mmLINK_CAP2[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x22, &ixD2F1_PCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixD2F1_PCIE_TX_VENDOR_SPECIFIC)/sizeof(ixD2F1_PCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 }, + { "mmLINK_STATUS2", REG_MMIO, 0x22, &mmLINK_STATUS2[0], sizeof(mmLINK_STATUS2)/sizeof(mmLINK_STATUS2[0]), 0, 0 }, + { "mmLINK_CNTL2", REG_MMIO, 0x22, &mmLINK_CNTL2[0], sizeof(mmLINK_CNTL2)/sizeof(mmLINK_CNTL2[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x23, &ixD2F1_PCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixD2F1_PCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixD2F1_PCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_SEQ", REG_SMC, 0x24, &ixD2F1_PCIE_TX_SEQ[0], sizeof(ixD2F1_PCIE_TX_SEQ)/sizeof(ixD2F1_PCIE_TX_SEQ[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_REPLAY", REG_SMC, 0x25, &ixD2F1_PCIE_TX_REPLAY[0], sizeof(ixD2F1_PCIE_TX_REPLAY)/sizeof(ixD2F1_PCIE_TX_REPLAY[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x26, &ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 }, + { "mmBIF_RFE_SNOOP_REG", REG_MMIO, 0x27, &mmBIF_RFE_SNOOP_REG[0], sizeof(mmBIF_RFE_SNOOP_REG)/sizeof(mmBIF_RFE_SNOOP_REG[0]), 0, 0 }, + { "mmPCIE_WRAPPER0_C_PCIE_INDEX", REG_MMIO, 0x28, NULL, 0, 0, 0 }, + { "mmMSI_CAP_LIST", REG_MMIO, 0x28, &mmMSI_CAP_LIST[0], sizeof(mmMSI_CAP_LIST)/sizeof(mmMSI_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_WRAPPER0_C_PCIE_DATA", REG_MMIO, 0x29, NULL, 0, 0, 0 }, + { "mmMSI_MSG_ADDR_LO", REG_MMIO, 0x29, &mmMSI_MSG_ADDR_LO[0], sizeof(mmMSI_MSG_ADDR_LO)/sizeof(mmMSI_MSG_ADDR_LO[0]), 0, 0 }, + { "mmC_PCIE_DATA", REG_MMIO, 0x29, &mmC_PCIE_DATA[0], sizeof(mmC_PCIE_DATA)/sizeof(mmC_PCIE_DATA[0]), 0, 0 }, + { "mmMSI_MSG_ADDR_HI", REG_MMIO, 0x2a, &mmMSI_MSG_ADDR_HI[0], sizeof(mmMSI_MSG_ADDR_HI)/sizeof(mmMSI_MSG_ADDR_HI[0]), 0, 0 }, + { "mmMSI_MSG_DATA", REG_MMIO, 0x2a, &mmMSI_MSG_DATA[0], sizeof(mmMSI_MSG_DATA)/sizeof(mmMSI_MSG_DATA[0]), 0, 0 }, + { "mmMSI_MSG_DATA_64", REG_MMIO, 0x2b, &mmMSI_MSG_DATA_64[0], sizeof(mmMSI_MSG_DATA_64)/sizeof(mmMSI_MSG_DATA_64[0]), 0, 0 }, + { "mmCACHE_LINE", REG_MMIO, 0x3, &mmCACHE_LINE[0], sizeof(mmCACHE_LINE)/sizeof(mmCACHE_LINE[0]), 0, 0 }, + { "mmLATENCY", REG_MMIO, 0x3, &mmLATENCY[0], sizeof(mmLATENCY)/sizeof(mmLATENCY[0]), 0, 0 }, + { "mmHEADER", REG_MMIO, 0x3, &mmHEADER[0], sizeof(mmHEADER)/sizeof(mmHEADER[0]), 0, 0 }, + { "mmBIST", REG_MMIO, 0x3, &mmBIST[0], sizeof(mmBIST)/sizeof(mmBIST[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x30, &ixD2F1_PCIE_TX_CREDITS_ADVT_P[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_P)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_P[0]), 0, 0 }, + { "ixD2F2_VENDOR_ID", REG_SMC, 0x3000000, &ixD2F2_VENDOR_ID[0], sizeof(ixD2F2_VENDOR_ID)/sizeof(ixD2F2_VENDOR_ID[0]), 0, 0 }, + { "ixD2F2_COMMAND", REG_SMC, 0x3000001, &ixD2F2_COMMAND[0], sizeof(ixD2F2_COMMAND)/sizeof(ixD2F2_COMMAND[0]), 0, 0 }, + { "ixD2F2_STATUS", REG_SMC, 0x3000001, &ixD2F2_STATUS[0], sizeof(ixD2F2_STATUS)/sizeof(ixD2F2_STATUS[0]), 0, 0 }, + { "ixD2F2_PROG_INTERFACE", REG_SMC, 0x3000002, &ixD2F2_PROG_INTERFACE[0], sizeof(ixD2F2_PROG_INTERFACE)/sizeof(ixD2F2_PROG_INTERFACE[0]), 0, 0 }, + { "ixD2F2_REVISION_ID", REG_SMC, 0x3000002, &ixD2F2_REVISION_ID[0], sizeof(ixD2F2_REVISION_ID)/sizeof(ixD2F2_REVISION_ID[0]), 0, 0 }, + { "ixD2F2_BASE_CLASS", REG_SMC, 0x3000002, &ixD2F2_BASE_CLASS[0], sizeof(ixD2F2_BASE_CLASS)/sizeof(ixD2F2_BASE_CLASS[0]), 0, 0 }, + { "ixD2F2_SUB_CLASS", REG_SMC, 0x3000002, &ixD2F2_SUB_CLASS[0], sizeof(ixD2F2_SUB_CLASS)/sizeof(ixD2F2_SUB_CLASS[0]), 0, 0 }, + { "ixD2F2_CACHE_LINE", REG_SMC, 0x3000003, &ixD2F2_CACHE_LINE[0], sizeof(ixD2F2_CACHE_LINE)/sizeof(ixD2F2_CACHE_LINE[0]), 0, 0 }, + { "ixD2F2_LATENCY", REG_SMC, 0x3000003, &ixD2F2_LATENCY[0], sizeof(ixD2F2_LATENCY)/sizeof(ixD2F2_LATENCY[0]), 0, 0 }, + { "ixD2F2_HEADER", REG_SMC, 0x3000003, &ixD2F2_HEADER[0], sizeof(ixD2F2_HEADER)/sizeof(ixD2F2_HEADER[0]), 0, 0 }, + { "ixD2F2_BIST", REG_SMC, 0x3000003, &ixD2F2_BIST[0], sizeof(ixD2F2_BIST)/sizeof(ixD2F2_BIST[0]), 0, 0 }, + { "ixD2F2_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x3000006, &ixD2F2_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F2_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F2_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD2F2_SECONDARY_STATUS", REG_SMC, 0x3000007, &ixD2F2_SECONDARY_STATUS[0], sizeof(ixD2F2_SECONDARY_STATUS)/sizeof(ixD2F2_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD2F2_IO_BASE_LIMIT", REG_SMC, 0x3000007, &ixD2F2_IO_BASE_LIMIT[0], sizeof(ixD2F2_IO_BASE_LIMIT)/sizeof(ixD2F2_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F2_MEM_BASE_LIMIT", REG_SMC, 0x3000008, &ixD2F2_MEM_BASE_LIMIT[0], sizeof(ixD2F2_MEM_BASE_LIMIT)/sizeof(ixD2F2_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F2_PREF_BASE_LIMIT", REG_SMC, 0x3000009, &ixD2F2_PREF_BASE_LIMIT[0], sizeof(ixD2F2_PREF_BASE_LIMIT)/sizeof(ixD2F2_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F2_PREF_BASE_UPPER", REG_SMC, 0x300000a, &ixD2F2_PREF_BASE_UPPER[0], sizeof(ixD2F2_PREF_BASE_UPPER)/sizeof(ixD2F2_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD2F2_PREF_LIMIT_UPPER", REG_SMC, 0x300000b, &ixD2F2_PREF_LIMIT_UPPER[0], sizeof(ixD2F2_PREF_LIMIT_UPPER)/sizeof(ixD2F2_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD2F2_IO_BASE_LIMIT_HI", REG_SMC, 0x300000c, &ixD2F2_IO_BASE_LIMIT_HI[0], sizeof(ixD2F2_IO_BASE_LIMIT_HI)/sizeof(ixD2F2_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD2F2_CAP_PTR", REG_SMC, 0x300000d, &ixD2F2_CAP_PTR[0], sizeof(ixD2F2_CAP_PTR)/sizeof(ixD2F2_CAP_PTR[0]), 0, 0 }, + { "ixD2F2_IRQ_BRIDGE_CNTL", REG_SMC, 0x300000f, &ixD2F2_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F2_IRQ_BRIDGE_CNTL)/sizeof(ixD2F2_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F2_INTERRUPT_LINE", REG_SMC, 0x300000f, &ixD2F2_INTERRUPT_LINE[0], sizeof(ixD2F2_INTERRUPT_LINE)/sizeof(ixD2F2_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD2F2_INTERRUPT_PIN", REG_SMC, 0x300000f, &ixD2F2_INTERRUPT_PIN[0], sizeof(ixD2F2_INTERRUPT_PIN)/sizeof(ixD2F2_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD2F2_EXT_BRIDGE_CNTL", REG_SMC, 0x3000010, &ixD2F2_EXT_BRIDGE_CNTL[0], sizeof(ixD2F2_EXT_BRIDGE_CNTL)/sizeof(ixD2F2_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F2_PMI_CAP_LIST", REG_SMC, 0x3000014, &ixD2F2_PMI_CAP_LIST[0], sizeof(ixD2F2_PMI_CAP_LIST)/sizeof(ixD2F2_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PMI_CAP", REG_SMC, 0x3000014, &ixD2F2_PMI_CAP[0], sizeof(ixD2F2_PMI_CAP)/sizeof(ixD2F2_PMI_CAP[0]), 0, 0 }, + { "ixD2F2_PMI_STATUS_CNTL", REG_SMC, 0x3000015, &ixD2F2_PMI_STATUS_CNTL[0], sizeof(ixD2F2_PMI_STATUS_CNTL)/sizeof(ixD2F2_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_CAP_LIST", REG_SMC, 0x3000016, &ixD2F2_PCIE_CAP_LIST[0], sizeof(ixD2F2_PCIE_CAP_LIST)/sizeof(ixD2F2_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_CAP", REG_SMC, 0x3000016, &ixD2F2_PCIE_CAP[0], sizeof(ixD2F2_PCIE_CAP)/sizeof(ixD2F2_PCIE_CAP[0]), 0, 0 }, + { "ixD2F2_DEVICE_CAP", REG_SMC, 0x3000017, &ixD2F2_DEVICE_CAP[0], sizeof(ixD2F2_DEVICE_CAP)/sizeof(ixD2F2_DEVICE_CAP[0]), 0, 0 }, + { "ixD2F2_DEVICE_STATUS", REG_SMC, 0x3000018, &ixD2F2_DEVICE_STATUS[0], sizeof(ixD2F2_DEVICE_STATUS)/sizeof(ixD2F2_DEVICE_STATUS[0]), 0, 0 }, + { "ixD2F2_DEVICE_CNTL", REG_SMC, 0x3000018, &ixD2F2_DEVICE_CNTL[0], sizeof(ixD2F2_DEVICE_CNTL)/sizeof(ixD2F2_DEVICE_CNTL[0]), 0, 0 }, + { "ixD2F2_LINK_CAP", REG_SMC, 0x3000019, &ixD2F2_LINK_CAP[0], sizeof(ixD2F2_LINK_CAP)/sizeof(ixD2F2_LINK_CAP[0]), 0, 0 }, + { "ixD2F2_LINK_STATUS", REG_SMC, 0x300001a, &ixD2F2_LINK_STATUS[0], sizeof(ixD2F2_LINK_STATUS)/sizeof(ixD2F2_LINK_STATUS[0]), 0, 0 }, + { "ixD2F2_LINK_CNTL", REG_SMC, 0x300001a, &ixD2F2_LINK_CNTL[0], sizeof(ixD2F2_LINK_CNTL)/sizeof(ixD2F2_LINK_CNTL[0]), 0, 0 }, + { "ixD2F2_SLOT_CAP", REG_SMC, 0x300001b, &ixD2F2_SLOT_CAP[0], sizeof(ixD2F2_SLOT_CAP)/sizeof(ixD2F2_SLOT_CAP[0]), 0, 0 }, + { "ixD2F2_SLOT_STATUS", REG_SMC, 0x300001c, &ixD2F2_SLOT_STATUS[0], sizeof(ixD2F2_SLOT_STATUS)/sizeof(ixD2F2_SLOT_STATUS[0]), 0, 0 }, + { "ixD2F2_SLOT_CNTL", REG_SMC, 0x300001c, &ixD2F2_SLOT_CNTL[0], sizeof(ixD2F2_SLOT_CNTL)/sizeof(ixD2F2_SLOT_CNTL[0]), 0, 0 }, + { "ixD2F2_ROOT_CNTL", REG_SMC, 0x300001d, &ixD2F2_ROOT_CNTL[0], sizeof(ixD2F2_ROOT_CNTL)/sizeof(ixD2F2_ROOT_CNTL[0]), 0, 0 }, + { "ixD2F2_ROOT_CAP", REG_SMC, 0x300001d, &ixD2F2_ROOT_CAP[0], sizeof(ixD2F2_ROOT_CAP)/sizeof(ixD2F2_ROOT_CAP[0]), 0, 0 }, + { "ixD2F2_ROOT_STATUS", REG_SMC, 0x300001e, &ixD2F2_ROOT_STATUS[0], sizeof(ixD2F2_ROOT_STATUS)/sizeof(ixD2F2_ROOT_STATUS[0]), 0, 0 }, + { "ixD2F2_DEVICE_CAP2", REG_SMC, 0x300001f, &ixD2F2_DEVICE_CAP2[0], sizeof(ixD2F2_DEVICE_CAP2)/sizeof(ixD2F2_DEVICE_CAP2[0]), 0, 0 }, + { "ixD2F2_DEVICE_STATUS2", REG_SMC, 0x3000020, &ixD2F2_DEVICE_STATUS2[0], sizeof(ixD2F2_DEVICE_STATUS2)/sizeof(ixD2F2_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD2F2_DEVICE_CNTL2", REG_SMC, 0x3000020, &ixD2F2_DEVICE_CNTL2[0], sizeof(ixD2F2_DEVICE_CNTL2)/sizeof(ixD2F2_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F2_LINK_CAP2", REG_SMC, 0x3000021, &ixD2F2_LINK_CAP2[0], sizeof(ixD2F2_LINK_CAP2)/sizeof(ixD2F2_LINK_CAP2[0]), 0, 0 }, + { "ixD2F2_LINK_STATUS2", REG_SMC, 0x3000022, &ixD2F2_LINK_STATUS2[0], sizeof(ixD2F2_LINK_STATUS2)/sizeof(ixD2F2_LINK_STATUS2[0]), 0, 0 }, + { "ixD2F2_LINK_CNTL2", REG_SMC, 0x3000022, &ixD2F2_LINK_CNTL2[0], sizeof(ixD2F2_LINK_CNTL2)/sizeof(ixD2F2_LINK_CNTL2[0]), 0, 0 }, + { "ixD2F2_SLOT_CAP2", REG_SMC, 0x3000023, &ixD2F2_SLOT_CAP2[0], sizeof(ixD2F2_SLOT_CAP2)/sizeof(ixD2F2_SLOT_CAP2[0]), 0, 0 }, + { "ixD2F2_SLOT_STATUS2", REG_SMC, 0x3000024, &ixD2F2_SLOT_STATUS2[0], sizeof(ixD2F2_SLOT_STATUS2)/sizeof(ixD2F2_SLOT_STATUS2[0]), 0, 0 }, + { "ixD2F2_SLOT_CNTL2", REG_SMC, 0x3000024, &ixD2F2_SLOT_CNTL2[0], sizeof(ixD2F2_SLOT_CNTL2)/sizeof(ixD2F2_SLOT_CNTL2[0]), 0, 0 }, + { "ixD2F2_MSI_CAP_LIST", REG_SMC, 0x3000028, &ixD2F2_MSI_CAP_LIST[0], sizeof(ixD2F2_MSI_CAP_LIST)/sizeof(ixD2F2_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_MSI_MSG_ADDR_LO", REG_SMC, 0x3000029, &ixD2F2_MSI_MSG_ADDR_LO[0], sizeof(ixD2F2_MSI_MSG_ADDR_LO)/sizeof(ixD2F2_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD2F2_MSI_MSG_ADDR_HI", REG_SMC, 0x300002a, &ixD2F2_MSI_MSG_ADDR_HI[0], sizeof(ixD2F2_MSI_MSG_ADDR_HI)/sizeof(ixD2F2_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD2F2_MSI_MSG_DATA", REG_SMC, 0x300002a, &ixD2F2_MSI_MSG_DATA[0], sizeof(ixD2F2_MSI_MSG_DATA)/sizeof(ixD2F2_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD2F2_MSI_MSG_DATA_64", REG_SMC, 0x300002b, &ixD2F2_MSI_MSG_DATA_64[0], sizeof(ixD2F2_MSI_MSG_DATA_64)/sizeof(ixD2F2_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD2F2_SSID_CAP_LIST", REG_SMC, 0x3000030, &ixD2F2_SSID_CAP_LIST[0], sizeof(ixD2F2_SSID_CAP_LIST)/sizeof(ixD2F2_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_SSID_CAP", REG_SMC, 0x3000031, &ixD2F2_SSID_CAP[0], sizeof(ixD2F2_SSID_CAP)/sizeof(ixD2F2_SSID_CAP[0]), 0, 0 }, + { "ixD2F2_MSI_MAP_CAP_LIST", REG_SMC, 0x3000032, &ixD2F2_MSI_MAP_CAP_LIST[0], sizeof(ixD2F2_MSI_MAP_CAP_LIST)/sizeof(ixD2F2_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_MSI_MAP_CAP", REG_SMC, 0x3000032, &ixD2F2_MSI_MAP_CAP[0], sizeof(ixD2F2_MSI_MAP_CAP)/sizeof(ixD2F2_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD2F2_MSI_MAP_ADDR_LO", REG_SMC, 0x3000033, &ixD2F2_MSI_MAP_ADDR_LO[0], sizeof(ixD2F2_MSI_MAP_ADDR_LO)/sizeof(ixD2F2_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD2F2_MSI_MAP_ADDR_HI", REG_SMC, 0x3000034, &ixD2F2_MSI_MAP_ADDR_HI[0], sizeof(ixD2F2_MSI_MAP_ADDR_HI)/sizeof(ixD2F2_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_INDEX", REG_SMC, 0x3000038, &ixD2F2_PCIE_PORT_INDEX[0], sizeof(ixD2F2_PCIE_PORT_INDEX)/sizeof(ixD2F2_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_DATA", REG_SMC, 0x3000039, &ixD2F2_PCIE_PORT_DATA[0], sizeof(ixD2F2_PCIE_PORT_DATA)/sizeof(ixD2F2_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x3000040, &ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x3000041, &ixD2F2_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD2F2_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x3000042, &ixD2F2_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD2F2_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x3000043, &ixD2F2_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD2F2_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x3000044, &ixD2F2_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x3000045, &ixD2F2_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x3000046, &ixD2F2_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_VC_STATUS", REG_SMC, 0x3000047, &ixD2F2_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F2_PCIE_PORT_VC_STATUS)/sizeof(ixD2F2_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_PORT_VC_CNTL", REG_SMC, 0x3000047, &ixD2F2_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F2_PCIE_PORT_VC_CNTL)/sizeof(ixD2F2_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x3000048, &ixD2F2_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F2_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x3000049, &ixD2F2_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x300004a, &ixD2F2_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x300004b, &ixD2F2_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F2_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x300004c, &ixD2F2_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x300004d, &ixD2F2_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x3000050, &ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x3000051, &ixD2F2_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD2F2_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x3000052, &ixD2F2_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x3000054, &ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x3000055, &ixD2F2_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F2_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x3000056, &ixD2F2_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F2_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F2_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x3000057, &ixD2F2_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F2_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD2F2_PCIE_CORR_ERR_STATUS", REG_SMC, 0x3000058, &ixD2F2_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F2_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F2_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_CORR_ERR_MASK", REG_SMC, 0x3000059, &ixD2F2_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F2_PCIE_CORR_ERR_MASK)/sizeof(ixD2F2_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F2_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x300005a, &ixD2F2_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F2_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F2_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_HDR_LOG0", REG_SMC, 0x300005b, &ixD2F2_PCIE_HDR_LOG0[0], sizeof(ixD2F2_PCIE_HDR_LOG0)/sizeof(ixD2F2_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD2F2_PCIE_HDR_LOG1", REG_SMC, 0x300005c, &ixD2F2_PCIE_HDR_LOG1[0], sizeof(ixD2F2_PCIE_HDR_LOG1)/sizeof(ixD2F2_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD2F2_PCIE_HDR_LOG2", REG_SMC, 0x300005d, &ixD2F2_PCIE_HDR_LOG2[0], sizeof(ixD2F2_PCIE_HDR_LOG2)/sizeof(ixD2F2_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD2F2_PCIE_HDR_LOG3", REG_SMC, 0x300005e, &ixD2F2_PCIE_HDR_LOG3[0], sizeof(ixD2F2_PCIE_HDR_LOG3)/sizeof(ixD2F2_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD2F2_PCIE_ROOT_ERR_CMD", REG_SMC, 0x300005f, &ixD2F2_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F2_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F2_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD2F2_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x3000060, &ixD2F2_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F2_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F2_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_ERR_SRC_ID", REG_SMC, 0x3000061, &ixD2F2_PCIE_ERR_SRC_ID[0], sizeof(ixD2F2_PCIE_ERR_SRC_ID)/sizeof(ixD2F2_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD2F2_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x3000062, &ixD2F2_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F2_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x3000063, &ixD2F2_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD2F2_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x3000064, &ixD2F2_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD2F2_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x3000065, &ixD2F2_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x300009c, &ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_LINK_CNTL3", REG_SMC, 0x300009d, &ixD2F2_PCIE_LINK_CNTL3[0], sizeof(ixD2F2_PCIE_LINK_CNTL3)/sizeof(ixD2F2_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x300009e, &ixD2F2_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F2_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F2_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x300009f, &ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x30000a0, &ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x30000a1, &ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x30000a2, &ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x30000a3, &ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x30000a4, &ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x30000a5, &ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x30000a6, &ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x30000a8, &ixD2F2_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_ACS_CNTL", REG_SMC, 0x30000a9, &ixD2F2_PCIE_ACS_CNTL[0], sizeof(ixD2F2_PCIE_ACS_CNTL)/sizeof(ixD2F2_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_ACS_CAP", REG_SMC, 0x30000a9, &ixD2F2_PCIE_ACS_CAP[0], sizeof(ixD2F2_PCIE_ACS_CAP)/sizeof(ixD2F2_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x30000bc, &ixD2F2_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_CNTL", REG_SMC, 0x30000bd, &ixD2F2_PCIE_MC_CNTL[0], sizeof(ixD2F2_PCIE_MC_CNTL)/sizeof(ixD2F2_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_CAP", REG_SMC, 0x30000bd, &ixD2F2_PCIE_MC_CAP[0], sizeof(ixD2F2_PCIE_MC_CAP)/sizeof(ixD2F2_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_ADDR0", REG_SMC, 0x30000be, &ixD2F2_PCIE_MC_ADDR0[0], sizeof(ixD2F2_PCIE_MC_ADDR0)/sizeof(ixD2F2_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_ADDR1", REG_SMC, 0x30000bf, &ixD2F2_PCIE_MC_ADDR1[0], sizeof(ixD2F2_PCIE_MC_ADDR1)/sizeof(ixD2F2_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_RCV0", REG_SMC, 0x30000c0, &ixD2F2_PCIE_MC_RCV0[0], sizeof(ixD2F2_PCIE_MC_RCV0)/sizeof(ixD2F2_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_RCV1", REG_SMC, 0x30000c1, &ixD2F2_PCIE_MC_RCV1[0], sizeof(ixD2F2_PCIE_MC_RCV1)/sizeof(ixD2F2_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x30000c2, &ixD2F2_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F2_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F2_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x30000c3, &ixD2F2_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F2_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F2_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x30000c4, &ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x30000c5, &ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x30000c6, &ixD2F2_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD2F2_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x30000c7, &ixD2F2_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x31, &ixD2F1_PCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_NP)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x32, &ixD2F1_PCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_INIT_P", REG_SMC, 0x33, &ixD2F1_PCIE_TX_CREDITS_INIT_P[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_P)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_P[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x34, &ixD2F1_PCIE_TX_CREDITS_INIT_NP[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_NP)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_NP[0]), 0, 0 }, + { "mmNB_GBIF_INDEX", REG_MMIO, 0x34, &mmNB_GBIF_INDEX[0], sizeof(mmNB_GBIF_INDEX)/sizeof(mmNB_GBIF_INDEX[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x35, &ixD2F1_PCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_CPL)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 }, + { "mmNB_GBIF_DATA", REG_MMIO, 0x35, &mmNB_GBIF_DATA[0], sizeof(mmNB_GBIF_DATA)/sizeof(mmNB_GBIF_DATA[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_STATUS", REG_SMC, 0x36, &ixD2F1_PCIE_TX_CREDITS_STATUS[0], sizeof(ixD2F1_PCIE_TX_CREDITS_STATUS)/sizeof(ixD2F1_PCIE_TX_CREDITS_STATUS[0]), 0, 0 }, + { "ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x37, &ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 }, + { "mmPCIE_WRAPPER1_C_PCIE_INDEX", REG_MMIO, 0x38, NULL, 0, 0, 0 }, + { "mmC_PCIE_P_INDEX", REG_MMIO, 0x38, &mmC_PCIE_P_INDEX[0], sizeof(mmC_PCIE_P_INDEX)/sizeof(mmC_PCIE_P_INDEX[0]), 0, 0 }, + { "mmPCIE_WRAPPER1_C_PCIE_DATA", REG_MMIO, 0x39, NULL, 0, 0, 0 }, + { "mmC_PCIE_P_DATA", REG_MMIO, 0x39, &mmC_PCIE_P_DATA[0], sizeof(mmC_PCIE_P_DATA)/sizeof(mmC_PCIE_P_DATA[0]), 0, 0 }, + { "mmRFE_SNOOP_RST", REG_MMIO, 0x3c, NULL, 0, 0, 0 }, + { "mmBASE_ADDR_1", REG_MMIO, 0x4, &mmBASE_ADDR_1[0], sizeof(mmBASE_ADDR_1)/sizeof(mmBASE_ADDR_1[0]), 0, 0 }, + { "mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_MMIO, 0x40, &mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_VENDOR_ID", REG_SMC, 0x4000000, &ixD2F3_VENDOR_ID[0], sizeof(ixD2F3_VENDOR_ID)/sizeof(ixD2F3_VENDOR_ID[0]), 0, 0 }, + { "ixD2F3_COMMAND", REG_SMC, 0x4000001, &ixD2F3_COMMAND[0], sizeof(ixD2F3_COMMAND)/sizeof(ixD2F3_COMMAND[0]), 0, 0 }, + { "ixD2F3_STATUS", REG_SMC, 0x4000001, &ixD2F3_STATUS[0], sizeof(ixD2F3_STATUS)/sizeof(ixD2F3_STATUS[0]), 0, 0 }, + { "ixD2F3_PROG_INTERFACE", REG_SMC, 0x4000002, &ixD2F3_PROG_INTERFACE[0], sizeof(ixD2F3_PROG_INTERFACE)/sizeof(ixD2F3_PROG_INTERFACE[0]), 0, 0 }, + { "ixD2F3_REVISION_ID", REG_SMC, 0x4000002, &ixD2F3_REVISION_ID[0], sizeof(ixD2F3_REVISION_ID)/sizeof(ixD2F3_REVISION_ID[0]), 0, 0 }, + { "ixD2F3_BASE_CLASS", REG_SMC, 0x4000002, &ixD2F3_BASE_CLASS[0], sizeof(ixD2F3_BASE_CLASS)/sizeof(ixD2F3_BASE_CLASS[0]), 0, 0 }, + { "ixD2F3_SUB_CLASS", REG_SMC, 0x4000002, &ixD2F3_SUB_CLASS[0], sizeof(ixD2F3_SUB_CLASS)/sizeof(ixD2F3_SUB_CLASS[0]), 0, 0 }, + { "ixD2F3_CACHE_LINE", REG_SMC, 0x4000003, &ixD2F3_CACHE_LINE[0], sizeof(ixD2F3_CACHE_LINE)/sizeof(ixD2F3_CACHE_LINE[0]), 0, 0 }, + { "ixD2F3_LATENCY", REG_SMC, 0x4000003, &ixD2F3_LATENCY[0], sizeof(ixD2F3_LATENCY)/sizeof(ixD2F3_LATENCY[0]), 0, 0 }, + { "ixD2F3_HEADER", REG_SMC, 0x4000003, &ixD2F3_HEADER[0], sizeof(ixD2F3_HEADER)/sizeof(ixD2F3_HEADER[0]), 0, 0 }, + { "ixD2F3_BIST", REG_SMC, 0x4000003, &ixD2F3_BIST[0], sizeof(ixD2F3_BIST)/sizeof(ixD2F3_BIST[0]), 0, 0 }, + { "ixD2F3_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x4000006, &ixD2F3_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F3_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F3_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD2F3_SECONDARY_STATUS", REG_SMC, 0x4000007, &ixD2F3_SECONDARY_STATUS[0], sizeof(ixD2F3_SECONDARY_STATUS)/sizeof(ixD2F3_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD2F3_IO_BASE_LIMIT", REG_SMC, 0x4000007, &ixD2F3_IO_BASE_LIMIT[0], sizeof(ixD2F3_IO_BASE_LIMIT)/sizeof(ixD2F3_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F3_MEM_BASE_LIMIT", REG_SMC, 0x4000008, &ixD2F3_MEM_BASE_LIMIT[0], sizeof(ixD2F3_MEM_BASE_LIMIT)/sizeof(ixD2F3_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F3_PREF_BASE_LIMIT", REG_SMC, 0x4000009, &ixD2F3_PREF_BASE_LIMIT[0], sizeof(ixD2F3_PREF_BASE_LIMIT)/sizeof(ixD2F3_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F3_PREF_BASE_UPPER", REG_SMC, 0x400000a, &ixD2F3_PREF_BASE_UPPER[0], sizeof(ixD2F3_PREF_BASE_UPPER)/sizeof(ixD2F3_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD2F3_PREF_LIMIT_UPPER", REG_SMC, 0x400000b, &ixD2F3_PREF_LIMIT_UPPER[0], sizeof(ixD2F3_PREF_LIMIT_UPPER)/sizeof(ixD2F3_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD2F3_IO_BASE_LIMIT_HI", REG_SMC, 0x400000c, &ixD2F3_IO_BASE_LIMIT_HI[0], sizeof(ixD2F3_IO_BASE_LIMIT_HI)/sizeof(ixD2F3_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD2F3_CAP_PTR", REG_SMC, 0x400000d, &ixD2F3_CAP_PTR[0], sizeof(ixD2F3_CAP_PTR)/sizeof(ixD2F3_CAP_PTR[0]), 0, 0 }, + { "ixD2F3_IRQ_BRIDGE_CNTL", REG_SMC, 0x400000f, &ixD2F3_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F3_IRQ_BRIDGE_CNTL)/sizeof(ixD2F3_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F3_INTERRUPT_LINE", REG_SMC, 0x400000f, &ixD2F3_INTERRUPT_LINE[0], sizeof(ixD2F3_INTERRUPT_LINE)/sizeof(ixD2F3_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD2F3_INTERRUPT_PIN", REG_SMC, 0x400000f, &ixD2F3_INTERRUPT_PIN[0], sizeof(ixD2F3_INTERRUPT_PIN)/sizeof(ixD2F3_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD2F3_EXT_BRIDGE_CNTL", REG_SMC, 0x4000010, &ixD2F3_EXT_BRIDGE_CNTL[0], sizeof(ixD2F3_EXT_BRIDGE_CNTL)/sizeof(ixD2F3_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F3_PMI_CAP_LIST", REG_SMC, 0x4000014, &ixD2F3_PMI_CAP_LIST[0], sizeof(ixD2F3_PMI_CAP_LIST)/sizeof(ixD2F3_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PMI_CAP", REG_SMC, 0x4000014, &ixD2F3_PMI_CAP[0], sizeof(ixD2F3_PMI_CAP)/sizeof(ixD2F3_PMI_CAP[0]), 0, 0 }, + { "ixD2F3_PMI_STATUS_CNTL", REG_SMC, 0x4000015, &ixD2F3_PMI_STATUS_CNTL[0], sizeof(ixD2F3_PMI_STATUS_CNTL)/sizeof(ixD2F3_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_CAP_LIST", REG_SMC, 0x4000016, &ixD2F3_PCIE_CAP_LIST[0], sizeof(ixD2F3_PCIE_CAP_LIST)/sizeof(ixD2F3_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_CAP", REG_SMC, 0x4000016, &ixD2F3_PCIE_CAP[0], sizeof(ixD2F3_PCIE_CAP)/sizeof(ixD2F3_PCIE_CAP[0]), 0, 0 }, + { "ixD2F3_DEVICE_CAP", REG_SMC, 0x4000017, &ixD2F3_DEVICE_CAP[0], sizeof(ixD2F3_DEVICE_CAP)/sizeof(ixD2F3_DEVICE_CAP[0]), 0, 0 }, + { "ixD2F3_DEVICE_STATUS", REG_SMC, 0x4000018, &ixD2F3_DEVICE_STATUS[0], sizeof(ixD2F3_DEVICE_STATUS)/sizeof(ixD2F3_DEVICE_STATUS[0]), 0, 0 }, + { "ixD2F3_DEVICE_CNTL", REG_SMC, 0x4000018, &ixD2F3_DEVICE_CNTL[0], sizeof(ixD2F3_DEVICE_CNTL)/sizeof(ixD2F3_DEVICE_CNTL[0]), 0, 0 }, + { "ixD2F3_LINK_CAP", REG_SMC, 0x4000019, &ixD2F3_LINK_CAP[0], sizeof(ixD2F3_LINK_CAP)/sizeof(ixD2F3_LINK_CAP[0]), 0, 0 }, + { "ixD2F3_LINK_STATUS", REG_SMC, 0x400001a, &ixD2F3_LINK_STATUS[0], sizeof(ixD2F3_LINK_STATUS)/sizeof(ixD2F3_LINK_STATUS[0]), 0, 0 }, + { "ixD2F3_LINK_CNTL", REG_SMC, 0x400001a, &ixD2F3_LINK_CNTL[0], sizeof(ixD2F3_LINK_CNTL)/sizeof(ixD2F3_LINK_CNTL[0]), 0, 0 }, + { "ixD2F3_SLOT_CAP", REG_SMC, 0x400001b, &ixD2F3_SLOT_CAP[0], sizeof(ixD2F3_SLOT_CAP)/sizeof(ixD2F3_SLOT_CAP[0]), 0, 0 }, + { "ixD2F3_SLOT_STATUS", REG_SMC, 0x400001c, &ixD2F3_SLOT_STATUS[0], sizeof(ixD2F3_SLOT_STATUS)/sizeof(ixD2F3_SLOT_STATUS[0]), 0, 0 }, + { "ixD2F3_SLOT_CNTL", REG_SMC, 0x400001c, &ixD2F3_SLOT_CNTL[0], sizeof(ixD2F3_SLOT_CNTL)/sizeof(ixD2F3_SLOT_CNTL[0]), 0, 0 }, + { "ixD2F3_ROOT_CNTL", REG_SMC, 0x400001d, &ixD2F3_ROOT_CNTL[0], sizeof(ixD2F3_ROOT_CNTL)/sizeof(ixD2F3_ROOT_CNTL[0]), 0, 0 }, + { "ixD2F3_ROOT_CAP", REG_SMC, 0x400001d, &ixD2F3_ROOT_CAP[0], sizeof(ixD2F3_ROOT_CAP)/sizeof(ixD2F3_ROOT_CAP[0]), 0, 0 }, + { "ixD2F3_ROOT_STATUS", REG_SMC, 0x400001e, &ixD2F3_ROOT_STATUS[0], sizeof(ixD2F3_ROOT_STATUS)/sizeof(ixD2F3_ROOT_STATUS[0]), 0, 0 }, + { "ixD2F3_DEVICE_CAP2", REG_SMC, 0x400001f, &ixD2F3_DEVICE_CAP2[0], sizeof(ixD2F3_DEVICE_CAP2)/sizeof(ixD2F3_DEVICE_CAP2[0]), 0, 0 }, + { "ixD2F3_DEVICE_STATUS2", REG_SMC, 0x4000020, &ixD2F3_DEVICE_STATUS2[0], sizeof(ixD2F3_DEVICE_STATUS2)/sizeof(ixD2F3_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD2F3_DEVICE_CNTL2", REG_SMC, 0x4000020, &ixD2F3_DEVICE_CNTL2[0], sizeof(ixD2F3_DEVICE_CNTL2)/sizeof(ixD2F3_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F3_LINK_CAP2", REG_SMC, 0x4000021, &ixD2F3_LINK_CAP2[0], sizeof(ixD2F3_LINK_CAP2)/sizeof(ixD2F3_LINK_CAP2[0]), 0, 0 }, + { "ixD2F3_LINK_STATUS2", REG_SMC, 0x4000022, &ixD2F3_LINK_STATUS2[0], sizeof(ixD2F3_LINK_STATUS2)/sizeof(ixD2F3_LINK_STATUS2[0]), 0, 0 }, + { "ixD2F3_LINK_CNTL2", REG_SMC, 0x4000022, &ixD2F3_LINK_CNTL2[0], sizeof(ixD2F3_LINK_CNTL2)/sizeof(ixD2F3_LINK_CNTL2[0]), 0, 0 }, + { "ixD2F3_SLOT_CAP2", REG_SMC, 0x4000023, &ixD2F3_SLOT_CAP2[0], sizeof(ixD2F3_SLOT_CAP2)/sizeof(ixD2F3_SLOT_CAP2[0]), 0, 0 }, + { "ixD2F3_SLOT_STATUS2", REG_SMC, 0x4000024, &ixD2F3_SLOT_STATUS2[0], sizeof(ixD2F3_SLOT_STATUS2)/sizeof(ixD2F3_SLOT_STATUS2[0]), 0, 0 }, + { "ixD2F3_SLOT_CNTL2", REG_SMC, 0x4000024, &ixD2F3_SLOT_CNTL2[0], sizeof(ixD2F3_SLOT_CNTL2)/sizeof(ixD2F3_SLOT_CNTL2[0]), 0, 0 }, + { "ixD2F3_MSI_CAP_LIST", REG_SMC, 0x4000028, &ixD2F3_MSI_CAP_LIST[0], sizeof(ixD2F3_MSI_CAP_LIST)/sizeof(ixD2F3_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_MSI_MSG_ADDR_LO", REG_SMC, 0x4000029, &ixD2F3_MSI_MSG_ADDR_LO[0], sizeof(ixD2F3_MSI_MSG_ADDR_LO)/sizeof(ixD2F3_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD2F3_MSI_MSG_ADDR_HI", REG_SMC, 0x400002a, &ixD2F3_MSI_MSG_ADDR_HI[0], sizeof(ixD2F3_MSI_MSG_ADDR_HI)/sizeof(ixD2F3_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD2F3_MSI_MSG_DATA", REG_SMC, 0x400002a, &ixD2F3_MSI_MSG_DATA[0], sizeof(ixD2F3_MSI_MSG_DATA)/sizeof(ixD2F3_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD2F3_MSI_MSG_DATA_64", REG_SMC, 0x400002b, &ixD2F3_MSI_MSG_DATA_64[0], sizeof(ixD2F3_MSI_MSG_DATA_64)/sizeof(ixD2F3_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD2F3_SSID_CAP_LIST", REG_SMC, 0x4000030, &ixD2F3_SSID_CAP_LIST[0], sizeof(ixD2F3_SSID_CAP_LIST)/sizeof(ixD2F3_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_SSID_CAP", REG_SMC, 0x4000031, &ixD2F3_SSID_CAP[0], sizeof(ixD2F3_SSID_CAP)/sizeof(ixD2F3_SSID_CAP[0]), 0, 0 }, + { "ixD2F3_MSI_MAP_CAP_LIST", REG_SMC, 0x4000032, &ixD2F3_MSI_MAP_CAP_LIST[0], sizeof(ixD2F3_MSI_MAP_CAP_LIST)/sizeof(ixD2F3_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_MSI_MAP_CAP", REG_SMC, 0x4000032, &ixD2F3_MSI_MAP_CAP[0], sizeof(ixD2F3_MSI_MAP_CAP)/sizeof(ixD2F3_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD2F3_MSI_MAP_ADDR_LO", REG_SMC, 0x4000033, &ixD2F3_MSI_MAP_ADDR_LO[0], sizeof(ixD2F3_MSI_MAP_ADDR_LO)/sizeof(ixD2F3_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD2F3_MSI_MAP_ADDR_HI", REG_SMC, 0x4000034, &ixD2F3_MSI_MAP_ADDR_HI[0], sizeof(ixD2F3_MSI_MAP_ADDR_HI)/sizeof(ixD2F3_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_INDEX", REG_SMC, 0x4000038, &ixD2F3_PCIE_PORT_INDEX[0], sizeof(ixD2F3_PCIE_PORT_INDEX)/sizeof(ixD2F3_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_DATA", REG_SMC, 0x4000039, &ixD2F3_PCIE_PORT_DATA[0], sizeof(ixD2F3_PCIE_PORT_DATA)/sizeof(ixD2F3_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x4000040, &ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x4000041, &ixD2F3_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD2F3_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x4000042, &ixD2F3_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD2F3_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x4000043, &ixD2F3_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD2F3_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x4000044, &ixD2F3_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x4000045, &ixD2F3_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x4000046, &ixD2F3_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_VC_STATUS", REG_SMC, 0x4000047, &ixD2F3_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F3_PCIE_PORT_VC_STATUS)/sizeof(ixD2F3_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_PORT_VC_CNTL", REG_SMC, 0x4000047, &ixD2F3_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F3_PCIE_PORT_VC_CNTL)/sizeof(ixD2F3_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x4000048, &ixD2F3_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F3_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x4000049, &ixD2F3_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x400004a, &ixD2F3_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x400004b, &ixD2F3_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F3_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x400004c, &ixD2F3_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x400004d, &ixD2F3_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x4000050, &ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x4000051, &ixD2F3_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD2F3_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x4000052, &ixD2F3_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x4000054, &ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x4000055, &ixD2F3_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F3_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x4000056, &ixD2F3_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F3_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F3_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x4000057, &ixD2F3_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F3_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD2F3_PCIE_CORR_ERR_STATUS", REG_SMC, 0x4000058, &ixD2F3_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F3_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F3_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_CORR_ERR_MASK", REG_SMC, 0x4000059, &ixD2F3_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F3_PCIE_CORR_ERR_MASK)/sizeof(ixD2F3_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F3_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x400005a, &ixD2F3_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F3_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F3_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_HDR_LOG0", REG_SMC, 0x400005b, &ixD2F3_PCIE_HDR_LOG0[0], sizeof(ixD2F3_PCIE_HDR_LOG0)/sizeof(ixD2F3_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD2F3_PCIE_HDR_LOG1", REG_SMC, 0x400005c, &ixD2F3_PCIE_HDR_LOG1[0], sizeof(ixD2F3_PCIE_HDR_LOG1)/sizeof(ixD2F3_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD2F3_PCIE_HDR_LOG2", REG_SMC, 0x400005d, &ixD2F3_PCIE_HDR_LOG2[0], sizeof(ixD2F3_PCIE_HDR_LOG2)/sizeof(ixD2F3_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD2F3_PCIE_HDR_LOG3", REG_SMC, 0x400005e, &ixD2F3_PCIE_HDR_LOG3[0], sizeof(ixD2F3_PCIE_HDR_LOG3)/sizeof(ixD2F3_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD2F3_PCIE_ROOT_ERR_CMD", REG_SMC, 0x400005f, &ixD2F3_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F3_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F3_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD2F3_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x4000060, &ixD2F3_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F3_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F3_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_ERR_SRC_ID", REG_SMC, 0x4000061, &ixD2F3_PCIE_ERR_SRC_ID[0], sizeof(ixD2F3_PCIE_ERR_SRC_ID)/sizeof(ixD2F3_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD2F3_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x4000062, &ixD2F3_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F3_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x4000063, &ixD2F3_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD2F3_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x4000064, &ixD2F3_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD2F3_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x4000065, &ixD2F3_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x400009c, &ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_LINK_CNTL3", REG_SMC, 0x400009d, &ixD2F3_PCIE_LINK_CNTL3[0], sizeof(ixD2F3_PCIE_LINK_CNTL3)/sizeof(ixD2F3_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x400009e, &ixD2F3_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F3_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F3_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x400009f, &ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x40000a0, &ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x40000a1, &ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x40000a2, &ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x40000a3, &ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x40000a4, &ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x40000a5, &ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x40000a6, &ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x40000a8, &ixD2F3_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_ACS_CNTL", REG_SMC, 0x40000a9, &ixD2F3_PCIE_ACS_CNTL[0], sizeof(ixD2F3_PCIE_ACS_CNTL)/sizeof(ixD2F3_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_ACS_CAP", REG_SMC, 0x40000a9, &ixD2F3_PCIE_ACS_CAP[0], sizeof(ixD2F3_PCIE_ACS_CAP)/sizeof(ixD2F3_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x40000bc, &ixD2F3_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_CNTL", REG_SMC, 0x40000bd, &ixD2F3_PCIE_MC_CNTL[0], sizeof(ixD2F3_PCIE_MC_CNTL)/sizeof(ixD2F3_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_CAP", REG_SMC, 0x40000bd, &ixD2F3_PCIE_MC_CAP[0], sizeof(ixD2F3_PCIE_MC_CAP)/sizeof(ixD2F3_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_ADDR0", REG_SMC, 0x40000be, &ixD2F3_PCIE_MC_ADDR0[0], sizeof(ixD2F3_PCIE_MC_ADDR0)/sizeof(ixD2F3_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_ADDR1", REG_SMC, 0x40000bf, &ixD2F3_PCIE_MC_ADDR1[0], sizeof(ixD2F3_PCIE_MC_ADDR1)/sizeof(ixD2F3_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_RCV0", REG_SMC, 0x40000c0, &ixD2F3_PCIE_MC_RCV0[0], sizeof(ixD2F3_PCIE_MC_RCV0)/sizeof(ixD2F3_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_RCV1", REG_SMC, 0x40000c1, &ixD2F3_PCIE_MC_RCV1[0], sizeof(ixD2F3_PCIE_MC_RCV1)/sizeof(ixD2F3_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x40000c2, &ixD2F3_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F3_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F3_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x40000c3, &ixD2F3_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F3_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F3_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x40000c4, &ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x40000c5, &ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x40000c6, &ixD2F3_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD2F3_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x40000c7, &ixD2F3_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "mmPCIE_VENDOR_SPECIFIC_HDR", REG_MMIO, 0x41, &mmPCIE_VENDOR_SPECIFIC_HDR[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "mmPCIE_VENDOR_SPECIFIC1", REG_MMIO, 0x42, &mmPCIE_VENDOR_SPECIFIC1[0], sizeof(mmPCIE_VENDOR_SPECIFIC1)/sizeof(mmPCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "mmPCIE_VENDOR_SPECIFIC2", REG_MMIO, 0x43, &mmPCIE_VENDOR_SPECIFIC2[0], sizeof(mmPCIE_VENDOR_SPECIFIC2)/sizeof(mmPCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "mmPCIE_VC_ENH_CAP_LIST", REG_MMIO, 0x44, &mmPCIE_VC_ENH_CAP_LIST[0], sizeof(mmPCIE_VC_ENH_CAP_LIST)/sizeof(mmPCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_PORT_VC_CAP_REG1", REG_MMIO, 0x45, &mmPCIE_PORT_VC_CAP_REG1[0], sizeof(mmPCIE_PORT_VC_CAP_REG1)/sizeof(mmPCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "mmPCIE_PORT_VC_CAP_REG2", REG_MMIO, 0x46, &mmPCIE_PORT_VC_CAP_REG2[0], sizeof(mmPCIE_PORT_VC_CAP_REG2)/sizeof(mmPCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "mmPCIE_PORT_VC_STATUS", REG_MMIO, 0x47, &mmPCIE_PORT_VC_STATUS[0], sizeof(mmPCIE_PORT_VC_STATUS)/sizeof(mmPCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "mmPCIE_PORT_VC_CNTL", REG_MMIO, 0x47, &mmPCIE_PORT_VC_CNTL[0], sizeof(mmPCIE_PORT_VC_CNTL)/sizeof(mmPCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "mmPCIE_VC0_RESOURCE_CAP", REG_MMIO, 0x48, &mmPCIE_VC0_RESOURCE_CAP[0], sizeof(mmPCIE_VC0_RESOURCE_CAP)/sizeof(mmPCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "mmPCIE_VC0_RESOURCE_CNTL", REG_MMIO, 0x49, &mmPCIE_VC0_RESOURCE_CNTL[0], sizeof(mmPCIE_VC0_RESOURCE_CNTL)/sizeof(mmPCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "mmPCIE_VC0_RESOURCE_STATUS", REG_MMIO, 0x4a, &mmPCIE_VC0_RESOURCE_STATUS[0], sizeof(mmPCIE_VC0_RESOURCE_STATUS)/sizeof(mmPCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "mmPCIE_VC1_RESOURCE_CAP", REG_MMIO, 0x4b, &mmPCIE_VC1_RESOURCE_CAP[0], sizeof(mmPCIE_VC1_RESOURCE_CAP)/sizeof(mmPCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "mmPCIE_VC1_RESOURCE_CNTL", REG_MMIO, 0x4c, &mmPCIE_VC1_RESOURCE_CNTL[0], sizeof(mmPCIE_VC1_RESOURCE_CNTL)/sizeof(mmPCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "mmPCIE_VC1_RESOURCE_STATUS", REG_MMIO, 0x4d, &mmPCIE_VC1_RESOURCE_STATUS[0], sizeof(mmPCIE_VC1_RESOURCE_STATUS)/sizeof(mmPCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "mmBASE_ADDR_2", REG_MMIO, 0x5, &mmBASE_ADDR_2[0], sizeof(mmBASE_ADDR_2)/sizeof(mmBASE_ADDR_2[0]), 0, 0 }, + { "mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_MMIO, 0x50, &mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_P_PORT_LANE_STATUS", REG_SMC, 0x50, &ixD2F1_PCIE_P_PORT_LANE_STATUS[0], sizeof(ixD2F1_PCIE_P_PORT_LANE_STATUS)/sizeof(ixD2F1_PCIE_P_PORT_LANE_STATUS[0]), 0, 0 }, + { "ixD2F4_VENDOR_ID", REG_SMC, 0x5000000, &ixD2F4_VENDOR_ID[0], sizeof(ixD2F4_VENDOR_ID)/sizeof(ixD2F4_VENDOR_ID[0]), 0, 0 }, + { "ixD2F4_COMMAND", REG_SMC, 0x5000001, &ixD2F4_COMMAND[0], sizeof(ixD2F4_COMMAND)/sizeof(ixD2F4_COMMAND[0]), 0, 0 }, + { "ixD2F4_STATUS", REG_SMC, 0x5000001, &ixD2F4_STATUS[0], sizeof(ixD2F4_STATUS)/sizeof(ixD2F4_STATUS[0]), 0, 0 }, + { "ixD2F4_PROG_INTERFACE", REG_SMC, 0x5000002, &ixD2F4_PROG_INTERFACE[0], sizeof(ixD2F4_PROG_INTERFACE)/sizeof(ixD2F4_PROG_INTERFACE[0]), 0, 0 }, + { "ixD2F4_REVISION_ID", REG_SMC, 0x5000002, &ixD2F4_REVISION_ID[0], sizeof(ixD2F4_REVISION_ID)/sizeof(ixD2F4_REVISION_ID[0]), 0, 0 }, + { "ixD2F4_BASE_CLASS", REG_SMC, 0x5000002, &ixD2F4_BASE_CLASS[0], sizeof(ixD2F4_BASE_CLASS)/sizeof(ixD2F4_BASE_CLASS[0]), 0, 0 }, + { "ixD2F4_SUB_CLASS", REG_SMC, 0x5000002, &ixD2F4_SUB_CLASS[0], sizeof(ixD2F4_SUB_CLASS)/sizeof(ixD2F4_SUB_CLASS[0]), 0, 0 }, + { "ixD2F4_CACHE_LINE", REG_SMC, 0x5000003, &ixD2F4_CACHE_LINE[0], sizeof(ixD2F4_CACHE_LINE)/sizeof(ixD2F4_CACHE_LINE[0]), 0, 0 }, + { "ixD2F4_LATENCY", REG_SMC, 0x5000003, &ixD2F4_LATENCY[0], sizeof(ixD2F4_LATENCY)/sizeof(ixD2F4_LATENCY[0]), 0, 0 }, + { "ixD2F4_HEADER", REG_SMC, 0x5000003, &ixD2F4_HEADER[0], sizeof(ixD2F4_HEADER)/sizeof(ixD2F4_HEADER[0]), 0, 0 }, + { "ixD2F4_BIST", REG_SMC, 0x5000003, &ixD2F4_BIST[0], sizeof(ixD2F4_BIST)/sizeof(ixD2F4_BIST[0]), 0, 0 }, + { "ixD2F4_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x5000006, &ixD2F4_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F4_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F4_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD2F4_SECONDARY_STATUS", REG_SMC, 0x5000007, &ixD2F4_SECONDARY_STATUS[0], sizeof(ixD2F4_SECONDARY_STATUS)/sizeof(ixD2F4_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD2F4_IO_BASE_LIMIT", REG_SMC, 0x5000007, &ixD2F4_IO_BASE_LIMIT[0], sizeof(ixD2F4_IO_BASE_LIMIT)/sizeof(ixD2F4_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F4_MEM_BASE_LIMIT", REG_SMC, 0x5000008, &ixD2F4_MEM_BASE_LIMIT[0], sizeof(ixD2F4_MEM_BASE_LIMIT)/sizeof(ixD2F4_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F4_PREF_BASE_LIMIT", REG_SMC, 0x5000009, &ixD2F4_PREF_BASE_LIMIT[0], sizeof(ixD2F4_PREF_BASE_LIMIT)/sizeof(ixD2F4_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F4_PREF_BASE_UPPER", REG_SMC, 0x500000a, &ixD2F4_PREF_BASE_UPPER[0], sizeof(ixD2F4_PREF_BASE_UPPER)/sizeof(ixD2F4_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD2F4_PREF_LIMIT_UPPER", REG_SMC, 0x500000b, &ixD2F4_PREF_LIMIT_UPPER[0], sizeof(ixD2F4_PREF_LIMIT_UPPER)/sizeof(ixD2F4_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD2F4_IO_BASE_LIMIT_HI", REG_SMC, 0x500000c, &ixD2F4_IO_BASE_LIMIT_HI[0], sizeof(ixD2F4_IO_BASE_LIMIT_HI)/sizeof(ixD2F4_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD2F4_CAP_PTR", REG_SMC, 0x500000d, &ixD2F4_CAP_PTR[0], sizeof(ixD2F4_CAP_PTR)/sizeof(ixD2F4_CAP_PTR[0]), 0, 0 }, + { "ixD2F4_IRQ_BRIDGE_CNTL", REG_SMC, 0x500000f, &ixD2F4_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F4_IRQ_BRIDGE_CNTL)/sizeof(ixD2F4_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F4_INTERRUPT_LINE", REG_SMC, 0x500000f, &ixD2F4_INTERRUPT_LINE[0], sizeof(ixD2F4_INTERRUPT_LINE)/sizeof(ixD2F4_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD2F4_INTERRUPT_PIN", REG_SMC, 0x500000f, &ixD2F4_INTERRUPT_PIN[0], sizeof(ixD2F4_INTERRUPT_PIN)/sizeof(ixD2F4_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD2F4_EXT_BRIDGE_CNTL", REG_SMC, 0x5000010, &ixD2F4_EXT_BRIDGE_CNTL[0], sizeof(ixD2F4_EXT_BRIDGE_CNTL)/sizeof(ixD2F4_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F4_PMI_CAP_LIST", REG_SMC, 0x5000014, &ixD2F4_PMI_CAP_LIST[0], sizeof(ixD2F4_PMI_CAP_LIST)/sizeof(ixD2F4_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PMI_CAP", REG_SMC, 0x5000014, &ixD2F4_PMI_CAP[0], sizeof(ixD2F4_PMI_CAP)/sizeof(ixD2F4_PMI_CAP[0]), 0, 0 }, + { "ixD2F4_PMI_STATUS_CNTL", REG_SMC, 0x5000015, &ixD2F4_PMI_STATUS_CNTL[0], sizeof(ixD2F4_PMI_STATUS_CNTL)/sizeof(ixD2F4_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_CAP_LIST", REG_SMC, 0x5000016, &ixD2F4_PCIE_CAP_LIST[0], sizeof(ixD2F4_PCIE_CAP_LIST)/sizeof(ixD2F4_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_CAP", REG_SMC, 0x5000016, &ixD2F4_PCIE_CAP[0], sizeof(ixD2F4_PCIE_CAP)/sizeof(ixD2F4_PCIE_CAP[0]), 0, 0 }, + { "ixD2F4_DEVICE_CAP", REG_SMC, 0x5000017, &ixD2F4_DEVICE_CAP[0], sizeof(ixD2F4_DEVICE_CAP)/sizeof(ixD2F4_DEVICE_CAP[0]), 0, 0 }, + { "ixD2F4_DEVICE_STATUS", REG_SMC, 0x5000018, &ixD2F4_DEVICE_STATUS[0], sizeof(ixD2F4_DEVICE_STATUS)/sizeof(ixD2F4_DEVICE_STATUS[0]), 0, 0 }, + { "ixD2F4_DEVICE_CNTL", REG_SMC, 0x5000018, &ixD2F4_DEVICE_CNTL[0], sizeof(ixD2F4_DEVICE_CNTL)/sizeof(ixD2F4_DEVICE_CNTL[0]), 0, 0 }, + { "ixD2F4_LINK_CAP", REG_SMC, 0x5000019, &ixD2F4_LINK_CAP[0], sizeof(ixD2F4_LINK_CAP)/sizeof(ixD2F4_LINK_CAP[0]), 0, 0 }, + { "ixD2F4_LINK_STATUS", REG_SMC, 0x500001a, &ixD2F4_LINK_STATUS[0], sizeof(ixD2F4_LINK_STATUS)/sizeof(ixD2F4_LINK_STATUS[0]), 0, 0 }, + { "ixD2F4_LINK_CNTL", REG_SMC, 0x500001a, &ixD2F4_LINK_CNTL[0], sizeof(ixD2F4_LINK_CNTL)/sizeof(ixD2F4_LINK_CNTL[0]), 0, 0 }, + { "ixD2F4_SLOT_CAP", REG_SMC, 0x500001b, &ixD2F4_SLOT_CAP[0], sizeof(ixD2F4_SLOT_CAP)/sizeof(ixD2F4_SLOT_CAP[0]), 0, 0 }, + { "ixD2F4_SLOT_STATUS", REG_SMC, 0x500001c, &ixD2F4_SLOT_STATUS[0], sizeof(ixD2F4_SLOT_STATUS)/sizeof(ixD2F4_SLOT_STATUS[0]), 0, 0 }, + { "ixD2F4_SLOT_CNTL", REG_SMC, 0x500001c, &ixD2F4_SLOT_CNTL[0], sizeof(ixD2F4_SLOT_CNTL)/sizeof(ixD2F4_SLOT_CNTL[0]), 0, 0 }, + { "ixD2F4_ROOT_CNTL", REG_SMC, 0x500001d, &ixD2F4_ROOT_CNTL[0], sizeof(ixD2F4_ROOT_CNTL)/sizeof(ixD2F4_ROOT_CNTL[0]), 0, 0 }, + { "ixD2F4_ROOT_CAP", REG_SMC, 0x500001d, &ixD2F4_ROOT_CAP[0], sizeof(ixD2F4_ROOT_CAP)/sizeof(ixD2F4_ROOT_CAP[0]), 0, 0 }, + { "ixD2F4_ROOT_STATUS", REG_SMC, 0x500001e, &ixD2F4_ROOT_STATUS[0], sizeof(ixD2F4_ROOT_STATUS)/sizeof(ixD2F4_ROOT_STATUS[0]), 0, 0 }, + { "ixD2F4_DEVICE_CAP2", REG_SMC, 0x500001f, &ixD2F4_DEVICE_CAP2[0], sizeof(ixD2F4_DEVICE_CAP2)/sizeof(ixD2F4_DEVICE_CAP2[0]), 0, 0 }, + { "ixD2F4_DEVICE_STATUS2", REG_SMC, 0x5000020, &ixD2F4_DEVICE_STATUS2[0], sizeof(ixD2F4_DEVICE_STATUS2)/sizeof(ixD2F4_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD2F4_DEVICE_CNTL2", REG_SMC, 0x5000020, &ixD2F4_DEVICE_CNTL2[0], sizeof(ixD2F4_DEVICE_CNTL2)/sizeof(ixD2F4_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F4_LINK_CAP2", REG_SMC, 0x5000021, &ixD2F4_LINK_CAP2[0], sizeof(ixD2F4_LINK_CAP2)/sizeof(ixD2F4_LINK_CAP2[0]), 0, 0 }, + { "ixD2F4_LINK_STATUS2", REG_SMC, 0x5000022, &ixD2F4_LINK_STATUS2[0], sizeof(ixD2F4_LINK_STATUS2)/sizeof(ixD2F4_LINK_STATUS2[0]), 0, 0 }, + { "ixD2F4_LINK_CNTL2", REG_SMC, 0x5000022, &ixD2F4_LINK_CNTL2[0], sizeof(ixD2F4_LINK_CNTL2)/sizeof(ixD2F4_LINK_CNTL2[0]), 0, 0 }, + { "ixD2F4_SLOT_CAP2", REG_SMC, 0x5000023, &ixD2F4_SLOT_CAP2[0], sizeof(ixD2F4_SLOT_CAP2)/sizeof(ixD2F4_SLOT_CAP2[0]), 0, 0 }, + { "ixD2F4_SLOT_STATUS2", REG_SMC, 0x5000024, &ixD2F4_SLOT_STATUS2[0], sizeof(ixD2F4_SLOT_STATUS2)/sizeof(ixD2F4_SLOT_STATUS2[0]), 0, 0 }, + { "ixD2F4_SLOT_CNTL2", REG_SMC, 0x5000024, &ixD2F4_SLOT_CNTL2[0], sizeof(ixD2F4_SLOT_CNTL2)/sizeof(ixD2F4_SLOT_CNTL2[0]), 0, 0 }, + { "ixD2F4_MSI_CAP_LIST", REG_SMC, 0x5000028, &ixD2F4_MSI_CAP_LIST[0], sizeof(ixD2F4_MSI_CAP_LIST)/sizeof(ixD2F4_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_MSI_MSG_ADDR_LO", REG_SMC, 0x5000029, &ixD2F4_MSI_MSG_ADDR_LO[0], sizeof(ixD2F4_MSI_MSG_ADDR_LO)/sizeof(ixD2F4_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD2F4_MSI_MSG_ADDR_HI", REG_SMC, 0x500002a, &ixD2F4_MSI_MSG_ADDR_HI[0], sizeof(ixD2F4_MSI_MSG_ADDR_HI)/sizeof(ixD2F4_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD2F4_MSI_MSG_DATA", REG_SMC, 0x500002a, &ixD2F4_MSI_MSG_DATA[0], sizeof(ixD2F4_MSI_MSG_DATA)/sizeof(ixD2F4_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD2F4_MSI_MSG_DATA_64", REG_SMC, 0x500002b, &ixD2F4_MSI_MSG_DATA_64[0], sizeof(ixD2F4_MSI_MSG_DATA_64)/sizeof(ixD2F4_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD2F4_SSID_CAP_LIST", REG_SMC, 0x5000030, &ixD2F4_SSID_CAP_LIST[0], sizeof(ixD2F4_SSID_CAP_LIST)/sizeof(ixD2F4_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_SSID_CAP", REG_SMC, 0x5000031, &ixD2F4_SSID_CAP[0], sizeof(ixD2F4_SSID_CAP)/sizeof(ixD2F4_SSID_CAP[0]), 0, 0 }, + { "ixD2F4_MSI_MAP_CAP_LIST", REG_SMC, 0x5000032, &ixD2F4_MSI_MAP_CAP_LIST[0], sizeof(ixD2F4_MSI_MAP_CAP_LIST)/sizeof(ixD2F4_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_MSI_MAP_CAP", REG_SMC, 0x5000032, &ixD2F4_MSI_MAP_CAP[0], sizeof(ixD2F4_MSI_MAP_CAP)/sizeof(ixD2F4_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD2F4_MSI_MAP_ADDR_LO", REG_SMC, 0x5000033, &ixD2F4_MSI_MAP_ADDR_LO[0], sizeof(ixD2F4_MSI_MAP_ADDR_LO)/sizeof(ixD2F4_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD2F4_MSI_MAP_ADDR_HI", REG_SMC, 0x5000034, &ixD2F4_MSI_MAP_ADDR_HI[0], sizeof(ixD2F4_MSI_MAP_ADDR_HI)/sizeof(ixD2F4_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_INDEX", REG_SMC, 0x5000038, &ixD2F4_PCIE_PORT_INDEX[0], sizeof(ixD2F4_PCIE_PORT_INDEX)/sizeof(ixD2F4_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_DATA", REG_SMC, 0x5000039, &ixD2F4_PCIE_PORT_DATA[0], sizeof(ixD2F4_PCIE_PORT_DATA)/sizeof(ixD2F4_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x5000040, &ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x5000041, &ixD2F4_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD2F4_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x5000042, &ixD2F4_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD2F4_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x5000043, &ixD2F4_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD2F4_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x5000044, &ixD2F4_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x5000045, &ixD2F4_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x5000046, &ixD2F4_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_VC_STATUS", REG_SMC, 0x5000047, &ixD2F4_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F4_PCIE_PORT_VC_STATUS)/sizeof(ixD2F4_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_PORT_VC_CNTL", REG_SMC, 0x5000047, &ixD2F4_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F4_PCIE_PORT_VC_CNTL)/sizeof(ixD2F4_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x5000048, &ixD2F4_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F4_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x5000049, &ixD2F4_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x500004a, &ixD2F4_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x500004b, &ixD2F4_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F4_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x500004c, &ixD2F4_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x500004d, &ixD2F4_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x5000050, &ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x5000051, &ixD2F4_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD2F4_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x5000052, &ixD2F4_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x5000054, &ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x5000055, &ixD2F4_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F4_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x5000056, &ixD2F4_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F4_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F4_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x5000057, &ixD2F4_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F4_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD2F4_PCIE_CORR_ERR_STATUS", REG_SMC, 0x5000058, &ixD2F4_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F4_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F4_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_CORR_ERR_MASK", REG_SMC, 0x5000059, &ixD2F4_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F4_PCIE_CORR_ERR_MASK)/sizeof(ixD2F4_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F4_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x500005a, &ixD2F4_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F4_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F4_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_HDR_LOG0", REG_SMC, 0x500005b, &ixD2F4_PCIE_HDR_LOG0[0], sizeof(ixD2F4_PCIE_HDR_LOG0)/sizeof(ixD2F4_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD2F4_PCIE_HDR_LOG1", REG_SMC, 0x500005c, &ixD2F4_PCIE_HDR_LOG1[0], sizeof(ixD2F4_PCIE_HDR_LOG1)/sizeof(ixD2F4_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD2F4_PCIE_HDR_LOG2", REG_SMC, 0x500005d, &ixD2F4_PCIE_HDR_LOG2[0], sizeof(ixD2F4_PCIE_HDR_LOG2)/sizeof(ixD2F4_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD2F4_PCIE_HDR_LOG3", REG_SMC, 0x500005e, &ixD2F4_PCIE_HDR_LOG3[0], sizeof(ixD2F4_PCIE_HDR_LOG3)/sizeof(ixD2F4_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD2F4_PCIE_ROOT_ERR_CMD", REG_SMC, 0x500005f, &ixD2F4_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F4_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F4_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD2F4_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x5000060, &ixD2F4_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F4_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F4_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_ERR_SRC_ID", REG_SMC, 0x5000061, &ixD2F4_PCIE_ERR_SRC_ID[0], sizeof(ixD2F4_PCIE_ERR_SRC_ID)/sizeof(ixD2F4_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD2F4_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x5000062, &ixD2F4_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F4_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x5000063, &ixD2F4_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD2F4_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x5000064, &ixD2F4_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD2F4_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x5000065, &ixD2F4_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x500009c, &ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_LINK_CNTL3", REG_SMC, 0x500009d, &ixD2F4_PCIE_LINK_CNTL3[0], sizeof(ixD2F4_PCIE_LINK_CNTL3)/sizeof(ixD2F4_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x500009e, &ixD2F4_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F4_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F4_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x500009f, &ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x50000a0, &ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x50000a1, &ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x50000a2, &ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x50000a3, &ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x50000a4, &ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x50000a5, &ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x50000a6, &ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x50000a8, &ixD2F4_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_ACS_CNTL", REG_SMC, 0x50000a9, &ixD2F4_PCIE_ACS_CNTL[0], sizeof(ixD2F4_PCIE_ACS_CNTL)/sizeof(ixD2F4_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_ACS_CAP", REG_SMC, 0x50000a9, &ixD2F4_PCIE_ACS_CAP[0], sizeof(ixD2F4_PCIE_ACS_CAP)/sizeof(ixD2F4_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x50000bc, &ixD2F4_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_CNTL", REG_SMC, 0x50000bd, &ixD2F4_PCIE_MC_CNTL[0], sizeof(ixD2F4_PCIE_MC_CNTL)/sizeof(ixD2F4_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_CAP", REG_SMC, 0x50000bd, &ixD2F4_PCIE_MC_CAP[0], sizeof(ixD2F4_PCIE_MC_CAP)/sizeof(ixD2F4_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_ADDR0", REG_SMC, 0x50000be, &ixD2F4_PCIE_MC_ADDR0[0], sizeof(ixD2F4_PCIE_MC_ADDR0)/sizeof(ixD2F4_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_ADDR1", REG_SMC, 0x50000bf, &ixD2F4_PCIE_MC_ADDR1[0], sizeof(ixD2F4_PCIE_MC_ADDR1)/sizeof(ixD2F4_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_RCV0", REG_SMC, 0x50000c0, &ixD2F4_PCIE_MC_RCV0[0], sizeof(ixD2F4_PCIE_MC_RCV0)/sizeof(ixD2F4_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_RCV1", REG_SMC, 0x50000c1, &ixD2F4_PCIE_MC_RCV1[0], sizeof(ixD2F4_PCIE_MC_RCV1)/sizeof(ixD2F4_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x50000c2, &ixD2F4_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F4_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F4_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x50000c3, &ixD2F4_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F4_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F4_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x50000c4, &ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x50000c5, &ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x50000c6, &ixD2F4_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD2F4_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x50000c7, &ixD2F4_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "mmPCIE_DEV_SERIAL_NUM_DW1", REG_MMIO, 0x51, &mmPCIE_DEV_SERIAL_NUM_DW1[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW1)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "mmPCIE_DEV_SERIAL_NUM_DW2", REG_MMIO, 0x52, &mmPCIE_DEV_SERIAL_NUM_DW2[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW2)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_MMIO, 0x54, &mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_UNCORR_ERR_STATUS", REG_MMIO, 0x55, &mmPCIE_UNCORR_ERR_STATUS[0], sizeof(mmPCIE_UNCORR_ERR_STATUS)/sizeof(mmPCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "mmPCIE_UNCORR_ERR_MASK", REG_MMIO, 0x56, &mmPCIE_UNCORR_ERR_MASK[0], sizeof(mmPCIE_UNCORR_ERR_MASK)/sizeof(mmPCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "mmPCIE_UNCORR_ERR_SEVERITY", REG_MMIO, 0x57, &mmPCIE_UNCORR_ERR_SEVERITY[0], sizeof(mmPCIE_UNCORR_ERR_SEVERITY)/sizeof(mmPCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "mmPCIE_CORR_ERR_STATUS", REG_MMIO, 0x58, &mmPCIE_CORR_ERR_STATUS[0], sizeof(mmPCIE_CORR_ERR_STATUS)/sizeof(mmPCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "mmPCIE_CORR_ERR_MASK", REG_MMIO, 0x59, &mmPCIE_CORR_ERR_MASK[0], sizeof(mmPCIE_CORR_ERR_MASK)/sizeof(mmPCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "mmPCIE_ADV_ERR_CAP_CNTL", REG_MMIO, 0x5a, &mmPCIE_ADV_ERR_CAP_CNTL[0], sizeof(mmPCIE_ADV_ERR_CAP_CNTL)/sizeof(mmPCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "mmPCIE_HDR_LOG0", REG_MMIO, 0x5b, &mmPCIE_HDR_LOG0[0], sizeof(mmPCIE_HDR_LOG0)/sizeof(mmPCIE_HDR_LOG0[0]), 0, 0 }, + { "mmPCIE_HDR_LOG1", REG_MMIO, 0x5c, &mmPCIE_HDR_LOG1[0], sizeof(mmPCIE_HDR_LOG1)/sizeof(mmPCIE_HDR_LOG1[0]), 0, 0 }, + { "mmBIOS_SCRATCH_0", REG_MMIO, 0x5c9, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 }, + { "mmBIOS_SCRATCH_1", REG_MMIO, 0x5ca, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 }, + { "mmBIOS_SCRATCH_2", REG_MMIO, 0x5cb, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 }, + { "mmBIOS_SCRATCH_3", REG_MMIO, 0x5cc, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 }, + { "mmBIOS_SCRATCH_4", REG_MMIO, 0x5cd, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 }, + { "mmBIOS_SCRATCH_5", REG_MMIO, 0x5ce, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 }, + { "mmBIOS_SCRATCH_6", REG_MMIO, 0x5cf, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 }, + { "mmPCIE_HDR_LOG2", REG_MMIO, 0x5d, &mmPCIE_HDR_LOG2[0], sizeof(mmPCIE_HDR_LOG2)/sizeof(mmPCIE_HDR_LOG2[0]), 0, 0 }, + { "mmBIOS_SCRATCH_7", REG_MMIO, 0x5d0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 }, + { "mmBIOS_SCRATCH_8", REG_MMIO, 0x5d1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 }, + { "mmBIOS_SCRATCH_9", REG_MMIO, 0x5d2, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 }, + { "mmBIOS_SCRATCH_10", REG_MMIO, 0x5d3, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 }, + { "mmBIOS_SCRATCH_11", REG_MMIO, 0x5d4, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 }, + { "mmBIOS_SCRATCH_12", REG_MMIO, 0x5d5, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 }, + { "mmBIOS_SCRATCH_13", REG_MMIO, 0x5d6, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 }, + { "mmBIOS_SCRATCH_14", REG_MMIO, 0x5d7, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 }, + { "mmBIOS_SCRATCH_15", REG_MMIO, 0x5d8, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 }, + { "mmPCIE_HDR_LOG3", REG_MMIO, 0x5e, &mmPCIE_HDR_LOG3[0], sizeof(mmPCIE_HDR_LOG3)/sizeof(mmPCIE_HDR_LOG3[0]), 0, 0 }, + { "mmMM_INDEX_HI", REG_MMIO, 0x6, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 }, + { "ixD2F1_PCIE_FC_P", REG_SMC, 0x60, &ixD2F1_PCIE_FC_P[0], sizeof(ixD2F1_PCIE_FC_P)/sizeof(ixD2F1_PCIE_FC_P[0]), 0, 0 }, + { "ixD2F5_VENDOR_ID", REG_SMC, 0x6000000, &ixD2F5_VENDOR_ID[0], sizeof(ixD2F5_VENDOR_ID)/sizeof(ixD2F5_VENDOR_ID[0]), 0, 0 }, + { "ixD2F5_COMMAND", REG_SMC, 0x6000001, &ixD2F5_COMMAND[0], sizeof(ixD2F5_COMMAND)/sizeof(ixD2F5_COMMAND[0]), 0, 0 }, + { "ixD2F5_STATUS", REG_SMC, 0x6000001, &ixD2F5_STATUS[0], sizeof(ixD2F5_STATUS)/sizeof(ixD2F5_STATUS[0]), 0, 0 }, + { "ixD2F5_PROG_INTERFACE", REG_SMC, 0x6000002, &ixD2F5_PROG_INTERFACE[0], sizeof(ixD2F5_PROG_INTERFACE)/sizeof(ixD2F5_PROG_INTERFACE[0]), 0, 0 }, + { "ixD2F5_REVISION_ID", REG_SMC, 0x6000002, &ixD2F5_REVISION_ID[0], sizeof(ixD2F5_REVISION_ID)/sizeof(ixD2F5_REVISION_ID[0]), 0, 0 }, + { "ixD2F5_BASE_CLASS", REG_SMC, 0x6000002, &ixD2F5_BASE_CLASS[0], sizeof(ixD2F5_BASE_CLASS)/sizeof(ixD2F5_BASE_CLASS[0]), 0, 0 }, + { "ixD2F5_SUB_CLASS", REG_SMC, 0x6000002, &ixD2F5_SUB_CLASS[0], sizeof(ixD2F5_SUB_CLASS)/sizeof(ixD2F5_SUB_CLASS[0]), 0, 0 }, + { "ixD2F5_CACHE_LINE", REG_SMC, 0x6000003, &ixD2F5_CACHE_LINE[0], sizeof(ixD2F5_CACHE_LINE)/sizeof(ixD2F5_CACHE_LINE[0]), 0, 0 }, + { "ixD2F5_LATENCY", REG_SMC, 0x6000003, &ixD2F5_LATENCY[0], sizeof(ixD2F5_LATENCY)/sizeof(ixD2F5_LATENCY[0]), 0, 0 }, + { "ixD2F5_HEADER", REG_SMC, 0x6000003, &ixD2F5_HEADER[0], sizeof(ixD2F5_HEADER)/sizeof(ixD2F5_HEADER[0]), 0, 0 }, + { "ixD2F5_BIST", REG_SMC, 0x6000003, &ixD2F5_BIST[0], sizeof(ixD2F5_BIST)/sizeof(ixD2F5_BIST[0]), 0, 0 }, + { "ixD2F5_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x6000006, &ixD2F5_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F5_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F5_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD2F5_SECONDARY_STATUS", REG_SMC, 0x6000007, &ixD2F5_SECONDARY_STATUS[0], sizeof(ixD2F5_SECONDARY_STATUS)/sizeof(ixD2F5_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD2F5_IO_BASE_LIMIT", REG_SMC, 0x6000007, &ixD2F5_IO_BASE_LIMIT[0], sizeof(ixD2F5_IO_BASE_LIMIT)/sizeof(ixD2F5_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F5_MEM_BASE_LIMIT", REG_SMC, 0x6000008, &ixD2F5_MEM_BASE_LIMIT[0], sizeof(ixD2F5_MEM_BASE_LIMIT)/sizeof(ixD2F5_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F5_PREF_BASE_LIMIT", REG_SMC, 0x6000009, &ixD2F5_PREF_BASE_LIMIT[0], sizeof(ixD2F5_PREF_BASE_LIMIT)/sizeof(ixD2F5_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD2F5_PREF_BASE_UPPER", REG_SMC, 0x600000a, &ixD2F5_PREF_BASE_UPPER[0], sizeof(ixD2F5_PREF_BASE_UPPER)/sizeof(ixD2F5_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD2F5_PREF_LIMIT_UPPER", REG_SMC, 0x600000b, &ixD2F5_PREF_LIMIT_UPPER[0], sizeof(ixD2F5_PREF_LIMIT_UPPER)/sizeof(ixD2F5_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD2F5_IO_BASE_LIMIT_HI", REG_SMC, 0x600000c, &ixD2F5_IO_BASE_LIMIT_HI[0], sizeof(ixD2F5_IO_BASE_LIMIT_HI)/sizeof(ixD2F5_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD2F5_CAP_PTR", REG_SMC, 0x600000d, &ixD2F5_CAP_PTR[0], sizeof(ixD2F5_CAP_PTR)/sizeof(ixD2F5_CAP_PTR[0]), 0, 0 }, + { "ixD2F5_IRQ_BRIDGE_CNTL", REG_SMC, 0x600000f, &ixD2F5_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F5_IRQ_BRIDGE_CNTL)/sizeof(ixD2F5_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F5_INTERRUPT_LINE", REG_SMC, 0x600000f, &ixD2F5_INTERRUPT_LINE[0], sizeof(ixD2F5_INTERRUPT_LINE)/sizeof(ixD2F5_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD2F5_INTERRUPT_PIN", REG_SMC, 0x600000f, &ixD2F5_INTERRUPT_PIN[0], sizeof(ixD2F5_INTERRUPT_PIN)/sizeof(ixD2F5_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD2F5_EXT_BRIDGE_CNTL", REG_SMC, 0x6000010, &ixD2F5_EXT_BRIDGE_CNTL[0], sizeof(ixD2F5_EXT_BRIDGE_CNTL)/sizeof(ixD2F5_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD2F5_PMI_CAP_LIST", REG_SMC, 0x6000014, &ixD2F5_PMI_CAP_LIST[0], sizeof(ixD2F5_PMI_CAP_LIST)/sizeof(ixD2F5_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PMI_CAP", REG_SMC, 0x6000014, &ixD2F5_PMI_CAP[0], sizeof(ixD2F5_PMI_CAP)/sizeof(ixD2F5_PMI_CAP[0]), 0, 0 }, + { "ixD2F5_PMI_STATUS_CNTL", REG_SMC, 0x6000015, &ixD2F5_PMI_STATUS_CNTL[0], sizeof(ixD2F5_PMI_STATUS_CNTL)/sizeof(ixD2F5_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_CAP_LIST", REG_SMC, 0x6000016, &ixD2F5_PCIE_CAP_LIST[0], sizeof(ixD2F5_PCIE_CAP_LIST)/sizeof(ixD2F5_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_CAP", REG_SMC, 0x6000016, &ixD2F5_PCIE_CAP[0], sizeof(ixD2F5_PCIE_CAP)/sizeof(ixD2F5_PCIE_CAP[0]), 0, 0 }, + { "ixD2F5_DEVICE_CAP", REG_SMC, 0x6000017, &ixD2F5_DEVICE_CAP[0], sizeof(ixD2F5_DEVICE_CAP)/sizeof(ixD2F5_DEVICE_CAP[0]), 0, 0 }, + { "ixD2F5_DEVICE_STATUS", REG_SMC, 0x6000018, &ixD2F5_DEVICE_STATUS[0], sizeof(ixD2F5_DEVICE_STATUS)/sizeof(ixD2F5_DEVICE_STATUS[0]), 0, 0 }, + { "ixD2F5_DEVICE_CNTL", REG_SMC, 0x6000018, &ixD2F5_DEVICE_CNTL[0], sizeof(ixD2F5_DEVICE_CNTL)/sizeof(ixD2F5_DEVICE_CNTL[0]), 0, 0 }, + { "ixD2F5_LINK_CAP", REG_SMC, 0x6000019, &ixD2F5_LINK_CAP[0], sizeof(ixD2F5_LINK_CAP)/sizeof(ixD2F5_LINK_CAP[0]), 0, 0 }, + { "ixD2F5_LINK_STATUS", REG_SMC, 0x600001a, &ixD2F5_LINK_STATUS[0], sizeof(ixD2F5_LINK_STATUS)/sizeof(ixD2F5_LINK_STATUS[0]), 0, 0 }, + { "ixD2F5_LINK_CNTL", REG_SMC, 0x600001a, &ixD2F5_LINK_CNTL[0], sizeof(ixD2F5_LINK_CNTL)/sizeof(ixD2F5_LINK_CNTL[0]), 0, 0 }, + { "ixD2F5_SLOT_CAP", REG_SMC, 0x600001b, &ixD2F5_SLOT_CAP[0], sizeof(ixD2F5_SLOT_CAP)/sizeof(ixD2F5_SLOT_CAP[0]), 0, 0 }, + { "ixD2F5_SLOT_STATUS", REG_SMC, 0x600001c, &ixD2F5_SLOT_STATUS[0], sizeof(ixD2F5_SLOT_STATUS)/sizeof(ixD2F5_SLOT_STATUS[0]), 0, 0 }, + { "ixD2F5_SLOT_CNTL", REG_SMC, 0x600001c, &ixD2F5_SLOT_CNTL[0], sizeof(ixD2F5_SLOT_CNTL)/sizeof(ixD2F5_SLOT_CNTL[0]), 0, 0 }, + { "ixD2F5_ROOT_CNTL", REG_SMC, 0x600001d, &ixD2F5_ROOT_CNTL[0], sizeof(ixD2F5_ROOT_CNTL)/sizeof(ixD2F5_ROOT_CNTL[0]), 0, 0 }, + { "ixD2F5_ROOT_CAP", REG_SMC, 0x600001d, &ixD2F5_ROOT_CAP[0], sizeof(ixD2F5_ROOT_CAP)/sizeof(ixD2F5_ROOT_CAP[0]), 0, 0 }, + { "ixD2F5_ROOT_STATUS", REG_SMC, 0x600001e, &ixD2F5_ROOT_STATUS[0], sizeof(ixD2F5_ROOT_STATUS)/sizeof(ixD2F5_ROOT_STATUS[0]), 0, 0 }, + { "ixD2F5_DEVICE_CAP2", REG_SMC, 0x600001f, &ixD2F5_DEVICE_CAP2[0], sizeof(ixD2F5_DEVICE_CAP2)/sizeof(ixD2F5_DEVICE_CAP2[0]), 0, 0 }, + { "ixD2F5_DEVICE_STATUS2", REG_SMC, 0x6000020, &ixD2F5_DEVICE_STATUS2[0], sizeof(ixD2F5_DEVICE_STATUS2)/sizeof(ixD2F5_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD2F5_DEVICE_CNTL2", REG_SMC, 0x6000020, &ixD2F5_DEVICE_CNTL2[0], sizeof(ixD2F5_DEVICE_CNTL2)/sizeof(ixD2F5_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD2F5_LINK_CAP2", REG_SMC, 0x6000021, &ixD2F5_LINK_CAP2[0], sizeof(ixD2F5_LINK_CAP2)/sizeof(ixD2F5_LINK_CAP2[0]), 0, 0 }, + { "ixD2F5_LINK_STATUS2", REG_SMC, 0x6000022, &ixD2F5_LINK_STATUS2[0], sizeof(ixD2F5_LINK_STATUS2)/sizeof(ixD2F5_LINK_STATUS2[0]), 0, 0 }, + { "ixD2F5_LINK_CNTL2", REG_SMC, 0x6000022, &ixD2F5_LINK_CNTL2[0], sizeof(ixD2F5_LINK_CNTL2)/sizeof(ixD2F5_LINK_CNTL2[0]), 0, 0 }, + { "ixD2F5_SLOT_CAP2", REG_SMC, 0x6000023, &ixD2F5_SLOT_CAP2[0], sizeof(ixD2F5_SLOT_CAP2)/sizeof(ixD2F5_SLOT_CAP2[0]), 0, 0 }, + { "ixD2F5_SLOT_STATUS2", REG_SMC, 0x6000024, &ixD2F5_SLOT_STATUS2[0], sizeof(ixD2F5_SLOT_STATUS2)/sizeof(ixD2F5_SLOT_STATUS2[0]), 0, 0 }, + { "ixD2F5_SLOT_CNTL2", REG_SMC, 0x6000024, &ixD2F5_SLOT_CNTL2[0], sizeof(ixD2F5_SLOT_CNTL2)/sizeof(ixD2F5_SLOT_CNTL2[0]), 0, 0 }, + { "ixD2F5_MSI_CAP_LIST", REG_SMC, 0x6000028, &ixD2F5_MSI_CAP_LIST[0], sizeof(ixD2F5_MSI_CAP_LIST)/sizeof(ixD2F5_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_MSI_MSG_ADDR_LO", REG_SMC, 0x6000029, &ixD2F5_MSI_MSG_ADDR_LO[0], sizeof(ixD2F5_MSI_MSG_ADDR_LO)/sizeof(ixD2F5_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD2F5_MSI_MSG_ADDR_HI", REG_SMC, 0x600002a, &ixD2F5_MSI_MSG_ADDR_HI[0], sizeof(ixD2F5_MSI_MSG_ADDR_HI)/sizeof(ixD2F5_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD2F5_MSI_MSG_DATA", REG_SMC, 0x600002a, &ixD2F5_MSI_MSG_DATA[0], sizeof(ixD2F5_MSI_MSG_DATA)/sizeof(ixD2F5_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD2F5_MSI_MSG_DATA_64", REG_SMC, 0x600002b, &ixD2F5_MSI_MSG_DATA_64[0], sizeof(ixD2F5_MSI_MSG_DATA_64)/sizeof(ixD2F5_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD2F5_SSID_CAP_LIST", REG_SMC, 0x6000030, &ixD2F5_SSID_CAP_LIST[0], sizeof(ixD2F5_SSID_CAP_LIST)/sizeof(ixD2F5_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_SSID_CAP", REG_SMC, 0x6000031, &ixD2F5_SSID_CAP[0], sizeof(ixD2F5_SSID_CAP)/sizeof(ixD2F5_SSID_CAP[0]), 0, 0 }, + { "ixD2F5_MSI_MAP_CAP_LIST", REG_SMC, 0x6000032, &ixD2F5_MSI_MAP_CAP_LIST[0], sizeof(ixD2F5_MSI_MAP_CAP_LIST)/sizeof(ixD2F5_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_MSI_MAP_CAP", REG_SMC, 0x6000032, &ixD2F5_MSI_MAP_CAP[0], sizeof(ixD2F5_MSI_MAP_CAP)/sizeof(ixD2F5_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD2F5_MSI_MAP_ADDR_LO", REG_SMC, 0x6000033, &ixD2F5_MSI_MAP_ADDR_LO[0], sizeof(ixD2F5_MSI_MAP_ADDR_LO)/sizeof(ixD2F5_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD2F5_MSI_MAP_ADDR_HI", REG_SMC, 0x6000034, &ixD2F5_MSI_MAP_ADDR_HI[0], sizeof(ixD2F5_MSI_MAP_ADDR_HI)/sizeof(ixD2F5_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_INDEX", REG_SMC, 0x6000038, &ixD2F5_PCIE_PORT_INDEX[0], sizeof(ixD2F5_PCIE_PORT_INDEX)/sizeof(ixD2F5_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_DATA", REG_SMC, 0x6000039, &ixD2F5_PCIE_PORT_DATA[0], sizeof(ixD2F5_PCIE_PORT_DATA)/sizeof(ixD2F5_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x6000040, &ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x6000041, &ixD2F5_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD2F5_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x6000042, &ixD2F5_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD2F5_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x6000043, &ixD2F5_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD2F5_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x6000044, &ixD2F5_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x6000045, &ixD2F5_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x6000046, &ixD2F5_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_VC_STATUS", REG_SMC, 0x6000047, &ixD2F5_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F5_PCIE_PORT_VC_STATUS)/sizeof(ixD2F5_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_PORT_VC_CNTL", REG_SMC, 0x6000047, &ixD2F5_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F5_PCIE_PORT_VC_CNTL)/sizeof(ixD2F5_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x6000048, &ixD2F5_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F5_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x6000049, &ixD2F5_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x600004a, &ixD2F5_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x600004b, &ixD2F5_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD2F5_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x600004c, &ixD2F5_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x600004d, &ixD2F5_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x6000050, &ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x6000051, &ixD2F5_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD2F5_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x6000052, &ixD2F5_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x6000054, &ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x6000055, &ixD2F5_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F5_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x6000056, &ixD2F5_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F5_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F5_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x6000057, &ixD2F5_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F5_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD2F5_PCIE_CORR_ERR_STATUS", REG_SMC, 0x6000058, &ixD2F5_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F5_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F5_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_CORR_ERR_MASK", REG_SMC, 0x6000059, &ixD2F5_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F5_PCIE_CORR_ERR_MASK)/sizeof(ixD2F5_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD2F5_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x600005a, &ixD2F5_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F5_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F5_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_HDR_LOG0", REG_SMC, 0x600005b, &ixD2F5_PCIE_HDR_LOG0[0], sizeof(ixD2F5_PCIE_HDR_LOG0)/sizeof(ixD2F5_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD2F5_PCIE_HDR_LOG1", REG_SMC, 0x600005c, &ixD2F5_PCIE_HDR_LOG1[0], sizeof(ixD2F5_PCIE_HDR_LOG1)/sizeof(ixD2F5_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD2F5_PCIE_HDR_LOG2", REG_SMC, 0x600005d, &ixD2F5_PCIE_HDR_LOG2[0], sizeof(ixD2F5_PCIE_HDR_LOG2)/sizeof(ixD2F5_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD2F5_PCIE_HDR_LOG3", REG_SMC, 0x600005e, &ixD2F5_PCIE_HDR_LOG3[0], sizeof(ixD2F5_PCIE_HDR_LOG3)/sizeof(ixD2F5_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD2F5_PCIE_ROOT_ERR_CMD", REG_SMC, 0x600005f, &ixD2F5_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F5_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F5_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD2F5_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x6000060, &ixD2F5_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F5_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F5_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_ERR_SRC_ID", REG_SMC, 0x6000061, &ixD2F5_PCIE_ERR_SRC_ID[0], sizeof(ixD2F5_PCIE_ERR_SRC_ID)/sizeof(ixD2F5_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD2F5_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x6000062, &ixD2F5_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F5_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x6000063, &ixD2F5_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD2F5_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x6000064, &ixD2F5_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD2F5_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x6000065, &ixD2F5_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x600009c, &ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_LINK_CNTL3", REG_SMC, 0x600009d, &ixD2F5_PCIE_LINK_CNTL3[0], sizeof(ixD2F5_PCIE_LINK_CNTL3)/sizeof(ixD2F5_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x600009e, &ixD2F5_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F5_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F5_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x600009f, &ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x60000a0, &ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x60000a1, &ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x60000a2, &ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x60000a3, &ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x60000a4, &ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x60000a5, &ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x60000a6, &ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x60000a8, &ixD2F5_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_ACS_CNTL", REG_SMC, 0x60000a9, &ixD2F5_PCIE_ACS_CNTL[0], sizeof(ixD2F5_PCIE_ACS_CNTL)/sizeof(ixD2F5_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_ACS_CAP", REG_SMC, 0x60000a9, &ixD2F5_PCIE_ACS_CAP[0], sizeof(ixD2F5_PCIE_ACS_CAP)/sizeof(ixD2F5_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x60000bc, &ixD2F5_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_CNTL", REG_SMC, 0x60000bd, &ixD2F5_PCIE_MC_CNTL[0], sizeof(ixD2F5_PCIE_MC_CNTL)/sizeof(ixD2F5_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_CAP", REG_SMC, 0x60000bd, &ixD2F5_PCIE_MC_CAP[0], sizeof(ixD2F5_PCIE_MC_CAP)/sizeof(ixD2F5_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_ADDR0", REG_SMC, 0x60000be, &ixD2F5_PCIE_MC_ADDR0[0], sizeof(ixD2F5_PCIE_MC_ADDR0)/sizeof(ixD2F5_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_ADDR1", REG_SMC, 0x60000bf, &ixD2F5_PCIE_MC_ADDR1[0], sizeof(ixD2F5_PCIE_MC_ADDR1)/sizeof(ixD2F5_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_RCV0", REG_SMC, 0x60000c0, &ixD2F5_PCIE_MC_RCV0[0], sizeof(ixD2F5_PCIE_MC_RCV0)/sizeof(ixD2F5_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_RCV1", REG_SMC, 0x60000c1, &ixD2F5_PCIE_MC_RCV1[0], sizeof(ixD2F5_PCIE_MC_RCV1)/sizeof(ixD2F5_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x60000c2, &ixD2F5_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F5_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F5_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x60000c3, &ixD2F5_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F5_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F5_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x60000c4, &ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x60000c5, &ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x60000c6, &ixD2F5_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD2F5_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x60000c7, &ixD2F5_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "ixD2F1_PCIE_FC_NP", REG_SMC, 0x61, &ixD2F1_PCIE_FC_NP[0], sizeof(ixD2F1_PCIE_FC_NP)/sizeof(ixD2F1_PCIE_FC_NP[0]), 0, 0 }, + { "mmPCIE_TLP_PREFIX_LOG0", REG_MMIO, 0x62, &mmPCIE_TLP_PREFIX_LOG0[0], sizeof(mmPCIE_TLP_PREFIX_LOG0)/sizeof(mmPCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD2F1_PCIE_FC_CPL", REG_SMC, 0x62, &ixD2F1_PCIE_FC_CPL[0], sizeof(ixD2F1_PCIE_FC_CPL)/sizeof(ixD2F1_PCIE_FC_CPL[0]), 0, 0 }, + { "mmPCIE_TLP_PREFIX_LOG1", REG_MMIO, 0x63, &mmPCIE_TLP_PREFIX_LOG1[0], sizeof(mmPCIE_TLP_PREFIX_LOG1)/sizeof(mmPCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "mmPCIE_TLP_PREFIX_LOG2", REG_MMIO, 0x64, &mmPCIE_TLP_PREFIX_LOG2[0], sizeof(mmPCIE_TLP_PREFIX_LOG2)/sizeof(mmPCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "mmPCIE_TLP_PREFIX_LOG3", REG_MMIO, 0x65, &mmPCIE_TLP_PREFIX_LOG3[0], sizeof(mmPCIE_TLP_PREFIX_LOG3)/sizeof(mmPCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD2F1_PCIE_ERR_CNTL", REG_SMC, 0x6a, &ixD2F1_PCIE_ERR_CNTL[0], sizeof(ixD2F1_PCIE_ERR_CNTL)/sizeof(ixD2F1_PCIE_ERR_CNTL[0]), 0, 0 }, + { "mmBASE_ADDR_4", REG_MMIO, 0x7, &mmBASE_ADDR_4[0], sizeof(mmBASE_ADDR_4)/sizeof(mmBASE_ADDR_4[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_CNTL", REG_SMC, 0x70, &ixD2F1_PCIE_RX_CNTL[0], sizeof(ixD2F1_PCIE_RX_CNTL)/sizeof(ixD2F1_PCIE_RX_CNTL[0]), 0, 0 }, + { "ixD3F1_VENDOR_ID", REG_SMC, 0x7000000, &ixD3F1_VENDOR_ID[0], sizeof(ixD3F1_VENDOR_ID)/sizeof(ixD3F1_VENDOR_ID[0]), 0, 0 }, + { "ixD3F1_COMMAND", REG_SMC, 0x7000001, &ixD3F1_COMMAND[0], sizeof(ixD3F1_COMMAND)/sizeof(ixD3F1_COMMAND[0]), 0, 0 }, + { "ixD3F1_STATUS", REG_SMC, 0x7000001, &ixD3F1_STATUS[0], sizeof(ixD3F1_STATUS)/sizeof(ixD3F1_STATUS[0]), 0, 0 }, + { "ixD3F1_PROG_INTERFACE", REG_SMC, 0x7000002, &ixD3F1_PROG_INTERFACE[0], sizeof(ixD3F1_PROG_INTERFACE)/sizeof(ixD3F1_PROG_INTERFACE[0]), 0, 0 }, + { "ixD3F1_REVISION_ID", REG_SMC, 0x7000002, &ixD3F1_REVISION_ID[0], sizeof(ixD3F1_REVISION_ID)/sizeof(ixD3F1_REVISION_ID[0]), 0, 0 }, + { "ixD3F1_BASE_CLASS", REG_SMC, 0x7000002, &ixD3F1_BASE_CLASS[0], sizeof(ixD3F1_BASE_CLASS)/sizeof(ixD3F1_BASE_CLASS[0]), 0, 0 }, + { "ixD3F1_SUB_CLASS", REG_SMC, 0x7000002, &ixD3F1_SUB_CLASS[0], sizeof(ixD3F1_SUB_CLASS)/sizeof(ixD3F1_SUB_CLASS[0]), 0, 0 }, + { "ixD3F1_CACHE_LINE", REG_SMC, 0x7000003, &ixD3F1_CACHE_LINE[0], sizeof(ixD3F1_CACHE_LINE)/sizeof(ixD3F1_CACHE_LINE[0]), 0, 0 }, + { "ixD3F1_LATENCY", REG_SMC, 0x7000003, &ixD3F1_LATENCY[0], sizeof(ixD3F1_LATENCY)/sizeof(ixD3F1_LATENCY[0]), 0, 0 }, + { "ixD3F1_HEADER", REG_SMC, 0x7000003, &ixD3F1_HEADER[0], sizeof(ixD3F1_HEADER)/sizeof(ixD3F1_HEADER[0]), 0, 0 }, + { "ixD3F1_BIST", REG_SMC, 0x7000003, &ixD3F1_BIST[0], sizeof(ixD3F1_BIST)/sizeof(ixD3F1_BIST[0]), 0, 0 }, + { "ixD3F1_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x7000006, &ixD3F1_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F1_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F1_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD3F1_SECONDARY_STATUS", REG_SMC, 0x7000007, &ixD3F1_SECONDARY_STATUS[0], sizeof(ixD3F1_SECONDARY_STATUS)/sizeof(ixD3F1_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD3F1_IO_BASE_LIMIT", REG_SMC, 0x7000007, &ixD3F1_IO_BASE_LIMIT[0], sizeof(ixD3F1_IO_BASE_LIMIT)/sizeof(ixD3F1_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F1_MEM_BASE_LIMIT", REG_SMC, 0x7000008, &ixD3F1_MEM_BASE_LIMIT[0], sizeof(ixD3F1_MEM_BASE_LIMIT)/sizeof(ixD3F1_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F1_PREF_BASE_LIMIT", REG_SMC, 0x7000009, &ixD3F1_PREF_BASE_LIMIT[0], sizeof(ixD3F1_PREF_BASE_LIMIT)/sizeof(ixD3F1_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F1_PREF_BASE_UPPER", REG_SMC, 0x700000a, &ixD3F1_PREF_BASE_UPPER[0], sizeof(ixD3F1_PREF_BASE_UPPER)/sizeof(ixD3F1_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD3F1_PREF_LIMIT_UPPER", REG_SMC, 0x700000b, &ixD3F1_PREF_LIMIT_UPPER[0], sizeof(ixD3F1_PREF_LIMIT_UPPER)/sizeof(ixD3F1_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD3F1_IO_BASE_LIMIT_HI", REG_SMC, 0x700000c, &ixD3F1_IO_BASE_LIMIT_HI[0], sizeof(ixD3F1_IO_BASE_LIMIT_HI)/sizeof(ixD3F1_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD3F1_CAP_PTR", REG_SMC, 0x700000d, &ixD3F1_CAP_PTR[0], sizeof(ixD3F1_CAP_PTR)/sizeof(ixD3F1_CAP_PTR[0]), 0, 0 }, + { "ixD3F1_IRQ_BRIDGE_CNTL", REG_SMC, 0x700000f, &ixD3F1_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F1_IRQ_BRIDGE_CNTL)/sizeof(ixD3F1_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F1_INTERRUPT_LINE", REG_SMC, 0x700000f, &ixD3F1_INTERRUPT_LINE[0], sizeof(ixD3F1_INTERRUPT_LINE)/sizeof(ixD3F1_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD3F1_INTERRUPT_PIN", REG_SMC, 0x700000f, &ixD3F1_INTERRUPT_PIN[0], sizeof(ixD3F1_INTERRUPT_PIN)/sizeof(ixD3F1_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD3F1_EXT_BRIDGE_CNTL", REG_SMC, 0x7000010, &ixD3F1_EXT_BRIDGE_CNTL[0], sizeof(ixD3F1_EXT_BRIDGE_CNTL)/sizeof(ixD3F1_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F1_PMI_CAP_LIST", REG_SMC, 0x7000014, &ixD3F1_PMI_CAP_LIST[0], sizeof(ixD3F1_PMI_CAP_LIST)/sizeof(ixD3F1_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PMI_CAP", REG_SMC, 0x7000014, &ixD3F1_PMI_CAP[0], sizeof(ixD3F1_PMI_CAP)/sizeof(ixD3F1_PMI_CAP[0]), 0, 0 }, + { "ixD3F1_PMI_STATUS_CNTL", REG_SMC, 0x7000015, &ixD3F1_PMI_STATUS_CNTL[0], sizeof(ixD3F1_PMI_STATUS_CNTL)/sizeof(ixD3F1_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_CAP_LIST", REG_SMC, 0x7000016, &ixD3F1_PCIE_CAP_LIST[0], sizeof(ixD3F1_PCIE_CAP_LIST)/sizeof(ixD3F1_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_CAP", REG_SMC, 0x7000016, &ixD3F1_PCIE_CAP[0], sizeof(ixD3F1_PCIE_CAP)/sizeof(ixD3F1_PCIE_CAP[0]), 0, 0 }, + { "ixD3F1_DEVICE_CAP", REG_SMC, 0x7000017, &ixD3F1_DEVICE_CAP[0], sizeof(ixD3F1_DEVICE_CAP)/sizeof(ixD3F1_DEVICE_CAP[0]), 0, 0 }, + { "ixD3F1_DEVICE_STATUS", REG_SMC, 0x7000018, &ixD3F1_DEVICE_STATUS[0], sizeof(ixD3F1_DEVICE_STATUS)/sizeof(ixD3F1_DEVICE_STATUS[0]), 0, 0 }, + { "ixD3F1_DEVICE_CNTL", REG_SMC, 0x7000018, &ixD3F1_DEVICE_CNTL[0], sizeof(ixD3F1_DEVICE_CNTL)/sizeof(ixD3F1_DEVICE_CNTL[0]), 0, 0 }, + { "ixD3F1_LINK_CAP", REG_SMC, 0x7000019, &ixD3F1_LINK_CAP[0], sizeof(ixD3F1_LINK_CAP)/sizeof(ixD3F1_LINK_CAP[0]), 0, 0 }, + { "ixD3F1_LINK_STATUS", REG_SMC, 0x700001a, &ixD3F1_LINK_STATUS[0], sizeof(ixD3F1_LINK_STATUS)/sizeof(ixD3F1_LINK_STATUS[0]), 0, 0 }, + { "ixD3F1_LINK_CNTL", REG_SMC, 0x700001a, &ixD3F1_LINK_CNTL[0], sizeof(ixD3F1_LINK_CNTL)/sizeof(ixD3F1_LINK_CNTL[0]), 0, 0 }, + { "ixD3F1_SLOT_CAP", REG_SMC, 0x700001b, &ixD3F1_SLOT_CAP[0], sizeof(ixD3F1_SLOT_CAP)/sizeof(ixD3F1_SLOT_CAP[0]), 0, 0 }, + { "ixD3F1_SLOT_STATUS", REG_SMC, 0x700001c, &ixD3F1_SLOT_STATUS[0], sizeof(ixD3F1_SLOT_STATUS)/sizeof(ixD3F1_SLOT_STATUS[0]), 0, 0 }, + { "ixD3F1_SLOT_CNTL", REG_SMC, 0x700001c, &ixD3F1_SLOT_CNTL[0], sizeof(ixD3F1_SLOT_CNTL)/sizeof(ixD3F1_SLOT_CNTL[0]), 0, 0 }, + { "ixD3F1_ROOT_CNTL", REG_SMC, 0x700001d, &ixD3F1_ROOT_CNTL[0], sizeof(ixD3F1_ROOT_CNTL)/sizeof(ixD3F1_ROOT_CNTL[0]), 0, 0 }, + { "ixD3F1_ROOT_CAP", REG_SMC, 0x700001d, &ixD3F1_ROOT_CAP[0], sizeof(ixD3F1_ROOT_CAP)/sizeof(ixD3F1_ROOT_CAP[0]), 0, 0 }, + { "ixD3F1_ROOT_STATUS", REG_SMC, 0x700001e, &ixD3F1_ROOT_STATUS[0], sizeof(ixD3F1_ROOT_STATUS)/sizeof(ixD3F1_ROOT_STATUS[0]), 0, 0 }, + { "ixD3F1_DEVICE_CAP2", REG_SMC, 0x700001f, &ixD3F1_DEVICE_CAP2[0], sizeof(ixD3F1_DEVICE_CAP2)/sizeof(ixD3F1_DEVICE_CAP2[0]), 0, 0 }, + { "ixD3F1_DEVICE_STATUS2", REG_SMC, 0x7000020, &ixD3F1_DEVICE_STATUS2[0], sizeof(ixD3F1_DEVICE_STATUS2)/sizeof(ixD3F1_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD3F1_DEVICE_CNTL2", REG_SMC, 0x7000020, &ixD3F1_DEVICE_CNTL2[0], sizeof(ixD3F1_DEVICE_CNTL2)/sizeof(ixD3F1_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD3F1_LINK_CAP2", REG_SMC, 0x7000021, &ixD3F1_LINK_CAP2[0], sizeof(ixD3F1_LINK_CAP2)/sizeof(ixD3F1_LINK_CAP2[0]), 0, 0 }, + { "ixD3F1_LINK_STATUS2", REG_SMC, 0x7000022, &ixD3F1_LINK_STATUS2[0], sizeof(ixD3F1_LINK_STATUS2)/sizeof(ixD3F1_LINK_STATUS2[0]), 0, 0 }, + { "ixD3F1_LINK_CNTL2", REG_SMC, 0x7000022, &ixD3F1_LINK_CNTL2[0], sizeof(ixD3F1_LINK_CNTL2)/sizeof(ixD3F1_LINK_CNTL2[0]), 0, 0 }, + { "ixD3F1_SLOT_CAP2", REG_SMC, 0x7000023, &ixD3F1_SLOT_CAP2[0], sizeof(ixD3F1_SLOT_CAP2)/sizeof(ixD3F1_SLOT_CAP2[0]), 0, 0 }, + { "ixD3F1_SLOT_STATUS2", REG_SMC, 0x7000024, &ixD3F1_SLOT_STATUS2[0], sizeof(ixD3F1_SLOT_STATUS2)/sizeof(ixD3F1_SLOT_STATUS2[0]), 0, 0 }, + { "ixD3F1_SLOT_CNTL2", REG_SMC, 0x7000024, &ixD3F1_SLOT_CNTL2[0], sizeof(ixD3F1_SLOT_CNTL2)/sizeof(ixD3F1_SLOT_CNTL2[0]), 0, 0 }, + { "ixD3F1_MSI_CAP_LIST", REG_SMC, 0x7000028, &ixD3F1_MSI_CAP_LIST[0], sizeof(ixD3F1_MSI_CAP_LIST)/sizeof(ixD3F1_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_MSI_MSG_ADDR_LO", REG_SMC, 0x7000029, &ixD3F1_MSI_MSG_ADDR_LO[0], sizeof(ixD3F1_MSI_MSG_ADDR_LO)/sizeof(ixD3F1_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD3F1_MSI_MSG_ADDR_HI", REG_SMC, 0x700002a, &ixD3F1_MSI_MSG_ADDR_HI[0], sizeof(ixD3F1_MSI_MSG_ADDR_HI)/sizeof(ixD3F1_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD3F1_MSI_MSG_DATA", REG_SMC, 0x700002a, &ixD3F1_MSI_MSG_DATA[0], sizeof(ixD3F1_MSI_MSG_DATA)/sizeof(ixD3F1_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD3F1_MSI_MSG_DATA_64", REG_SMC, 0x700002b, &ixD3F1_MSI_MSG_DATA_64[0], sizeof(ixD3F1_MSI_MSG_DATA_64)/sizeof(ixD3F1_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD3F1_SSID_CAP_LIST", REG_SMC, 0x7000030, &ixD3F1_SSID_CAP_LIST[0], sizeof(ixD3F1_SSID_CAP_LIST)/sizeof(ixD3F1_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_SSID_CAP", REG_SMC, 0x7000031, &ixD3F1_SSID_CAP[0], sizeof(ixD3F1_SSID_CAP)/sizeof(ixD3F1_SSID_CAP[0]), 0, 0 }, + { "ixD3F1_MSI_MAP_CAP_LIST", REG_SMC, 0x7000032, &ixD3F1_MSI_MAP_CAP_LIST[0], sizeof(ixD3F1_MSI_MAP_CAP_LIST)/sizeof(ixD3F1_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_MSI_MAP_CAP", REG_SMC, 0x7000032, &ixD3F1_MSI_MAP_CAP[0], sizeof(ixD3F1_MSI_MAP_CAP)/sizeof(ixD3F1_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD3F1_MSI_MAP_ADDR_LO", REG_SMC, 0x7000033, &ixD3F1_MSI_MAP_ADDR_LO[0], sizeof(ixD3F1_MSI_MAP_ADDR_LO)/sizeof(ixD3F1_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD3F1_MSI_MAP_ADDR_HI", REG_SMC, 0x7000034, &ixD3F1_MSI_MAP_ADDR_HI[0], sizeof(ixD3F1_MSI_MAP_ADDR_HI)/sizeof(ixD3F1_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_INDEX", REG_SMC, 0x7000038, &ixD3F1_PCIE_PORT_INDEX[0], sizeof(ixD3F1_PCIE_PORT_INDEX)/sizeof(ixD3F1_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_DATA", REG_SMC, 0x7000039, &ixD3F1_PCIE_PORT_DATA[0], sizeof(ixD3F1_PCIE_PORT_DATA)/sizeof(ixD3F1_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x7000040, &ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x7000041, &ixD3F1_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD3F1_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x7000042, &ixD3F1_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD3F1_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x7000043, &ixD3F1_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD3F1_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x7000044, &ixD3F1_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x7000045, &ixD3F1_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x7000046, &ixD3F1_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_VC_STATUS", REG_SMC, 0x7000047, &ixD3F1_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F1_PCIE_PORT_VC_STATUS)/sizeof(ixD3F1_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_PORT_VC_CNTL", REG_SMC, 0x7000047, &ixD3F1_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F1_PCIE_PORT_VC_CNTL)/sizeof(ixD3F1_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x7000048, &ixD3F1_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F1_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x7000049, &ixD3F1_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x700004a, &ixD3F1_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x700004b, &ixD3F1_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F1_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x700004c, &ixD3F1_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x700004d, &ixD3F1_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x7000050, &ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x7000051, &ixD3F1_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD3F1_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x7000052, &ixD3F1_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x7000054, &ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x7000055, &ixD3F1_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F1_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x7000056, &ixD3F1_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F1_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F1_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x7000057, &ixD3F1_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F1_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD3F1_PCIE_CORR_ERR_STATUS", REG_SMC, 0x7000058, &ixD3F1_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F1_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F1_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_CORR_ERR_MASK", REG_SMC, 0x7000059, &ixD3F1_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F1_PCIE_CORR_ERR_MASK)/sizeof(ixD3F1_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F1_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x700005a, &ixD3F1_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F1_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F1_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_HDR_LOG0", REG_SMC, 0x700005b, &ixD3F1_PCIE_HDR_LOG0[0], sizeof(ixD3F1_PCIE_HDR_LOG0)/sizeof(ixD3F1_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD3F1_PCIE_HDR_LOG1", REG_SMC, 0x700005c, &ixD3F1_PCIE_HDR_LOG1[0], sizeof(ixD3F1_PCIE_HDR_LOG1)/sizeof(ixD3F1_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD3F1_PCIE_HDR_LOG2", REG_SMC, 0x700005d, &ixD3F1_PCIE_HDR_LOG2[0], sizeof(ixD3F1_PCIE_HDR_LOG2)/sizeof(ixD3F1_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD3F1_PCIE_HDR_LOG3", REG_SMC, 0x700005e, &ixD3F1_PCIE_HDR_LOG3[0], sizeof(ixD3F1_PCIE_HDR_LOG3)/sizeof(ixD3F1_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD3F1_PCIE_ROOT_ERR_CMD", REG_SMC, 0x700005f, &ixD3F1_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F1_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F1_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD3F1_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x7000060, &ixD3F1_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F1_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F1_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_ERR_SRC_ID", REG_SMC, 0x7000061, &ixD3F1_PCIE_ERR_SRC_ID[0], sizeof(ixD3F1_PCIE_ERR_SRC_ID)/sizeof(ixD3F1_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD3F1_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x7000062, &ixD3F1_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD3F1_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x7000063, &ixD3F1_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD3F1_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x7000064, &ixD3F1_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD3F1_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x7000065, &ixD3F1_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x700009c, &ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_LINK_CNTL3", REG_SMC, 0x700009d, &ixD3F1_PCIE_LINK_CNTL3[0], sizeof(ixD3F1_PCIE_LINK_CNTL3)/sizeof(ixD3F1_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x700009e, &ixD3F1_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F1_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F1_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x700009f, &ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x70000a0, &ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x70000a1, &ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x70000a2, &ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x70000a3, &ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x70000a4, &ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x70000a5, &ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x70000a6, &ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x70000a8, &ixD3F1_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_ACS_CNTL", REG_SMC, 0x70000a9, &ixD3F1_PCIE_ACS_CNTL[0], sizeof(ixD3F1_PCIE_ACS_CNTL)/sizeof(ixD3F1_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_ACS_CAP", REG_SMC, 0x70000a9, &ixD3F1_PCIE_ACS_CAP[0], sizeof(ixD3F1_PCIE_ACS_CAP)/sizeof(ixD3F1_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x70000bc, &ixD3F1_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_CNTL", REG_SMC, 0x70000bd, &ixD3F1_PCIE_MC_CNTL[0], sizeof(ixD3F1_PCIE_MC_CNTL)/sizeof(ixD3F1_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_CAP", REG_SMC, 0x70000bd, &ixD3F1_PCIE_MC_CAP[0], sizeof(ixD3F1_PCIE_MC_CAP)/sizeof(ixD3F1_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_ADDR0", REG_SMC, 0x70000be, &ixD3F1_PCIE_MC_ADDR0[0], sizeof(ixD3F1_PCIE_MC_ADDR0)/sizeof(ixD3F1_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_ADDR1", REG_SMC, 0x70000bf, &ixD3F1_PCIE_MC_ADDR1[0], sizeof(ixD3F1_PCIE_MC_ADDR1)/sizeof(ixD3F1_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_RCV0", REG_SMC, 0x70000c0, &ixD3F1_PCIE_MC_RCV0[0], sizeof(ixD3F1_PCIE_MC_RCV0)/sizeof(ixD3F1_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_RCV1", REG_SMC, 0x70000c1, &ixD3F1_PCIE_MC_RCV1[0], sizeof(ixD3F1_PCIE_MC_RCV1)/sizeof(ixD3F1_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x70000c2, &ixD3F1_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F1_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F1_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x70000c3, &ixD3F1_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F1_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F1_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x70000c4, &ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x70000c5, &ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x70000c6, &ixD3F1_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD3F1_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x70000c7, &ixD3F1_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x71, &ixD2F1_PCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixD2F1_PCIE_RX_EXPECTED_SEQNUM)/sizeof(ixD2F1_PCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x72, &ixD2F1_PCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixD2F1_PCIE_RX_VENDOR_SPECIFIC)/sizeof(ixD2F1_PCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_CNTL3", REG_SMC, 0x74, &ixD2F1_PCIE_RX_CNTL3[0], sizeof(ixD2F1_PCIE_RX_CNTL3)/sizeof(ixD2F1_PCIE_RX_CNTL3[0]), 0, 0 }, + { "mmBASE_ADDR_5", REG_MMIO, 0x8, &mmBASE_ADDR_5[0], sizeof(mmBASE_ADDR_5)/sizeof(mmBASE_ADDR_5[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x80, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 }, + { "mmPCIE_BAR_ENH_CAP_LIST", REG_MMIO, 0x80, &mmPCIE_BAR_ENH_CAP_LIST[0], sizeof(mmPCIE_BAR_ENH_CAP_LIST)/sizeof(mmPCIE_BAR_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_VENDOR_ID", REG_SMC, 0x8000000, &ixD3F2_VENDOR_ID[0], sizeof(ixD3F2_VENDOR_ID)/sizeof(ixD3F2_VENDOR_ID[0]), 0, 0 }, + { "ixD3F2_COMMAND", REG_SMC, 0x8000001, &ixD3F2_COMMAND[0], sizeof(ixD3F2_COMMAND)/sizeof(ixD3F2_COMMAND[0]), 0, 0 }, + { "ixD3F2_STATUS", REG_SMC, 0x8000001, &ixD3F2_STATUS[0], sizeof(ixD3F2_STATUS)/sizeof(ixD3F2_STATUS[0]), 0, 0 }, + { "ixD3F2_PROG_INTERFACE", REG_SMC, 0x8000002, &ixD3F2_PROG_INTERFACE[0], sizeof(ixD3F2_PROG_INTERFACE)/sizeof(ixD3F2_PROG_INTERFACE[0]), 0, 0 }, + { "ixD3F2_REVISION_ID", REG_SMC, 0x8000002, &ixD3F2_REVISION_ID[0], sizeof(ixD3F2_REVISION_ID)/sizeof(ixD3F2_REVISION_ID[0]), 0, 0 }, + { "ixD3F2_BASE_CLASS", REG_SMC, 0x8000002, &ixD3F2_BASE_CLASS[0], sizeof(ixD3F2_BASE_CLASS)/sizeof(ixD3F2_BASE_CLASS[0]), 0, 0 }, + { "ixD3F2_SUB_CLASS", REG_SMC, 0x8000002, &ixD3F2_SUB_CLASS[0], sizeof(ixD3F2_SUB_CLASS)/sizeof(ixD3F2_SUB_CLASS[0]), 0, 0 }, + { "ixD3F2_CACHE_LINE", REG_SMC, 0x8000003, &ixD3F2_CACHE_LINE[0], sizeof(ixD3F2_CACHE_LINE)/sizeof(ixD3F2_CACHE_LINE[0]), 0, 0 }, + { "ixD3F2_LATENCY", REG_SMC, 0x8000003, &ixD3F2_LATENCY[0], sizeof(ixD3F2_LATENCY)/sizeof(ixD3F2_LATENCY[0]), 0, 0 }, + { "ixD3F2_HEADER", REG_SMC, 0x8000003, &ixD3F2_HEADER[0], sizeof(ixD3F2_HEADER)/sizeof(ixD3F2_HEADER[0]), 0, 0 }, + { "ixD3F2_BIST", REG_SMC, 0x8000003, &ixD3F2_BIST[0], sizeof(ixD3F2_BIST)/sizeof(ixD3F2_BIST[0]), 0, 0 }, + { "ixD3F2_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x8000006, &ixD3F2_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F2_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F2_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD3F2_SECONDARY_STATUS", REG_SMC, 0x8000007, &ixD3F2_SECONDARY_STATUS[0], sizeof(ixD3F2_SECONDARY_STATUS)/sizeof(ixD3F2_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD3F2_IO_BASE_LIMIT", REG_SMC, 0x8000007, &ixD3F2_IO_BASE_LIMIT[0], sizeof(ixD3F2_IO_BASE_LIMIT)/sizeof(ixD3F2_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F2_MEM_BASE_LIMIT", REG_SMC, 0x8000008, &ixD3F2_MEM_BASE_LIMIT[0], sizeof(ixD3F2_MEM_BASE_LIMIT)/sizeof(ixD3F2_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F2_PREF_BASE_LIMIT", REG_SMC, 0x8000009, &ixD3F2_PREF_BASE_LIMIT[0], sizeof(ixD3F2_PREF_BASE_LIMIT)/sizeof(ixD3F2_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F2_PREF_BASE_UPPER", REG_SMC, 0x800000a, &ixD3F2_PREF_BASE_UPPER[0], sizeof(ixD3F2_PREF_BASE_UPPER)/sizeof(ixD3F2_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD3F2_PREF_LIMIT_UPPER", REG_SMC, 0x800000b, &ixD3F2_PREF_LIMIT_UPPER[0], sizeof(ixD3F2_PREF_LIMIT_UPPER)/sizeof(ixD3F2_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD3F2_IO_BASE_LIMIT_HI", REG_SMC, 0x800000c, &ixD3F2_IO_BASE_LIMIT_HI[0], sizeof(ixD3F2_IO_BASE_LIMIT_HI)/sizeof(ixD3F2_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD3F2_CAP_PTR", REG_SMC, 0x800000d, &ixD3F2_CAP_PTR[0], sizeof(ixD3F2_CAP_PTR)/sizeof(ixD3F2_CAP_PTR[0]), 0, 0 }, + { "ixD3F2_IRQ_BRIDGE_CNTL", REG_SMC, 0x800000f, &ixD3F2_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F2_IRQ_BRIDGE_CNTL)/sizeof(ixD3F2_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F2_INTERRUPT_LINE", REG_SMC, 0x800000f, &ixD3F2_INTERRUPT_LINE[0], sizeof(ixD3F2_INTERRUPT_LINE)/sizeof(ixD3F2_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD3F2_INTERRUPT_PIN", REG_SMC, 0x800000f, &ixD3F2_INTERRUPT_PIN[0], sizeof(ixD3F2_INTERRUPT_PIN)/sizeof(ixD3F2_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD3F2_EXT_BRIDGE_CNTL", REG_SMC, 0x8000010, &ixD3F2_EXT_BRIDGE_CNTL[0], sizeof(ixD3F2_EXT_BRIDGE_CNTL)/sizeof(ixD3F2_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F2_PMI_CAP_LIST", REG_SMC, 0x8000014, &ixD3F2_PMI_CAP_LIST[0], sizeof(ixD3F2_PMI_CAP_LIST)/sizeof(ixD3F2_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PMI_CAP", REG_SMC, 0x8000014, &ixD3F2_PMI_CAP[0], sizeof(ixD3F2_PMI_CAP)/sizeof(ixD3F2_PMI_CAP[0]), 0, 0 }, + { "ixD3F2_PMI_STATUS_CNTL", REG_SMC, 0x8000015, &ixD3F2_PMI_STATUS_CNTL[0], sizeof(ixD3F2_PMI_STATUS_CNTL)/sizeof(ixD3F2_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_CAP_LIST", REG_SMC, 0x8000016, &ixD3F2_PCIE_CAP_LIST[0], sizeof(ixD3F2_PCIE_CAP_LIST)/sizeof(ixD3F2_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_CAP", REG_SMC, 0x8000016, &ixD3F2_PCIE_CAP[0], sizeof(ixD3F2_PCIE_CAP)/sizeof(ixD3F2_PCIE_CAP[0]), 0, 0 }, + { "ixD3F2_DEVICE_CAP", REG_SMC, 0x8000017, &ixD3F2_DEVICE_CAP[0], sizeof(ixD3F2_DEVICE_CAP)/sizeof(ixD3F2_DEVICE_CAP[0]), 0, 0 }, + { "ixD3F2_DEVICE_STATUS", REG_SMC, 0x8000018, &ixD3F2_DEVICE_STATUS[0], sizeof(ixD3F2_DEVICE_STATUS)/sizeof(ixD3F2_DEVICE_STATUS[0]), 0, 0 }, + { "ixD3F2_DEVICE_CNTL", REG_SMC, 0x8000018, &ixD3F2_DEVICE_CNTL[0], sizeof(ixD3F2_DEVICE_CNTL)/sizeof(ixD3F2_DEVICE_CNTL[0]), 0, 0 }, + { "ixD3F2_LINK_CAP", REG_SMC, 0x8000019, &ixD3F2_LINK_CAP[0], sizeof(ixD3F2_LINK_CAP)/sizeof(ixD3F2_LINK_CAP[0]), 0, 0 }, + { "ixD3F2_LINK_STATUS", REG_SMC, 0x800001a, &ixD3F2_LINK_STATUS[0], sizeof(ixD3F2_LINK_STATUS)/sizeof(ixD3F2_LINK_STATUS[0]), 0, 0 }, + { "ixD3F2_LINK_CNTL", REG_SMC, 0x800001a, &ixD3F2_LINK_CNTL[0], sizeof(ixD3F2_LINK_CNTL)/sizeof(ixD3F2_LINK_CNTL[0]), 0, 0 }, + { "ixD3F2_SLOT_CAP", REG_SMC, 0x800001b, &ixD3F2_SLOT_CAP[0], sizeof(ixD3F2_SLOT_CAP)/sizeof(ixD3F2_SLOT_CAP[0]), 0, 0 }, + { "ixD3F2_SLOT_STATUS", REG_SMC, 0x800001c, &ixD3F2_SLOT_STATUS[0], sizeof(ixD3F2_SLOT_STATUS)/sizeof(ixD3F2_SLOT_STATUS[0]), 0, 0 }, + { "ixD3F2_SLOT_CNTL", REG_SMC, 0x800001c, &ixD3F2_SLOT_CNTL[0], sizeof(ixD3F2_SLOT_CNTL)/sizeof(ixD3F2_SLOT_CNTL[0]), 0, 0 }, + { "ixD3F2_ROOT_CNTL", REG_SMC, 0x800001d, &ixD3F2_ROOT_CNTL[0], sizeof(ixD3F2_ROOT_CNTL)/sizeof(ixD3F2_ROOT_CNTL[0]), 0, 0 }, + { "ixD3F2_ROOT_CAP", REG_SMC, 0x800001d, &ixD3F2_ROOT_CAP[0], sizeof(ixD3F2_ROOT_CAP)/sizeof(ixD3F2_ROOT_CAP[0]), 0, 0 }, + { "ixD3F2_ROOT_STATUS", REG_SMC, 0x800001e, &ixD3F2_ROOT_STATUS[0], sizeof(ixD3F2_ROOT_STATUS)/sizeof(ixD3F2_ROOT_STATUS[0]), 0, 0 }, + { "ixD3F2_DEVICE_CAP2", REG_SMC, 0x800001f, &ixD3F2_DEVICE_CAP2[0], sizeof(ixD3F2_DEVICE_CAP2)/sizeof(ixD3F2_DEVICE_CAP2[0]), 0, 0 }, + { "ixD3F2_DEVICE_STATUS2", REG_SMC, 0x8000020, &ixD3F2_DEVICE_STATUS2[0], sizeof(ixD3F2_DEVICE_STATUS2)/sizeof(ixD3F2_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD3F2_DEVICE_CNTL2", REG_SMC, 0x8000020, &ixD3F2_DEVICE_CNTL2[0], sizeof(ixD3F2_DEVICE_CNTL2)/sizeof(ixD3F2_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD3F2_LINK_CAP2", REG_SMC, 0x8000021, &ixD3F2_LINK_CAP2[0], sizeof(ixD3F2_LINK_CAP2)/sizeof(ixD3F2_LINK_CAP2[0]), 0, 0 }, + { "ixD3F2_LINK_STATUS2", REG_SMC, 0x8000022, &ixD3F2_LINK_STATUS2[0], sizeof(ixD3F2_LINK_STATUS2)/sizeof(ixD3F2_LINK_STATUS2[0]), 0, 0 }, + { "ixD3F2_LINK_CNTL2", REG_SMC, 0x8000022, &ixD3F2_LINK_CNTL2[0], sizeof(ixD3F2_LINK_CNTL2)/sizeof(ixD3F2_LINK_CNTL2[0]), 0, 0 }, + { "ixD3F2_SLOT_CAP2", REG_SMC, 0x8000023, &ixD3F2_SLOT_CAP2[0], sizeof(ixD3F2_SLOT_CAP2)/sizeof(ixD3F2_SLOT_CAP2[0]), 0, 0 }, + { "ixD3F2_SLOT_STATUS2", REG_SMC, 0x8000024, &ixD3F2_SLOT_STATUS2[0], sizeof(ixD3F2_SLOT_STATUS2)/sizeof(ixD3F2_SLOT_STATUS2[0]), 0, 0 }, + { "ixD3F2_SLOT_CNTL2", REG_SMC, 0x8000024, &ixD3F2_SLOT_CNTL2[0], sizeof(ixD3F2_SLOT_CNTL2)/sizeof(ixD3F2_SLOT_CNTL2[0]), 0, 0 }, + { "ixD3F2_MSI_CAP_LIST", REG_SMC, 0x8000028, &ixD3F2_MSI_CAP_LIST[0], sizeof(ixD3F2_MSI_CAP_LIST)/sizeof(ixD3F2_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_MSI_MSG_ADDR_LO", REG_SMC, 0x8000029, &ixD3F2_MSI_MSG_ADDR_LO[0], sizeof(ixD3F2_MSI_MSG_ADDR_LO)/sizeof(ixD3F2_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD3F2_MSI_MSG_ADDR_HI", REG_SMC, 0x800002a, &ixD3F2_MSI_MSG_ADDR_HI[0], sizeof(ixD3F2_MSI_MSG_ADDR_HI)/sizeof(ixD3F2_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD3F2_MSI_MSG_DATA", REG_SMC, 0x800002a, &ixD3F2_MSI_MSG_DATA[0], sizeof(ixD3F2_MSI_MSG_DATA)/sizeof(ixD3F2_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD3F2_MSI_MSG_DATA_64", REG_SMC, 0x800002b, &ixD3F2_MSI_MSG_DATA_64[0], sizeof(ixD3F2_MSI_MSG_DATA_64)/sizeof(ixD3F2_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD3F2_SSID_CAP_LIST", REG_SMC, 0x8000030, &ixD3F2_SSID_CAP_LIST[0], sizeof(ixD3F2_SSID_CAP_LIST)/sizeof(ixD3F2_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_SSID_CAP", REG_SMC, 0x8000031, &ixD3F2_SSID_CAP[0], sizeof(ixD3F2_SSID_CAP)/sizeof(ixD3F2_SSID_CAP[0]), 0, 0 }, + { "ixD3F2_MSI_MAP_CAP_LIST", REG_SMC, 0x8000032, &ixD3F2_MSI_MAP_CAP_LIST[0], sizeof(ixD3F2_MSI_MAP_CAP_LIST)/sizeof(ixD3F2_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_MSI_MAP_CAP", REG_SMC, 0x8000032, &ixD3F2_MSI_MAP_CAP[0], sizeof(ixD3F2_MSI_MAP_CAP)/sizeof(ixD3F2_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD3F2_MSI_MAP_ADDR_LO", REG_SMC, 0x8000033, &ixD3F2_MSI_MAP_ADDR_LO[0], sizeof(ixD3F2_MSI_MAP_ADDR_LO)/sizeof(ixD3F2_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD3F2_MSI_MAP_ADDR_HI", REG_SMC, 0x8000034, &ixD3F2_MSI_MAP_ADDR_HI[0], sizeof(ixD3F2_MSI_MAP_ADDR_HI)/sizeof(ixD3F2_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_INDEX", REG_SMC, 0x8000038, &ixD3F2_PCIE_PORT_INDEX[0], sizeof(ixD3F2_PCIE_PORT_INDEX)/sizeof(ixD3F2_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_DATA", REG_SMC, 0x8000039, &ixD3F2_PCIE_PORT_DATA[0], sizeof(ixD3F2_PCIE_PORT_DATA)/sizeof(ixD3F2_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x8000040, &ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x8000041, &ixD3F2_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD3F2_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x8000042, &ixD3F2_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD3F2_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x8000043, &ixD3F2_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD3F2_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x8000044, &ixD3F2_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x8000045, &ixD3F2_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x8000046, &ixD3F2_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_VC_STATUS", REG_SMC, 0x8000047, &ixD3F2_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F2_PCIE_PORT_VC_STATUS)/sizeof(ixD3F2_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_PORT_VC_CNTL", REG_SMC, 0x8000047, &ixD3F2_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F2_PCIE_PORT_VC_CNTL)/sizeof(ixD3F2_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x8000048, &ixD3F2_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F2_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x8000049, &ixD3F2_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x800004a, &ixD3F2_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x800004b, &ixD3F2_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F2_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x800004c, &ixD3F2_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x800004d, &ixD3F2_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x8000050, &ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x8000051, &ixD3F2_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD3F2_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x8000052, &ixD3F2_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x8000054, &ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x8000055, &ixD3F2_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F2_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x8000056, &ixD3F2_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F2_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F2_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x8000057, &ixD3F2_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F2_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD3F2_PCIE_CORR_ERR_STATUS", REG_SMC, 0x8000058, &ixD3F2_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F2_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F2_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_CORR_ERR_MASK", REG_SMC, 0x8000059, &ixD3F2_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F2_PCIE_CORR_ERR_MASK)/sizeof(ixD3F2_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F2_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x800005a, &ixD3F2_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F2_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F2_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_HDR_LOG0", REG_SMC, 0x800005b, &ixD3F2_PCIE_HDR_LOG0[0], sizeof(ixD3F2_PCIE_HDR_LOG0)/sizeof(ixD3F2_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD3F2_PCIE_HDR_LOG1", REG_SMC, 0x800005c, &ixD3F2_PCIE_HDR_LOG1[0], sizeof(ixD3F2_PCIE_HDR_LOG1)/sizeof(ixD3F2_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD3F2_PCIE_HDR_LOG2", REG_SMC, 0x800005d, &ixD3F2_PCIE_HDR_LOG2[0], sizeof(ixD3F2_PCIE_HDR_LOG2)/sizeof(ixD3F2_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD3F2_PCIE_HDR_LOG3", REG_SMC, 0x800005e, &ixD3F2_PCIE_HDR_LOG3[0], sizeof(ixD3F2_PCIE_HDR_LOG3)/sizeof(ixD3F2_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD3F2_PCIE_ROOT_ERR_CMD", REG_SMC, 0x800005f, &ixD3F2_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F2_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F2_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD3F2_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x8000060, &ixD3F2_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F2_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F2_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_ERR_SRC_ID", REG_SMC, 0x8000061, &ixD3F2_PCIE_ERR_SRC_ID[0], sizeof(ixD3F2_PCIE_ERR_SRC_ID)/sizeof(ixD3F2_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD3F2_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x8000062, &ixD3F2_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD3F2_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x8000063, &ixD3F2_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD3F2_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x8000064, &ixD3F2_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD3F2_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x8000065, &ixD3F2_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x800009c, &ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_LINK_CNTL3", REG_SMC, 0x800009d, &ixD3F2_PCIE_LINK_CNTL3[0], sizeof(ixD3F2_PCIE_LINK_CNTL3)/sizeof(ixD3F2_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x800009e, &ixD3F2_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F2_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F2_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x800009f, &ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x80000a0, &ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x80000a1, &ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x80000a2, &ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x80000a3, &ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x80000a4, &ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x80000a5, &ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x80000a6, &ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x80000a8, &ixD3F2_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_ACS_CNTL", REG_SMC, 0x80000a9, &ixD3F2_PCIE_ACS_CNTL[0], sizeof(ixD3F2_PCIE_ACS_CNTL)/sizeof(ixD3F2_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_ACS_CAP", REG_SMC, 0x80000a9, &ixD3F2_PCIE_ACS_CAP[0], sizeof(ixD3F2_PCIE_ACS_CAP)/sizeof(ixD3F2_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x80000bc, &ixD3F2_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_CNTL", REG_SMC, 0x80000bd, &ixD3F2_PCIE_MC_CNTL[0], sizeof(ixD3F2_PCIE_MC_CNTL)/sizeof(ixD3F2_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_CAP", REG_SMC, 0x80000bd, &ixD3F2_PCIE_MC_CAP[0], sizeof(ixD3F2_PCIE_MC_CAP)/sizeof(ixD3F2_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_ADDR0", REG_SMC, 0x80000be, &ixD3F2_PCIE_MC_ADDR0[0], sizeof(ixD3F2_PCIE_MC_ADDR0)/sizeof(ixD3F2_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_ADDR1", REG_SMC, 0x80000bf, &ixD3F2_PCIE_MC_ADDR1[0], sizeof(ixD3F2_PCIE_MC_ADDR1)/sizeof(ixD3F2_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_RCV0", REG_SMC, 0x80000c0, &ixD3F2_PCIE_MC_RCV0[0], sizeof(ixD3F2_PCIE_MC_RCV0)/sizeof(ixD3F2_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_RCV1", REG_SMC, 0x80000c1, &ixD3F2_PCIE_MC_RCV1[0], sizeof(ixD3F2_PCIE_MC_RCV1)/sizeof(ixD3F2_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x80000c2, &ixD3F2_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F2_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F2_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x80000c3, &ixD3F2_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F2_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F2_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x80000c4, &ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x80000c5, &ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x80000c6, &ixD3F2_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD3F2_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x80000c7, &ixD3F2_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x81, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 }, + { "mmPCIE_BAR1_CAP", REG_MMIO, 0x81, &mmPCIE_BAR1_CAP[0], sizeof(mmPCIE_BAR1_CAP)/sizeof(mmPCIE_BAR1_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x82, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 }, + { "mmPCIE_BAR1_CNTL", REG_MMIO, 0x82, &mmPCIE_BAR1_CNTL[0], sizeof(mmPCIE_BAR1_CNTL)/sizeof(mmPCIE_BAR1_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL", REG_SMC, 0x83, &ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL[0], sizeof(ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL)/sizeof(ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL[0]), 0, 0 }, + { "mmPCIE_BAR2_CAP", REG_MMIO, 0x83, &mmPCIE_BAR2_CAP[0], sizeof(mmPCIE_BAR2_CAP)/sizeof(mmPCIE_BAR2_CAP[0]), 0, 0 }, + { "ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION", REG_SMC, 0x84, &ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION[0], sizeof(ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION)/sizeof(ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION[0]), 0, 0 }, + { "mmPCIE_BAR2_CNTL", REG_MMIO, 0x84, &mmPCIE_BAR2_CNTL[0], sizeof(mmPCIE_BAR2_CNTL)/sizeof(mmPCIE_BAR2_CNTL[0]), 0, 0 }, + { "mmPCIE_BAR3_CAP", REG_MMIO, 0x85, &mmPCIE_BAR3_CAP[0], sizeof(mmPCIE_BAR3_CAP)/sizeof(mmPCIE_BAR3_CAP[0]), 0, 0 }, + { "mmPCIE_BAR3_CNTL", REG_MMIO, 0x86, &mmPCIE_BAR3_CNTL[0], sizeof(mmPCIE_BAR3_CNTL)/sizeof(mmPCIE_BAR3_CNTL[0]), 0, 0 }, + { "mmPCIE_BAR4_CAP", REG_MMIO, 0x87, &mmPCIE_BAR4_CAP[0], sizeof(mmPCIE_BAR4_CAP)/sizeof(mmPCIE_BAR4_CAP[0]), 0, 0 }, + { "mmPCIE_BAR4_CNTL", REG_MMIO, 0x88, &mmPCIE_BAR4_CNTL[0], sizeof(mmPCIE_BAR4_CNTL)/sizeof(mmPCIE_BAR4_CNTL[0]), 0, 0 }, + { "mmPCIE_BAR5_CAP", REG_MMIO, 0x89, &mmPCIE_BAR5_CAP[0], sizeof(mmPCIE_BAR5_CAP)/sizeof(mmPCIE_BAR5_CAP[0]), 0, 0 }, + { "mmPCIE_BAR5_CNTL", REG_MMIO, 0x8a, &mmPCIE_BAR5_CNTL[0], sizeof(mmPCIE_BAR5_CNTL)/sizeof(mmPCIE_BAR5_CNTL[0]), 0, 0 }, + { "mmPCIE_BAR6_CAP", REG_MMIO, 0x8b, &mmPCIE_BAR6_CAP[0], sizeof(mmPCIE_BAR6_CAP)/sizeof(mmPCIE_BAR6_CAP[0]), 0, 0 }, + { "mmPCIE_BAR6_CNTL", REG_MMIO, 0x8c, &mmPCIE_BAR6_CNTL[0], sizeof(mmPCIE_BAR6_CNTL)/sizeof(mmPCIE_BAR6_CNTL[0]), 0, 0 }, + { "mmBASE_ADDR_6", REG_MMIO, 0x9, &mmBASE_ADDR_6[0], sizeof(mmBASE_ADDR_6)/sizeof(mmBASE_ADDR_6[0]), 0, 0 }, + { "mmPCIE_PWR_BUDGET_ENH_CAP_LIST", REG_MMIO, 0x90, &mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0], sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST)/sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_VENDOR_ID", REG_SMC, 0x9000000, &ixD3F3_VENDOR_ID[0], sizeof(ixD3F3_VENDOR_ID)/sizeof(ixD3F3_VENDOR_ID[0]), 0, 0 }, + { "ixD3F3_COMMAND", REG_SMC, 0x9000001, &ixD3F3_COMMAND[0], sizeof(ixD3F3_COMMAND)/sizeof(ixD3F3_COMMAND[0]), 0, 0 }, + { "ixD3F3_STATUS", REG_SMC, 0x9000001, &ixD3F3_STATUS[0], sizeof(ixD3F3_STATUS)/sizeof(ixD3F3_STATUS[0]), 0, 0 }, + { "ixD3F3_PROG_INTERFACE", REG_SMC, 0x9000002, &ixD3F3_PROG_INTERFACE[0], sizeof(ixD3F3_PROG_INTERFACE)/sizeof(ixD3F3_PROG_INTERFACE[0]), 0, 0 }, + { "ixD3F3_REVISION_ID", REG_SMC, 0x9000002, &ixD3F3_REVISION_ID[0], sizeof(ixD3F3_REVISION_ID)/sizeof(ixD3F3_REVISION_ID[0]), 0, 0 }, + { "ixD3F3_BASE_CLASS", REG_SMC, 0x9000002, &ixD3F3_BASE_CLASS[0], sizeof(ixD3F3_BASE_CLASS)/sizeof(ixD3F3_BASE_CLASS[0]), 0, 0 }, + { "ixD3F3_SUB_CLASS", REG_SMC, 0x9000002, &ixD3F3_SUB_CLASS[0], sizeof(ixD3F3_SUB_CLASS)/sizeof(ixD3F3_SUB_CLASS[0]), 0, 0 }, + { "ixD3F3_CACHE_LINE", REG_SMC, 0x9000003, &ixD3F3_CACHE_LINE[0], sizeof(ixD3F3_CACHE_LINE)/sizeof(ixD3F3_CACHE_LINE[0]), 0, 0 }, + { "ixD3F3_LATENCY", REG_SMC, 0x9000003, &ixD3F3_LATENCY[0], sizeof(ixD3F3_LATENCY)/sizeof(ixD3F3_LATENCY[0]), 0, 0 }, + { "ixD3F3_HEADER", REG_SMC, 0x9000003, &ixD3F3_HEADER[0], sizeof(ixD3F3_HEADER)/sizeof(ixD3F3_HEADER[0]), 0, 0 }, + { "ixD3F3_BIST", REG_SMC, 0x9000003, &ixD3F3_BIST[0], sizeof(ixD3F3_BIST)/sizeof(ixD3F3_BIST[0]), 0, 0 }, + { "ixD3F3_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x9000006, &ixD3F3_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F3_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F3_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD3F3_SECONDARY_STATUS", REG_SMC, 0x9000007, &ixD3F3_SECONDARY_STATUS[0], sizeof(ixD3F3_SECONDARY_STATUS)/sizeof(ixD3F3_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD3F3_IO_BASE_LIMIT", REG_SMC, 0x9000007, &ixD3F3_IO_BASE_LIMIT[0], sizeof(ixD3F3_IO_BASE_LIMIT)/sizeof(ixD3F3_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F3_MEM_BASE_LIMIT", REG_SMC, 0x9000008, &ixD3F3_MEM_BASE_LIMIT[0], sizeof(ixD3F3_MEM_BASE_LIMIT)/sizeof(ixD3F3_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F3_PREF_BASE_LIMIT", REG_SMC, 0x9000009, &ixD3F3_PREF_BASE_LIMIT[0], sizeof(ixD3F3_PREF_BASE_LIMIT)/sizeof(ixD3F3_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F3_PREF_BASE_UPPER", REG_SMC, 0x900000a, &ixD3F3_PREF_BASE_UPPER[0], sizeof(ixD3F3_PREF_BASE_UPPER)/sizeof(ixD3F3_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD3F3_PREF_LIMIT_UPPER", REG_SMC, 0x900000b, &ixD3F3_PREF_LIMIT_UPPER[0], sizeof(ixD3F3_PREF_LIMIT_UPPER)/sizeof(ixD3F3_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD3F3_IO_BASE_LIMIT_HI", REG_SMC, 0x900000c, &ixD3F3_IO_BASE_LIMIT_HI[0], sizeof(ixD3F3_IO_BASE_LIMIT_HI)/sizeof(ixD3F3_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD3F3_CAP_PTR", REG_SMC, 0x900000d, &ixD3F3_CAP_PTR[0], sizeof(ixD3F3_CAP_PTR)/sizeof(ixD3F3_CAP_PTR[0]), 0, 0 }, + { "ixD3F3_IRQ_BRIDGE_CNTL", REG_SMC, 0x900000f, &ixD3F3_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F3_IRQ_BRIDGE_CNTL)/sizeof(ixD3F3_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F3_INTERRUPT_LINE", REG_SMC, 0x900000f, &ixD3F3_INTERRUPT_LINE[0], sizeof(ixD3F3_INTERRUPT_LINE)/sizeof(ixD3F3_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD3F3_INTERRUPT_PIN", REG_SMC, 0x900000f, &ixD3F3_INTERRUPT_PIN[0], sizeof(ixD3F3_INTERRUPT_PIN)/sizeof(ixD3F3_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD3F3_EXT_BRIDGE_CNTL", REG_SMC, 0x9000010, &ixD3F3_EXT_BRIDGE_CNTL[0], sizeof(ixD3F3_EXT_BRIDGE_CNTL)/sizeof(ixD3F3_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F3_PMI_CAP_LIST", REG_SMC, 0x9000014, &ixD3F3_PMI_CAP_LIST[0], sizeof(ixD3F3_PMI_CAP_LIST)/sizeof(ixD3F3_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PMI_CAP", REG_SMC, 0x9000014, &ixD3F3_PMI_CAP[0], sizeof(ixD3F3_PMI_CAP)/sizeof(ixD3F3_PMI_CAP[0]), 0, 0 }, + { "ixD3F3_PMI_STATUS_CNTL", REG_SMC, 0x9000015, &ixD3F3_PMI_STATUS_CNTL[0], sizeof(ixD3F3_PMI_STATUS_CNTL)/sizeof(ixD3F3_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_CAP_LIST", REG_SMC, 0x9000016, &ixD3F3_PCIE_CAP_LIST[0], sizeof(ixD3F3_PCIE_CAP_LIST)/sizeof(ixD3F3_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_CAP", REG_SMC, 0x9000016, &ixD3F3_PCIE_CAP[0], sizeof(ixD3F3_PCIE_CAP)/sizeof(ixD3F3_PCIE_CAP[0]), 0, 0 }, + { "ixD3F3_DEVICE_CAP", REG_SMC, 0x9000017, &ixD3F3_DEVICE_CAP[0], sizeof(ixD3F3_DEVICE_CAP)/sizeof(ixD3F3_DEVICE_CAP[0]), 0, 0 }, + { "ixD3F3_DEVICE_STATUS", REG_SMC, 0x9000018, &ixD3F3_DEVICE_STATUS[0], sizeof(ixD3F3_DEVICE_STATUS)/sizeof(ixD3F3_DEVICE_STATUS[0]), 0, 0 }, + { "ixD3F3_DEVICE_CNTL", REG_SMC, 0x9000018, &ixD3F3_DEVICE_CNTL[0], sizeof(ixD3F3_DEVICE_CNTL)/sizeof(ixD3F3_DEVICE_CNTL[0]), 0, 0 }, + { "ixD3F3_LINK_CAP", REG_SMC, 0x9000019, &ixD3F3_LINK_CAP[0], sizeof(ixD3F3_LINK_CAP)/sizeof(ixD3F3_LINK_CAP[0]), 0, 0 }, + { "ixD3F3_LINK_STATUS", REG_SMC, 0x900001a, &ixD3F3_LINK_STATUS[0], sizeof(ixD3F3_LINK_STATUS)/sizeof(ixD3F3_LINK_STATUS[0]), 0, 0 }, + { "ixD3F3_LINK_CNTL", REG_SMC, 0x900001a, &ixD3F3_LINK_CNTL[0], sizeof(ixD3F3_LINK_CNTL)/sizeof(ixD3F3_LINK_CNTL[0]), 0, 0 }, + { "ixD3F3_SLOT_CAP", REG_SMC, 0x900001b, &ixD3F3_SLOT_CAP[0], sizeof(ixD3F3_SLOT_CAP)/sizeof(ixD3F3_SLOT_CAP[0]), 0, 0 }, + { "ixD3F3_SLOT_STATUS", REG_SMC, 0x900001c, &ixD3F3_SLOT_STATUS[0], sizeof(ixD3F3_SLOT_STATUS)/sizeof(ixD3F3_SLOT_STATUS[0]), 0, 0 }, + { "ixD3F3_SLOT_CNTL", REG_SMC, 0x900001c, &ixD3F3_SLOT_CNTL[0], sizeof(ixD3F3_SLOT_CNTL)/sizeof(ixD3F3_SLOT_CNTL[0]), 0, 0 }, + { "ixD3F3_ROOT_CNTL", REG_SMC, 0x900001d, &ixD3F3_ROOT_CNTL[0], sizeof(ixD3F3_ROOT_CNTL)/sizeof(ixD3F3_ROOT_CNTL[0]), 0, 0 }, + { "ixD3F3_ROOT_CAP", REG_SMC, 0x900001d, &ixD3F3_ROOT_CAP[0], sizeof(ixD3F3_ROOT_CAP)/sizeof(ixD3F3_ROOT_CAP[0]), 0, 0 }, + { "ixD3F3_ROOT_STATUS", REG_SMC, 0x900001e, &ixD3F3_ROOT_STATUS[0], sizeof(ixD3F3_ROOT_STATUS)/sizeof(ixD3F3_ROOT_STATUS[0]), 0, 0 }, + { "ixD3F3_DEVICE_CAP2", REG_SMC, 0x900001f, &ixD3F3_DEVICE_CAP2[0], sizeof(ixD3F3_DEVICE_CAP2)/sizeof(ixD3F3_DEVICE_CAP2[0]), 0, 0 }, + { "ixD3F3_DEVICE_STATUS2", REG_SMC, 0x9000020, &ixD3F3_DEVICE_STATUS2[0], sizeof(ixD3F3_DEVICE_STATUS2)/sizeof(ixD3F3_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD3F3_DEVICE_CNTL2", REG_SMC, 0x9000020, &ixD3F3_DEVICE_CNTL2[0], sizeof(ixD3F3_DEVICE_CNTL2)/sizeof(ixD3F3_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD3F3_LINK_CAP2", REG_SMC, 0x9000021, &ixD3F3_LINK_CAP2[0], sizeof(ixD3F3_LINK_CAP2)/sizeof(ixD3F3_LINK_CAP2[0]), 0, 0 }, + { "ixD3F3_LINK_STATUS2", REG_SMC, 0x9000022, &ixD3F3_LINK_STATUS2[0], sizeof(ixD3F3_LINK_STATUS2)/sizeof(ixD3F3_LINK_STATUS2[0]), 0, 0 }, + { "ixD3F3_LINK_CNTL2", REG_SMC, 0x9000022, &ixD3F3_LINK_CNTL2[0], sizeof(ixD3F3_LINK_CNTL2)/sizeof(ixD3F3_LINK_CNTL2[0]), 0, 0 }, + { "ixD3F3_SLOT_CAP2", REG_SMC, 0x9000023, &ixD3F3_SLOT_CAP2[0], sizeof(ixD3F3_SLOT_CAP2)/sizeof(ixD3F3_SLOT_CAP2[0]), 0, 0 }, + { "ixD3F3_SLOT_STATUS2", REG_SMC, 0x9000024, &ixD3F3_SLOT_STATUS2[0], sizeof(ixD3F3_SLOT_STATUS2)/sizeof(ixD3F3_SLOT_STATUS2[0]), 0, 0 }, + { "ixD3F3_SLOT_CNTL2", REG_SMC, 0x9000024, &ixD3F3_SLOT_CNTL2[0], sizeof(ixD3F3_SLOT_CNTL2)/sizeof(ixD3F3_SLOT_CNTL2[0]), 0, 0 }, + { "ixD3F3_MSI_CAP_LIST", REG_SMC, 0x9000028, &ixD3F3_MSI_CAP_LIST[0], sizeof(ixD3F3_MSI_CAP_LIST)/sizeof(ixD3F3_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_MSI_MSG_ADDR_LO", REG_SMC, 0x9000029, &ixD3F3_MSI_MSG_ADDR_LO[0], sizeof(ixD3F3_MSI_MSG_ADDR_LO)/sizeof(ixD3F3_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD3F3_MSI_MSG_ADDR_HI", REG_SMC, 0x900002a, &ixD3F3_MSI_MSG_ADDR_HI[0], sizeof(ixD3F3_MSI_MSG_ADDR_HI)/sizeof(ixD3F3_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD3F3_MSI_MSG_DATA", REG_SMC, 0x900002a, &ixD3F3_MSI_MSG_DATA[0], sizeof(ixD3F3_MSI_MSG_DATA)/sizeof(ixD3F3_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD3F3_MSI_MSG_DATA_64", REG_SMC, 0x900002b, &ixD3F3_MSI_MSG_DATA_64[0], sizeof(ixD3F3_MSI_MSG_DATA_64)/sizeof(ixD3F3_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD3F3_SSID_CAP_LIST", REG_SMC, 0x9000030, &ixD3F3_SSID_CAP_LIST[0], sizeof(ixD3F3_SSID_CAP_LIST)/sizeof(ixD3F3_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_SSID_CAP", REG_SMC, 0x9000031, &ixD3F3_SSID_CAP[0], sizeof(ixD3F3_SSID_CAP)/sizeof(ixD3F3_SSID_CAP[0]), 0, 0 }, + { "ixD3F3_MSI_MAP_CAP_LIST", REG_SMC, 0x9000032, &ixD3F3_MSI_MAP_CAP_LIST[0], sizeof(ixD3F3_MSI_MAP_CAP_LIST)/sizeof(ixD3F3_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_MSI_MAP_CAP", REG_SMC, 0x9000032, &ixD3F3_MSI_MAP_CAP[0], sizeof(ixD3F3_MSI_MAP_CAP)/sizeof(ixD3F3_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD3F3_MSI_MAP_ADDR_LO", REG_SMC, 0x9000033, &ixD3F3_MSI_MAP_ADDR_LO[0], sizeof(ixD3F3_MSI_MAP_ADDR_LO)/sizeof(ixD3F3_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD3F3_MSI_MAP_ADDR_HI", REG_SMC, 0x9000034, &ixD3F3_MSI_MAP_ADDR_HI[0], sizeof(ixD3F3_MSI_MAP_ADDR_HI)/sizeof(ixD3F3_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_INDEX", REG_SMC, 0x9000038, &ixD3F3_PCIE_PORT_INDEX[0], sizeof(ixD3F3_PCIE_PORT_INDEX)/sizeof(ixD3F3_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_DATA", REG_SMC, 0x9000039, &ixD3F3_PCIE_PORT_DATA[0], sizeof(ixD3F3_PCIE_PORT_DATA)/sizeof(ixD3F3_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x9000040, &ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x9000041, &ixD3F3_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD3F3_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x9000042, &ixD3F3_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD3F3_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x9000043, &ixD3F3_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD3F3_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x9000044, &ixD3F3_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x9000045, &ixD3F3_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x9000046, &ixD3F3_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_VC_STATUS", REG_SMC, 0x9000047, &ixD3F3_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F3_PCIE_PORT_VC_STATUS)/sizeof(ixD3F3_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_PORT_VC_CNTL", REG_SMC, 0x9000047, &ixD3F3_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F3_PCIE_PORT_VC_CNTL)/sizeof(ixD3F3_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x9000048, &ixD3F3_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F3_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x9000049, &ixD3F3_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x900004a, &ixD3F3_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x900004b, &ixD3F3_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F3_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x900004c, &ixD3F3_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x900004d, &ixD3F3_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x9000050, &ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x9000051, &ixD3F3_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD3F3_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x9000052, &ixD3F3_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x9000054, &ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x9000055, &ixD3F3_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F3_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x9000056, &ixD3F3_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F3_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F3_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x9000057, &ixD3F3_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F3_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD3F3_PCIE_CORR_ERR_STATUS", REG_SMC, 0x9000058, &ixD3F3_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F3_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F3_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_CORR_ERR_MASK", REG_SMC, 0x9000059, &ixD3F3_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F3_PCIE_CORR_ERR_MASK)/sizeof(ixD3F3_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F3_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x900005a, &ixD3F3_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F3_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F3_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_HDR_LOG0", REG_SMC, 0x900005b, &ixD3F3_PCIE_HDR_LOG0[0], sizeof(ixD3F3_PCIE_HDR_LOG0)/sizeof(ixD3F3_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD3F3_PCIE_HDR_LOG1", REG_SMC, 0x900005c, &ixD3F3_PCIE_HDR_LOG1[0], sizeof(ixD3F3_PCIE_HDR_LOG1)/sizeof(ixD3F3_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD3F3_PCIE_HDR_LOG2", REG_SMC, 0x900005d, &ixD3F3_PCIE_HDR_LOG2[0], sizeof(ixD3F3_PCIE_HDR_LOG2)/sizeof(ixD3F3_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD3F3_PCIE_HDR_LOG3", REG_SMC, 0x900005e, &ixD3F3_PCIE_HDR_LOG3[0], sizeof(ixD3F3_PCIE_HDR_LOG3)/sizeof(ixD3F3_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD3F3_PCIE_ROOT_ERR_CMD", REG_SMC, 0x900005f, &ixD3F3_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F3_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F3_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD3F3_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x9000060, &ixD3F3_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F3_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F3_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_ERR_SRC_ID", REG_SMC, 0x9000061, &ixD3F3_PCIE_ERR_SRC_ID[0], sizeof(ixD3F3_PCIE_ERR_SRC_ID)/sizeof(ixD3F3_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD3F3_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x9000062, &ixD3F3_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD3F3_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x9000063, &ixD3F3_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD3F3_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x9000064, &ixD3F3_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD3F3_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x9000065, &ixD3F3_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x900009c, &ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_LINK_CNTL3", REG_SMC, 0x900009d, &ixD3F3_PCIE_LINK_CNTL3[0], sizeof(ixD3F3_PCIE_LINK_CNTL3)/sizeof(ixD3F3_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x900009e, &ixD3F3_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F3_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F3_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x900009f, &ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x90000a0, &ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x90000a1, &ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x90000a2, &ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x90000a3, &ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x90000a4, &ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x90000a5, &ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x90000a6, &ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x90000a8, &ixD3F3_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_ACS_CNTL", REG_SMC, 0x90000a9, &ixD3F3_PCIE_ACS_CNTL[0], sizeof(ixD3F3_PCIE_ACS_CNTL)/sizeof(ixD3F3_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_ACS_CAP", REG_SMC, 0x90000a9, &ixD3F3_PCIE_ACS_CAP[0], sizeof(ixD3F3_PCIE_ACS_CAP)/sizeof(ixD3F3_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x90000bc, &ixD3F3_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_CNTL", REG_SMC, 0x90000bd, &ixD3F3_PCIE_MC_CNTL[0], sizeof(ixD3F3_PCIE_MC_CNTL)/sizeof(ixD3F3_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_CAP", REG_SMC, 0x90000bd, &ixD3F3_PCIE_MC_CAP[0], sizeof(ixD3F3_PCIE_MC_CAP)/sizeof(ixD3F3_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_ADDR0", REG_SMC, 0x90000be, &ixD3F3_PCIE_MC_ADDR0[0], sizeof(ixD3F3_PCIE_MC_ADDR0)/sizeof(ixD3F3_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_ADDR1", REG_SMC, 0x90000bf, &ixD3F3_PCIE_MC_ADDR1[0], sizeof(ixD3F3_PCIE_MC_ADDR1)/sizeof(ixD3F3_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_RCV0", REG_SMC, 0x90000c0, &ixD3F3_PCIE_MC_RCV0[0], sizeof(ixD3F3_PCIE_MC_RCV0)/sizeof(ixD3F3_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_RCV1", REG_SMC, 0x90000c1, &ixD3F3_PCIE_MC_RCV1[0], sizeof(ixD3F3_PCIE_MC_RCV1)/sizeof(ixD3F3_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x90000c2, &ixD3F3_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F3_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F3_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x90000c3, &ixD3F3_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F3_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F3_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x90000c4, &ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x90000c5, &ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x90000c6, &ixD3F3_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD3F3_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x90000c7, &ixD3F3_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "mmPCIE_PWR_BUDGET_DATA_SELECT", REG_MMIO, 0x91, &mmPCIE_PWR_BUDGET_DATA_SELECT[0], sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT)/sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT[0]), 0, 0 }, + { "mmPCIE_PWR_BUDGET_DATA", REG_MMIO, 0x92, &mmPCIE_PWR_BUDGET_DATA[0], sizeof(mmPCIE_PWR_BUDGET_DATA)/sizeof(mmPCIE_PWR_BUDGET_DATA[0]), 0, 0 }, + { "mmPCIE_PWR_BUDGET_CAP", REG_MMIO, 0x93, &mmPCIE_PWR_BUDGET_CAP[0], sizeof(mmPCIE_PWR_BUDGET_CAP)/sizeof(mmPCIE_PWR_BUDGET_CAP[0]), 0, 0 }, + { "mmPCIE_DPA_ENH_CAP_LIST", REG_MMIO, 0x94, &mmPCIE_DPA_ENH_CAP_LIST[0], sizeof(mmPCIE_DPA_ENH_CAP_LIST)/sizeof(mmPCIE_DPA_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_DPA_CAP", REG_MMIO, 0x95, &mmPCIE_DPA_CAP[0], sizeof(mmPCIE_DPA_CAP)/sizeof(mmPCIE_DPA_CAP[0]), 0, 0 }, + { "mmPCIE_DPA_LATENCY_INDICATOR", REG_MMIO, 0x96, &mmPCIE_DPA_LATENCY_INDICATOR[0], sizeof(mmPCIE_DPA_LATENCY_INDICATOR)/sizeof(mmPCIE_DPA_LATENCY_INDICATOR[0]), 0, 0 }, + { "mmPCIE_DPA_STATUS", REG_MMIO, 0x97, &mmPCIE_DPA_STATUS[0], sizeof(mmPCIE_DPA_STATUS)/sizeof(mmPCIE_DPA_STATUS[0]), 0, 0 }, + { "mmPCIE_DPA_CNTL", REG_MMIO, 0x97, &mmPCIE_DPA_CNTL[0], sizeof(mmPCIE_DPA_CNTL)/sizeof(mmPCIE_DPA_CNTL[0]), 0, 0 }, + { "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x98, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 }, + { "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x99, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 }, + { "mmPCIE_SECONDARY_ENH_CAP_LIST", REG_MMIO, 0x9c, &mmPCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST)/sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_LINK_CNTL3", REG_MMIO, 0x9d, &mmPCIE_LINK_CNTL3[0], sizeof(mmPCIE_LINK_CNTL3)/sizeof(mmPCIE_LINK_CNTL3[0]), 0, 0 }, + { "mmPCIE_LANE_ERROR_STATUS", REG_MMIO, 0x9e, &mmPCIE_LANE_ERROR_STATUS[0], sizeof(mmPCIE_LANE_ERROR_STATUS)/sizeof(mmPCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "mmPCIE_LANE_0_EQUALIZATION_CNTL", REG_MMIO, 0x9f, &mmPCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "mmPCIE_LANE_2_EQUALIZATION_CNTL", REG_MMIO, 0xa0, &mmPCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CNTL", REG_SMC, 0xa0, &ixD2F1_PCIE_LC_CNTL[0], sizeof(ixD2F1_PCIE_LC_CNTL)/sizeof(ixD2F1_PCIE_LC_CNTL[0]), 0, 0 }, + { "ixD3F4_VENDOR_ID", REG_SMC, 0xa000000, &ixD3F4_VENDOR_ID[0], sizeof(ixD3F4_VENDOR_ID)/sizeof(ixD3F4_VENDOR_ID[0]), 0, 0 }, + { "ixD3F4_COMMAND", REG_SMC, 0xa000001, &ixD3F4_COMMAND[0], sizeof(ixD3F4_COMMAND)/sizeof(ixD3F4_COMMAND[0]), 0, 0 }, + { "ixD3F4_STATUS", REG_SMC, 0xa000001, &ixD3F4_STATUS[0], sizeof(ixD3F4_STATUS)/sizeof(ixD3F4_STATUS[0]), 0, 0 }, + { "ixD3F4_PROG_INTERFACE", REG_SMC, 0xa000002, &ixD3F4_PROG_INTERFACE[0], sizeof(ixD3F4_PROG_INTERFACE)/sizeof(ixD3F4_PROG_INTERFACE[0]), 0, 0 }, + { "ixD3F4_REVISION_ID", REG_SMC, 0xa000002, &ixD3F4_REVISION_ID[0], sizeof(ixD3F4_REVISION_ID)/sizeof(ixD3F4_REVISION_ID[0]), 0, 0 }, + { "ixD3F4_BASE_CLASS", REG_SMC, 0xa000002, &ixD3F4_BASE_CLASS[0], sizeof(ixD3F4_BASE_CLASS)/sizeof(ixD3F4_BASE_CLASS[0]), 0, 0 }, + { "ixD3F4_SUB_CLASS", REG_SMC, 0xa000002, &ixD3F4_SUB_CLASS[0], sizeof(ixD3F4_SUB_CLASS)/sizeof(ixD3F4_SUB_CLASS[0]), 0, 0 }, + { "ixD3F4_CACHE_LINE", REG_SMC, 0xa000003, &ixD3F4_CACHE_LINE[0], sizeof(ixD3F4_CACHE_LINE)/sizeof(ixD3F4_CACHE_LINE[0]), 0, 0 }, + { "ixD3F4_LATENCY", REG_SMC, 0xa000003, &ixD3F4_LATENCY[0], sizeof(ixD3F4_LATENCY)/sizeof(ixD3F4_LATENCY[0]), 0, 0 }, + { "ixD3F4_HEADER", REG_SMC, 0xa000003, &ixD3F4_HEADER[0], sizeof(ixD3F4_HEADER)/sizeof(ixD3F4_HEADER[0]), 0, 0 }, + { "ixD3F4_BIST", REG_SMC, 0xa000003, &ixD3F4_BIST[0], sizeof(ixD3F4_BIST)/sizeof(ixD3F4_BIST[0]), 0, 0 }, + { "ixD3F4_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0xa000006, &ixD3F4_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F4_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F4_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD3F4_SECONDARY_STATUS", REG_SMC, 0xa000007, &ixD3F4_SECONDARY_STATUS[0], sizeof(ixD3F4_SECONDARY_STATUS)/sizeof(ixD3F4_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD3F4_IO_BASE_LIMIT", REG_SMC, 0xa000007, &ixD3F4_IO_BASE_LIMIT[0], sizeof(ixD3F4_IO_BASE_LIMIT)/sizeof(ixD3F4_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F4_MEM_BASE_LIMIT", REG_SMC, 0xa000008, &ixD3F4_MEM_BASE_LIMIT[0], sizeof(ixD3F4_MEM_BASE_LIMIT)/sizeof(ixD3F4_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F4_PREF_BASE_LIMIT", REG_SMC, 0xa000009, &ixD3F4_PREF_BASE_LIMIT[0], sizeof(ixD3F4_PREF_BASE_LIMIT)/sizeof(ixD3F4_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F4_PREF_BASE_UPPER", REG_SMC, 0xa00000a, &ixD3F4_PREF_BASE_UPPER[0], sizeof(ixD3F4_PREF_BASE_UPPER)/sizeof(ixD3F4_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD3F4_PREF_LIMIT_UPPER", REG_SMC, 0xa00000b, &ixD3F4_PREF_LIMIT_UPPER[0], sizeof(ixD3F4_PREF_LIMIT_UPPER)/sizeof(ixD3F4_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD3F4_IO_BASE_LIMIT_HI", REG_SMC, 0xa00000c, &ixD3F4_IO_BASE_LIMIT_HI[0], sizeof(ixD3F4_IO_BASE_LIMIT_HI)/sizeof(ixD3F4_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD3F4_CAP_PTR", REG_SMC, 0xa00000d, &ixD3F4_CAP_PTR[0], sizeof(ixD3F4_CAP_PTR)/sizeof(ixD3F4_CAP_PTR[0]), 0, 0 }, + { "ixD3F4_IRQ_BRIDGE_CNTL", REG_SMC, 0xa00000f, &ixD3F4_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F4_IRQ_BRIDGE_CNTL)/sizeof(ixD3F4_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F4_INTERRUPT_LINE", REG_SMC, 0xa00000f, &ixD3F4_INTERRUPT_LINE[0], sizeof(ixD3F4_INTERRUPT_LINE)/sizeof(ixD3F4_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD3F4_INTERRUPT_PIN", REG_SMC, 0xa00000f, &ixD3F4_INTERRUPT_PIN[0], sizeof(ixD3F4_INTERRUPT_PIN)/sizeof(ixD3F4_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD3F4_EXT_BRIDGE_CNTL", REG_SMC, 0xa000010, &ixD3F4_EXT_BRIDGE_CNTL[0], sizeof(ixD3F4_EXT_BRIDGE_CNTL)/sizeof(ixD3F4_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F4_PMI_CAP_LIST", REG_SMC, 0xa000014, &ixD3F4_PMI_CAP_LIST[0], sizeof(ixD3F4_PMI_CAP_LIST)/sizeof(ixD3F4_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PMI_CAP", REG_SMC, 0xa000014, &ixD3F4_PMI_CAP[0], sizeof(ixD3F4_PMI_CAP)/sizeof(ixD3F4_PMI_CAP[0]), 0, 0 }, + { "ixD3F4_PMI_STATUS_CNTL", REG_SMC, 0xa000015, &ixD3F4_PMI_STATUS_CNTL[0], sizeof(ixD3F4_PMI_STATUS_CNTL)/sizeof(ixD3F4_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_CAP_LIST", REG_SMC, 0xa000016, &ixD3F4_PCIE_CAP_LIST[0], sizeof(ixD3F4_PCIE_CAP_LIST)/sizeof(ixD3F4_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_CAP", REG_SMC, 0xa000016, &ixD3F4_PCIE_CAP[0], sizeof(ixD3F4_PCIE_CAP)/sizeof(ixD3F4_PCIE_CAP[0]), 0, 0 }, + { "ixD3F4_DEVICE_CAP", REG_SMC, 0xa000017, &ixD3F4_DEVICE_CAP[0], sizeof(ixD3F4_DEVICE_CAP)/sizeof(ixD3F4_DEVICE_CAP[0]), 0, 0 }, + { "ixD3F4_DEVICE_STATUS", REG_SMC, 0xa000018, &ixD3F4_DEVICE_STATUS[0], sizeof(ixD3F4_DEVICE_STATUS)/sizeof(ixD3F4_DEVICE_STATUS[0]), 0, 0 }, + { "ixD3F4_DEVICE_CNTL", REG_SMC, 0xa000018, &ixD3F4_DEVICE_CNTL[0], sizeof(ixD3F4_DEVICE_CNTL)/sizeof(ixD3F4_DEVICE_CNTL[0]), 0, 0 }, + { "ixD3F4_LINK_CAP", REG_SMC, 0xa000019, &ixD3F4_LINK_CAP[0], sizeof(ixD3F4_LINK_CAP)/sizeof(ixD3F4_LINK_CAP[0]), 0, 0 }, + { "ixD3F4_LINK_STATUS", REG_SMC, 0xa00001a, &ixD3F4_LINK_STATUS[0], sizeof(ixD3F4_LINK_STATUS)/sizeof(ixD3F4_LINK_STATUS[0]), 0, 0 }, + { "ixD3F4_LINK_CNTL", REG_SMC, 0xa00001a, &ixD3F4_LINK_CNTL[0], sizeof(ixD3F4_LINK_CNTL)/sizeof(ixD3F4_LINK_CNTL[0]), 0, 0 }, + { "ixD3F4_SLOT_CAP", REG_SMC, 0xa00001b, &ixD3F4_SLOT_CAP[0], sizeof(ixD3F4_SLOT_CAP)/sizeof(ixD3F4_SLOT_CAP[0]), 0, 0 }, + { "ixD3F4_SLOT_STATUS", REG_SMC, 0xa00001c, &ixD3F4_SLOT_STATUS[0], sizeof(ixD3F4_SLOT_STATUS)/sizeof(ixD3F4_SLOT_STATUS[0]), 0, 0 }, + { "ixD3F4_SLOT_CNTL", REG_SMC, 0xa00001c, &ixD3F4_SLOT_CNTL[0], sizeof(ixD3F4_SLOT_CNTL)/sizeof(ixD3F4_SLOT_CNTL[0]), 0, 0 }, + { "ixD3F4_ROOT_CNTL", REG_SMC, 0xa00001d, &ixD3F4_ROOT_CNTL[0], sizeof(ixD3F4_ROOT_CNTL)/sizeof(ixD3F4_ROOT_CNTL[0]), 0, 0 }, + { "ixD3F4_ROOT_CAP", REG_SMC, 0xa00001d, &ixD3F4_ROOT_CAP[0], sizeof(ixD3F4_ROOT_CAP)/sizeof(ixD3F4_ROOT_CAP[0]), 0, 0 }, + { "ixD3F4_ROOT_STATUS", REG_SMC, 0xa00001e, &ixD3F4_ROOT_STATUS[0], sizeof(ixD3F4_ROOT_STATUS)/sizeof(ixD3F4_ROOT_STATUS[0]), 0, 0 }, + { "ixD3F4_DEVICE_CAP2", REG_SMC, 0xa00001f, &ixD3F4_DEVICE_CAP2[0], sizeof(ixD3F4_DEVICE_CAP2)/sizeof(ixD3F4_DEVICE_CAP2[0]), 0, 0 }, + { "ixD3F4_DEVICE_STATUS2", REG_SMC, 0xa000020, &ixD3F4_DEVICE_STATUS2[0], sizeof(ixD3F4_DEVICE_STATUS2)/sizeof(ixD3F4_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD3F4_DEVICE_CNTL2", REG_SMC, 0xa000020, &ixD3F4_DEVICE_CNTL2[0], sizeof(ixD3F4_DEVICE_CNTL2)/sizeof(ixD3F4_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD3F4_LINK_CAP2", REG_SMC, 0xa000021, &ixD3F4_LINK_CAP2[0], sizeof(ixD3F4_LINK_CAP2)/sizeof(ixD3F4_LINK_CAP2[0]), 0, 0 }, + { "ixD3F4_LINK_STATUS2", REG_SMC, 0xa000022, &ixD3F4_LINK_STATUS2[0], sizeof(ixD3F4_LINK_STATUS2)/sizeof(ixD3F4_LINK_STATUS2[0]), 0, 0 }, + { "ixD3F4_LINK_CNTL2", REG_SMC, 0xa000022, &ixD3F4_LINK_CNTL2[0], sizeof(ixD3F4_LINK_CNTL2)/sizeof(ixD3F4_LINK_CNTL2[0]), 0, 0 }, + { "ixD3F4_SLOT_CAP2", REG_SMC, 0xa000023, &ixD3F4_SLOT_CAP2[0], sizeof(ixD3F4_SLOT_CAP2)/sizeof(ixD3F4_SLOT_CAP2[0]), 0, 0 }, + { "ixD3F4_SLOT_STATUS2", REG_SMC, 0xa000024, &ixD3F4_SLOT_STATUS2[0], sizeof(ixD3F4_SLOT_STATUS2)/sizeof(ixD3F4_SLOT_STATUS2[0]), 0, 0 }, + { "ixD3F4_SLOT_CNTL2", REG_SMC, 0xa000024, &ixD3F4_SLOT_CNTL2[0], sizeof(ixD3F4_SLOT_CNTL2)/sizeof(ixD3F4_SLOT_CNTL2[0]), 0, 0 }, + { "ixD3F4_MSI_CAP_LIST", REG_SMC, 0xa000028, &ixD3F4_MSI_CAP_LIST[0], sizeof(ixD3F4_MSI_CAP_LIST)/sizeof(ixD3F4_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_MSI_MSG_ADDR_LO", REG_SMC, 0xa000029, &ixD3F4_MSI_MSG_ADDR_LO[0], sizeof(ixD3F4_MSI_MSG_ADDR_LO)/sizeof(ixD3F4_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD3F4_MSI_MSG_ADDR_HI", REG_SMC, 0xa00002a, &ixD3F4_MSI_MSG_ADDR_HI[0], sizeof(ixD3F4_MSI_MSG_ADDR_HI)/sizeof(ixD3F4_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD3F4_MSI_MSG_DATA", REG_SMC, 0xa00002a, &ixD3F4_MSI_MSG_DATA[0], sizeof(ixD3F4_MSI_MSG_DATA)/sizeof(ixD3F4_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD3F4_MSI_MSG_DATA_64", REG_SMC, 0xa00002b, &ixD3F4_MSI_MSG_DATA_64[0], sizeof(ixD3F4_MSI_MSG_DATA_64)/sizeof(ixD3F4_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD3F4_SSID_CAP_LIST", REG_SMC, 0xa000030, &ixD3F4_SSID_CAP_LIST[0], sizeof(ixD3F4_SSID_CAP_LIST)/sizeof(ixD3F4_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_SSID_CAP", REG_SMC, 0xa000031, &ixD3F4_SSID_CAP[0], sizeof(ixD3F4_SSID_CAP)/sizeof(ixD3F4_SSID_CAP[0]), 0, 0 }, + { "ixD3F4_MSI_MAP_CAP_LIST", REG_SMC, 0xa000032, &ixD3F4_MSI_MAP_CAP_LIST[0], sizeof(ixD3F4_MSI_MAP_CAP_LIST)/sizeof(ixD3F4_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_MSI_MAP_CAP", REG_SMC, 0xa000032, &ixD3F4_MSI_MAP_CAP[0], sizeof(ixD3F4_MSI_MAP_CAP)/sizeof(ixD3F4_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD3F4_MSI_MAP_ADDR_LO", REG_SMC, 0xa000033, &ixD3F4_MSI_MAP_ADDR_LO[0], sizeof(ixD3F4_MSI_MAP_ADDR_LO)/sizeof(ixD3F4_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD3F4_MSI_MAP_ADDR_HI", REG_SMC, 0xa000034, &ixD3F4_MSI_MAP_ADDR_HI[0], sizeof(ixD3F4_MSI_MAP_ADDR_HI)/sizeof(ixD3F4_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_INDEX", REG_SMC, 0xa000038, &ixD3F4_PCIE_PORT_INDEX[0], sizeof(ixD3F4_PCIE_PORT_INDEX)/sizeof(ixD3F4_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_DATA", REG_SMC, 0xa000039, &ixD3F4_PCIE_PORT_DATA[0], sizeof(ixD3F4_PCIE_PORT_DATA)/sizeof(ixD3F4_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0xa000040, &ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0xa000041, &ixD3F4_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD3F4_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0xa000042, &ixD3F4_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD3F4_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0xa000043, &ixD3F4_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD3F4_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0xa000044, &ixD3F4_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0xa000045, &ixD3F4_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0xa000046, &ixD3F4_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_VC_STATUS", REG_SMC, 0xa000047, &ixD3F4_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F4_PCIE_PORT_VC_STATUS)/sizeof(ixD3F4_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_PORT_VC_CNTL", REG_SMC, 0xa000047, &ixD3F4_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F4_PCIE_PORT_VC_CNTL)/sizeof(ixD3F4_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0xa000048, &ixD3F4_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F4_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0xa000049, &ixD3F4_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0xa00004a, &ixD3F4_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0xa00004b, &ixD3F4_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F4_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0xa00004c, &ixD3F4_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0xa00004d, &ixD3F4_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0xa000050, &ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0xa000051, &ixD3F4_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD3F4_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0xa000052, &ixD3F4_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0xa000054, &ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0xa000055, &ixD3F4_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F4_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_UNCORR_ERR_MASK", REG_SMC, 0xa000056, &ixD3F4_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F4_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F4_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0xa000057, &ixD3F4_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F4_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD3F4_PCIE_CORR_ERR_STATUS", REG_SMC, 0xa000058, &ixD3F4_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F4_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F4_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_CORR_ERR_MASK", REG_SMC, 0xa000059, &ixD3F4_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F4_PCIE_CORR_ERR_MASK)/sizeof(ixD3F4_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F4_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0xa00005a, &ixD3F4_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F4_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F4_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_HDR_LOG0", REG_SMC, 0xa00005b, &ixD3F4_PCIE_HDR_LOG0[0], sizeof(ixD3F4_PCIE_HDR_LOG0)/sizeof(ixD3F4_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD3F4_PCIE_HDR_LOG1", REG_SMC, 0xa00005c, &ixD3F4_PCIE_HDR_LOG1[0], sizeof(ixD3F4_PCIE_HDR_LOG1)/sizeof(ixD3F4_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD3F4_PCIE_HDR_LOG2", REG_SMC, 0xa00005d, &ixD3F4_PCIE_HDR_LOG2[0], sizeof(ixD3F4_PCIE_HDR_LOG2)/sizeof(ixD3F4_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD3F4_PCIE_HDR_LOG3", REG_SMC, 0xa00005e, &ixD3F4_PCIE_HDR_LOG3[0], sizeof(ixD3F4_PCIE_HDR_LOG3)/sizeof(ixD3F4_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD3F4_PCIE_ROOT_ERR_CMD", REG_SMC, 0xa00005f, &ixD3F4_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F4_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F4_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD3F4_PCIE_ROOT_ERR_STATUS", REG_SMC, 0xa000060, &ixD3F4_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F4_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F4_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_ERR_SRC_ID", REG_SMC, 0xa000061, &ixD3F4_PCIE_ERR_SRC_ID[0], sizeof(ixD3F4_PCIE_ERR_SRC_ID)/sizeof(ixD3F4_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD3F4_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0xa000062, &ixD3F4_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD3F4_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0xa000063, &ixD3F4_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD3F4_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0xa000064, &ixD3F4_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD3F4_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0xa000065, &ixD3F4_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0xa00009c, &ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_LINK_CNTL3", REG_SMC, 0xa00009d, &ixD3F4_PCIE_LINK_CNTL3[0], sizeof(ixD3F4_PCIE_LINK_CNTL3)/sizeof(ixD3F4_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_ERROR_STATUS", REG_SMC, 0xa00009e, &ixD3F4_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F4_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F4_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0xa00009f, &ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0xa0000a0, &ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0xa0000a1, &ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0xa0000a2, &ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0xa0000a3, &ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0xa0000a4, &ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0xa0000a5, &ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0xa0000a6, &ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0xa0000a8, &ixD3F4_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_ACS_CNTL", REG_SMC, 0xa0000a9, &ixD3F4_PCIE_ACS_CNTL[0], sizeof(ixD3F4_PCIE_ACS_CNTL)/sizeof(ixD3F4_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_ACS_CAP", REG_SMC, 0xa0000a9, &ixD3F4_PCIE_ACS_CAP[0], sizeof(ixD3F4_PCIE_ACS_CAP)/sizeof(ixD3F4_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0xa0000bc, &ixD3F4_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_CNTL", REG_SMC, 0xa0000bd, &ixD3F4_PCIE_MC_CNTL[0], sizeof(ixD3F4_PCIE_MC_CNTL)/sizeof(ixD3F4_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_CAP", REG_SMC, 0xa0000bd, &ixD3F4_PCIE_MC_CAP[0], sizeof(ixD3F4_PCIE_MC_CAP)/sizeof(ixD3F4_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_ADDR0", REG_SMC, 0xa0000be, &ixD3F4_PCIE_MC_ADDR0[0], sizeof(ixD3F4_PCIE_MC_ADDR0)/sizeof(ixD3F4_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_ADDR1", REG_SMC, 0xa0000bf, &ixD3F4_PCIE_MC_ADDR1[0], sizeof(ixD3F4_PCIE_MC_ADDR1)/sizeof(ixD3F4_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_RCV0", REG_SMC, 0xa0000c0, &ixD3F4_PCIE_MC_RCV0[0], sizeof(ixD3F4_PCIE_MC_RCV0)/sizeof(ixD3F4_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_RCV1", REG_SMC, 0xa0000c1, &ixD3F4_PCIE_MC_RCV1[0], sizeof(ixD3F4_PCIE_MC_RCV1)/sizeof(ixD3F4_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_BLOCK_ALL0", REG_SMC, 0xa0000c2, &ixD3F4_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F4_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F4_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_BLOCK_ALL1", REG_SMC, 0xa0000c3, &ixD3F4_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F4_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F4_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0xa0000c4, &ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0xa0000c5, &ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0xa0000c6, &ixD3F4_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD3F4_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0xa0000c7, &ixD3F4_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "mmPCIE_LANE_4_EQUALIZATION_CNTL", REG_MMIO, 0xa1, &mmPCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_TRAINING_CNTL", REG_SMC, 0xa1, &ixD2F1_PCIE_LC_TRAINING_CNTL[0], sizeof(ixD2F1_PCIE_LC_TRAINING_CNTL)/sizeof(ixD2F1_PCIE_LC_TRAINING_CNTL[0]), 0, 0 }, + { "mmPCIE_LANE_6_EQUALIZATION_CNTL", REG_MMIO, 0xa2, &mmPCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0xa2, &ixD2F1_PCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixD2F1_PCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixD2F1_PCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 }, + { "mmPCIE_LANE_8_EQUALIZATION_CNTL", REG_MMIO, 0xa3, &mmPCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_N_FTS_CNTL", REG_SMC, 0xa3, &ixD2F1_PCIE_LC_N_FTS_CNTL[0], sizeof(ixD2F1_PCIE_LC_N_FTS_CNTL)/sizeof(ixD2F1_PCIE_LC_N_FTS_CNTL[0]), 0, 0 }, + { "mmPCIE_LANE_10_EQUALIZATION_CNTL", REG_MMIO, 0xa4, &mmPCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_SPEED_CNTL", REG_SMC, 0xa4, &ixD2F1_PCIE_LC_SPEED_CNTL[0], sizeof(ixD2F1_PCIE_LC_SPEED_CNTL)/sizeof(ixD2F1_PCIE_LC_SPEED_CNTL[0]), 0, 0 }, + { "mmPCIE_LANE_12_EQUALIZATION_CNTL", REG_MMIO, 0xa5, &mmPCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE0", REG_SMC, 0xa5, &ixD2F1_PCIE_LC_STATE0[0], sizeof(ixD2F1_PCIE_LC_STATE0)/sizeof(ixD2F1_PCIE_LC_STATE0[0]), 0, 0 }, + { "mmPCIE_LANE_14_EQUALIZATION_CNTL", REG_MMIO, 0xa6, &mmPCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE1", REG_SMC, 0xa6, &ixD2F1_PCIE_LC_STATE1[0], sizeof(ixD2F1_PCIE_LC_STATE1)/sizeof(ixD2F1_PCIE_LC_STATE1[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE2", REG_SMC, 0xa7, &ixD2F1_PCIE_LC_STATE2[0], sizeof(ixD2F1_PCIE_LC_STATE2)/sizeof(ixD2F1_PCIE_LC_STATE2[0]), 0, 0 }, + { "mmPCIE_ACS_ENH_CAP_LIST", REG_MMIO, 0xa8, &mmPCIE_ACS_ENH_CAP_LIST[0], sizeof(mmPCIE_ACS_ENH_CAP_LIST)/sizeof(mmPCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE3", REG_SMC, 0xa8, &ixD2F1_PCIE_LC_STATE3[0], sizeof(ixD2F1_PCIE_LC_STATE3)/sizeof(ixD2F1_PCIE_LC_STATE3[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE4", REG_SMC, 0xa9, &ixD2F1_PCIE_LC_STATE4[0], sizeof(ixD2F1_PCIE_LC_STATE4)/sizeof(ixD2F1_PCIE_LC_STATE4[0]), 0, 0 }, + { "mmPCIE_ACS_CNTL", REG_MMIO, 0xa9, &mmPCIE_ACS_CNTL[0], sizeof(mmPCIE_ACS_CNTL)/sizeof(mmPCIE_ACS_CNTL[0]), 0, 0 }, + { "mmPCIE_ACS_CAP", REG_MMIO, 0xa9, &mmPCIE_ACS_CAP[0], sizeof(mmPCIE_ACS_CAP)/sizeof(mmPCIE_ACS_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_STATE5", REG_SMC, 0xaa, &ixD2F1_PCIE_LC_STATE5[0], sizeof(ixD2F1_PCIE_LC_STATE5)/sizeof(ixD2F1_PCIE_LC_STATE5[0]), 0, 0 }, + { "mmPCIE_ATS_ENH_CAP_LIST", REG_MMIO, 0xac, &mmPCIE_ATS_ENH_CAP_LIST[0], sizeof(mmPCIE_ATS_ENH_CAP_LIST)/sizeof(mmPCIE_ATS_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_ATS_CNTL", REG_MMIO, 0xad, &mmPCIE_ATS_CNTL[0], sizeof(mmPCIE_ATS_CNTL)/sizeof(mmPCIE_ATS_CNTL[0]), 0, 0 }, + { "mmPCIE_ATS_CAP", REG_MMIO, 0xad, &mmPCIE_ATS_CAP[0], sizeof(mmPCIE_ATS_CAP)/sizeof(mmPCIE_ATS_CAP[0]), 0, 0 }, + { "mmADAPTER_ID", REG_MMIO, 0xb, &mmADAPTER_ID[0], sizeof(mmADAPTER_ID)/sizeof(mmADAPTER_ID[0]), 0, 0 }, + { "mmPCIE_PAGE_REQ_ENH_CAP_LIST", REG_MMIO, 0xb0, &mmPCIE_PAGE_REQ_ENH_CAP_LIST[0], sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST)/sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_VENDOR_ID", REG_SMC, 0xb000000, &ixD3F5_VENDOR_ID[0], sizeof(ixD3F5_VENDOR_ID)/sizeof(ixD3F5_VENDOR_ID[0]), 0, 0 }, + { "ixD3F5_COMMAND", REG_SMC, 0xb000001, &ixD3F5_COMMAND[0], sizeof(ixD3F5_COMMAND)/sizeof(ixD3F5_COMMAND[0]), 0, 0 }, + { "ixD3F5_STATUS", REG_SMC, 0xb000001, &ixD3F5_STATUS[0], sizeof(ixD3F5_STATUS)/sizeof(ixD3F5_STATUS[0]), 0, 0 }, + { "ixD3F5_PROG_INTERFACE", REG_SMC, 0xb000002, &ixD3F5_PROG_INTERFACE[0], sizeof(ixD3F5_PROG_INTERFACE)/sizeof(ixD3F5_PROG_INTERFACE[0]), 0, 0 }, + { "ixD3F5_REVISION_ID", REG_SMC, 0xb000002, &ixD3F5_REVISION_ID[0], sizeof(ixD3F5_REVISION_ID)/sizeof(ixD3F5_REVISION_ID[0]), 0, 0 }, + { "ixD3F5_BASE_CLASS", REG_SMC, 0xb000002, &ixD3F5_BASE_CLASS[0], sizeof(ixD3F5_BASE_CLASS)/sizeof(ixD3F5_BASE_CLASS[0]), 0, 0 }, + { "ixD3F5_SUB_CLASS", REG_SMC, 0xb000002, &ixD3F5_SUB_CLASS[0], sizeof(ixD3F5_SUB_CLASS)/sizeof(ixD3F5_SUB_CLASS[0]), 0, 0 }, + { "ixD3F5_CACHE_LINE", REG_SMC, 0xb000003, &ixD3F5_CACHE_LINE[0], sizeof(ixD3F5_CACHE_LINE)/sizeof(ixD3F5_CACHE_LINE[0]), 0, 0 }, + { "ixD3F5_LATENCY", REG_SMC, 0xb000003, &ixD3F5_LATENCY[0], sizeof(ixD3F5_LATENCY)/sizeof(ixD3F5_LATENCY[0]), 0, 0 }, + { "ixD3F5_HEADER", REG_SMC, 0xb000003, &ixD3F5_HEADER[0], sizeof(ixD3F5_HEADER)/sizeof(ixD3F5_HEADER[0]), 0, 0 }, + { "ixD3F5_BIST", REG_SMC, 0xb000003, &ixD3F5_BIST[0], sizeof(ixD3F5_BIST)/sizeof(ixD3F5_BIST[0]), 0, 0 }, + { "ixD3F5_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0xb000006, &ixD3F5_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F5_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F5_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 }, + { "ixD3F5_SECONDARY_STATUS", REG_SMC, 0xb000007, &ixD3F5_SECONDARY_STATUS[0], sizeof(ixD3F5_SECONDARY_STATUS)/sizeof(ixD3F5_SECONDARY_STATUS[0]), 0, 0 }, + { "ixD3F5_IO_BASE_LIMIT", REG_SMC, 0xb000007, &ixD3F5_IO_BASE_LIMIT[0], sizeof(ixD3F5_IO_BASE_LIMIT)/sizeof(ixD3F5_IO_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F5_MEM_BASE_LIMIT", REG_SMC, 0xb000008, &ixD3F5_MEM_BASE_LIMIT[0], sizeof(ixD3F5_MEM_BASE_LIMIT)/sizeof(ixD3F5_MEM_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F5_PREF_BASE_LIMIT", REG_SMC, 0xb000009, &ixD3F5_PREF_BASE_LIMIT[0], sizeof(ixD3F5_PREF_BASE_LIMIT)/sizeof(ixD3F5_PREF_BASE_LIMIT[0]), 0, 0 }, + { "ixD3F5_PREF_BASE_UPPER", REG_SMC, 0xb00000a, &ixD3F5_PREF_BASE_UPPER[0], sizeof(ixD3F5_PREF_BASE_UPPER)/sizeof(ixD3F5_PREF_BASE_UPPER[0]), 0, 0 }, + { "ixD3F5_PREF_LIMIT_UPPER", REG_SMC, 0xb00000b, &ixD3F5_PREF_LIMIT_UPPER[0], sizeof(ixD3F5_PREF_LIMIT_UPPER)/sizeof(ixD3F5_PREF_LIMIT_UPPER[0]), 0, 0 }, + { "ixD3F5_IO_BASE_LIMIT_HI", REG_SMC, 0xb00000c, &ixD3F5_IO_BASE_LIMIT_HI[0], sizeof(ixD3F5_IO_BASE_LIMIT_HI)/sizeof(ixD3F5_IO_BASE_LIMIT_HI[0]), 0, 0 }, + { "ixD3F5_CAP_PTR", REG_SMC, 0xb00000d, &ixD3F5_CAP_PTR[0], sizeof(ixD3F5_CAP_PTR)/sizeof(ixD3F5_CAP_PTR[0]), 0, 0 }, + { "ixD3F5_IRQ_BRIDGE_CNTL", REG_SMC, 0xb00000f, &ixD3F5_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F5_IRQ_BRIDGE_CNTL)/sizeof(ixD3F5_IRQ_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F5_INTERRUPT_LINE", REG_SMC, 0xb00000f, &ixD3F5_INTERRUPT_LINE[0], sizeof(ixD3F5_INTERRUPT_LINE)/sizeof(ixD3F5_INTERRUPT_LINE[0]), 0, 0 }, + { "ixD3F5_INTERRUPT_PIN", REG_SMC, 0xb00000f, &ixD3F5_INTERRUPT_PIN[0], sizeof(ixD3F5_INTERRUPT_PIN)/sizeof(ixD3F5_INTERRUPT_PIN[0]), 0, 0 }, + { "ixD3F5_EXT_BRIDGE_CNTL", REG_SMC, 0xb000010, &ixD3F5_EXT_BRIDGE_CNTL[0], sizeof(ixD3F5_EXT_BRIDGE_CNTL)/sizeof(ixD3F5_EXT_BRIDGE_CNTL[0]), 0, 0 }, + { "ixD3F5_PMI_CAP_LIST", REG_SMC, 0xb000014, &ixD3F5_PMI_CAP_LIST[0], sizeof(ixD3F5_PMI_CAP_LIST)/sizeof(ixD3F5_PMI_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PMI_CAP", REG_SMC, 0xb000014, &ixD3F5_PMI_CAP[0], sizeof(ixD3F5_PMI_CAP)/sizeof(ixD3F5_PMI_CAP[0]), 0, 0 }, + { "ixD3F5_PMI_STATUS_CNTL", REG_SMC, 0xb000015, &ixD3F5_PMI_STATUS_CNTL[0], sizeof(ixD3F5_PMI_STATUS_CNTL)/sizeof(ixD3F5_PMI_STATUS_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_CAP_LIST", REG_SMC, 0xb000016, &ixD3F5_PCIE_CAP_LIST[0], sizeof(ixD3F5_PCIE_CAP_LIST)/sizeof(ixD3F5_PCIE_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_CAP", REG_SMC, 0xb000016, &ixD3F5_PCIE_CAP[0], sizeof(ixD3F5_PCIE_CAP)/sizeof(ixD3F5_PCIE_CAP[0]), 0, 0 }, + { "ixD3F5_DEVICE_CAP", REG_SMC, 0xb000017, &ixD3F5_DEVICE_CAP[0], sizeof(ixD3F5_DEVICE_CAP)/sizeof(ixD3F5_DEVICE_CAP[0]), 0, 0 }, + { "ixD3F5_DEVICE_STATUS", REG_SMC, 0xb000018, &ixD3F5_DEVICE_STATUS[0], sizeof(ixD3F5_DEVICE_STATUS)/sizeof(ixD3F5_DEVICE_STATUS[0]), 0, 0 }, + { "ixD3F5_DEVICE_CNTL", REG_SMC, 0xb000018, &ixD3F5_DEVICE_CNTL[0], sizeof(ixD3F5_DEVICE_CNTL)/sizeof(ixD3F5_DEVICE_CNTL[0]), 0, 0 }, + { "ixD3F5_LINK_CAP", REG_SMC, 0xb000019, &ixD3F5_LINK_CAP[0], sizeof(ixD3F5_LINK_CAP)/sizeof(ixD3F5_LINK_CAP[0]), 0, 0 }, + { "ixD3F5_LINK_STATUS", REG_SMC, 0xb00001a, &ixD3F5_LINK_STATUS[0], sizeof(ixD3F5_LINK_STATUS)/sizeof(ixD3F5_LINK_STATUS[0]), 0, 0 }, + { "ixD3F5_LINK_CNTL", REG_SMC, 0xb00001a, &ixD3F5_LINK_CNTL[0], sizeof(ixD3F5_LINK_CNTL)/sizeof(ixD3F5_LINK_CNTL[0]), 0, 0 }, + { "ixD3F5_SLOT_CAP", REG_SMC, 0xb00001b, &ixD3F5_SLOT_CAP[0], sizeof(ixD3F5_SLOT_CAP)/sizeof(ixD3F5_SLOT_CAP[0]), 0, 0 }, + { "ixD3F5_SLOT_STATUS", REG_SMC, 0xb00001c, &ixD3F5_SLOT_STATUS[0], sizeof(ixD3F5_SLOT_STATUS)/sizeof(ixD3F5_SLOT_STATUS[0]), 0, 0 }, + { "ixD3F5_SLOT_CNTL", REG_SMC, 0xb00001c, &ixD3F5_SLOT_CNTL[0], sizeof(ixD3F5_SLOT_CNTL)/sizeof(ixD3F5_SLOT_CNTL[0]), 0, 0 }, + { "ixD3F5_ROOT_CNTL", REG_SMC, 0xb00001d, &ixD3F5_ROOT_CNTL[0], sizeof(ixD3F5_ROOT_CNTL)/sizeof(ixD3F5_ROOT_CNTL[0]), 0, 0 }, + { "ixD3F5_ROOT_CAP", REG_SMC, 0xb00001d, &ixD3F5_ROOT_CAP[0], sizeof(ixD3F5_ROOT_CAP)/sizeof(ixD3F5_ROOT_CAP[0]), 0, 0 }, + { "ixD3F5_ROOT_STATUS", REG_SMC, 0xb00001e, &ixD3F5_ROOT_STATUS[0], sizeof(ixD3F5_ROOT_STATUS)/sizeof(ixD3F5_ROOT_STATUS[0]), 0, 0 }, + { "ixD3F5_DEVICE_CAP2", REG_SMC, 0xb00001f, &ixD3F5_DEVICE_CAP2[0], sizeof(ixD3F5_DEVICE_CAP2)/sizeof(ixD3F5_DEVICE_CAP2[0]), 0, 0 }, + { "ixD3F5_DEVICE_STATUS2", REG_SMC, 0xb000020, &ixD3F5_DEVICE_STATUS2[0], sizeof(ixD3F5_DEVICE_STATUS2)/sizeof(ixD3F5_DEVICE_STATUS2[0]), 0, 0 }, + { "ixD3F5_DEVICE_CNTL2", REG_SMC, 0xb000020, &ixD3F5_DEVICE_CNTL2[0], sizeof(ixD3F5_DEVICE_CNTL2)/sizeof(ixD3F5_DEVICE_CNTL2[0]), 0, 0 }, + { "ixD3F5_LINK_CAP2", REG_SMC, 0xb000021, &ixD3F5_LINK_CAP2[0], sizeof(ixD3F5_LINK_CAP2)/sizeof(ixD3F5_LINK_CAP2[0]), 0, 0 }, + { "ixD3F5_LINK_STATUS2", REG_SMC, 0xb000022, &ixD3F5_LINK_STATUS2[0], sizeof(ixD3F5_LINK_STATUS2)/sizeof(ixD3F5_LINK_STATUS2[0]), 0, 0 }, + { "ixD3F5_LINK_CNTL2", REG_SMC, 0xb000022, &ixD3F5_LINK_CNTL2[0], sizeof(ixD3F5_LINK_CNTL2)/sizeof(ixD3F5_LINK_CNTL2[0]), 0, 0 }, + { "ixD3F5_SLOT_CAP2", REG_SMC, 0xb000023, &ixD3F5_SLOT_CAP2[0], sizeof(ixD3F5_SLOT_CAP2)/sizeof(ixD3F5_SLOT_CAP2[0]), 0, 0 }, + { "ixD3F5_SLOT_STATUS2", REG_SMC, 0xb000024, &ixD3F5_SLOT_STATUS2[0], sizeof(ixD3F5_SLOT_STATUS2)/sizeof(ixD3F5_SLOT_STATUS2[0]), 0, 0 }, + { "ixD3F5_SLOT_CNTL2", REG_SMC, 0xb000024, &ixD3F5_SLOT_CNTL2[0], sizeof(ixD3F5_SLOT_CNTL2)/sizeof(ixD3F5_SLOT_CNTL2[0]), 0, 0 }, + { "ixD3F5_MSI_CAP_LIST", REG_SMC, 0xb000028, &ixD3F5_MSI_CAP_LIST[0], sizeof(ixD3F5_MSI_CAP_LIST)/sizeof(ixD3F5_MSI_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_MSI_MSG_ADDR_LO", REG_SMC, 0xb000029, &ixD3F5_MSI_MSG_ADDR_LO[0], sizeof(ixD3F5_MSI_MSG_ADDR_LO)/sizeof(ixD3F5_MSI_MSG_ADDR_LO[0]), 0, 0 }, + { "ixD3F5_MSI_MSG_ADDR_HI", REG_SMC, 0xb00002a, &ixD3F5_MSI_MSG_ADDR_HI[0], sizeof(ixD3F5_MSI_MSG_ADDR_HI)/sizeof(ixD3F5_MSI_MSG_ADDR_HI[0]), 0, 0 }, + { "ixD3F5_MSI_MSG_DATA", REG_SMC, 0xb00002a, &ixD3F5_MSI_MSG_DATA[0], sizeof(ixD3F5_MSI_MSG_DATA)/sizeof(ixD3F5_MSI_MSG_DATA[0]), 0, 0 }, + { "ixD3F5_MSI_MSG_DATA_64", REG_SMC, 0xb00002b, &ixD3F5_MSI_MSG_DATA_64[0], sizeof(ixD3F5_MSI_MSG_DATA_64)/sizeof(ixD3F5_MSI_MSG_DATA_64[0]), 0, 0 }, + { "ixD3F5_SSID_CAP_LIST", REG_SMC, 0xb000030, &ixD3F5_SSID_CAP_LIST[0], sizeof(ixD3F5_SSID_CAP_LIST)/sizeof(ixD3F5_SSID_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_SSID_CAP", REG_SMC, 0xb000031, &ixD3F5_SSID_CAP[0], sizeof(ixD3F5_SSID_CAP)/sizeof(ixD3F5_SSID_CAP[0]), 0, 0 }, + { "ixD3F5_MSI_MAP_CAP_LIST", REG_SMC, 0xb000032, &ixD3F5_MSI_MAP_CAP_LIST[0], sizeof(ixD3F5_MSI_MAP_CAP_LIST)/sizeof(ixD3F5_MSI_MAP_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_MSI_MAP_CAP", REG_SMC, 0xb000032, &ixD3F5_MSI_MAP_CAP[0], sizeof(ixD3F5_MSI_MAP_CAP)/sizeof(ixD3F5_MSI_MAP_CAP[0]), 0, 0 }, + { "ixD3F5_MSI_MAP_ADDR_LO", REG_SMC, 0xb000033, &ixD3F5_MSI_MAP_ADDR_LO[0], sizeof(ixD3F5_MSI_MAP_ADDR_LO)/sizeof(ixD3F5_MSI_MAP_ADDR_LO[0]), 0, 0 }, + { "ixD3F5_MSI_MAP_ADDR_HI", REG_SMC, 0xb000034, &ixD3F5_MSI_MAP_ADDR_HI[0], sizeof(ixD3F5_MSI_MAP_ADDR_HI)/sizeof(ixD3F5_MSI_MAP_ADDR_HI[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_INDEX", REG_SMC, 0xb000038, &ixD3F5_PCIE_PORT_INDEX[0], sizeof(ixD3F5_PCIE_PORT_INDEX)/sizeof(ixD3F5_PCIE_PORT_INDEX[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_DATA", REG_SMC, 0xb000039, &ixD3F5_PCIE_PORT_DATA[0], sizeof(ixD3F5_PCIE_PORT_DATA)/sizeof(ixD3F5_PCIE_PORT_DATA[0]), 0, 0 }, + { "ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0xb000040, &ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0xb000041, &ixD3F5_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 }, + { "ixD3F5_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0xb000042, &ixD3F5_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 }, + { "ixD3F5_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0xb000043, &ixD3F5_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 }, + { "ixD3F5_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0xb000044, &ixD3F5_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0xb000045, &ixD3F5_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0xb000046, &ixD3F5_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_VC_STATUS", REG_SMC, 0xb000047, &ixD3F5_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F5_PCIE_PORT_VC_STATUS)/sizeof(ixD3F5_PCIE_PORT_VC_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_PORT_VC_CNTL", REG_SMC, 0xb000047, &ixD3F5_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F5_PCIE_PORT_VC_CNTL)/sizeof(ixD3F5_PCIE_PORT_VC_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0xb000048, &ixD3F5_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F5_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0xb000049, &ixD3F5_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0xb00004a, &ixD3F5_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0xb00004b, &ixD3F5_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 }, + { "ixD3F5_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0xb00004c, &ixD3F5_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0xb00004d, &ixD3F5_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0xb000050, &ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0xb000051, &ixD3F5_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 }, + { "ixD3F5_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0xb000052, &ixD3F5_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 }, + { "ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0xb000054, &ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0xb000055, &ixD3F5_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F5_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_UNCORR_ERR_MASK", REG_SMC, 0xb000056, &ixD3F5_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F5_PCIE_UNCORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F5_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0xb000057, &ixD3F5_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F5_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 }, + { "ixD3F5_PCIE_CORR_ERR_STATUS", REG_SMC, 0xb000058, &ixD3F5_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F5_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F5_PCIE_CORR_ERR_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_CORR_ERR_MASK", REG_SMC, 0xb000059, &ixD3F5_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F5_PCIE_CORR_ERR_MASK)/sizeof(ixD3F5_PCIE_CORR_ERR_MASK[0]), 0, 0 }, + { "ixD3F5_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0xb00005a, &ixD3F5_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F5_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F5_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_HDR_LOG0", REG_SMC, 0xb00005b, &ixD3F5_PCIE_HDR_LOG0[0], sizeof(ixD3F5_PCIE_HDR_LOG0)/sizeof(ixD3F5_PCIE_HDR_LOG0[0]), 0, 0 }, + { "ixD3F5_PCIE_HDR_LOG1", REG_SMC, 0xb00005c, &ixD3F5_PCIE_HDR_LOG1[0], sizeof(ixD3F5_PCIE_HDR_LOG1)/sizeof(ixD3F5_PCIE_HDR_LOG1[0]), 0, 0 }, + { "ixD3F5_PCIE_HDR_LOG2", REG_SMC, 0xb00005d, &ixD3F5_PCIE_HDR_LOG2[0], sizeof(ixD3F5_PCIE_HDR_LOG2)/sizeof(ixD3F5_PCIE_HDR_LOG2[0]), 0, 0 }, + { "ixD3F5_PCIE_HDR_LOG3", REG_SMC, 0xb00005e, &ixD3F5_PCIE_HDR_LOG3[0], sizeof(ixD3F5_PCIE_HDR_LOG3)/sizeof(ixD3F5_PCIE_HDR_LOG3[0]), 0, 0 }, + { "ixD3F5_PCIE_ROOT_ERR_CMD", REG_SMC, 0xb00005f, &ixD3F5_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F5_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F5_PCIE_ROOT_ERR_CMD[0]), 0, 0 }, + { "ixD3F5_PCIE_ROOT_ERR_STATUS", REG_SMC, 0xb000060, &ixD3F5_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F5_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F5_PCIE_ROOT_ERR_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_ERR_SRC_ID", REG_SMC, 0xb000061, &ixD3F5_PCIE_ERR_SRC_ID[0], sizeof(ixD3F5_PCIE_ERR_SRC_ID)/sizeof(ixD3F5_PCIE_ERR_SRC_ID[0]), 0, 0 }, + { "ixD3F5_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0xb000062, &ixD3F5_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 }, + { "ixD3F5_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0xb000063, &ixD3F5_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 }, + { "ixD3F5_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0xb000064, &ixD3F5_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 }, + { "ixD3F5_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0xb000065, &ixD3F5_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 }, + { "ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0xb00009c, &ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_LINK_CNTL3", REG_SMC, 0xb00009d, &ixD3F5_PCIE_LINK_CNTL3[0], sizeof(ixD3F5_PCIE_LINK_CNTL3)/sizeof(ixD3F5_PCIE_LINK_CNTL3[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_ERROR_STATUS", REG_SMC, 0xb00009e, &ixD3F5_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F5_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F5_PCIE_LANE_ERROR_STATUS[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0xb00009f, &ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0xb0000a0, &ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0xb0000a1, &ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0xb0000a2, &ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0xb0000a3, &ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0xb0000a4, &ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0xb0000a5, &ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0xb0000a6, &ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0xb0000a8, &ixD3F5_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_ACS_CNTL", REG_SMC, 0xb0000a9, &ixD3F5_PCIE_ACS_CNTL[0], sizeof(ixD3F5_PCIE_ACS_CNTL)/sizeof(ixD3F5_PCIE_ACS_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_ACS_CAP", REG_SMC, 0xb0000a9, &ixD3F5_PCIE_ACS_CAP[0], sizeof(ixD3F5_PCIE_ACS_CAP)/sizeof(ixD3F5_PCIE_ACS_CAP[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0xb0000bc, &ixD3F5_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_CNTL", REG_SMC, 0xb0000bd, &ixD3F5_PCIE_MC_CNTL[0], sizeof(ixD3F5_PCIE_MC_CNTL)/sizeof(ixD3F5_PCIE_MC_CNTL[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_CAP", REG_SMC, 0xb0000bd, &ixD3F5_PCIE_MC_CAP[0], sizeof(ixD3F5_PCIE_MC_CAP)/sizeof(ixD3F5_PCIE_MC_CAP[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_ADDR0", REG_SMC, 0xb0000be, &ixD3F5_PCIE_MC_ADDR0[0], sizeof(ixD3F5_PCIE_MC_ADDR0)/sizeof(ixD3F5_PCIE_MC_ADDR0[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_ADDR1", REG_SMC, 0xb0000bf, &ixD3F5_PCIE_MC_ADDR1[0], sizeof(ixD3F5_PCIE_MC_ADDR1)/sizeof(ixD3F5_PCIE_MC_ADDR1[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_RCV0", REG_SMC, 0xb0000c0, &ixD3F5_PCIE_MC_RCV0[0], sizeof(ixD3F5_PCIE_MC_RCV0)/sizeof(ixD3F5_PCIE_MC_RCV0[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_RCV1", REG_SMC, 0xb0000c1, &ixD3F5_PCIE_MC_RCV1[0], sizeof(ixD3F5_PCIE_MC_RCV1)/sizeof(ixD3F5_PCIE_MC_RCV1[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_BLOCK_ALL0", REG_SMC, 0xb0000c2, &ixD3F5_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F5_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F5_PCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_BLOCK_ALL1", REG_SMC, 0xb0000c3, &ixD3F5_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F5_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F5_PCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0xb0000c4, &ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0xb0000c5, &ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0xb0000c6, &ixD3F5_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 }, + { "ixD3F5_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0xb0000c7, &ixD3F5_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 }, + { "mmPCIE_PAGE_REQ_STATUS", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_STATUS[0], sizeof(mmPCIE_PAGE_REQ_STATUS)/sizeof(mmPCIE_PAGE_REQ_STATUS[0]), 0, 0 }, + { "mmPCIE_PAGE_REQ_CNTL", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_CNTL[0], sizeof(mmPCIE_PAGE_REQ_CNTL)/sizeof(mmPCIE_PAGE_REQ_CNTL[0]), 0, 0 }, + { "mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY", REG_MMIO, 0xb2, &mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0xb2, &ixD2F1_PCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixD2F1_PCIE_LC_BW_CHANGE_CNTL)/sizeof(ixD2F1_PCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 }, + { "mmPCIE_OUTSTAND_PAGE_REQ_ALLOC", REG_MMIO, 0xb3, &mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CDR_CNTL", REG_SMC, 0xb3, &ixD2F1_PCIE_LC_CDR_CNTL[0], sizeof(ixD2F1_PCIE_LC_CDR_CNTL)/sizeof(ixD2F1_PCIE_LC_CDR_CNTL[0]), 0, 0 }, + { "mmPCIE_PASID_ENH_CAP_LIST", REG_MMIO, 0xb4, &mmPCIE_PASID_ENH_CAP_LIST[0], sizeof(mmPCIE_PASID_ENH_CAP_LIST)/sizeof(mmPCIE_PASID_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_LANE_CNTL", REG_SMC, 0xb4, &ixD2F1_PCIE_LC_LANE_CNTL[0], sizeof(ixD2F1_PCIE_LC_LANE_CNTL)/sizeof(ixD2F1_PCIE_LC_LANE_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CNTL3", REG_SMC, 0xb5, &ixD2F1_PCIE_LC_CNTL3[0], sizeof(ixD2F1_PCIE_LC_CNTL3)/sizeof(ixD2F1_PCIE_LC_CNTL3[0]), 0, 0 }, + { "mmPCIE_PASID_CNTL", REG_MMIO, 0xb5, &mmPCIE_PASID_CNTL[0], sizeof(mmPCIE_PASID_CNTL)/sizeof(mmPCIE_PASID_CNTL[0]), 0, 0 }, + { "mmPCIE_PASID_CAP", REG_MMIO, 0xb5, &mmPCIE_PASID_CAP[0], sizeof(mmPCIE_PASID_CAP)/sizeof(mmPCIE_PASID_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CNTL4", REG_SMC, 0xb6, &ixD2F1_PCIE_LC_CNTL4[0], sizeof(ixD2F1_PCIE_LC_CNTL4)/sizeof(ixD2F1_PCIE_LC_CNTL4[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CNTL5", REG_SMC, 0xb7, &ixD2F1_PCIE_LC_CNTL5[0], sizeof(ixD2F1_PCIE_LC_CNTL5)/sizeof(ixD2F1_PCIE_LC_CNTL5[0]), 0, 0 }, + { "mmPCIE_TPH_REQR_ENH_CAP_LIST", REG_MMIO, 0xb8, &mmPCIE_TPH_REQR_ENH_CAP_LIST[0], sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST)/sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_FORCE_COEFF", REG_SMC, 0xb8, &ixD2F1_PCIE_LC_FORCE_COEFF[0], sizeof(ixD2F1_PCIE_LC_FORCE_COEFF)/sizeof(ixD2F1_PCIE_LC_FORCE_COEFF[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0xb9, &ixD2F1_PCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixD2F1_PCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixD2F1_PCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 }, + { "mmPCIE_TPH_REQR_CAP", REG_MMIO, 0xb9, &mmPCIE_TPH_REQR_CAP[0], sizeof(mmPCIE_TPH_REQR_CAP)/sizeof(mmPCIE_TPH_REQR_CAP[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0xba, &ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 }, + { "mmPCIE_TPH_REQR_CNTL", REG_MMIO, 0xba, &mmPCIE_TPH_REQR_CNTL[0], sizeof(mmPCIE_TPH_REQR_CNTL)/sizeof(mmPCIE_TPH_REQR_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIE_LC_CNTL6", REG_SMC, 0xbb, &ixD2F1_PCIE_LC_CNTL6[0], sizeof(ixD2F1_PCIE_LC_CNTL6)/sizeof(ixD2F1_PCIE_LC_CNTL6[0]), 0, 0 }, + { "mmPCIE_MC_ENH_CAP_LIST", REG_MMIO, 0xbc, &mmPCIE_MC_ENH_CAP_LIST[0], sizeof(mmPCIE_MC_ENH_CAP_LIST)/sizeof(mmPCIE_MC_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_MC_CNTL", REG_MMIO, 0xbd, &mmPCIE_MC_CNTL[0], sizeof(mmPCIE_MC_CNTL)/sizeof(mmPCIE_MC_CNTL[0]), 0, 0 }, + { "mmPCIE_MC_CAP", REG_MMIO, 0xbd, &mmPCIE_MC_CAP[0], sizeof(mmPCIE_MC_CAP)/sizeof(mmPCIE_MC_CAP[0]), 0, 0 }, + { "mmPCIE_MC_ADDR0", REG_MMIO, 0xbe, &mmPCIE_MC_ADDR0[0], sizeof(mmPCIE_MC_ADDR0)/sizeof(mmPCIE_MC_ADDR0[0]), 0, 0 }, + { "mmPCIE_MC_ADDR1", REG_MMIO, 0xbf, &mmPCIE_MC_ADDR1[0], sizeof(mmPCIE_MC_ADDR1)/sizeof(mmPCIE_MC_ADDR1[0]), 0, 0 }, + { "mmROM_BASE_ADDR", REG_MMIO, 0xc, &mmROM_BASE_ADDR[0], sizeof(mmROM_BASE_ADDR)/sizeof(mmROM_BASE_ADDR[0]), 0, 0 }, + { "mmPCIE_INDEX_2", REG_MMIO, 0xc, &mmPCIE_INDEX_2[0], sizeof(mmPCIE_INDEX_2)/sizeof(mmPCIE_INDEX_2[0]), 0, 0 }, + { "ixD2F1_PCIEP_STRAP_LC", REG_SMC, 0xc0, &ixD2F1_PCIEP_STRAP_LC[0], sizeof(ixD2F1_PCIEP_STRAP_LC)/sizeof(ixD2F1_PCIEP_STRAP_LC[0]), 0, 0 }, + { "mmPCIE_MC_RCV0", REG_MMIO, 0xc0, &mmPCIE_MC_RCV0[0], sizeof(mmPCIE_MC_RCV0)/sizeof(mmPCIE_MC_RCV0[0]), 0, 0 }, + { "ixD2F1_PCIEP_STRAP_MISC", REG_SMC, 0xc1, &ixD2F1_PCIEP_STRAP_MISC[0], sizeof(ixD2F1_PCIEP_STRAP_MISC)/sizeof(ixD2F1_PCIEP_STRAP_MISC[0]), 0, 0 }, + { "mmPCIE_MC_RCV1", REG_MMIO, 0xc1, &mmPCIE_MC_RCV1[0], sizeof(mmPCIE_MC_RCV1)/sizeof(mmPCIE_MC_RCV1[0]), 0, 0 }, + { "mmPCIE_MC_BLOCK_ALL0", REG_MMIO, 0xc2, &mmPCIE_MC_BLOCK_ALL0[0], sizeof(mmPCIE_MC_BLOCK_ALL0)/sizeof(mmPCIE_MC_BLOCK_ALL0[0]), 0, 0 }, + { "mmPCIE_MC_BLOCK_ALL1", REG_MMIO, 0xc3, &mmPCIE_MC_BLOCK_ALL1[0], sizeof(mmPCIE_MC_BLOCK_ALL1)/sizeof(mmPCIE_MC_BLOCK_ALL1[0]), 0, 0 }, + { "mmPCIE_MC_BLOCK_UNTRANSLATED_0", REG_MMIO, 0xc4, &mmPCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 }, + { "mmPCIE_MC_BLOCK_UNTRANSLATED_1", REG_MMIO, 0xc5, &mmPCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 }, + { "mmPCIE_LTR_ENH_CAP_LIST", REG_MMIO, 0xc8, &mmPCIE_LTR_ENH_CAP_LIST[0], sizeof(mmPCIE_LTR_ENH_CAP_LIST)/sizeof(mmPCIE_LTR_ENH_CAP_LIST[0]), 0, 0 }, + { "mmPCIE_LTR_CAP", REG_MMIO, 0xc9, &mmPCIE_LTR_CAP[0], sizeof(mmPCIE_LTR_CAP)/sizeof(mmPCIE_LTR_CAP[0]), 0, 0 }, + { "mmPCIE_DATA_2", REG_MMIO, 0xd, &mmPCIE_DATA_2[0], sizeof(mmPCIE_DATA_2)/sizeof(mmPCIE_DATA_2[0]), 0, 0 }, + { "mmCAP_PTR", REG_MMIO, 0xd, &mmCAP_PTR[0], sizeof(mmCAP_PTR)/sizeof(mmCAP_PTR[0]), 0, 0 }, + { "ixD2F1_PCIEP_BCH_ECC_CNTL", REG_SMC, 0xd0, &ixD2F1_PCIEP_BCH_ECC_CNTL[0], sizeof(ixD2F1_PCIEP_BCH_ECC_CNTL)/sizeof(ixD2F1_PCIEP_BCH_ECC_CNTL[0]), 0, 0 }, + { "ixD2F1_PCIEP_HPGI_PRIVATE", REG_SMC, 0xd2, &ixD2F1_PCIEP_HPGI_PRIVATE[0], sizeof(ixD2F1_PCIEP_HPGI_PRIVATE)/sizeof(ixD2F1_PCIEP_HPGI_PRIVATE[0]), 0, 0 }, + { "ixD2F1_PCIEP_HPGI", REG_SMC, 0xda, &ixD2F1_PCIEP_HPGI[0], sizeof(ixD2F1_PCIEP_HPGI)/sizeof(ixD2F1_PCIEP_HPGI[0]), 0, 0 }, + { "mmPCIE_INDEX", REG_MMIO, 0xe, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 }, + { "mmINTERRUPT_LINE", REG_MMIO, 0xf, &mmINTERRUPT_LINE[0], sizeof(mmINTERRUPT_LINE)/sizeof(mmINTERRUPT_LINE[0]), 0, 0 }, + { "mmINTERRUPT_PIN", REG_MMIO, 0xf, &mmINTERRUPT_PIN[0], sizeof(mmINTERRUPT_PIN)/sizeof(mmINTERRUPT_PIN[0]), 0, 0 }, + { "mmMAX_LATENCY", REG_MMIO, 0xf, &mmMAX_LATENCY[0], sizeof(mmMAX_LATENCY)/sizeof(mmMAX_LATENCY[0]), 0, 0 }, + { "mmMIN_GRANT", REG_MMIO, 0xf, &mmMIN_GRANT[0], sizeof(mmMIN_GRANT)/sizeof(mmMIN_GRANT[0]), 0, 0 }, |