path: root/rnndb/falcon.xml

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
	xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
	xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<import file="copyright.xml"/>

<import file="nvchipsets.xml" />
<import file="g80_defs.xml" />

<bitset name="falcon_intr" inline="yes">
	<bitfield pos="0" name="PERIODIC"/>
	<bitfield pos="1" name="WATCHDOG"/>
	<bitfield pos="2" name="FIFO_DATA"/>
	<bitfield pos="3" name="CHANNEL_SWITCH"/>
	<bitfield pos="4" name="EXIT"/>
	<bitfield pos="5" name="PAUSE"/>
	<bitfield pos="6" name="USER1"/>
	<bitfield pos="7" name="USER2"/>
</bitset>

<bitset name="FALCON_BREAK_MASK">
	<bitfield pos="7" name="BREAKPOINT"/>
</bitset>

<group name="falcon_base">
	<reg32 offset="0x000" name="INTR_TRIGGER" access="w" type="falcon_intr"/>
	<reg32 offset="0x004" name="INTR_ACK" access="w" type="falcon_intr"/>
	<reg32 offset="0x008" name="INTR" access="r" type="falcon_intr"/>
	<reg32 offset="0x010" name="INTR_EN_SET" access="w" type="falcon_intr"/>
	<reg32 offset="0x014" name="INTR_EN_CLR" access="w" type="falcon_intr"/>
	<reg32 offset="0x018" name="INTR_EN" access="r" type="falcon_intr"/>
	<reg32 offset="0x01c" name="INTR_ROUTING">
		<doc>
			Each interrupt has 2 bits in here, and its handling
			is determined by their combination:
			<ul>
			<li>M1 = 0, M2 = 0: falcon interrupt 0</li>
			<li>M1 = 0, M2 = 1: falcon interrupt 1</li>
			<li>M1 = 1, M2 = 0: PMC HOST/DAEMON interrupt</li>
			<li>M1 = 1, M2 = 1: PMC UNK1 interrupt [GF100+ only]</li>
			</ul>
		</doc>
		<bitfield low="0" high="15" name="M1" type="falcon_intr"/>
		<bitfield low="16" high="31" name="M2" type="falcon_intr"/>
	</reg32>
	<!-- the following are conspiciously absent from PGRAPH. -->
	<reg32 offset="0x020" name="PERIODIC_PERIOD"/>
	<reg32 offset="0x024" name="PERIODIC_TIME"/>
	<reg32 offset="0x028" name="PERIODIC_ENABLE"/>
	<reg32 offset="0x02c" name="TIME_LOW"/>
	<reg32 offset="0x030" name="TIME_HIGH"/>
	<reg32 offset="0x034" name="WATCHDOG_TIME"/>
	<reg32 offset="0x038" name="WATCHDOG_ENABLE"/>

	<reg32 offset="0x040" name="SCRATCH0"/>
	<reg32 offset="0x044" name="SCRATCH1"/>
	<reg32 offset="0x048" name="ACCESS_EN">
		<bitfield pos="0" name="CHANNEL_SWITCH"/>
		<bitfield pos="1" name="FIFO"/>
	</reg32>
	<reg32 offset="0x04c" name="STATUS_BUSY"/> <!-- bits depend on engine -->

	<!-- the following two are also conspiciously absent from PGRAPH. -->
	<reg32 offset="0x050" name="CHANNEL_CUR">
		<bitfield name="CHAN" high="29" low="0" type="g80_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x054" name="CHANNEL_NEXT">
		<bitfield name="CHAN" high="29" low="0" type="g80_channel"/>
		<bitfield name="VALID" pos="30"/>
	</reg32>
	<reg32 offset="0x058" name="CHANNEL_TRIGGER">
		<bitfield pos="0" name="UNLOAD"/>
		<bitfield pos="1" name="LOAD"/>
	</reg32>
	<reg32 offset="0x05c" name="STATUS_PAUSE">
		<bitfield low="0" high="15" name="PAUSED_MASK"/>
		<bitfield pos="16" name="FAULTED"/>
		<bitfield pos="17" name="PAUSED"/>
	</reg32>
	<reg32 offset="0x060" name="VM_SUPERVISOR" type="boolean"/>
	<reg32 offset="0x064" name="FIFO_DATA"/>
	<reg32 offset="0x068" name="FIFO_CMD">
		<bitfield low="0" high="10" name="MTHD" shr="2"/>
		<bitfield low="11" high="13" name="SUBC"/>
		<bitfield pos="14" name="IB_UNK40"/>
		<bitfield pos="15" name="UNK15" variants="GF119-"/> <!-- v4+ -->
		<bitfield pos="16" name="WR_PENDING" variants="GF119-"/> <!-- v4+ -->
	</reg32>
	<reg32 offset="0x06c" name="FIFO_DATA_WR" variants="GF119-"/> <!-- v4+ -->
	<reg32 offset="0x070" name="FIFO_OCCUPIED"/>
	<reg32 offset="0x074" name="FIFO_ACK">
		<doc>Write 1 to go to next command.</doc>
	</reg32>
	<reg32 offset="0x078" name="FIFO_LIMIT">
		<doc>Up to 0x10</doc>
	</reg32>
	<reg32 offset="0x07c" name="SUBENGINE_RESET"/>
	<reg32 offset="0x080" name="SCRATCH2"/>
	<reg32 offset="0x084" name="SCRATCH3"/>
	<reg32 offset="0x088" name="PM_SIGNAL">
		<bitfield pos="0" name="0"/>
		<bitfield pos="1" name="1"/>
		<bitfield pos="2" name="2"/>
		<bitfield pos="3" name="3"/>
		<bitfield pos="4" name="4"/>
		<bitfield pos="5" name="5"/>
		<bitfield pos="16" name="WRCACHE_FLUSH"/>
		<bitfield pos="17" name="PM_TRIGGER"/>
	</reg32>
	<enum name="falcon_pm_mode" inline="yes">
		<value value="0" name="PULSE"/>
		<value value="1" name="CONTINUOUS"/>
	</enum>
	<reg32 offset="0x08c" name="PM_MODE">
		<bitfield pos="0" name="0" type="falcon_pm_mode"/>
		<bitfield pos="1" name="1" type="falcon_pm_mode"/>
		<bitfield pos="2" name="2" type="falcon_pm_mode"/>
		<bitfield pos="3" name="3" type="falcon_pm_mode"/>
		<bitfield pos="4" name="4" type="falcon_pm_mode"/>
		<bitfield pos="5" name="5" type="falcon_pm_mode"/>
	</reg32>
	<reg32 offset="0x090" name="UNK090">
		<bitfield low="0" high="15" name="UNK0"/>
		<bitfield pos="16" name="UNK16" variants="GT215-"/>
	</reg32>
	<reg32 offset="0x094" name="UNK094" variants="GT215-"/>
	<reg32 offset="0x098" name="BREAKPOINT" length="2" variants="GT215-">
		<bitfield low="0" high="23" name="PC"/>
		<bitfield pos="30" name="SKIP_ONE"/>
		<bitfield pos="31" name="ENABLED"/>
	</reg32>
	<reg32 offset="0x0a0" name="UNK0A0" variants="GT215-" type="boolean"/>
	<reg32 offset="0x0a4" name="PAUSE_CONTROL" variants="GT215-">
		<bitfield pos="0" name="UNK0"/>
		<bitfield pos="1" name="PAUSE_TRIGGER"/>
		<bitfield pos="2" name="UNPAUSE_TRIGGER"/>
		<bitfield pos="8" name="PAUSE_REQ"/>
		<bitfield pos="9" name="PAUSE_DONE"/>
	</reg32>
	<reg32 offset="0x0a8" name="PM_SEL_V4" variants="GF119-"> <!-- v4+ only -->
		<!-- XXX: bitfields probably wrong for v4 -->
		<bitfield low="0" high="3" name="0"/> <!-- from ??? -->
		<bitfield low="4" high="7" name="1"/> <!-- from ??? -->
		<bitfield low="8" high="11" name="2"/> <!-- from USER signals -->
		<bitfield low="12" high="15" name="3"/> <!-- from USER signals -->
		<bitfield low="17" high="31" name="UNK17"/>
	</reg32>
	<reg32 offset="0x0ac" name="HOST_IO_INDEX_V4" variants="GF119-"/> <!-- XXX: wtf are the high 6 bits for? -->

	<reg32 offset="0x100" name="UC_CTRL">
		<bitfield pos="1" name="START_TRIGGER"/>
		<bitfield pos="2" name="RESET_UNK2_TRIGGER"/>
		<bitfield pos="3" name="RESET_UNK3_TRIGGER"/>
		<bitfield pos="4" name="STOPPED"/>
		<bitfield pos="5" name="SLEEPING"/>
	</reg32>

	<reg32 offset="0x104" name="ENTRY"/>

	<reg32 offset="0x108" name="CAPS">
		<bitfield low="0" high="8" name="CODE_SIZE" shr="8"/>
		<bitfield low="9" high="17" name="DATA_SIZE" shr="8"/>
		<bitfield low="18" high="25" name="FIFO_SIZE"/>
		<bitfield low="26" high="31" name="XFER_SLOTS"/>
	</reg32>

	<reg32 offset="0x10c" name="UC_BLOCK_ON_FIFO"/>
	<reg32 offset="0x110" name="XFER_EXT_BASE" shr="8"/>
	<reg32 offset="0x114" name="XFER_FALCON_ADDR"/>
	<reg32 offset="0x118" name="XFER_CTRL">
		<bitfield pos="0" name="FULL"/>
		<bitfield pos="4" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/>
		</bitfield>
		<bitfield pos="5" name="DIR">
			<value value="0" name="LOAD"/>
			<value value="1" name="STORE"/>
		</bitfield>
		<bitfield low="8" high="10" name="SIZE">
			<value value="2" name="16"/>
			<value value="3" name="32"/>
			<value value="4" name="64"/>
			<value value="5" name="128"/>
			<value value="6" name="256"/>
		</bitfield>
		<bitfield low="12" high="14" name="PORT"/>
	</reg32>
	<reg32 offset="0x11c" name="XFER_EXT_ADDR">
		<doc>Also virtual address for code.</doc>
	</reg32>

	<reg32 offset="0x120" name="XFER_STATUS">
		<bitfield pos="1" name="PENDING"/>
		<bitfield low="4" high="5" name="UNK4"/>
		<bitfield low="16" high="18" name="STORES_PENDING"/>
		<bitfield low="24" high="26" name="LOADS_PENDING"/>
	</reg32>
	<reg32 offset="0x128" name="UC_STATUS" variants="GT215-">
		<bitfield pos="0" name="FIFO_IDLE"/>
		<bitfield pos="1" name="CTXSW_IDLE"/>
		<bitfield pos="2" name="XFER_IDLE"/>
		<bitfield pos="3" name="CRYPT_IDLE"/>
		<bitfield pos="6" name="FLAGS_I0E"/>
		<bitfield pos="7" name="FLAGS_I1E"/>
		<bitfield pos="8" name="FLAGS_TA"/>
		<bitfield pos="18" name="XDST_IDLE"/>
		<bitfield pos="19" name="XDLD_IDLE"/>
		<bitfield pos="20" name="XFER_STORE_FULL"/>
		<bitfield pos="21" name="XFER_LOAD_FULL"/>
	</reg32>
	<reg32 offset="0x12c" name="CAPS2" variants="GT215-">
		<bitfield low="0" high="3" name="VERSION">
			<value value="3" name="V3"/>
			<value value="4" name="V4"/>
			<value value="5" name="V5"/>
		</bitfield>
		<bitfield low="4" high="5" name="CRYPT">
			<value value="0" name="NONE"/>
			<value value="3" name="HEAVY"/>
		</bitfield>
		<bitfield low="6" high="7" name="SUBVERSION">
			<value value="0" name="V0"/>
			<value value="1" name="V1"/>
		</bitfield>
		<bitfield low="8" high="11" name="CODE_PORTS">
			<doc># of CODE access ports?</doc>
		</bitfield>
		<bitfield low="12" high="15" name="DATA_PORTS">
			<doc># of DATA access ports</doc>
		</bitfield>
		<bitfield low="16" high="19" name="VM_PAGES_LOG2">
			<doc># of valid bits in code page number.</doc>
		</bitfield>
		<bitfield pos="27" name="UNK27" variants="GF119-"/> <!-- priv debug -->
		<bitfield low="28" high="29" name="IO_ADDR_TYPE" variants="GF119-">
			<value value="0" name="INDEXED"/>
			<value value="2" name="SIMPLE"/>
			<value value="3" name="FULL"/>
		</bitfield>
		<bitfield pos="30" name="UAS" variants="GF119-"/> <!-- unified address space -->
		<bitfield pos="31" name="UNK31" variants="GF119-"/> <!-- auto fill -->
	</reg32>

	<reg32 offset="0x140" name="TLB_CMD" variants="GT215-">
		<bitfield low="0" high="23" name="PARAM"/>
		<bitfield low="24" high="25" name="CMD">
			<value value="1" name="ITLB"/>
			<value value="2" name="PTLB"/>
			<value value="3" name="VTLB"/>
		</bitfield>
	</reg32>
	<reg32 offset="0x144" name="TLB_CMD_RES" variants="GT215-"/>
	<reg32 offset="0x148" name="BRANCH_HISTORY_CTRL" variants="GF119-">
		<bitfield low="0" high="7" name="IDX"/>
		<bitfield low="16" high="23" name="IDX_VALID_MASK"/> <!-- RO -->
	</reg32>
	<reg32 offset="0x14c" name="BRANCH_HISTORY_PC" variants="GF119-"/>

	<reg32 offset="0x160" name="UAS_IO_WINDOW" variants="GF119-" align="0x40000"/>
	<reg32 offset="0x164" name="UAS_CONFIG" variants="GF119-">
		<bitfield low="0" high="11" name="UNK0"/>
		<bitfield pos="16" name="ENABLE"/>
	</reg32>
	<reg32 offset="0x168" name="UAS_FAULT_ADDR" variants="GF119-"/>
	<reg32 offset="0x16c" name="UAS_FAULT_STATUS">
		<bitfield low="0" high="23" name="PC"/>
		<bitfield low="24" high="26" name="TYPE"/> <!-- ??? -->
		<bitfield pos="31" name="VALID"/> <!-- write *0* to clear, for a change -->
	</reg32>

	<reg32 offset="0x180" name="CODE_INDEX" variants="GT215-">
		<bitfield high="15" low="2" name="PHYS_ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
		<bitfield pos="28" name="SECRET"/>
		<bitfield pos="29" name="SECRET_LOCKDOWN"/>
		<bitfield pos="30" name="SECRET_FAIL"/>
		<bitfield pos="31" name="SECRET_SCRUBBER_ACTIVE"/>
	</reg32>
	<reg32 offset="0x184" name="CODE" variants="GT215-"/>
	<reg32 offset="0x188" name="CODE_VIRT_ADDR" shr="8" variants="GT215-"/>
	<reg32 offset="0x1c0" name="DATA_INDEX" stride="8" length="8" variants="GT215-">
		<doc>Actual number of ports available in CAPS2.</doc>
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="24" name="WRITE_AUTOINCR"/>
		<bitfield pos="25" name="READ_AUTOINCR"/>
	</reg32>
	<reg32 offset="0x1c4" name="DATA" stride="8" length="8" variants="GT215-"/>

	<reg32 offset="0x200" name="DEBUG_CMD" variants="GF119-"> <!-- actually v4 -->
		<bitfield low="0" high="3" name="CMD">
			<value value="0x0" name="BREAK"/>
			<value value="0x1" name="CONTINUE_FROM_PC"/>
			<value value="0x2" name="CONTINUE_FROM_ADDR"/>
			<value value="0x3" name="CONTINUE_UNK1_FROM_PC"/>
			<value value="0x4" name="CONTINUE_UNK1_FROM_ADDR"/>
			<value value="0x5" name="SINGLE_STEP_FROM_PC"/>
			<value value="0x6" name="SINGLE_STEP_FROM_ADDR"/>
			<value value="0x7" name="SET_BREAK_MASK"/>
			<value value="0x8" name="REG_READ"/>
			<value value="0x9" name="REG_WRITE"/>
			<value value="0xa" name="DATA_READ"/>
			<value value="0xb" name="DATA_WRITE"/>
			<value value="0xc" name="IO_READ"/>
			<value value="0xd" name="IO_WRITE"/>
			<value value="0xe" name="STATUS_READ"/>
		</bitfield>
		<bitfield low="6" high="7" name="DATA_SIZE"> <!-- used for DATA_* -->
			<value value="0" name="B8"/>
			<value value="1" name="B16"/>
			<value value="2" name="B32"/>
		</bitfield>
		<bitfield low="8" high="12" name="IDX"/> <!-- used for REG_* and STATUS_READ -->
		<bitfield pos="14" name="ERROR"/> <!-- RO -->
		<bitfield pos="15" name="DONE"/> <!-- RO -->
		<bitfield low="16" high="31" name="BREAK_MASK" type="FALCON_BREAK_MASK"/>
	</reg32>
	<reg32 offset="0x204" name="DEBUG_ADDR" variants="GF119-"/> <!-- actually v4; used for DATA_*, IO_*, CONTINUE_FROM_ADDR -->
	<reg32 offset="0x208" name="DEBUG_DATA_WR" variants="GF119-"/>
	<reg32 offset="0x20c" name="DEBUG_DATA_RD" variants="GF119-"/>

	<reg32 offset="0xfe8" name="PM_SEL" variants="GF100-">
		<!-- XXX: what the fuck? -->
		<bitfield low="0" high="3" name="0"/> <!-- from ??? -->
		<bitfield low="4" high="7" name="1"/> <!-- from ??? -->
		<bitfield low="8" high="11" name="2"/> <!-- from USER signals -->
		<bitfield low="12" high="15" name="3"/> <!-- from USER signals -->
		<bitfield low="17" high="31" name="UNK17"/>
	</reg32>
	<reg32 offset="0xfec" name="SP"/>
	<reg32 offset="0xff0" name="PC"/>
	<reg32 offset="0xff4" name="UPLOAD"/>
	<reg32 offset="0xff8" name="UPLOAD_ADDR">
		<bitfield high="15" low="2" name="ADDR" shr="2"/>
		<bitfield pos="20" name="SEG">
			<value value="0" name="DATA"/>
			<value value="1" name="CODE"/> <!-- pre-GT215 only? -->
		</bitfield>
		<bitfield pos="21" name="READBACK"/>
		<bitfield pos="24" name="XFER_BUSY"/>
		<bitfield pos="28" name="SECRET"/>
		<bitfield pos="29" name="CODE_BUSY"/>
	</reg32>
	<reg32 offset="0xffc" name="HOST_IO_INDEX"/>
</group>

<group name="falcon_memif">
	<array offset="0x600" length="1" stride="0x40" name="MEMIF">
		<reg32 offset="0x00" length="8" name="PORT" variants="G80:GF100">
			<doc>Note that port 7 is hardwired to point to context DMAobj.</doc>
			<bitfield low="0" high="15" name="INST" shr="4"/>
			<bitfield low="24" high="26" name="TYPE">
				<value value="0" name="DMAOBJ"/>
				<value value="4" name="VRAM"/>
				<value value="5" name="SYSRAM"/>
				<value value="6" name="SYSRAM_NO_SNOOP"/>
			</bitfield>
			<bitfield pos="30" name="ENABLE_REQ"/>
			<bitfield pos="31" name="ENABLE_ACK"/>
		</reg32>
		<reg32 offset="0x00" length="8" name="PORT" variants="GF100-">
			<bitfield low="0" high="2" name="TYPE">
				<value value="0" name="VM"/>
				<value value="1" name="UNK1"/>
				<value value="2" name="UNK2"/>
				<value value="4" name="VRAM"/>
				<value value="5" name="SYSRAM"/>
				<value value="6" name="SYSRAM_NO_SNOOP"/>
			</bitfield>
			<bitfield low="4" high="5" name="REQ_UNK16_WRITE"/>
			<bitfield low="8" high="9" name="REQ_UNK16_READ"/>
			<bitfield pos="12" name="STORE_BREAK0_ENABLE"/>
			<bitfield pos="13" name="STORE_BREAK1_ENABLE"/>
			<bitfield pos="14" name="LOAD_BREAK0_ENABLE"/>
			<bitfield pos="15" name="LOAD_BREAK1_ENABLE"/>
		</reg32>
		<reg32 offset="0x20" name="CHANNEL" access="r" type="g80_channel"/>
		<reg32 offset="0x24" name="CTRL">
			<bitfield pos="0" name="FLUSH_TRIGGER"/>
			<bitfield pos="1" name="DISABLE_ALL_TRIGGER"/>
			<bitfield pos="2" name="DEACTIVATE_TRIGGER"/>
			<bitfield pos="3" name="COUNTER_CLEAR_TRIGGER"/>
			<bitfield pos="4" name="ENABLE"/>
			<bitfield pos="6" name="RESET_TRIGGER"/>
			<bitfield pos="7" name="IGNORE_ACTIVATION" variants="GF100-"/> <!-- XXX: on some engines only: GF100+ PCOPY0, GF119+ everything -->
			<bitfield pos="8" name="IDLE"/>
			<bitfield pos="9" name="UNK9_RO"/>
			<bitfield pos="10" name="UNK10_RO"/>
			<bitfield low="16" high="19" name="UNK16"/>
		</reg32>
		<reg32 offset="0x28" name="STATUS"/> <!-- indexed -->
		<domain name="FALCON_MEMIF_STATUS" width="32">
			<reg32 offset="0" name="UNK0">
				<!-- ... -->
			</reg32>
			<reg32 offset="1" name="UNK1">
				<!-- ... -->
			</reg32>
			<reg32 offset="2" name="LOAD_COUNTER_LOW"/> <!-- # of loads, counted in 8-byte units -->
			<reg32 offset="3" name="LOAD_COUNTER_HIGH"/>
			<reg32 offset="4" name="STORE_COUNTER_LOW"/>
			<reg32 offset="5" name="STORE_COUNTER_HIGH"/>
		</domain>
		<reg32 offset="0x2c" name="THROTTLE" variants="GT215-">
			<bitfield low="0" high="11" name="UNK0"/> <!-- no effect? -->
			<bitfield low="16" high="27" name="UNK16"/> <!-- speed ~ 1/UNK16 -->
			<bitfield low="30" high="31" name="UNK30_LOG2"/> <!-- speed ~ 2^UNK30_LOG2 -->
		</reg32>
		<!-- XXX: VP3 PPDEC has 4 unrelated [PPDEC-specific] registers here that got moved elsewhere on VP4+ -->
		<reg32 offset="0x30" name="BREAK_MATCH_BASE" stride="8" length="2" variants="GF100-"/>
		<reg32 offset="0x34" name="BREAK_CONFIG" stride="8" length="2" variants="GF100-">
			<bitfield low="0" high="4" name="MATCH_SIZE_LOG2"/>
			<bitfield pos="6" name="MATCH_NEG"/>
			<bitfield pos="7" name="ARMED"/>
			<bitfield low="16" high="31" name="COUNT_LEFT"/>
		</reg32>
	</array>
</group>

</database>