diff options
| author | Dave Airlie <airlied@redhat.com> | 2016-03-01 15:48:44 +1000 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-03-04 11:54:17 +0000 |
| commit | 50c678c7069cf97178b97d6c46972680e8e6495e (patch) | |
| tree | c8e6f5bedbb54246f7ad0267ec1486d68bedebe4 | |
| parent | ae4a7a5962d418b3dc29325169f301ee4a8fc945 (diff) | |
virgl: add support for passing render condition flags to host.
This just passes the extra blit info to fix the render condition
tests.
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit ac222626adfc7a03bf537deba66bad5e57b2c91d)
| -rw-r--r-- | src/gallium/drivers/virgl/virgl_encode.c | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/virgl/virgl_protocol.h | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/gallium/drivers/virgl/virgl_encode.c b/src/gallium/drivers/virgl/virgl_encode.c index 22fb529281..1a1c40bac7 100644 --- a/src/gallium/drivers/virgl/virgl_encode.c +++ b/src/gallium/drivers/virgl/virgl_encode.c @@ -741,7 +741,9 @@ int virgl_encode_blit(struct virgl_context *ctx, virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_BLIT, 0, VIRGL_CMD_BLIT_SIZE)); tmp = VIRGL_CMD_BLIT_S0_MASK(blit->mask) | VIRGL_CMD_BLIT_S0_FILTER(blit->filter) | - VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable); + VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(blit->scissor_enable) | + VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(blit->render_condition_enable) | + VIRGL_CMD_BLIT_S0_ALPHA_BLEND(blit->alpha_blend); virgl_encoder_write_dword(ctx->cbuf, tmp); virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.minx | blit->scissor.miny << 16)); virgl_encoder_write_dword(ctx->cbuf, (blit->scissor.maxx | blit->scissor.maxy << 16)); diff --git a/src/gallium/drivers/virgl/virgl_protocol.h b/src/gallium/drivers/virgl/virgl_protocol.h index ca3142f5f7..a2f1e81830 100644 --- a/src/gallium/drivers/virgl/virgl_protocol.h +++ b/src/gallium/drivers/virgl/virgl_protocol.h @@ -388,6 +388,8 @@ enum virgl_context_cmd { #define VIRGL_CMD_BLIT_S0_MASK(x) (((x) & 0xff) << 0) #define VIRGL_CMD_BLIT_S0_FILTER(x) (((x) & 0x3) << 8) #define VIRGL_CMD_BLIT_S0_SCISSOR_ENABLE(x) (((x) & 0x1) << 10) +#define VIRGL_CMD_BLIT_S0_RENDER_CONDITION_ENABLE(x) (((x) & 0x1) << 11) +#define VIRGL_CMD_BLIT_S0_ALPHA_BLEND(x) (((x) & 0x1) << 12) #define VIRGL_CMD_BLIT_SCISSOR_MINX_MINY 2 #define VIRGL_CMD_BLIT_SCISSOR_MAXX_MAXY 3 #define VIRGL_CMD_BLIT_DST_RES_HANDLE 4 |