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AgeCommit message (Expand)AuthorFilesLines
2017-11-06lima: lower matrix ops for standalone compilercwabbott-limaConnor Abbott4-5/+95
2017-11-03lima: remove unneccesary debug printsConnor Abbott1-10/+0
2017-11-03lima: make the cmdline compiler compile againConnor Abbott3-9/+28
2017-11-03Revert "lima: remove the stand alone compiler"Connor Abbott2-0/+249
2017-10-28lima/gpir: fix the schedule load return wrong node indexQiang Yu1-1/+4
2017-10-28lima/gpir: more debug print for schedulerQiang Yu1-23/+46
2017-10-28lima/ir: add LIMA_SHADER_DEBUG for ir print on/offQiang Yu20-186/+172
2017-10-28lima: reset context dirty flags at onceQiang Yu1-36/+2
2017-10-27lima: for glBufferSubDataQiang Yu1-0/+3
2017-10-26lima/gpir: fix store node not insert to block node listQiang Yu1-0/+4
2017-10-26lima/gpir: print scheduler statisticQiang Yu1-0/+47
2017-10-26lima/gpir: limit load attr node usageQiang Yu1-45/+68
2017-10-24lima/gpir: add neg codegenQiang Yu2-0/+13
2017-10-24lima/gpir: add max node supportQiang Yu3-14/+42
2017-10-24lima/gpir: add rsqrt supportQiang Yu4-3/+22
2017-10-24lima/gpir: fix instr insert store free alu checkQiang Yu1-1/+1
2017-10-24lima/gpir: use gpir_instr_arrayQiang Yu4-7/+13
2017-10-24lima/ppir: add ppir_lower_vec_to_scalarQiang Yu1-0/+102
2017-10-23lima/gpir: add gpir_node_replace_predQiang Yu3-26/+18
2017-10-23lima/gpir: fix gpir_remove_all_created_nodeQiang Yu1-3/+7
2017-10-23lima/gpir: scheduler insert load support use regQiang Yu1-57/+240
2017-10-22lima/gpir: drop the schedule reuse move codeQiang Yu1-60/+1
2017-10-22lima/ppir: support div/rcp nodeQiang Yu5-2/+10
2017-10-21lima/gpir: optimiz instr insert slot chooseQiang Yu1-0/+33
2017-10-21lima: skip draw if no shader (compile fail)Qiang Yu1-0/+5
2017-10-21lima/ppir: fix ssa dest write mask not setQiang Yu1-0/+1
2017-10-21lima/ppir: add neg lowerQiang Yu1-0/+52
2017-10-21lima/ppir: support maxQiang Yu4-0/+9
2017-10-21lima/ppir: support pow/exp2/log2Qiang Yu6-1/+21
2017-10-21lima/ppir: add rsqrt codegenQiang Yu4-1/+42
2017-10-21lima/ppir: remove dot replicate optionQiang Yu2-4/+3
2017-10-21lima/ppir: fix codegen swizzle encodeQiang Yu1-8/+12
2017-10-21lima/ppir: add sum node codegenQiang Yu5-5/+14
2017-10-21lima/ppir: add dot node lowerQiang Yu3-0/+84
2017-10-20lima: make info print when debug compile onlyQiang Yu19-98/+147
2017-10-19lima/gpir: fix alu node schedule info printQiang Yu1-1/+6
2017-10-19lima/gpir: add some TODO comments for schedulerQiang Yu1-2/+11
2017-10-19lima/gpir: alu node schedule refineQiang Yu1-81/+108
2017-10-19lima/gpir: add assert for dep max dist calcQiang Yu1-2/+6
2017-10-18lima/gpir: refine schedule load regQiang Yu3-54/+130
2017-10-15lima/gpir: tmp solution for store reg in same instrQiang Yu1-0/+18
2017-10-15lima/gpir: schedule load node earlyQiang Yu1-2/+5
2017-10-15lima/gpir: handle schedule fail for move only caseQiang Yu1-11/+66
2017-10-15lima/gpir: add instr remove nodeQiang Yu4-17/+98
2017-10-15lima/gpir: fix free slot calc when instr insert for complex1Qiang Yu1-3/+9
2017-10-13lima/gpir: reduce the schedule reg/move thresholdQiang Yu1-1/+1
2017-10-13lima/gpir: move pass ahead of complex slot for move nodeQiang Yu1-1/+1
2017-10-13lima/gpir: fix instr free alu calc when insert storeQiang Yu1-2/+11
2017-10-13lima/gpir: print more info when fail to schedule a nodeQiang Yu1-0/+22
2017-10-13lima/gpir: add rcp codegenQiang Yu1-1/+29
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