diff options
| author | Marek Olšák <marek.olsak@amd.com> | 2017-07-29 22:03:38 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2017-08-01 17:06:38 +0200 |
| commit | 404f524fe2a3e3cc0024b3b8f8dc2e592a8aafed (patch) | |
| tree | a4edac6c0e5585858b7a65e0e866450081bf2b13 | |
| parent | 94965b8219508954a5fddd74e7c6de4503cd9931 (diff) | |
radeonsi: don't flush sL1 conditionally in WAIT_ON_CE_COUNTER
I don't know the condition for the flush, but we better turn this off.
The sL1 flush is used when CE dumps stuff into a ring buffer and the ring
buffer wraps.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index a5f5b7f98a..dfe423610b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1145,10 +1145,10 @@ void si_ce_pre_draw_synchronization(struct si_context *sctx) { if (sctx->ce_need_synchronization) { radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0)); - radeon_emit(sctx->ce_ib, 1); + radeon_emit(sctx->ce_ib, 1); /* 1 = increment CE counter */ radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0)); - radeon_emit(sctx->b.gfx.cs, 1); + radeon_emit(sctx->b.gfx.cs, 0); /* 0 = don't flush sL1 conditionally */ } } @@ -1156,7 +1156,7 @@ void si_ce_post_draw_synchronization(struct si_context *sctx) { if (sctx->ce_need_synchronization) { radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0)); - radeon_emit(sctx->b.gfx.cs, 0); + radeon_emit(sctx->b.gfx.cs, 0); /* unused */ sctx->ce_need_synchronization = false; } |