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| author | Connor Abbott <connor.w.abbott@intel.com> | 2015-08-13 15:56:22 -0700 |
|---|---|---|
| committer | Connor Abbott <connor.w.abbott@intel.com> | 2015-08-13 16:02:54 -0700 |
| commit | eeb218f43f20d96a578fe8368b7733b260f1d166 (patch) | |
| tree | 1986019f3ba0ed3eac4160d1f198014a0f9e9606 | |
| parent | 4a09f65bd830995f7843c58a5df5a5bae6a4a5de (diff) | |
i965/vec4/nir: translate d2f/f2di965-fp64
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 995f2fdb7e..5759ce43ca 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -813,6 +813,38 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) inst = emit(MOV(dst, op[0])); break; + case nir_op_d2f: { + dst_reg temp = dst_reg(GRF, alloc.allocate(1)); + temp.type = BRW_REGISTER_TYPE_DF; + emit(MOV(temp, op[0])); + src_reg temp_src = src_reg(temp); + dst_reg temp2 = dst_reg(GRF, alloc.allocate(1)); + temp2.type = BRW_REGISTER_TYPE_F; + emit(VEC4_OPCODE_DOUBLE_TO_FLOAT, temp2, temp_src); + src_reg temp2_src = src_reg(temp2); + temp2_src.swizzle = BRW_SWIZZLE_XZXZ; + inst = emit(MOV(dst, temp2_src)); + inst->saturate = instr->dest.saturate; + break; + } + + case nir_op_f2d: { + dst_reg temp = dst_reg(GRF, alloc.allocate(1)); + temp.type = BRW_REGISTER_TYPE_F; + temp.writemask = 0x5; + op[0].swizzle = brw_compose_swizzle(BRW_SWIZZLE_XXYY, op[0].swizzle); + inst = emit(MOV(temp, op[0])); + inst->saturate = instr->dest.saturate; + src_reg temp_src = src_reg(temp); + temp_src.swizzle = BRW_SWIZZLE_NOOP; + dst_reg temp2 = dst_reg(GRF, alloc.allocate(1)); + temp2.type = BRW_REGISTER_TYPE_DF; + emit(VEC4_OPCODE_FLOAT_TO_DOUBLE, temp2, temp_src); + src_reg temp2_src = src_reg(temp2); + emit(MOV(dst, temp2_src)); + break; + } + case nir_op_fadd: /* fall through */ case nir_op_iadd: |