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/*
* Copyright 2008 Stuart Bennett
* Copyright 2009-2010 Francisco Jerez
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __NVHW_H__
#define __NVHW_H__
#include <stdbool.h>
#include <errno.h>
#include "nvreg.h"
#define NV04_CLASS (1 << 0)
#define NV10_CLASS (1 << 1)
#define NV20_CLASS (1 << 2)
#define NV30_CLASS (1 << 3)
#define NV40_CLASS (1 << 4)
#define NV50_CLASS (1 << 5)
#define NVC0_CLASS (1 << 6)
#define DUALHEAD_CLASS (1 << 7)
#define TWOREG_PLL_CLASS (1 << 8)
#define TWOSTAGE_PLL_CLASS (1 << 9)
#define NV04_OVERLAY_CLASS (1 << 10)
#define NV17_DISPLAY_CLASS (1 << 11)
#define NV17_TVOUT_CLASS (1 << 12)
#define NV04_DISPLAY_CLASS (NV04_CLASS | NV10_CLASS | NV20_CLASS | \
NV30_CLASS | NV40_CLASS)
extern uint32_t chipset;
extern uint64_t class;
int nv_detect_chipset(void *regs);
static inline bool
nv_class(uint64_t ks)
{
return ks & class;
}
static inline uint8_t
nv_rd08(void *regs, uint32_t reg)
{
return *(volatile uint8_t *)((char *)regs + reg);
}
static inline uint32_t
nv_rd32(void *regs, uint32_t reg)
{
return *(volatile uint32_t *)((char *)regs + reg);
}
static inline void
nv_wr08(void *regs, uint32_t reg, uint8_t val)
{
*(volatile uint8_t *)((char *)regs + reg) = val;
}
static inline void
nv_wr32(void *regs, uint32_t reg, uint32_t val)
{
*(volatile uint32_t *)((char *)regs + reg) = val;
}
static inline uint8_t
head_rd08(void *regs, int head, uint32_t reg)
{
if (head)
reg += 0x2000;
return nv_rd08(regs, reg);
}
static inline uint32_t
head_rd32(void *regs, int head, uint32_t reg)
{
if (head)
reg += 0x2000;
return nv_rd32(regs, reg);
}
static inline void
head_wr08(void *regs, int head, uint32_t reg, uint8_t val)
{
if (head)
reg += 0x2000;
nv_wr08(regs, reg, val);
}
static inline void
head_wr32(void *regs, int head, uint32_t reg, uint32_t val)
{
if (head)
reg += 0x2000;
nv_wr32(regs, reg, val);
}
static inline uint8_t
read_prmvio(void *regs, int head, uint32_t reg)
{
return head_rd08(regs, (nv_class(NV40_CLASS) ? head : 0), reg);
}
static inline void
write_prmvio(void *regs, int head, uint32_t reg, uint8_t val)
{
head_wr08(regs, (nv_class(NV40_CLASS) ? head : 0), reg, val);
}
static inline uint8_t
read_vga_crtc(void *regs, int head, uint8_t idx)
{
head_wr08(regs, head, NV_PRMCIO_CRX__COLOR, idx);
return head_rd08(regs, head, NV_PRMCIO_CR__COLOR);
}
static inline void
write_vga_crtc(void *regs, int head, uint8_t idx, uint8_t val)
{
head_wr08(regs, head, NV_PRMCIO_CRX__COLOR, idx);
head_wr08(regs, head, NV_PRMCIO_CR__COLOR, val);
}
static inline uint8_t
read_vga_seq(void *regs, int head, uint8_t idx)
{
write_prmvio(regs, head, NV_PRMVIO_SRX, idx);
return read_prmvio(regs, head, NV_PRMVIO_SR);
}
static inline void
write_vga_seq(void *regs, int head, uint8_t idx, uint8_t val)
{
write_prmvio(regs, head, NV_PRMVIO_SRX, idx);
write_prmvio(regs, head, NV_PRMVIO_SR, val);
}
static inline uint8_t
read_tmds(void *regs, int ramdac, int dl, uint8_t idx)
{
head_wr32(regs, ramdac, 0x6808b0 + dl * 8, 0x10000 | idx);
return head_rd32(regs, ramdac, 0x6808b4 + dl * 8);
}
static inline void
write_tmds(void *regs, int ramdac, int dl, uint8_t idx, uint8_t val)
{
head_wr32(regs, ramdac, 0x6808b4 + dl * 8, val);
head_wr32(regs, ramdac, 0x6808b0 + dl * 8, idx);
}
static inline uint8_t
read_itv(void *regs, uint8_t idx)
{
nv_wr32(regs, 0xd220, idx);
return nv_rd32(regs, 0xd224);
}
static inline void
write_itv(void *regs, uint8_t idx, uint8_t val)
{
nv_wr32(regs, 0xd220, idx);
nv_wr32(regs, 0xd224, val);
}
#endif
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