diff options
| -rw-r--r-- | Makefile | 7 | ||||
| -rw-r--r-- | nvhw.c | 115 | ||||
| -rw-r--r-- | nvhw.h | 186 | ||||
| -rw-r--r-- | nvreg.c | 746 | ||||
| -rw-r--r-- | nvreg.h | 578 | ||||
| -rw-r--r-- | tvdump.c | 821 | ||||
| -rw-r--r-- | tvdump2code.py | 87 | ||||
| -rw-r--r-- | util.h | 43 |
8 files changed, 1474 insertions, 1109 deletions
@@ -1,2 +1,5 @@ -tvdump: tvdump.c nvreg.h - gcc -Wall -O0 -g -o $@ $< -lpciaccess +SOURCES = tvdump.c nvreg.c nvhw.c +HEADERS = nvhw.h nvreg.h util.h + +tvdump: $(SOURCES) $(HEADERS) + gcc -Wall -Wno-trampolines -O0 -g -o $@ $(SOURCES) -lpciaccess @@ -0,0 +1,115 @@ +/* + * Copyright 2005 Stephane Marchesin + * Copyright 2008 Stuart Bennett + * Copyright 2009-2010 Francisco Jerez + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "nvhw.h" + +uint32_t chipset = 0xff; +uint64_t class; + +static bool +have_class(void *regs, uint64_t k) +{ + int arch = (chipset & 0xf0); + + switch (k) { + case NV04_CLASS: + return arch == 0x00; + + case NV10_CLASS: + return arch == 0x10; + + case NV20_CLASS: + return arch == 0x20; + + case NV30_CLASS: + return arch == 0x30; + + case NV40_CLASS: + return arch == 0x40 || arch == 0x60; + + case NV50_CLASS: + return arch == 0x50 || arch == 0x80 || + arch == 0x90 || arch == 0xa0; + + case NVC0_CLASS: + return arch == 0xc0; + + case DUALHEAD_CLASS: + return chipset > 0x10 && chipset != 0x15 && + chipset != 0x1a && chipset != 0x20; + + case TWOREG_PLL_CLASS: + return chipset == 0x31 || chipset == 0x36 || + chipset >= 0x40; + + case TWOSTAGE_PLL_CLASS: + return chipset >= 0x30 && chipset != 0x34; + + case NV04_OVERLAY_CLASS: + return chipset <= 0x40 || chipset == 0x44; + + case NV17_DISPLAY_CLASS: + return chipset >= 0x17 && + (chipset != 0x1a && chipset != 0x20); + + case NV17_TVOUT_CLASS: + return chipset >= 0x17 && + (chipset != 0x1a && arch != 0x20); + + default: + return false; + } +} + +int +nv_detect_chipset(void *regs) +{ + uint32_t reg0 = nv_rd32(regs, 0); + uint64_t k; + + /* We're dealing with >= NV10 */ + if ((reg0 & 0x0f000000) > 0) { + /* Bit 27-20 contain the architecture in hex */ + chipset = (reg0 & 0xff00000) >> 20; + /* NV04 or NV05 */ + } else if ((reg0 & 0xff00fff0) == 0x20004000) { + if (reg0 & 0x00f00000) + chipset = 0x05; + else + chipset = 0x04; + } else { + return -ENODEV; + } + + for (k = 1; k; k <<= 1) { + if (have_class(regs, k)) + class |= k; + } + + return 0; +} @@ -0,0 +1,186 @@ +/* + * Copyright 2008 Stuart Bennett + * Copyright 2009-2010 Francisco Jerez + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __NVHW_H__ +#define __NVHW_H__ + +#include <stdbool.h> +#include <errno.h> +#include "nvreg.h" + +#define NV04_CLASS (1 << 0) +#define NV10_CLASS (1 << 1) +#define NV20_CLASS (1 << 2) +#define NV30_CLASS (1 << 3) +#define NV40_CLASS (1 << 4) +#define NV50_CLASS (1 << 5) +#define NVC0_CLASS (1 << 6) +#define DUALHEAD_CLASS (1 << 7) +#define TWOREG_PLL_CLASS (1 << 8) +#define TWOSTAGE_PLL_CLASS (1 << 9) +#define NV04_OVERLAY_CLASS (1 << 10) +#define NV17_DISPLAY_CLASS (1 << 11) +#define NV17_TVOUT_CLASS (1 << 12) +#define NV04_DISPLAY_CLASS (NV04_CLASS | NV10_CLASS | NV20_CLASS | \ + NV30_CLASS | NV40_CLASS) + +extern uint32_t chipset; +extern uint64_t class; + +int nv_detect_chipset(void *regs); + +static inline bool +nv_class(uint64_t ks) +{ + return ks & class; +} + +static inline uint8_t +nv_rd08(void *regs, uint32_t reg) +{ + return *(volatile uint8_t *)((char *)regs + reg); +} + +static inline uint32_t +nv_rd32(void *regs, uint32_t reg) +{ + return *(volatile uint32_t *)((char *)regs + reg); +} + +static inline void +nv_wr08(void *regs, uint32_t reg, uint8_t val) +{ + *(volatile uint8_t *)((char *)regs + reg) = val; +} + +static inline void +nv_wr32(void *regs, uint32_t reg, uint32_t val) +{ + *(volatile uint32_t *)((char *)regs + reg) = val; +} + +static inline uint8_t +head_rd08(void *regs, int head, uint32_t reg) +{ + if (head) + reg += 0x2000; + return nv_rd08(regs, reg); +} + +static inline uint32_t +head_rd32(void *regs, int head, uint32_t reg) +{ + if (head) + reg += 0x2000; + return nv_rd32(regs, reg); +} + +static inline void +head_wr08(void *regs, int head, uint32_t reg, uint8_t val) +{ + if (head) + reg += 0x2000; + nv_wr08(regs, reg, val); +} + +static inline void +head_wr32(void *regs, int head, uint32_t reg, uint32_t val) +{ + if (head) + reg += 0x2000; + nv_wr32(regs, reg, val); +} + +static inline uint8_t +read_prmvio(void *regs, int head, uint32_t reg) +{ + return head_rd08(regs, (nv_class(NV40_CLASS) ? head : 0), reg); +} + +static inline void +write_prmvio(void *regs, int head, uint32_t reg, uint8_t val) +{ + head_wr08(regs, (nv_class(NV40_CLASS) ? head : 0), reg, val); +} + +static inline uint8_t +read_vga_crtc(void *regs, int head, uint8_t idx) +{ + head_wr08(regs, head, NV_PRMCIO_CRX__COLOR, idx); + return head_rd08(regs, head, NV_PRMCIO_CR__COLOR); +} + +static inline void +write_vga_crtc(void *regs, int head, uint8_t idx, uint8_t val) +{ + head_wr08(regs, head, NV_PRMCIO_CRX__COLOR, idx); + head_wr08(regs, head, NV_PRMCIO_CR__COLOR, val); +} + +static inline uint8_t +read_vga_seq(void *regs, int head, uint8_t idx) +{ + write_prmvio(regs, head, NV_PRMVIO_SRX, idx); + return read_prmvio(regs, head, NV_PRMVIO_SR); +} + +static inline void +write_vga_seq(void *regs, int head, uint8_t idx, uint8_t val) +{ + write_prmvio(regs, head, NV_PRMVIO_SRX, idx); + write_prmvio(regs, head, NV_PRMVIO_SR, val); +} + +static inline uint8_t +read_tmds(void *regs, int ramdac, int dl, uint8_t idx) +{ + head_wr32(regs, ramdac, 0x6808b0 + dl * 8, 0x10000 | idx); + return head_rd32(regs, ramdac, 0x6808b4 + dl * 8); +} + +static inline void +write_tmds(void *regs, int ramdac, int dl, uint8_t idx, uint8_t val) +{ + head_wr32(regs, ramdac, 0x6808b4 + dl * 8, val); + head_wr32(regs, ramdac, 0x6808b0 + dl * 8, idx); +} + +static inline uint8_t +read_itv(void *regs, uint8_t idx) +{ + nv_wr32(regs, 0xd220, idx); + return nv_rd32(regs, 0xd224); +} + +static inline void +write_itv(void *regs, uint8_t idx, uint8_t val) +{ + nv_wr32(regs, 0xd220, idx); + nv_wr32(regs, 0xd224, val); +} + +#endif @@ -0,0 +1,746 @@ +/* + * Copyright 2010 Francisco Jerez. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "nvhw.h" +#include "nvreg.h" + +struct reg pmc_block[] = { + { ~0, 0x000, "BOOT_0" }, + { ~0, 0x001, "BOOT_1" }, + { ~0, 0x100, "INTR_0" }, + { ~0, 0x140, "INTR_EN_0" }, + { ~0, 0x160, "INTR_READ_0" }, + { ~0, 0x200, "ENABLE" }, + { ~0, 0x300, "FRAME_PROTECT_MIN" }, + { ~0, 0x304, "FRAME_PROTECT_MAX" }, + { }, +}; + +struct reg pbus_block[] = { + { ~0, 0x1084, "DEBUG_1" }, + { ~0, 0x1088, "DEBUG_2" }, + { ~0, 0x108c, "DEBUG_3" }, + { ~0, 0x1098 }, + { ~0, 0x10b8, "DEBUG_CTRIM_2" }, + { ~0, 0x10d8 }, + { ~0, 0x10e0, "DEBUG_PRIV_ASRC" }, + { ~0, 0x10f0, "DEBUG_DUALHEAD_CTL" }, + { ~0, 0x1100, "INTR_0" }, + { ~0, 0x1140, "INTR_EN_0" }, + { ~0, 0x1210 }, + { ~0, 0x1214 }, + { ~0, 0x1218 }, + { ~0, 0x121c }, + { ~0, 0x1220 }, + { ~0, 0x1224 }, + { ~0, 0x1228 }, + { ~0, 0x122c }, + { ~0, 0x1230 }, + { ~0, 0x1234 }, + { ~0, 0x1238 }, + { ~0, 0x123c }, + { ~0, 0x1240 }, + { ~0, 0x1244 }, + { ~0, 0x1248 }, + { ~0, 0x124c }, + { ~0, 0x1250 }, + { ~0, 0x1518 }, + { ~0, 0x1580 }, + { ~0, 0x1584, "POWERCTRL_1" }, + { ~0, 0x1588, "POWERCTRL_2" }, + { ~0, 0x158c }, + { ~0, 0x1590, "POWERCTRL_4" }, + { ~0, 0x15a0 }, + { ~0, 0x1800 }, + { ~0, 0x1804 }, + { ~0, 0x1808 }, + { ~0, 0x180c }, + { ~0, 0x1810 }, + { ~0, 0x1814 }, + { ~0, 0x1818 }, + { ~0, 0x182c }, + { ~0, 0x1830 }, + { ~0, 0x1844 }, + { ~0, 0x1848 }, + { ~0, 0x184c }, + { ~0, 0x1850 }, + { ~0, 0x1854 }, + { ~0, 0x1860 }, + { } +}; + +struct reg pfb_block[] = { + { ~0, 0x100000, "BOOT_0" }, + { ~0, 0x100080, "DEBUG_0" }, + { ~0, 0x1000f0 }, + { ~0, 0x100200, "CFG0" }, + { ~0, 0x100204, "CFG1" }, + { ~0, 0x100208, "FIFO_CTL" }, + { ~0, 0x10020c, "FIFO_DATA" }, + { ~0, 0x100210, "REFCTRL" }, + { ~0, 0x100214, "NVM" }, + { ~0, 0x100218, "PIN" }, + { ~0, 0x10021c, "PAD" }, + { ~0, 0x100220, "TIMING0" }, + { ~0, 0x100224, "TIMING1" }, + { ~0, 0x100228, "TIMING2" }, + { ~0, 0x1002c0, "MRS" }, + { ~0, 0x1002c4, "EMRS" }, + { ~0, 0x1002c8 }, + { ~0, 0x1002cc }, + { ~0, 0x1002d0, "REF" }, + { ~0, 0x1002d4, "PRE" }, + { ~0, 0x100300, "ZCOMP0" }, + { ~0, 0x100304, "ZCOMP1" }, + { ~0, 0x100308, "ZCOMP2" }, + { ~0, 0x10030c, "ZCOMP3" }, + { ~0, 0x100310, "ZCOMP4" }, + { ~0, 0x100314, "ZCOMP5" }, + { ~0, 0x100318, "ZCOMP6" }, + { ~0, 0x10031c, "ZCOMP7" }, + { ~0, 0x100320, "ZCOMP_MAX_TAG" }, + { ~0, 0x100324, "ZCOMP_OFFSET" }, + { ~0, 0x100328, "ARB_PREDIVIDER" }, + { ~0, 0x10032c, "ARB_TIMEOUT" }, + { ~0, 0x100330, "ARB_XFER_SZ" }, + { ~0, 0x100334, "CLOSE_PAGE0" }, + { ~0, 0x100338, "CLOSE_PAGE1" }, + { ~0, 0x100340 }, + { ~0, 0x100344 }, + { ~0, 0x100348 }, + { ~0, 0x10034c }, + { ~0, 0x100350 }, + { ~0, 0x100360 }, + { ~0, 0x10037c }, + { ~0, 0x100380 }, + { ~0, 0x100384 }, + { ~0, 0x100388 }, + { ~0, 0x10038c }, + { ~0, 0x100390 }, + { ~0, 0x100394 }, + { ~0, 0x100398 }, + { ~0, 0x10039c }, + { ~0, 0x1003a0 }, + { ~0, 0x1003a4 }, + { ~0, 0x1003a8 }, + { ~0, 0x1003ac }, + { ~0, 0x1003b0 }, + { ~0, 0x1003b4 }, + { ~0, 0x1003b8 }, + { ~0, 0x1003bc }, + { ~0, 0x1003c0 }, + { ~0, 0x1003c4 }, + { ~0, 0x1003c8 }, + { ~0, 0x1003d0 }, + { } +}; + +struct reg pcrtc_block[] = { + { NV04_DISPLAY_CLASS, 0x600100, "INTR_0" }, + { NV04_DISPLAY_CLASS, 0x600140, "INTR_EN_0" }, + { NV04_DISPLAY_CLASS, 0x600800, "START" }, + { NV04_DISPLAY_CLASS, 0x600804, "CONFIG" }, + { NV04_DISPLAY_CLASS, 0x600808, "RASTER" }, + { NV04_DISPLAY_CLASS, 0x60080C, "CURSOR" }, + { NV04_DISPLAY_CLASS, 0x600810, "CURSOR_CONFIG" }, + { NV04_DISPLAY_CLASS, 0x600814, "VIP_RASTER" }, + { NV04_DISPLAY_CLASS, 0x600818, "GPIO" }, + { NV04_DISPLAY_CLASS, 0x60081c, "GPIO_EXT" }, + { NV04_DISPLAY_CLASS, 0x600820, "FIFO_CNTRL" }, + { NV04_DISPLAY_CLASS, 0x600824, "FIFO_DATA" }, + { NV04_DISPLAY_CLASS, 0x600830 }, + { NV04_DISPLAY_CLASS, 0x600834 }, + { NV04_DISPLAY_CLASS, 0x600850 }, + { NV04_DISPLAY_CLASS, 0x600860, "ENGINE_CTRL" }, + { } +}; + +struct reg vga_crtc_block[] = { + { NV04_DISPLAY_CLASS, 0 }, + { NV04_DISPLAY_CLASS, 0x1 }, + { NV04_DISPLAY_CLASS, 0x2 }, + { NV04_DISPLAY_CLASS, 0x3 }, + { NV04_DISPLAY_CLASS, 0x4 }, + { NV04_DISPLAY_CLASS, 0x5 }, + { NV04_DISPLAY_CLASS, 0x6 }, + { NV04_DISPLAY_CLASS, 0x7 }, + { NV04_DISPLAY_CLASS, 0x8 }, + { NV04_DISPLAY_CLASS, 0x9 }, + { NV04_DISPLAY_CLASS, 0xa }, + { NV04_DISPLAY_CLASS, 0xb }, + { NV04_DISPLAY_CLASS, 0xc }, + { NV04_DISPLAY_CLASS, 0xd }, + { NV04_DISPLAY_CLASS, 0xe }, + { NV04_DISPLAY_CLASS, 0xf }, + { NV04_DISPLAY_CLASS, 0x10 }, + { NV04_DISPLAY_CLASS, 0x11 }, + { NV04_DISPLAY_CLASS, 0x12 }, + { NV04_DISPLAY_CLASS, 0x13 }, + { NV04_DISPLAY_CLASS, 0x14 }, + { NV04_DISPLAY_CLASS, 0x15 }, + { NV04_DISPLAY_CLASS, 0x16 }, + { NV04_DISPLAY_CLASS, 0x17 }, + { NV04_DISPLAY_CLASS, 0x18 }, + { NV04_DISPLAY_CLASS, 0x19 }, + { NV04_DISPLAY_CLASS, 0x1a, "RPC1" }, + { NV04_DISPLAY_CLASS, 0x1b }, + { NV04_DISPLAY_CLASS, 0x1c, "ENH" }, + { NV04_DISPLAY_CLASS, 0x1d }, + { NV04_DISPLAY_CLASS, 0x1e }, + { NV04_DISPLAY_CLASS, 0x1f }, + { NV04_DISPLAY_CLASS, 0x20 }, + { NV04_DISPLAY_CLASS, 0x21 }, + { NV04_DISPLAY_CLASS, 0x22 }, + { NV04_DISPLAY_CLASS, 0x23 }, + { NV04_DISPLAY_CLASS, 0x24 }, + { NV04_DISPLAY_CLASS, 0x25 }, + { NV04_DISPLAY_CLASS, 0x26 }, + { NV04_DISPLAY_CLASS, 0x27 }, + { NV04_DISPLAY_CLASS, 0x28, "PIXEL" }, + { NV04_DISPLAY_CLASS, 0x29 }, + { NV04_DISPLAY_CLASS, 0x2a }, + { NV04_DISPLAY_CLASS, 0x2b }, + { NV04_DISPLAY_CLASS, 0x2c }, + { NV04_DISPLAY_CLASS, 0x2d }, + { NV04_DISPLAY_CLASS, 0x2e }, + { NV04_DISPLAY_CLASS, 0x2f }, + { NV04_DISPLAY_CLASS, 0x30 }, + { NV04_DISPLAY_CLASS, 0x31 }, + { NV04_DISPLAY_CLASS, 0x32 }, + { NV04_DISPLAY_CLASS, 0x33, "LCD" }, + { NV04_DISPLAY_CLASS, 0x34 }, + { NV04_DISPLAY_CLASS, 0x35 }, + { NV04_DISPLAY_CLASS, 0x36 }, + { NV04_DISPLAY_CLASS, 0x37 }, + { NV04_DISPLAY_CLASS, 0x38 }, + { NV04_DISPLAY_CLASS, 0x39 }, + { NV04_DISPLAY_CLASS, 0x3a }, + { NV04_DISPLAY_CLASS, 0x3b }, + { NV04_DISPLAY_CLASS, 0x3c }, + { NV04_DISPLAY_CLASS, 0x3d }, + { NV04_DISPLAY_CLASS, 0x3e }, + { NV04_DISPLAY_CLASS, 0x3f }, + { NV04_DISPLAY_CLASS, 0x40 }, + { NV04_DISPLAY_CLASS, 0x41 }, + { NV04_DISPLAY_CLASS, 0x42 }, + { NV04_DISPLAY_CLASS, 0x43 }, + { NV04_DISPLAY_CLASS, 0x44 }, + { NV04_DISPLAY_CLASS, 0x45 }, + { NV04_DISPLAY_CLASS, 0x46 }, + { NV04_DISPLAY_CLASS, 0x47 }, + { NV04_DISPLAY_CLASS, 0x48 }, + { NV04_DISPLAY_CLASS, 0x49 }, + { NV04_DISPLAY_CLASS, 0x4a }, + { NV04_DISPLAY_CLASS, 0x4b }, + { NV04_DISPLAY_CLASS, 0x4c }, + { NV04_DISPLAY_CLASS, 0x4d }, + { NV04_DISPLAY_CLASS, 0x4e }, + { NV04_DISPLAY_CLASS, 0x4f }, + { NV04_DISPLAY_CLASS, 0x50 }, + { NV04_DISPLAY_CLASS, 0x51 }, + { NV04_DISPLAY_CLASS, 0x52 }, + { NV04_DISPLAY_CLASS, 0x53, "FP_HTIMING" }, + { NV04_DISPLAY_CLASS, 0x54, "FP_VTIMING" }, + { NV04_DISPLAY_CLASS, 0x55 }, + { NV04_DISPLAY_CLASS, 0x56 }, + { NV04_DISPLAY_CLASS, 0x57 }, + { NV04_DISPLAY_CLASS, 0x58 }, + { NV04_DISPLAY_CLASS, 0x59 }, + { NV04_DISPLAY_CLASS, 0x5a }, + { NV04_DISPLAY_CLASS, 0x5b }, + { NV04_DISPLAY_CLASS, 0x5c }, + { NV04_DISPLAY_CLASS, 0x5d }, + { NV04_DISPLAY_CLASS, 0x5e }, + { NV04_DISPLAY_CLASS, 0x5f }, + { NV04_DISPLAY_CLASS, 0x60 }, + { NV04_DISPLAY_CLASS, 0x61 }, + { NV04_DISPLAY_CLASS, 0x62 }, + { NV04_DISPLAY_CLASS, 0x63 }, + { NV04_DISPLAY_CLASS, 0x64 }, + { NV04_DISPLAY_CLASS, 0x65 }, + { NV04_DISPLAY_CLASS, 0x66 }, + { NV04_DISPLAY_CLASS, 0x67 }, + { NV04_DISPLAY_CLASS, 0x68 }, + { NV04_DISPLAY_CLASS, 0x69 }, + { NV04_DISPLAY_CLASS, 0x6a }, + { NV04_DISPLAY_CLASS, 0x6b }, + { NV04_DISPLAY_CLASS, 0x6c }, + { NV04_DISPLAY_CLASS, 0x6d }, + { NV04_DISPLAY_CLASS, 0x6e }, + { NV04_DISPLAY_CLASS, 0x6f }, + { NV04_DISPLAY_CLASS, 0x70 }, + { NV04_DISPLAY_CLASS, 0x71 }, + { NV04_DISPLAY_CLASS, 0x72 }, + { NV04_DISPLAY_CLASS, 0x73 }, + { NV04_DISPLAY_CLASS, 0x74 }, + { NV04_DISPLAY_CLASS, 0x75 }, + { NV04_DISPLAY_CLASS, 0x76 }, + { NV04_DISPLAY_CLASS, 0x77 }, + { NV04_DISPLAY_CLASS, 0x78 }, + { NV04_DISPLAY_CLASS, 0x79 }, + { NV04_DISPLAY_CLASS, 0x7a }, + { NV04_DISPLAY_CLASS, 0x7b }, + { NV04_DISPLAY_CLASS, 0x7c }, + { NV04_DISPLAY_CLASS, 0x7d }, + { NV04_DISPLAY_CLASS, 0x7e }, + { NV04_DISPLAY_CLASS, 0x7f }, + { NV04_DISPLAY_CLASS, 0x80 }, + { NV04_DISPLAY_CLASS, 0x81 }, + { NV04_DISPLAY_CLASS, 0x82 }, + { NV04_DISPLAY_CLASS, 0x83 }, + { NV04_DISPLAY_CLASS, 0x84 }, + { NV04_DISPLAY_CLASS, 0x85 }, + { NV04_DISPLAY_CLASS, 0x86 }, + { NV04_DISPLAY_CLASS, 0x87 }, + { NV04_DISPLAY_CLASS, 0x88 }, + { NV04_DISPLAY_CLASS, 0x89 }, + { NV04_DISPLAY_CLASS, 0x8a }, + { NV04_DISPLAY_CLASS, 0x8b }, + { NV04_DISPLAY_CLASS, 0x8c }, + { NV04_DISPLAY_CLASS, 0x8d }, + { NV04_DISPLAY_CLASS, 0x8e }, + { NV04_DISPLAY_CLASS, 0x8f }, + { NV04_DISPLAY_CLASS, 0x90 }, + { NV04_DISPLAY_CLASS, 0x91 }, + { NV04_DISPLAY_CLASS, 0x92 }, + { NV04_DISPLAY_CLASS, 0x93 }, + { NV04_DISPLAY_CLASS, 0x94 }, + { NV04_DISPLAY_CLASS, 0x95 }, + { NV04_DISPLAY_CLASS, 0x96 }, + { NV04_DISPLAY_CLASS, 0x97 }, + { NV04_DISPLAY_CLASS, 0x98 }, + { NV04_DISPLAY_CLASS, 0x99 }, + { NV04_DISPLAY_CLASS, 0x9a }, + { NV04_DISPLAY_CLASS, 0x9b }, + { NV04_DISPLAY_CLASS, 0x9c }, + { NV04_DISPLAY_CLASS, 0x9d }, + { NV04_DISPLAY_CLASS, 0x9e }, + { NV04_DISPLAY_CLASS, 0x9f }, + { } +}; + +struct reg pramdac_block[] = { + { NV04_DISPLAY_CLASS, 0x680510, "PLL_SETUP_CONTROL" }, + { NV04_DISPLAY_CLASS, 0x680524, "SEL_CLK" }, + { NV17_DISPLAY_CLASS, 0x68052c, "DACCLK_A" }, + { NV17_DISPLAY_CLASS, 0x680594, "DACCLK_B" }, + { NV04_DISPLAY_CLASS, 0x68050c, "PLL_COEFF_SELECT" }, + { NV04_DISPLAY_CLASS, 0x680630 }, + { NV04_DISPLAY_CLASS, 0x680674 }, + { NV04_DISPLAY_CLASS, 0x680700, "TV_SETUP" }, + { NV04_DISPLAY_CLASS, 0x680704, "TV_VBLANK_START" }, + { NV04_DISPLAY_CLASS, 0x680708, "TV_VBLANK_END" }, + { NV04_DISPLAY_CLASS, 0x68070c, "TV_HBLANK_START" }, + { NV04_DISPLAY_CLASS, 0x680710, "TV_HBLANK_END" }, + { NV04_DISPLAY_CLASS, 0x680714, "TV_BLANK_COLOR" }, + { NV04_DISPLAY_CLASS, 0x680720, "TV_VTOTAL" }, + { NV04_DISPLAY_CLASS, 0x680724, "TV_VSYNC_START" }, + { NV04_DISPLAY_CLASS, 0x680728, "TV_VSYNC_END" }, + { NV04_DISPLAY_CLASS, 0x68072c, "TV_HTOTAL" }, + { NV04_DISPLAY_CLASS, 0x680730, "TV_HSYNC_START" }, + { NV04_DISPLAY_CLASS, 0x680734, "TV_HSYNC_STOP" }, + { NV04_DISPLAY_CLASS, 0x680738, "TV_SYNC_DELAY" }, + { NV04_DISPLAY_CLASS, 0x680880, "FP_DEBUG_0" }, + { NV04_DISPLAY_CLASS, 0x680884, "FP_DEBUG_1" }, + { NV04_DISPLAY_CLASS, 0x680888, "FP_DEBUG_2" }, + { NV04_DISPLAY_CLASS, 0x680848, "FP_TG_CONTROL" }, + { NV04_DISPLAY_CLASS, 0x680824, "FP_HTOTAL" }, + { NV04_DISPLAY_CLASS, 0x680834, "FP_HVALID_START" }, + { NV04_DISPLAY_CLASS, 0x680838, "FP_HVALID_END" }, + { NV04_DISPLAY_CLASS, 0x680820, "FP_HDISPLAY_END" }, + { NV04_DISPLAY_CLASS, 0x680828, "FP_HCRTC" }, + { NV04_DISPLAY_CLASS, 0x68082c, "FP_HSYNC_START" }, + { NV04_DISPLAY_CLASS, 0x680830, "FP_HSYNC_END" }, + { NV04_DISPLAY_CLASS, 0x680804, "FP_VTOTAL" }, + { NV04_DISPLAY_CLASS, 0x680814, "FP_VVALID_START" }, + { NV04_DISPLAY_CLASS, 0x680818, "FP_VVALID_END" }, + { NV04_DISPLAY_CLASS, 0x680800, "FP_VDISPLAY_END" }, + { NV04_DISPLAY_CLASS, 0x680808, "FP_VCRTC" }, + { NV04_DISPLAY_CLASS, 0x68080c, "FP_VSYNC_START" }, + { NV04_DISPLAY_CLASS, 0x680810, "FP_VSYNC_END" }, + { NV04_DISPLAY_CLASS, 0x68084c }, + { NV04_DISPLAY_CLASS, 0x680898 }, + { NV04_DISPLAY_CLASS, 0x68089c }, + { NV04_DISPLAY_CLASS, 0x6808c0 }, + { NV04_DISPLAY_CLASS, 0x680900 }, + { NV40_CLASS, 0x680c00 }, + { NV40_CLASS, 0x680c04 }, + { NV40_CLASS, 0x680c08 }, + { NV40_CLASS, 0x680c0c }, + { NV40_CLASS, 0x680c10 }, + { NV40_CLASS, 0x680c14 }, + { NV40_CLASS, 0x680c18 }, + { NV40_CLASS, 0x680c1c }, + { NV40_CLASS, 0x680c20 }, + { NV40_CLASS, 0x680c24 }, + { NV40_CLASS, 0x680c28 }, + { NV40_CLASS, 0x680c2c }, + { NV40_CLASS, 0x680c30 }, + { NV40_CLASS, 0x680c34 }, + { NV40_CLASS, 0x680c38 }, + { NV40_CLASS, 0x680c3c }, + { NV40_CLASS, 0x680c40 }, + { NV40_CLASS, 0x680c44 }, + { NV40_CLASS, 0x680c48 }, + { NV40_CLASS, 0x680c4c }, + { NV40_CLASS, 0x680c50 }, + { NV40_CLASS, 0x680c54 }, + { NV40_CLASS, 0x680c58 }, + { NV40_CLASS, 0x680c5c }, + { NV40_CLASS, 0x680c60 }, + { NV40_CLASS, 0x680c64 }, + { NV40_CLASS, 0x680c68 }, + { NV40_CLASS, 0x680c6c }, + { NV40_CLASS, 0x680c70 }, + { NV40_CLASS, 0x680c74 }, + { NV40_CLASS, 0x680c78 }, + { NV40_CLASS, 0x680c7c }, + { NV40_CLASS, 0x680c80 }, + { NV40_CLASS, 0x680c84 }, + { NV40_CLASS, 0x680c88 }, + { NV40_CLASS, 0x680c8c }, + { NV40_CLASS, 0x680c90 }, + { NV40_CLASS, 0x680c94 }, + { NV40_CLASS, 0x680c98 }, + { NV40_CLASS, 0x680c9c }, + { NV40_CLASS, 0x680ca0 }, + { NV40_CLASS, 0x680ca4 }, + { NV40_CLASS, 0x680ca8 }, + { NV40_CLASS, 0x680cac }, + { NV40_CLASS, 0x680cb0 }, + { NV40_CLASS, 0x680cb4 }, + { NV40_CLASS, 0x680cb8 }, + { NV40_CLASS, 0x680cbc }, + { NV40_CLASS, 0x680cc0 }, + { NV40_CLASS, 0x680cc4 }, + { NV40_CLASS, 0x680cc8 }, + { NV40_CLASS, 0x680ccc }, + { NV40_CLASS, 0x680cd0 }, + { NV40_CLASS, 0x680cd4 }, + { NV40_CLASS, 0x680cd8 }, + { NV40_CLASS, 0x680cdc }, + { NV40_CLASS, 0x680ce0 }, + { NV40_CLASS, 0x680ce4 }, + { NV40_CLASS, 0x680ce8 }, + { NV40_CLASS, 0x680cec }, + { NV40_CLASS, 0x680cf0 }, + { NV40_CLASS, 0x680cf4 }, + { NV40_CLASS, 0x680cf8 }, + { NV40_CLASS, 0x680cfc }, + { } +}; + +struct reg ptv_block[] = { + { NV17_TVOUT_CLASS, 0xd200 }, + { NV17_TVOUT_CLASS, 0xd204 }, + { NV17_TVOUT_CLASS, 0xd208 }, + { NV17_TVOUT_CLASS, 0xd20c }, + { NV17_TVOUT_CLASS, 0xd300 }, + { NV17_TVOUT_CLASS, 0xd304 }, + { NV17_TVOUT_CLASS, 0xd308 }, + { NV17_TVOUT_CLASS, 0xd30c }, + { NV17_TVOUT_CLASS, 0xd310 }, + { NV17_TVOUT_CLASS, 0xd314 }, + { NV17_TVOUT_CLASS, 0xd318 }, + { NV17_TVOUT_CLASS, 0xd31c }, + { NV17_TVOUT_CLASS, 0xd320 }, + { NV17_TVOUT_CLASS, 0xd324 }, + { NV17_TVOUT_CLASS, 0xd328 }, + { NV17_TVOUT_CLASS, 0xd32c }, + { NV17_TVOUT_CLASS, 0xd330 }, + { NV17_TVOUT_CLASS, 0xd334 }, + { NV17_TVOUT_CLASS, 0xd338 }, + { NV17_TVOUT_CLASS, 0xd33c }, + { NV17_TVOUT_CLASS, 0xd340 }, + { NV17_TVOUT_CLASS, 0xd344 }, + { NV17_TVOUT_CLASS, 0xd348 }, + { NV17_TVOUT_CLASS, 0xd34c }, + { NV17_TVOUT_CLASS, 0xd350 }, + { NV17_TVOUT_CLASS, 0xd354 }, + { NV17_TVOUT_CLASS, 0xd358 }, + { NV17_TVOUT_CLASS, 0xd35c }, + { NV17_TVOUT_CLASS, 0xd360 }, + { NV17_TVOUT_CLASS, 0xd364 }, + { NV17_TVOUT_CLASS, 0xd368 }, + { NV17_TVOUT_CLASS, 0xd36c }, + { NV17_TVOUT_CLASS, 0xd370 }, + { NV17_TVOUT_CLASS, 0xd374 }, + { NV17_TVOUT_CLASS, 0xd378 }, + { NV17_TVOUT_CLASS, 0xd37c }, + { NV17_TVOUT_CLASS, 0xd380 }, + { NV17_TVOUT_CLASS, 0xd384 }, + { NV17_TVOUT_CLASS, 0xd388 }, + { NV17_TVOUT_CLASS, 0xd38c }, + { NV17_TVOUT_CLASS, 0xd390 }, + { NV17_TVOUT_CLASS, 0xd394 }, + { NV17_TVOUT_CLASS, 0xd398 }, + { NV17_TVOUT_CLASS, 0xd39c }, + { NV17_TVOUT_CLASS, 0xd3a0 }, + { NV17_TVOUT_CLASS, 0xd3a4 }, + { NV17_TVOUT_CLASS, 0xd3a8 }, + { NV17_TVOUT_CLASS, 0xd3ac }, + { NV17_TVOUT_CLASS, 0xd3b0 }, + { NV17_TVOUT_CLASS, 0xd3b4 }, + { NV17_TVOUT_CLASS, 0xd3b8 }, + { NV17_TVOUT_CLASS, 0xd3bc }, + { NV17_TVOUT_CLASS, 0xd3c0 }, + { NV17_TVOUT_CLASS, 0xd3c4 }, + { NV17_TVOUT_CLASS, 0xd3c8 }, + { NV17_TVOUT_CLASS, 0xd3cc }, + { NV17_TVOUT_CLASS, 0xd3d0 }, + { NV17_TVOUT_CLASS, 0xd3d4 }, + { NV17_TVOUT_CLASS, 0xd3d8 }, + { NV17_TVOUT_CLASS, 0xd3dc }, + { NV17_TVOUT_CLASS, 0xd3e0 }, + { NV17_TVOUT_CLASS, 0xd3e4 }, + { NV17_TVOUT_CLASS, 0xd3e8 }, + { NV17_TVOUT_CLASS, 0xd3ec }, + { NV17_TVOUT_CLASS, 0xd3f0 }, + { NV17_TVOUT_CLASS, 0xd3f4 }, + { NV17_TVOUT_CLASS, 0xd3f8 }, + { NV17_TVOUT_CLASS, 0xd3fc }, + { NV17_TVOUT_CLASS, 0xd400 }, + { NV17_TVOUT_CLASS, 0xd404 }, + { NV17_TVOUT_CLASS, 0xd408 }, + { NV17_TVOUT_CLASS, 0xd40c }, + { NV17_TVOUT_CLASS, 0xd500 }, + { NV17_TVOUT_CLASS, 0xd504 }, + { NV17_TVOUT_CLASS, 0xd508 }, + { NV17_TVOUT_CLASS, 0xd50c }, + { NV17_TVOUT_CLASS, 0xd510 }, + { NV17_TVOUT_CLASS, 0xd514 }, + { NV17_TVOUT_CLASS, 0xd518 }, + { NV17_TVOUT_CLASS, 0xd51c }, + { NV17_TVOUT_CLASS, 0xd520 }, + { NV17_TVOUT_CLASS, 0xd524 }, + { NV17_TVOUT_CLASS, 0xd528 }, + { NV17_TVOUT_CLASS, 0xd52c }, + { NV17_TVOUT_CLASS, 0xd530 }, + { NV17_TVOUT_CLASS, 0xd534 }, + { NV17_TVOUT_CLASS, 0xd538 }, + { NV17_TVOUT_CLASS, 0xd53c }, + { NV17_TVOUT_CLASS, 0xd540 }, + { NV17_TVOUT_CLASS, 0xd544 }, + { NV17_TVOUT_CLASS, 0xd548 }, + { NV17_TVOUT_CLASS, 0xd54c }, + { NV17_TVOUT_CLASS, 0xd550 }, + { NV17_TVOUT_CLASS, 0xd554 }, + { NV17_TVOUT_CLASS, 0xd558 }, + { NV17_TVOUT_CLASS, 0xd55c }, + { NV17_TVOUT_CLASS, 0xd560 }, + { NV17_TVOUT_CLASS, 0xd564 }, + { NV17_TVOUT_CLASS, 0xd568 }, + { NV17_TVOUT_CLASS, 0xd56c }, + { NV17_TVOUT_CLASS, 0xd570 }, + { NV17_TVOUT_CLASS, 0xd574 }, + { NV17_TVOUT_CLASS, 0xd578 }, + { NV17_TVOUT_CLASS, 0xd57c }, + { NV17_TVOUT_CLASS, 0xd580 }, + { NV17_TVOUT_CLASS, 0xd584 }, + { NV17_TVOUT_CLASS, 0xd588 }, + { NV17_TVOUT_CLASS, 0xd58c }, + { NV17_TVOUT_CLASS, 0xd600 }, + { NV17_TVOUT_CLASS, 0xd604 }, + { NV17_TVOUT_CLASS, 0xd608 }, + { NV17_TVOUT_CLASS, 0xd60c }, + { NV17_TVOUT_CLASS, 0xd610 }, + { NV17_TVOUT_CLASS, 0xd614 }, + { NV17_TVOUT_CLASS, 0xd618 }, + { NV17_TVOUT_CLASS, 0xd61c }, + { } +}; + +struct reg itv_block[] = { + { NV17_TVOUT_CLASS, 0x0 }, + { NV17_TVOUT_CLASS, 0x1 }, + { NV17_TVOUT_CLASS, 0x2 }, + { NV17_TVOUT_CLASS, 0x3 }, + { NV17_TVOUT_CLASS, 0x4 }, + { NV17_TVOUT_CLASS, 0x5 }, + { NV17_TVOUT_CLASS, 0x6 }, + { NV17_TVOUT_CLASS, 0x7 }, + { NV17_TVOUT_CLASS, 0x8 }, + { NV17_TVOUT_CLASS, 0x9 }, + { NV17_TVOUT_CLASS, 0xa }, + { NV17_TVOUT_CLASS, 0xb }, + { NV17_TVOUT_CLASS, 0xc }, + { NV17_TVOUT_CLASS, 0xd }, + { NV17_TVOUT_CLASS, 0xe }, + { NV17_TVOUT_CLASS, 0xf }, + { NV17_TVOUT_CLASS, 0x10 }, + { NV17_TVOUT_CLASS, 0x11 }, + { NV17_TVOUT_CLASS, 0x12 }, + { NV17_TVOUT_CLASS, 0x13 }, + { NV17_TVOUT_CLASS, 0x14 }, + { NV17_TVOUT_CLASS, 0x15 }, + { NV17_TVOUT_CLASS, 0x16 }, + { NV17_TVOUT_CLASS, 0x17 }, + { NV17_TVOUT_CLASS, 0x18 }, + { NV17_TVOUT_CLASS, 0x19 }, + { NV17_TVOUT_CLASS, 0x1a }, + { NV17_TVOUT_CLASS, 0x1b }, + { NV17_TVOUT_CLASS, 0x1c }, + { NV17_TVOUT_CLASS, 0x1d }, + { NV17_TVOUT_CLASS, 0x1e }, + { NV17_TVOUT_CLASS, 0x1f }, + { NV17_TVOUT_CLASS, 0x20 }, + { NV17_TVOUT_CLASS, 0x21 }, + { NV17_TVOUT_CLASS, 0x22 }, + { NV17_TVOUT_CLASS, 0x23 }, + { NV17_TVOUT_CLASS, 0x24 }, + { NV17_TVOUT_CLASS, 0x25 }, + { NV17_TVOUT_CLASS, 0x26 }, + { NV17_TVOUT_CLASS, 0x27 }, + { NV17_TVOUT_CLASS, 0x28 }, + { NV17_TVOUT_CLASS, 0x29 }, + { NV17_TVOUT_CLASS, 0x2a }, + { NV17_TVOUT_CLASS, 0x2b }, + { NV17_TVOUT_CLASS, 0x2c }, + { NV17_TVOUT_CLASS, 0x2d }, + { NV17_TVOUT_CLASS, 0x2e }, + { NV17_TVOUT_CLASS, 0x2f }, + { NV17_TVOUT_CLASS, 0x30 }, + { NV17_TVOUT_CLASS, 0x31 }, + { NV17_TVOUT_CLASS, 0x32 }, + { NV17_TVOUT_CLASS, 0x33 }, + { NV17_TVOUT_CLASS, 0x34 }, + { NV17_TVOUT_CLASS, 0x35 }, + { NV17_TVOUT_CLASS, 0x36 }, + { NV17_TVOUT_CLASS, 0x37 }, + { NV17_TVOUT_CLASS, 0x38 }, + { NV17_TVOUT_CLASS, 0x39 }, + { NV17_TVOUT_CLASS, 0x3a }, + { NV17_TVOUT_CLASS, 0x3b }, + { NV17_TVOUT_CLASS, 0x3c }, + { NV17_TVOUT_CLASS, 0x3d }, + { NV17_TVOUT_CLASS, 0x3e }, + { NV17_TVOUT_CLASS, 0x3f }, + { } +}; + +struct reg tmds_block[] = { + { NV04_DISPLAY_CLASS, 0x0 }, + { NV04_DISPLAY_CLASS, 0x1 }, + { NV04_DISPLAY_CLASS, 0x2 }, + { NV04_DISPLAY_CLASS, 0x3 }, + { NV04_DISPLAY_CLASS, 0x4 }, + { NV04_DISPLAY_CLASS, 0x5 }, + { NV04_DISPLAY_CLASS, 0x6 }, + { NV04_DISPLAY_CLASS, 0x7 }, + { NV04_DISPLAY_CLASS, 0x8 }, + { NV04_DISPLAY_CLASS, 0x9 }, + { NV04_DISPLAY_CLASS, 0xa }, + { NV04_DISPLAY_CLASS, 0xb }, + { NV04_DISPLAY_CLASS, 0xc }, + { NV04_DISPLAY_CLASS, 0xd }, + { NV04_DISPLAY_CLASS, 0xe }, + { NV04_DISPLAY_CLASS, 0xf }, + { NV04_DISPLAY_CLASS, 0x10 }, + { NV04_DISPLAY_CLASS, 0x11 }, + { NV04_DISPLAY_CLASS, 0x12 }, + { NV04_DISPLAY_CLASS, 0x13 }, + { NV04_DISPLAY_CLASS, 0x14 }, + { NV04_DISPLAY_CLASS, 0x15 }, + { NV04_DISPLAY_CLASS, 0x16 }, + { NV04_DISPLAY_CLASS, 0x17 }, + { NV04_DISPLAY_CLASS, 0x18 }, + { NV04_DISPLAY_CLASS, 0x19 }, + { NV04_DISPLAY_CLASS, 0x1a }, + { NV04_DISPLAY_CLASS, 0x1b }, + { NV04_DISPLAY_CLASS, 0x1c }, + { NV04_DISPLAY_CLASS, 0x1d }, + { NV04_DISPLAY_CLASS, 0x1e }, + { NV04_DISPLAY_CLASS, 0x1f }, + { NV04_DISPLAY_CLASS, 0x20 }, + { NV04_DISPLAY_CLASS, 0x21 }, + { NV04_DISPLAY_CLASS, 0x22 }, + { NV04_DISPLAY_CLASS, 0x23 }, + { NV04_DISPLAY_CLASS, 0x24 }, + { NV04_DISPLAY_CLASS, 0x25 }, + { NV04_DISPLAY_CLASS, 0x26 }, + { NV04_DISPLAY_CLASS, 0x27 }, + { NV04_DISPLAY_CLASS, 0x28 }, + { NV04_DISPLAY_CLASS, 0x29 }, + { NV04_DISPLAY_CLASS, 0x2a }, + { NV04_DISPLAY_CLASS, 0x2b }, + { NV04_DISPLAY_CLASS, 0x2c }, + { NV04_DISPLAY_CLASS, 0x2d }, + { NV04_DISPLAY_CLASS, 0x2e }, + { NV04_DISPLAY_CLASS, 0x2f }, + { NV04_DISPLAY_CLASS, 0x30 }, + { NV04_DISPLAY_CLASS, 0x31 }, + { NV04_DISPLAY_CLASS, 0x32 }, + { NV04_DISPLAY_CLASS, 0x33 }, + { NV04_DISPLAY_CLASS, 0x34 }, + { NV04_DISPLAY_CLASS, 0x35 }, + { NV04_DISPLAY_CLASS, 0x36 }, + { NV04_DISPLAY_CLASS, 0x37 }, + { NV04_DISPLAY_CLASS, 0x38 }, + { NV04_DISPLAY_CLASS, 0x39 }, + { NV04_DISPLAY_CLASS, 0x3a }, + { NV04_DISPLAY_CLASS, 0x3b }, + { NV04_DISPLAY_CLASS, 0x3c }, + { NV04_DISPLAY_CLASS, 0x3d }, + { NV04_DISPLAY_CLASS, 0x3e }, + { NV04_DISPLAY_CLASS, 0x3f }, + { } +}; + +struct reg pvideo_block[] = { + { NV04_OVERLAY_CLASS, 0x8080, "DEBUG_0" }, + { NV04_OVERLAY_CLASS, 0x8084, "DEBUG_1" }, + { NV04_OVERLAY_CLASS, 0x8088, "DEBUG_2" }, + { NV04_OVERLAY_CLASS, 0x808c, "DEBUG_3" }, + { NV04_OVERLAY_CLASS, 0x8090, "DEBUG_4" }, + { NV04_OVERLAY_CLASS, 0x8094, "DEBUG_5" }, + { NV04_OVERLAY_CLASS, 0x8098, "DEBUG_6" }, + { NV04_OVERLAY_CLASS, 0x809c, "DEBUG_7" }, + { NV04_OVERLAY_CLASS, 0x80a0, "DEBUG_8" }, + { NV04_OVERLAY_CLASS, 0x80a4, "DEBUG_9" }, + { NV04_OVERLAY_CLASS, 0x80a8, "DEBUG_10" }, + { NV04_OVERLAY_CLASS, 0x8100, "INTR" }, + { NV04_OVERLAY_CLASS, 0x8104, "INTR_REASON" }, + { NV04_OVERLAY_CLASS, 0x8140, "INTR_EN" }, + { NV04_OVERLAY_CLASS, 0x8700, "BUFFER" }, + { NV04_OVERLAY_CLASS, 0x8704, "STOP" }, + { NV04_OVERLAY_CLASS, 0x8900, "BASE" }, + { NV04_OVERLAY_CLASS, 0x8908, "LIMIT" }, + { NV04_OVERLAY_CLASS, 0x8910, "LUMINANCE" }, + { NV04_OVERLAY_CLASS, 0x8918, "CHROMINANCE" }, + { NV04_OVERLAY_CLASS, 0x8920, "OFFSET" }, + { NV04_OVERLAY_CLASS, 0x8928, "SIZE_IN" }, + { NV04_OVERLAY_CLASS, 0x8930, "POINT_IN" }, + { NV04_OVERLAY_CLASS, 0x8938, "DS_DX" }, + { NV04_OVERLAY_CLASS, 0x8940, "DT_DY" }, + { NV04_OVERLAY_CLASS, 0x8948, "POINT_OUT" }, + { NV04_OVERLAY_CLASS, 0x8950, "SIZE_OUT" }, + { NV04_OVERLAY_CLASS, 0x8958, "FORMAT" }, + { NV04_OVERLAY_CLASS, 0x8b00, "COLOR_KEY" }, + { NV04_OVERLAY_CLASS, 0x8d00, "TEST" }, + { NV04_OVERLAY_CLASS, 0x8d10, "TST_WRITE" }, + { NV04_OVERLAY_CLASS, 0x8d40, "TST_READ" }, + { } +}; @@ -1,508 +1,86 @@ -/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ /* - * Copyright 1996-1997 David J. McKay + * Copyright 1996-1997 David J. McKay + * Copyright 2010 Francisco Jerez. + * All Rights Reserved. * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */ - -#ifndef __NVREG_H_ -#define __NVREG_H_ - -#define NV_PMC_OFFSET 0x00000000 -#define NV_PMC_SIZE 0x00001000 - -#define NV_PBUS_OFFSET 0x00001000 -#define NV_PBUS_SIZE 0x00001000 - -#define NV_PFIFO_OFFSET 0x00002000 -#define NV_PFIFO_SIZE 0x00002000 - -#define NV_HDIAG_OFFSET 0x00005000 -#define NV_HDIAG_SIZE 0x00001000 - -#define NV_PRAM_OFFSET 0x00006000 -#define NV_PRAM_SIZE 0x00001000 - -#define NV_PVIDEO_OFFSET 0x00008000 -#define NV_PVIDEO_SIZE 0x00001000 - -#define NV_PTIMER_OFFSET 0x00009000 -#define NV_PTIMER_SIZE 0x00001000 - -#define NV_PPM_OFFSET 0x0000A000 -#define NV_PPM_SIZE 0x00001000 - -#define NV_PRMVGA_OFFSET 0x000A0000 -#define NV_PRMVGA_SIZE 0x00020000 - -#define NV_PRMVIO0_OFFSET 0x000C0000 -#define NV_PRMVIO_SIZE 0x00002000 -#define NV_PRMVIO1_OFFSET 0x000C2000 - -#define NV_PFB_OFFSET 0x00100000 -#define NV_PFB_SIZE 0x00001000 - -#define NV_PEXTDEV_OFFSET 0x00101000 -#define NV_PEXTDEV_SIZE 0x00001000 - -#define NV_PME_OFFSET 0x00200000 -#define NV_PME_SIZE 0x00001000 - -#define NV_PROM_OFFSET 0x00300000 -#define NV_PROM_SIZE 0x00010000 - -#define NV_PGRAPH_OFFSET 0x00400000 -#define NV_PGRAPH_SIZE 0x00010000 - -#define NV_PCRTC0_OFFSET 0x00600000 -#define NV_PCRTC0_SIZE 0x00002000 /* empirical */ - -#define NV_PRMCIO0_OFFSET 0x00601000 -#define NV_PRMCIO_SIZE 0x00002000 -#define NV_PRMCIO1_OFFSET 0x00603000 - -#define NV50_DISPLAY_OFFSET 0x00610000 -#define NV50_DISPLAY_SIZE 0x0000FFFF - -#define NV_PRAMDAC0_OFFSET 0x00680000 -#define NV_PRAMDAC0_SIZE 0x00002000 - -#define NV_PRMDIO0_OFFSET 0x00681000 -#define NV_PRMDIO_SIZE 0x00002000 -#define NV_PRMDIO1_OFFSET 0x00683000 - -#define NV_PRAMIN_OFFSET 0x00700000 -#define NV_PRAMIN_SIZE 0x00100000 - -#define NV_FIFO_OFFSET 0x00800000 -#define NV_FIFO_SIZE 0x00800000 - -#define NV_PMC_BOOT_0 0x00000000 -#define NV_PMC_ENABLE 0x00000200 - -#define NV_VIO_VSE2 0x000003c3 -#define NV_VIO_SRX 0x000003c4 - -#define NV_CIO_CRX__COLOR 0x000003d4 -#define NV_CIO_CR__COLOR 0x000003d5 - -#define NV_PBUS_DEBUG_1 0x00001084 -#define NV_PBUS_DEBUG_4 0x00001098 -#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0 -#define NV_PBUS_POWERCTRL_1 0x00001584 -#define NV_PBUS_POWERCTRL_2 0x00001588 -#define NV_PBUS_POWERCTRL_4 0x00001590 -#define NV_PBUS_PCI_NV_19 0x0000184C -#define NV_PBUS_PCI_NV_20 0x00001850 -# define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) -# define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) - -#define NV_PFIFO_RAMHT 0x00002210 - -#define NV_PRMVIO_MISC__WRITE 0x000c03c2 -#define NV_PRMVIO_SRX 0x000c03c4 -#define NV_PRMVIO_SR 0x000c03c5 -# define NV_VIO_SR_RESET_INDEX 0x00 -# define NV_VIO_SR_CLOCK_INDEX 0x01 -# define NV_VIO_SR_PLANE_MASK_INDEX 0x02 -# define NV_VIO_SR_CHAR_MAP_INDEX 0x03 -# define NV_VIO_SR_MEM_MODE_INDEX 0x04 -#define NV_PRMVIO_MISC__READ 0x000c03cc -#define NV_PRMVIO_GRX 0x000c03ce -#define NV_PRMVIO_GX 0x000c03cf -# define NV_VIO_GX_SR_INDEX 0x00 -# define NV_VIO_GX_SREN_INDEX 0x01 -# define NV_VIO_GX_CCOMP_INDEX 0x02 -# define NV_VIO_GX_ROP_INDEX 0x03 -# define NV_VIO_GX_READ_MAP_INDEX 0x04 -# define NV_VIO_GX_MODE_INDEX 0x05 -# define NV_VIO_GX_MISC_INDEX 0x06 -# define NV_VIO_GX_DONT_CARE_INDEX 0x07 -# define NV_VIO_GX_BIT_MASK_INDEX 0x08 - -#define NV_PFB_BOOT_0 0x00100000 -#define NV_PFB_CFG0 0x00100200 -#define NV_PFB_CFG1 0x00100204 -#define NV_PFB_CSTATUS 0x0010020C -#define NV_PFB_REFCTRL 0x00100210 -# define NV_PFB_REFCTRL_VALID_1 (1 << 31) -#define NV_PFB_PAD 0x0010021C -# define NV_PFB_PAD_CKE_NORMAL (1 << 0) -#define NV_PFB_TILE_NV10 0x00100240 -#define NV_PFB_TILE_SIZE_NV10 0x00100244 -#define NV_PFB_REF 0x001002D0 -# define NV_PFB_REF_CMD_REFRESH (1 << 0) -#define NV_PFB_PRE 0x001002D4 -# define NV_PFB_PRE_CMD_PRECHARGE (1 << 0) -#define NV_PFB_CLOSE_PAGE2 0x0010033C -#define NV_PFB_TILE_NV40 0x00100600 -#define NV_PFB_TILE_SIZE_NV40 0x00100604 - -#define NV_PEXTDEV_BOOT_0 0x00101000 -# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12) -#define NV_PEXTDEV_BOOT_3 0x0010100c - -#define NV_PCRTC_INTR_0 0x00600100 -# define NV_PCRTC_INTR_0_VBLANK (1 << 0) -#define NV_PCRTC_INTR_EN_0 0x00600140 -#define NV_PCRTC_START 0x00600800 -#define NV_PCRTC_CONFIG 0x00600804 -# define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA (1 << 0) -# define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC (2 << 0) -#define NV_PCRTC_CURSOR_CONFIG 0x00600810 -# define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE (1 << 0) -# define NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE (1 << 4) -# define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM (1 << 8) -# define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32 (1 << 12) -# define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 (1 << 16) -# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32 (2 << 24) -# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 (4 << 24) -# define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA (1 << 28) - -/* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */ -#define NV_PCRTC_GPIO 0x00600818 -#define NV_PCRTC_GPIO_EXT 0x0060081c -#define NV_PCRTC_830 0x00600830 -#define NV_PCRTC_834 0x00600834 -#define NV_PCRTC_850 0x00600850 -#define NV_PCRTC_ENGINE_CTRL 0x00600860 -# define NV_CRTC_FSEL_I2C (1 << 4) -# define NV_CRTC_FSEL_OVERLAY (1 << 12) - -#define NV_PRMCIO_ARX 0x006013c0 -#define NV_PRMCIO_AR__WRITE 0x006013c0 -#define NV_PRMCIO_AR__READ 0x006013c1 -# define NV_CIO_AR_MODE_INDEX 0x10 -# define NV_CIO_AR_OSCAN_INDEX 0x11 -# define NV_CIO_AR_PLANE_INDEX 0x12 -# define NV_CIO_AR_HPP_INDEX 0x13 -# define NV_CIO_AR_CSEL_INDEX 0x14 -#define NV_PRMCIO_INP0 0x006013c2 -#define NV_PRMCIO_CRX__COLOR 0x006013d4 -#define NV_PRMCIO_CR__COLOR 0x006013d5 - /* Standard VGA CRTC registers */ -# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */ -# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */ -# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */ -# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */ -# define NV_CIO_CR_HBE_4_0 4:0 -# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */ -# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */ -# define NV_CIO_CR_HRE_4_0 4:0 -# define NV_CIO_CR_HRE_HBE_5 7:7 -# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */ -# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */ -# define NV_CIO_CR_OVL_VDT_8 0:0 -# define NV_CIO_CR_OVL_VDE_8 1:1 -# define NV_CIO_CR_OVL_VRS_8 2:2 -# define NV_CIO_CR_OVL_VBS_8 3:3 -# define NV_CIO_CR_OVL_VDT_9 5:5 -# define NV_CIO_CR_OVL_VDE_9 6:6 -# define NV_CIO_CR_OVL_VRS_9 7:7 -# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */ -# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */ -# define NV_CIO_CR_CELL_HT_VBS_9 5:5 -# define NV_CIO_CR_CELL_HT_SCANDBL 7:7 -# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */ -# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */ -# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */ -# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */ -# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */ -# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */ -# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */ -# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */ -# define NV_CIO_CR_VRE_3_0 3:0 -# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */ -# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */ -# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */ -# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */ -# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */ -# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */ -# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */ - /* Extended VGA CRTC registers */ -# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */ -# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5 -# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */ -# define NV_CIO_CRE_RPC1_LARGE 2:2 -# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */ -# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */ -# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */ -# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57 -# define NV_CIO_SR_LOCK_VALUE 0x99 -# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */ -# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */ -# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */ -# define NV_CIO_CRE_LSR_VDT_10 0:0 -# define NV_CIO_CRE_LSR_VDE_10 1:1 -# define NV_CIO_CRE_LSR_VRS_10 2:2 -# define NV_CIO_CRE_LSR_VBS_10 3:3 -# define NV_CIO_CRE_LSR_HBE_6 4:4 -# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */ -# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */ -# define NV_CIO_CRE_PIXEL_INDEX 0x28 -# define NV_CIO_CRE_PIXEL_FORMAT 1:0 -# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */ -# define NV_CIO_CRE_HEB_HDT_8 0:0 -# define NV_CIO_CRE_HEB_HDE_8 1:1 -# define NV_CIO_CRE_HEB_HBS_8 2:2 -# define NV_CIO_CRE_HEB_HRS_8 3:3 -# define NV_CIO_CRE_HEB_ILC_8 4:4 -# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */ -# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */ -# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */ -# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0 -# define NV_CIO_CRE_HCUR_ASI 7:7 -# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */ -# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0 -# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1 -# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2 -# define NV_CIO_CRE_LCD__INDEX 0x33 -# define NV_CIO_CRE_LCD_LCD_SELECT 0:0 -# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36 -# define NV_CIO_CRE_DDC0_WR__INDEX 0x37 -# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */ -# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b -# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c -# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e -# define NV_CIO_CRE_DDC_WR__INDEX 0x3f -# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */ -# define NV_CIO_CRE_EBR_VDT_11 0:0 -# define NV_CIO_CRE_EBR_VDE_11 2:2 -# define NV_CIO_CRE_EBR_VRS_11 4:4 -# define NV_CIO_CRE_EBR_VBS_11 6:6 -# define NV_CIO_CRE_43 0x43 -# define NV_CIO_CRE_44 0x44 /* head control */ -# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */ -# define NV_CIO_CRE_RCR 0x46 -# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7 -# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */ -# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */ -# define NV_CIO_CRE_TVOUT_LATENCY 0x52 -# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */ -# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */ -# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */ -# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */ -# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */ -# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */ -# define NV_CIO_CRE_85 0x85 -# define NV_CIO_CRE_86 0x86 -#define NV_PRMCIO_INP0__COLOR 0x006013da - -#define NV_PRAMDAC_CU_START_POS 0x00680300 -# define NV_PRAMDAC_CU_START_POS_X 15:0 -# define NV_PRAMDAC_CU_START_POS_Y 31:16 -#define NV_RAMDAC_NV10_CURSYNC 0x00680404 - -#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 -#define NV_PRAMDAC_MPLL_COEFF 0x00680504 -#define NV_PRAMDAC_VPLL_COEFF 0x00680508 -# define NV30_RAMDAC_ENABLE_VCO2 (8 << 4) - -#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c -# define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (4 << 0) -# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL (1 << 8) -# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL (2 << 8) -# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL (4 << 8) -# define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (8 << 8) -# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 (1 << 28) -# define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (2 << 28) - -#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510 -#define NV_RAMDAC_VPLL2 0x00680520 -#define NV_PRAMDAC_SEL_CLK 0x00680524 -#define NV_RAMDAC_DITHER_NV11 0x00680528 -#define NV_PRAMDAC_DACCLK 0x0068052c -# define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0) - -#define NV_RAMDAC_NVPLL_B 0x00680570 -#define NV_RAMDAC_MPLL_B 0x00680574 -#define NV_RAMDAC_VPLL_B 0x00680578 -#define NV_RAMDAC_VPLL2_B 0x0068057c -# define NV31_RAMDAC_ENABLE_VCO2 (8 << 28) -#define NV_PRAMDAC_580 0x00680580 -# define NV_RAMDAC_580_VPLL1_ACTIVE (1 << 8) -# define NV_RAMDAC_580_VPLL2_ACTIVE (1 << 28) - -#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 -# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4) -# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8) -# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12) -# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16) -# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20) -# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28) -#define NV_PRAMDAC_TEST_CONTROL 0x00680608 -# define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12) -# define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16) -# define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28) -#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610 -# define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (8 << 28) -#define NV_PRAMDAC_630 0x00680630 -#define NV_PRAMDAC_634 0x00680634 - -#define NV_PRAMDAC_TV_SETUP 0x00680700 - -#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800 -#define NV_PRAMDAC_FP_VTOTAL 0x00680804 -#define NV_PRAMDAC_FP_VCRTC 0x00680808 -#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c -#define NV_PRAMDAC_FP_VSYNC_END 0x00680810 -#define NV_PRAMDAC_FP_VVALID_START 0x00680814 -#define NV_PRAMDAC_FP_VVALID_END 0x00680818 -#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820 -#define NV_PRAMDAC_FP_HTOTAL 0x00680824 -#define NV_PRAMDAC_FP_HCRTC 0x00680828 -#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c -#define NV_PRAMDAC_FP_HSYNC_END 0x00680830 -#define NV_PRAMDAC_FP_HVALID_START 0x00680834 -#define NV_PRAMDAC_FP_HVALID_END 0x00680838 - -#define NV_RAMDAC_FP_DITHER 0x0068083c -#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848 -# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0) -# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0) -# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS (1 << 4) -# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE (2 << 4) -# define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8) -# define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER (1 << 8) -# define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE (2 << 8) -# define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG (1 << 20) -# define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24) -# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28) -# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28) -#define NV_PRAMDAC_850 0x00680850 -#define NV_PRAMDAC_85C 0x0068085c -#define NV_PRAMDAC_FP_DEBUG_0 0x00680880 -# define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0) -# define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE (1 << 4) -/* This doesn't seem to be essential for tmds, but still often set */ -# define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (8 << 4) -# define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR (1 << 8) -# define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR (1 << 12) -# define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND (1 << 20) -# define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND (1 << 24) -# define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28) -#define NV_PRAMDAC_FP_DEBUG_1 0x00680884 -# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0 -# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE (1 << 12) -# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16 -# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE (1 << 28) -#define NV_PRAMDAC_FP_DEBUG_2 0x00680888 -#define NV_PRAMDAC_FP_DEBUG_3 0x0068088C - -/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */ -#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0 -# define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1 << 16) -#define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4 - -#define NV_PRAMDAC_8C0 0x006808c0 - -/* Some kind of switch */ -#define NV_PRAMDAC_900 0x00680900 -#define NV_PRAMDAC_A20 0x00680A20 -#define NV_PRAMDAC_A24 0x00680A24 -#define NV_PRAMDAC_A34 0x00680A34 - -/* names fabricated from NV_USER_DAC info */ -#define NV_PRMDIO_PIXEL_MASK 0x006813c6 -# define NV_PRMDIO_PIXEL_MASK_MASK 0xff -#define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7 -#define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8 -#define NV_PRMDIO_PALETTE_DATA 0x006813c9 - -#define NV_PGRAPH_DEBUG_0 0x00400080 -#define NV_PGRAPH_DEBUG_1 0x00400084 -#define NV_PGRAPH_DEBUG_2_NV04 0x00400088 -#define NV_PGRAPH_DEBUG_2 0x00400620 -#define NV_PGRAPH_DEBUG_3 0x0040008c -#define NV_PGRAPH_DEBUG_4 0x00400090 -#define NV_PGRAPH_INTR 0x00400100 -#define NV_PGRAPH_INTR_EN 0x00400140 -#define NV_PGRAPH_CTX_CONTROL 0x00400144 -#define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170 -#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C -#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 -#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 -#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 -#define NV_PGRAPH_BETA_AND 0x00400608 -#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 -#define NV_PGRAPH_BOFFSET0 0x00400640 -#define NV_PGRAPH_BOFFSET1 0x00400644 -#define NV_PGRAPH_BOFFSET2 0x00400648 -#define NV_PGRAPH_BLIMIT0 0x00400684 -#define NV_PGRAPH_BLIMIT1 0x00400688 -#define NV_PGRAPH_BLIMIT2 0x0040068c -#define NV_PGRAPH_STATUS 0x00400700 -#define NV_PGRAPH_SURFACE 0x00400710 -#define NV_PGRAPH_STATE 0x00400714 -#define NV_PGRAPH_FIFO 0x00400720 -#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 -#define NV_PGRAPH_TILE 0x00400b00 - -#define NV_PVIDEO_INTR_EN 0x00008140 -#define NV_PVIDEO_BUFFER 0x00008700 -#define NV_PVIDEO_STOP 0x00008704 -#define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4) -#define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4) -#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4) -#define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4) -#define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4) -#define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4) -#define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4) -#define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4) -#define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4) -#define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4) -#define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4) -#define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4) -#define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4) -#define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4) -#define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4) -# define NV_PVIDEO_FORMAT_PLANAR (1 << 0) -# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16) -# define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20) -# define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24) -#define NV_PVIDEO_COLOR_KEY 0x00008B00 - -/* NV04 overlay defines from VIDIX & Haiku */ -#define NV_PVIDEO_INTR_EN_0 0x00680140 -#define NV_PVIDEO_STEP_SIZE 0x00680200 -#define NV_PVIDEO_CONTROL_Y 0x00680204 -#define NV_PVIDEO_CONTROL_X 0x00680208 -#define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c -#define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214 -#define NV_PVIDEO_BUFF0_OFFSET 0x0068021c -#define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210 -#define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218 -#define NV_PVIDEO_BUFF1_OFFSET 0x00680220 -#define NV_PVIDEO_OE_STATE 0x00680224 -#define NV_PVIDEO_SU_STATE 0x00680228 -#define NV_PVIDEO_RM_STATE 0x0068022c -#define NV_PVIDEO_WINDOW_START 0x00680230 -#define NV_PVIDEO_WINDOW_SIZE 0x00680234 -#define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238 -#define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c -#define NV_PVIDEO_KEY 0x00680240 -#define NV_PVIDEO_OVERLAY 0x00680244 -#define NV_PVIDEO_RED_CSC_OFFSET 0x00680280 -#define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284 -#define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288 -#define NV_PVIDEO_CSC_ADJUST 0x0068028c +#ifndef __NVREG_H__ +#define __NVREG_H__ + +#include <stdint.h> + +#define NV_PEXTDEV_BOOT_0 0x101000 + +#define NV_PRMVIO_SRX 0xc03c4 +#define NV_PRMVIO_SR 0xc03c5 +#define NV_PRMVIO_MISC__READ 0xc03cc + +#define NV_VIO_SR_CLOCK 0x01 + +#define NV_PRMCIO_CRX__COLOR 0x6013d4 +#define NV_PRMCIO_CR__COLOR 0x6013d5 + +#define NV_CIO_CR_HDT 0x00 +#define NV_CIO_CR_HDE 0x01 +#define NV_CIO_CR_HBS 0x02 +#define NV_CIO_CR_HBE 0x03 +#define NV_CIO_CR_HRS 0x04 +#define NV_CIO_CR_HRE 0x05 +#define NV_CIO_CR_VDT 0x06 +#define NV_CIO_CR_OVL 0x07 +#define NV_CIO_CR_CELL_HT 0x09 +#define NV_CIO_CR_VRS 0x10 +#define NV_CIO_CR_VRE 0x11 +#define NV_CIO_CR_VDE 0x12 +#define NV_CIO_CR_VBS 0x15 +#define NV_CIO_CR_VBE 0x16 +#define NV_CIO_SR_LOCK 0x1f +#define NV_CIO_CRE_LSR 0x25 +#define NV_CIO_CRE_HEB 0x2d +#define NV_CIO_CRE_ILACE 0x39 +#define NV_CIO_CRE_EBR 0x41 + +#define NV_PRAMDAC_NVPLL 0x680500 +#define NV_PRAMDAC_MPLL 0x680504 +#define NV_PRAMDAC_VPLL1 0x680508 +#define NV_PRAMDAC_VPLL2 0x680520 + +struct reg { + uint64_t class; + uint32_t offset; + const char *name; +}; + +extern struct reg pmc_block[]; +extern struct reg pbus_block[]; +extern struct reg pfb_block[]; +extern struct reg pcrtc_block[]; +extern struct reg vga_crtc_block[]; +extern struct reg pramdac_block[]; +extern struct reg ptv_block[]; +extern struct reg itv_block[]; +extern struct reg tmds_block[]; +extern struct reg pvideo_block[]; #endif @@ -1,550 +1,331 @@ /* - * Copyright 1996-1997 David J. McKay - * Copyright 2005-2006 Erik Waling - * Copyright 2006 Stephane Marchesin - * Copyright 2007-2009 Stuart Bennett - * Copyright 2009 Francisco Jerez + * Copyright 2009-2010 Francisco Jerez + * All Rights Reserved. * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF - * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. */ #include <stdio.h> #include <pciaccess.h> -#include "nvreg.h" #include <string.h> #include <unistd.h> - -#define NV_CIO_CRE_FP_HTIMING_INDEX 0x53 -#define NV_CIO_CRE_FP_VTIMING_INDEX 0x54 -#define NV_CIO_CRE_43 0x43 -#define NV_PRAMDAC_8C0 0x006808c0 - -#define NV_PRAMDAC_84C 0x0068084c -#define NV_PRAMDAC_898 0x00680898 -#define NV_PRAMDAC_89C 0x0068089c - -#define NV_PRAMDAC_TV_SETUP 0x00680700 -#define NV_PRAMDAC_TV_VBLANK_START 0x00680704 -#define NV_PRAMDAC_TV_VBLANK_END 0x00680708 -#define NV_PRAMDAC_TV_HBLANK_START 0x0068070c -#define NV_PRAMDAC_TV_HBLANK_END 0x00680710 -#define NV_PRAMDAC_TV_BLANK_COLOR 0x00680714 -#define NV_PRAMDAC_TV_VTOTAL 0x00680720 -#define NV_PRAMDAC_TV_VSYNC_START 0x00680724 -#define NV_PRAMDAC_TV_VSYNC_END 0x00680728 -#define NV_PRAMDAC_TV_HTOTAL 0x0068072c -#define NV_PRAMDAC_TV_HSYNC_START 0x00680730 -#define NV_PRAMDAC_TV_HSYNC_STOP 0x00680734 -#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738 - -int arch; - -#define NV_RD32(p, reg) (*(volatile uint32_t*)((char*)(p)+(reg))) -#define NV_RD08(p, reg) (*(volatile uint8_t*)((char*)(p)+(reg))) -#define NV_WR32(p, reg, val) do{ \ - *(volatile uint32_t*)((char*)(p)+(reg)) = (val); \ - }while(0) -#define NV_WR08(p, reg, val) do{ \ - *(volatile uint8_t*)((char*)(p)+(reg)) = (val); \ - }while(0) - - -static uint8_t read_vga_crtc(void* regs, int head, uint8_t index) -{ - NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); - return NV_RD08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); -} -static void write_vga_crtc(void* regs, int head, uint8_t index, uint8_t val) +#include "nvhw.h" +#include "util.h" + +#define mmio_domain(p) \ + lambda(uint32_t *x, nv_rd32(p, *x)) +#define vga_crtc_domain(p, i) \ + lambda(uint32_t *x, (uint32_t)read_vga_crtc(p, i, *x)) +#define itv_domain(p) \ + lambda(uint32_t *x, (uint32_t)read_itv(p, *x)) +#define tmds_domain(p, i, j) \ + lambda(uint32_t *x, (uint32_t)read_tmds(p, i, j, *x)) + +#define head_domain(p, i) \ + lambda(uint32_t *x, { \ + *x += i * 0x2000; \ + nv_rd32(p, *x); \ + }) + +static void +dump_block(struct reg *rs, uint32_t (*f)(uint32_t *), + const char *name) { - NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); - NV_WR08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, val); -} + printf("-- %s registers\n", name); -static uint8_t read_prmvio(void* regs, int head, uint32_t reg) -{ - if(head && (arch & 0xf0) == 0x40) - reg += NV_PRMVIO_SIZE; + for (; rs->class; rs++) { + if (nv_class(rs->class)) { + uint32_t addr = rs->offset; + uint32_t val = f(&addr); - return NV_RD08(regs, reg); -} + printf(" %s 0x%x: 0x%-8x", name, addr, val); + if (rs->name) + printf("\t(%s)", rs->name); + printf("\n"); + } + } -static void write_prmvio(void* regs, int head, uint32_t reg, uint8_t val) -{ - if(head && (arch & 0xf0) == 0x40) - reg += NV_PRMVIO_SIZE; - - NV_WR08(regs, reg, val); + printf("\n"); } -static uint32_t NVReadRAMDAC(void* regs, int head, uint32_t reg) +static void +dump_pll(void *regs, const char *name, uint32_t reg) { - if (head) - reg += NV_PRAMDAC0_SIZE; - return NV_RD32(regs, reg); -} + int pll = nv_rd32(regs, reg); + int n1, m1, n2, m2, p, vco2; + uint32_t strap_mask; + float f0; -void NVWriteRAMDAC(void* regs, int head, uint32_t reg, uint32_t val) -{ - if (head) - reg += NV_PRAMDAC0_SIZE; - NV_WR32(regs, reg,val); -} + strap_mask = 1 << 6; + if (nv_class(DUALHEAD_CLASS)) + strap_mask |= 1 << 22; -static uint32_t NVReadCRTC(void* regs, int head, uint32_t reg) -{ - if (head) - reg += NV_PCRTC0_SIZE; - return NV_RD32(regs, reg); + switch (nv_rd32(regs, NV_PEXTDEV_BOOT_0) & strap_mask) { + case 0: + f0 = 13.500; + break; + case (1 << 6): + f0 = 14.318; + break; + case (1 << 22): + f0 = 27.000; + break; + case (1 << 22 | 1 << 6): + f0 = 25.000; + break; + } + + if (nv_class(TWOREG_PLL_CLASS)) { + uint32_t reg2 = reg + (reg == NV_PRAMDAC_VPLL2 ? 0x5c : 0x70); + uint32_t vco2_ctrl = nv_rd32(regs, 0x680580); + int pll2 = nv_rd32(regs, reg2); + + vco2 = (chipset < 0x40 || + (reg == NV_PRAMDAC_VPLL1 && !(vco2_ctrl & (1 << 8))) || + (reg == NV_PRAMDAC_VPLL2 && !(vco2_ctrl & (1 << 28)))); + + n1 = (pll & 0xff00) >> 8; + m1 = pll & 0xff; + p = (pll & 0x70000) >> 16; + + n2 = (pll2 & 0xff00) >> 8; + m2 = pll2 & 0xff; + + } else if (nv_class(TWOSTAGE_PLL_CLASS)) { + n1 = (pll & 0xff00) >> 8; + m1 = pll & 0xf; + n2 = (pll & 0x380000) >> 19 | (pll & 0x3000000) >> 24 << 3; + m2 = (pll & 0x70) >> 4; + p = (pll & 0x70000) >> 16; + vco2 = pll & 0x80; + + } else { + n1 = (pll & 0xff00) >> 8; + m1 = pll & 0xff; + n2 = 1; + m2 = 1; + p = (pll & 0x70000) >> 16; + vco2 = 0; + } + + printf(" %s: 0x%x N1=0x%x M1=0x%x N2=0x%x M2=0x%x" + " P=0x%x VCO2=%d f0=%f f=%f\n", + name, pll, n1, m1, n2, m2, p, vco2, f0, + (f0 * (float)n1 / m1 * (vco2 ? n2 / m2 : 1) * + (float)(1 << (7 - p)) / (1 << 7))); } -void NVWriteCRTC(void* regs, int head, uint32_t reg, uint32_t val) +static void +dump_crtc_timings(void *regs, int head) { - if (head) - reg += NV_PCRTC0_SIZE; - NV_WR32(regs, reg ,val); -} - -void nv_write_ptv(void* regs, uint32_t reg, uint32_t val){ - NV_WR32(regs, 0xd000+reg, val); + int hdisplay, htotal, hsync_start, hsync_end, hblank_start, hblank_end, + vdisplay, vtotal, vsync_start, vsync_end, vblank_start, + vblank_end, ilace, dblscan, clkdiv, nhsync, nvsync; + + write_vga_crtc(regs, 0, NV_CIO_SR_LOCK, 0x57); + write_vga_crtc(regs, 0, 0x44, head); + + hdisplay = read_vga_crtc(regs, head, NV_CIO_CR_HDE) | + (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x2) >> 1 << 8; + + htotal = read_vga_crtc(regs, head, NV_CIO_CR_HDT) | + (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x1) << 8; + + hsync_start = read_vga_crtc(regs, head, NV_CIO_CR_HRS) | + (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x8) >> 3 << 8; + + hsync_end = read_vga_crtc(regs, head, NV_CIO_CR_HRE) & 0x1F; + + hblank_start = read_vga_crtc(regs, head, NV_CIO_CR_HBS) | + (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x4) >> 2 << 8; + + hblank_end = (read_vga_crtc(regs, head, NV_CIO_CR_HBE) & 0x1f) | + (read_vga_crtc(regs, head, NV_CIO_CR_HRE) & 0x80) >> 7 << 5 | + (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x10) >> 4 << 6; + + vdisplay = read_vga_crtc(regs, head, NV_CIO_CR_VDE) | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x2) >> 1 << 8 | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x40) >> 6 << 9 | + (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x2) >> 1 << 10 | + (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x4) >> 2 << 11; + + vtotal = read_vga_crtc(regs, head, NV_CIO_CR_VDT) | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x20) >> 5 << 9 | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x1) << 8 | + (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x1) << 10 | + (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x1) << 11; + + vsync_start = read_vga_crtc(regs, head, NV_CIO_CR_VRS) | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x80) >> 7 << 9 | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x4) >> 2 << 8 | + (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x4) >> 2 << 10 | + (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x10) >> 4 << 11; + + vsync_end = read_vga_crtc(regs, head, NV_CIO_CR_VRE) & 0xF; + + vblank_start = read_vga_crtc(regs, head, NV_CIO_CR_VBS) | + (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x8) >> 3 << 8 | + (read_vga_crtc(regs, head, NV_CIO_CR_CELL_HT) & 0x20) >> 5 << 9 | + (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x8) >> 3 << 10 | + (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x40) >> 6 << 11; + + vblank_end = read_vga_crtc(regs, head, NV_CIO_CR_VBE); + + ilace = read_vga_crtc(regs, head, NV_CIO_CRE_ILACE) | + (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x10) >> 4 << 8; + + dblscan = read_vga_crtc(regs, head, NV_CIO_CR_CELL_HT) & 0x80; + clkdiv = read_vga_seq(regs, head, NV_VIO_SR_CLOCK) & 0x8; + nhsync = read_prmvio(regs, head, NV_PRMVIO_MISC__READ) & 0x40; + nvsync = read_prmvio(regs, head, NV_PRMVIO_MISC__READ) & 0x80; + + printf("-- CRTC%d timings\n", head); + + printf(" hdisplay: %d\n", (hdisplay + 1) * 8); + printf(" htotal: %d\n", (htotal + 5) * 8); + printf(" hsync start: %d\n", (hsync_start - 1) * 8); + printf(" hsync end: %d\n", + (subm(hsync_end, hsync_start, 32) + hsync_start - 1) * 8); + printf(" hblank start: %d\n", (hblank_start + 1) * 8); + printf(" hblank end: %d\n", + (subm(hblank_end, hblank_start, 128) + hblank_start + 1) * 8); + + printf(" vdisplay: %d\n", vdisplay + 1); + printf(" vtotal: %d\n", vtotal + 2); + printf(" vsync start: %d\n", vsync_start + 1); + printf(" vsync end: %d\n", + subm(vsync_end, vsync_start, 16) + vsync_start + 1); + printf(" vblank start: %d\n", vblank_start + 1); + printf(" vblank end: %d\n", + subm(vblank_end, vblank_start, 256) + vblank_start + 1); + printf(" ilace: %d%s\n", ilace, + (ilace & 0xff) == 0xff ? " [off]" : ""); + + printf(" dblscan: %d\n", dblscan); + printf(" clkdiv2: %d\n", clkdiv); + printf(" nhsync: %d\n", nhsync); + printf(" nvsync: %d\n", nvsync); + printf("\n"); } -uint32_t nv_read_ptv(void* regs, uint32_t reg){ - return NV_RD32(regs, 0xd000+reg); -} - -void nv_write_tve(void* regs, uint32_t reg, uint32_t val){ - NV_WR32(regs, 0xd220, reg); - NV_WR32(regs, 0xd224, val); -} +#define block_name(buf, ...) \ + ({ \ + snprintf(buf, sizeof(buf), __VA_ARGS__); \ + buf; \ + }) -uint8_t nv_read_tmds(void *regs, - int ramdac, int dl, uint8_t address) +static int +tv_dump(void *regs) { - NVWriteRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, - NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address); - return NVReadRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8); + char buf[64]; + int i, j; + + nv_detect_chipset(regs); + printf("-- Chipset: NV%x\n", chipset); + + dump_block(pmc_block, mmio_domain(regs), block_name(buf, "PMC")); + dump_block(pbus_block, mmio_domain(regs), block_name(buf, "PBUS")); + dump_block(pfb_block, mmio_domain(regs), block_name(buf, "PFB")); + + printf("-- PLLs\n"); + dump_pll(regs, "NVPLL", NV_PRAMDAC_NVPLL); + dump_pll(regs, "MPLL", NV_PRAMDAC_MPLL); + dump_pll(regs, "VPLL1", NV_PRAMDAC_VPLL1); + dump_pll(regs, "VPLL2", NV_PRAMDAC_VPLL2); + printf("\n"); + + for (i = 0; i < 2; i++) { + dump_block(pcrtc_block, head_domain(regs, i), + block_name(buf, "PCRTC%d", i)); + dump_block(vga_crtc_block, vga_crtc_domain(regs, i), + block_name(buf, "CIO%d", i)); + dump_crtc_timings(regs, i); + } + + for (i = 0; i < 2; i++) + dump_block(pramdac_block, head_domain(regs, i), + block_name(buf, "PRAMDAC%d", i)); + + dump_block(ptv_block, mmio_domain(regs), block_name(buf, "PTV")); + dump_block(itv_block, itv_domain(regs), block_name(buf, "ITV")); + + for (i = 0; i < 2; i++) { + for (j = 0; j < 2; j++) { + dump_block(tmds_block, tmds_domain(regs, i, j), + block_name(buf, "TMDS%dL%d", i, j)); + } + } + + dump_block(pvideo_block, mmio_domain(regs), block_name(buf, "PVIDEO")); + + return 0; } -int NVGetArchitecture(volatile uint32_t *regs) +int +main(int argc, char *argv[]) { - int architecture = 0; - - /* We're dealing with >=NV10 */ - if ((regs[0] & 0x0f000000) > 0 ) - /* Bit 27-20 contain the architecture in hex */ - architecture = (regs[0] & 0xff00000) >> 20; - /* NV04 or NV05 */ - else if ((regs[0] & 0xff00fff0) == 0x20004000) - architecture = 0x04; - - return architecture; -} - -#define DIFFM(A,B,M) ((A%M + M - B%M)%M) -#define MASK(field) ((0xffffffff >> (31 - ((1?field) - (0?field)))) << (0?field)) -#define XLATE(src, srclowbit, outfield) ((((src) >> (srclowbit)) << (0?outfield)) & MASK(outfield)) -#define LEN(xs) (sizeof(xs) / sizeof(*(xs))) - -void tv_dump(void* regs){ - int i,j; - arch = NVGetArchitecture(regs); - - printf("-- Architecture: NV%x\n", arch); - - printf("-- TV encoder register dump --\n"); - for(i=0; i<0x40; i++){ - NV_WR32(regs, 0xd220, i); - printf("%x: %x\n",i,NV_RD32(regs, 0xd224)); - } - - printf("-- PTV register dump --\n"); - for(i=0; i<0x10; i+=4) - printf("%x: %x\n",0x200+i,NV_RD32(regs, 0xd200+i)); - for(i=0; i<0x100; i+=4) - printf("%x: %x\n",0x300+i,NV_RD32(regs, 0xd300+i)); - for(i=0; i<0x10; i+=4) - printf("%x: %x\n",0x400+i,NV_RD32(regs, 0xd400+i)); - for(i=0; i<0x90; i+=4) - printf("%x: %x\n",0x500+i,NV_RD32(regs, 0xd500+i)); - for(i=0; i<0x20; i+=4) - printf("%x: %x\n",0x600+i,NV_RD32(regs, 0xd600+i)); - - write_vga_crtc(regs, 0, NV_CIO_SR_LOCK_INDEX, NV_CIO_SR_UNLOCK_RW_VALUE); - - for(i=0; i<2; i++){ - write_vga_crtc(regs, 0, NV_CIO_CRE_44, i); - - int horizDisplay = read_vga_crtc(regs, i, NV_CIO_CR_HDE_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),1,8:8); - int horizTotal = read_vga_crtc(regs, i, NV_CIO_CR_HDT_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),0,8:8); - int horizStart = read_vga_crtc(regs, i, NV_CIO_CR_HRS_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),3,8:8); - int horizEnd = read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX) & 0x1F; - int horizBlankStart = read_vga_crtc(regs, i, NV_CIO_CR_HBS_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),2,8:8); - int horizBlankEnd = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HBE_INDEX),0,4:0) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX),7, 5:5) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),4,6:6); - - int vertDisplay = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),6,9:9)| - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),1,8:8) | - read_vga_crtc(regs, i, NV_CIO_CR_VDE_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),1,10:10) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),2,11:11); - int vertTotal = read_vga_crtc(regs, i, NV_CIO_CR_VDT_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),5,9:9) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),0,8:8) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),0,10:10) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),0,11:11); - int vertStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),7,9:9) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),2,8:8) | - read_vga_crtc(regs, i, NV_CIO_CR_VRS_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),2,10:10) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),4,11:11); - int vertEnd = read_vga_crtc(regs, i, NV_CIO_CR_VRE_INDEX) & 0xF; - int vertBlankStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),3,8:8) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX),5,9:9) | - read_vga_crtc(regs, i, NV_CIO_CR_VBS_INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),3,10:10) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),6,11:11); - int vertBlankEnd = read_vga_crtc(regs, i, NV_CIO_CR_VBE_INDEX); - - int ilace_idx = read_vga_crtc(regs, i, NV_CIO_CRE_ILACE__INDEX) | - XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),4,8:8); - int dblscan = read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX) & 0x80; - - write_prmvio(regs, i, NV_PRMVIO_SRX, NV_VIO_SR_CLOCK_INDEX); - int clkdiv2 = read_prmvio(regs, i, NV_PRMVIO_SR)& 0x8; - - int nhsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x40; - int nvsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x80; - - printf("-- CRTC %d timings --\n",i); - printf("horizDisplay: %d\n",(horizDisplay+1)*8); - printf("horizTotal: %d\n",(horizTotal+5)*8); - printf("horizSyncStart: %d\n",(horizStart-1)*8); - printf("horizSyncEnd: %d\n",(DIFFM(horizEnd,horizStart,0x20)+horizStart-1)*8); - printf("horizBlankStart: %d\n",(horizBlankStart+1)*8); - printf("horizBlankEnd: %d\n",(DIFFM(horizBlankEnd,horizBlankStart,128)+horizBlankStart+1)*8); - printf("vertDisplay: %d\n",vertDisplay+1); - printf("vertTotal: %d\n",vertTotal+2); - printf("vertSyncStart: %d\n",vertStart+1); - printf("vertSyncEnd: %d\n",DIFFM(vertEnd,vertStart,16)+vertStart+1); - printf("vertBlankStart: %d\n",vertBlankStart+1); - printf("vertBlankEnd: %d\n",DIFFM(vertBlankEnd,vertBlankStart,256)+vertBlankStart+1); - printf("ilace_idx: %d%s\n",ilace_idx,(ilace_idx&0xff) == 0xff ? " [off]":""); - printf("dblscan: %d\n",dblscan); - printf("clkdiv2: %d\n",clkdiv2); - printf("nhsync: %d\n",nhsync); - printf("nvsync: %d\n",nvsync); - - } - - for(i=0; i<2; i++){ - int pll = NV_RD32(regs, i? NV_RAMDAC_VPLL2: NV_PRAMDAC_VPLL_COEFF); - int n1,m1,n2,m2,p,vco2; - float f0; - - { - uint32_t crystal_strap_mask = 1 << 6; - /* open coded pNv->twoHeads test */ - if (arch > 0x10 && arch != 0x15 && arch != 0x1a && arch != 0x20) - crystal_strap_mask |= 1 << 22; - - switch (NV_RD32(regs, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) { - case 0: - f0 = 13.500; - break; - case (1 << 6): - f0 = 14.318; - break; - case (1 << 22): - f0 = 27.000; - break; - case (1 << 22 | 1 << 6): - f0 = 25.000; - break; - } - } - - - if(arch == 0x35 || arch == 0x30){ - n1=XLATE(pll,8,7:0); - m1=XLATE(pll, 0, 3:0); - n2=XLATE(pll, 19, 2:0) | XLATE(pll, 24, 4:3); - m2=XLATE(pll, 4, 2:0); - p=XLATE(pll, 16, 2:0); - vco2=pll&0x80; - - } else if(arch == 0x31 || arch == 0x36 || arch >= 0x40) { - int pll2 = NV_RD32(regs, i? NV_RAMDAC_VPLL2 + 0x5c: NV_PRAMDAC_VPLL_COEFF + 0x70); - - if(arch >= 0x40) - vco2 = (i==0 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL1_ACTIVE)) || - (i==1 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL2_ACTIVE)); - else - vco2 = 1; - - n1=XLATE(pll,8,7:0); - m1=XLATE(pll, 0, 7:0); - p=XLATE(pll, 16, 2:0); - - n2=XLATE(pll2,8,7:0); - m2=XLATE(pll2, 0, 7:0); - - } else { - n1=XLATE(pll,8,7:0); - m1=XLATE(pll, 0, 7:0); - n2=1; - m2=1; - p=XLATE(pll, 16, 2:0); - vco2=0; - } - - printf("-- VPLL%d: 0x%x N1=0x%x M1=0x%x N2=0x%x M2=0x%x P=0x%x VCO2=%d f0=%f f=%f\n", - i ,pll, n1, m1, n2, m2, p, vco2, f0, f0*(float)n1/m1*(vco2?n2/m2:1)*(float)(1<<(7-p))/(1<<7)); - } - - for(i=0; i<2; i++){ - printf("-- VGA CRTC%d registers --\n",i); - printf("NV_CIO_CRE_PIXEL_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_PIXEL_INDEX)); - printf("NV_CIO_CRE_LCD__INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_LCD__INDEX)); - printf("NV_CIO_CRE_FP_HTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_HTIMING_INDEX)); - printf("NV_CIO_CRE_FP_VTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_VTIMING_INDEX)); - printf("NV_CIO_CRE_43: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_43)); - printf("NV_CIO_CRE_RPC1_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_RPC1_INDEX)); - printf("NV_CIO_CRE_ENH_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_ENH_INDEX)); - } - - - for(j=0; j<2; j++){ - printf("-- VGA CRTC%d registers --\n", j); - for(i=0; i<0xa0; i++) - printf("CRTC%x %x: %x\n", j, i, read_vga_crtc(regs, j, i)); - } - - for(i=0; i<2; i++){ - printf("-- PRAMDAC%d registers --\n",i); - printf("NV_PRAMDAC_630: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_630)); - printf("NV_PRAMDAC0_OFFSET+0x674: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0x674)); - printf("NV_PRAMDAC_TV_SETUP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SETUP)); - printf("NV_PRAMDAC_TV_VBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_START)); - printf("NV_PRAMDAC_TV_VBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_END)); - printf("NV_PRAMDAC_TV_HBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_START)); - printf("NV_PRAMDAC_TV_HBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_END)); - printf("NV_PRAMDAC_TV_BLANK_COLOR: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_BLANK_COLOR)); - printf("NV_PRAMDAC_TV_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VTOTAL)); - printf("NV_PRAMDAC_TV_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_START)); - printf("NV_PRAMDAC_TV_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_END)); - printf("NV_PRAMDAC_TV_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HTOTAL)); - printf("NV_PRAMDAC_TV_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_START)); - printf("NV_PRAMDAC_TV_HSYNC_STOP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_STOP)); - printf("NV_PRAMDAC_TV_SYNC_DELAY: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SYNC_DELAY)); - printf("NV_PRAMDAC_FP_DEBUG_0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_0)); - printf("NV_PRAMDAC_FP_DEBUG_1: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_1)); - printf("NV_PRAMDAC_FP_DEBUG_2: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_2)); - printf("NV_PRAMDAC_FP_TG_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_TG_CONTROL)); - printf("NV_PRAMDAC_FP_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HTOTAL)); - printf("NV_PRAMDAC_FP_HVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_START)); - printf("NV_PRAMDAC_FP_HVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_END)); - printf("NV_PRAMDAC_FP_HDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HDISPLAY_END)); - printf("NV_PRAMDAC_FP_HCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HCRTC)); - printf("NV_PRAMDAC_FP_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_START)); - printf("NV_PRAMDAC_FP_HSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_END)); - printf("NV_PRAMDAC_FP_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VTOTAL)); - printf("NV_PRAMDAC_FP_VVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_START)); - printf("NV_PRAMDAC_FP_VVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_END)); - printf("NV_PRAMDAC_FP_VDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VDISPLAY_END)); - printf("NV_PRAMDAC_FP_VCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VCRTC)); - printf("NV_PRAMDAC_FP_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_START)); - printf("NV_PRAMDAC_FP_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_END)); - printf("NV_PRAMDAC_84C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_84C)); - printf("NV_PRAMDAC_898: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_898)); - printf("NV_PRAMDAC_89C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_89C)); - printf("NV_PRAMDAC_8C0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_8C0)); - printf("NV_PRAMDAC_900: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_900)); - printf("NV_PRAMDAC_PLL_SETUP_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_SETUP_CONTROL)); - printf("NV_PRAMDAC_SEL_CLK: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_SEL_CLK)); - printf("NV_PRAMDAC_PLL_COEFF_SELECT: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_COEFF_SELECT)); - - for(j=0; j<64; j++) - printf("NV_PRAMDAC0_OFFSET+0xc%02x: 0x%x\n", 4*j, NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0xc00+4*j)); - } - - for(i=0; i<2; i++){ - printf("-- TMDS%d registers --\n",i); - for (j=0; j<0x40; j++) - printf("TMDS%d_%x: 0x%x\n", i, j, nv_read_tmds(regs, i, 0, j)); - - } - - for(i=0; i<2; i++){ - printf("-- PCRTC%d registers --\n",i); - printf("NV_PCRTC_CONFIG: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_CONFIG)); - printf("NV_PCRTC_START: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_START)); - printf("NV_PCRTC_GPIO_EXT: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_GPIO_EXT)); - printf("NV_PCRTC_830: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_830)); - printf("NV_PCRTC_834: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_834)); - } - - printf("-- OUTPUT registers--\n"); - int offsets[] = {0, 0x68, 0x2000, 0x2068}; - - for(i=0; i< LEN(offsets); i++) - printf("NV_PRAMDAC_DACCLK+0x%x: 0x%x\n",offsets[i], NVReadRAMDAC(regs, 0, NV_PRAMDAC_DACCLK+offsets[i])); - - printf("-- PVIDEO registers --\n"); - printf("NV_PVIDEO_DEBUG_0: 0x%x\n", NV_RD32(regs,0x00008080)); - printf("NV_PVIDEO_DEBUG_1: 0x%x\n", NV_RD32(regs,0x00008084)); - printf("NV_PVIDEO_DEBUG_2: 0x%x\n", NV_RD32(regs,0x00008088)); - printf("NV_PVIDEO_DEBUG_3: 0x%x\n", NV_RD32(regs,0x0000808C)); - printf("NV_PVIDEO_DEBUG_4: 0x%x\n", NV_RD32(regs,0x00008090)); - printf("NV_PVIDEO_DEBUG_5: 0x%x\n", NV_RD32(regs,0x00008094)); - printf("NV_PVIDEO_DEBUG_6: 0x%x\n", NV_RD32(regs,0x00008098)); - printf("NV_PVIDEO_DEBUG_7: 0x%x\n", NV_RD32(regs,0x0000809C)); - printf("NV_PVIDEO_DEBUG_8: 0x%x\n", NV_RD32(regs,0x000080A0)); - printf("NV_PVIDEO_DEBUG_9: 0x%x\n", NV_RD32(regs,0x000080A4)); - printf("NV_PVIDEO_DEBUG_10: 0x%x\n", NV_RD32(regs,0x000080A8)); - printf("NV_PVIDEO_INTR: 0x%x\n", NV_RD32(regs,0x00008100)); - printf("NV_PVIDEO_INTR_REASON: 0x%x\n", NV_RD32(regs,0x00008104)); - printf("NV_PVIDEO_INTR_EN: 0x%x\n", NV_RD32(regs,0x00008140)); - printf("NV_PVIDEO_BUFFER: 0x%x\n", NV_RD32(regs,0x00008700)); - printf("NV_PVIDEO_STOP: 0x%x\n", NV_RD32(regs,0x00008704)); - printf("NV_PVIDEO_BASE: 0x%x\n", NV_RD32(regs,0x00008900)); - printf("NV_PVIDEO_LIMIT: 0x%x\n", NV_RD32(regs,0x00008908)); - printf("NV_PVIDEO_LUMINANCE: 0x%x\n", NV_RD32(regs,0x00008910)); - printf("NV_PVIDEO_CHROMINANCE: 0x%x\n", NV_RD32(regs,0x00008918)); - printf("NV_PVIDEO_OFFSET: 0x%x\n", NV_RD32(regs,0x00008920)); - printf("NV_PVIDEO_SIZE_IN: 0x%x\n", NV_RD32(regs,0x00008928)); - printf("NV_PVIDEO_POINT_IN: 0x%x\n", NV_RD32(regs,0x00008930)); - printf("NV_PVIDEO_DS_DX: 0x%x\n", NV_RD32(regs,0x00008938)); - printf("NV_PVIDEO_DT_DY: 0x%x\n", NV_RD32(regs,0x00008940)); - printf("NV_PVIDEO_POINT_OUT: 0x%x\n", NV_RD32(regs,0x00008948)); - printf("NV_PVIDEO_SIZE_OUT: 0x%x\n", NV_RD32(regs,0x00008950)); - printf("NV_PVIDEO_FORMAT: 0x%x\n", NV_RD32(regs,0x00008958)); - printf("NV_PVIDEO_COLOR_KEY: 0x%x\n", NV_RD32(regs,0x00008B00)); - printf("NV_PVIDEO_TEST: 0x%x\n", NV_RD32(regs,0x00008D00)); - printf("NV_PVIDEO_TST_WRITE: 0x%x\n", NV_RD32(regs,0x00008D10)); - printf("NV_PVIDEO_TST_READ: 0x%x\n", NV_RD32(regs,0x00008D40)); - - printf("-- PBUS registers --\n"); - { - uint32_t pbus_regs[] = { - 0x1084, 0x108c, 0x1098, 0x10b8, 0x10d8, 0x10e0, 0x10f0, - 0x1100, 0x1140, 0x1210, 0x1214, 0x1218, 0x121c, 0x1220, - 0x1228, 0x122c, 0x1230, 0x1234, 0x1238, 0x123c, 0x1240, - 0x1244, 0x1248, 0x1518, 0x1580, 0x1584, 0x1588, 0x158c, - 0x1590, 0x15a0, 0x1800, 0x1804, 0x1808, 0x180c, 0x1810, - 0x1814, 0x1818, 0x182c, 0x1830, 0x1844, 0x1848, 0x184c, - 0x1850, 0x1854, 0x1860 - }; - - for (i = 0; i < LEN(pbus_regs); i++) - printf("PBUS: 0x%x: 0x%x\n", pbus_regs[i], - NV_RD32(regs, pbus_regs[i])); - } - - printf("-- PFB registers --\n"); - { - uint32_t pfb_regs[] = { - 0x100000, 0x100080, 0x100200, 0x100204, - 0x10020c, 0x100210, 0x100300, 0x100304, - 0x100308, 0x100328, 0x10032c, 0x100330, - 0x100334, 0x100338, 0x100350, 0x100360, - 0x10037c, 0x100380, 0x100384, 0x100388, - 0x10038c, 0x100390, 0x100394, 0x100398, - 0x10039c, 0x1003a0, 0x1003a4, 0x1003a8, - 0x1003ac, 0x1003b0, 0x1003b4, 0x1003b8, - 0x1003bc, 0x1003c0, 0x1003c4, 0x1003c8, - 0x1003d0 - }; - - for (i = 0; i < LEN(pfb_regs); i++) - printf("PFB: 0x%x: 0x%x\n", pfb_regs[i], - NV_RD32(regs, pfb_regs[i])); - - } - -} - -int main(){ - void* regs; - int ret; - - ret = pci_system_init(); - - if(ret){ - fprintf(stderr,"Error calling pci_system_init().\n"); - - return 1; - } - - struct pci_id_match nv_match = {0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x30000, 0xffff0000}; - struct pci_device_iterator* it = pci_id_match_iterator_create(&nv_match); - - if(!it){ - fprintf(stderr,"Error calling pci_id_match_iterator_create().\n"); - - pci_iterator_destroy(it); - - return 1; - } - - struct pci_device* dev = pci_device_next(it); - - if(!dev){ - fprintf(stderr,"No devices found.\n"); - - pci_iterator_destroy(it); - pci_system_cleanup(); - - return 1; - } - - ret = pci_device_probe(dev); - - if(ret){ - fprintf(stderr, "Error calling pci_device_probe().\n"); - - pci_iterator_destroy(it); - pci_system_cleanup(); - - return 1; - } - - ret = pci_device_map_range(dev, dev->regions[0].base_addr, dev->regions[0].size, PCI_DEV_MAP_FLAG_WRITABLE,®s); - - if(ret){ - fprintf(stderr, "Error calling pci_device_map_range().\n"); - - pci_iterator_destroy(it); - pci_system_cleanup(); - - return 1; - } - - tv_dump(regs); - - pci_device_unmap_range(dev, regs, dev->regions[0].size); - pci_iterator_destroy(it); - pci_system_cleanup(); - - return 0; + struct pci_id_match match = { 0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, + PCI_MATCH_ANY, 0x30000, 0xffff0000 }; + struct pci_device_iterator *it; + struct pci_device *dev; + void *regs; + int ret; + + ret = pci_system_init(); + if (ret) + goto out; + + it = pci_id_match_iterator_create(&match); + if (!it) { + ret = ENOMEM; + goto out_sys; + } + + dev = pci_device_next(it); + if (!dev) { + ret = ENODEV; + goto out_iter; + } + + ret = pci_device_probe(dev); + if (ret) + goto out_iter; + + ret = pci_device_map_range(dev, dev->regions[0].base_addr, + dev->regions[0].size, + PCI_DEV_MAP_FLAG_WRITABLE, ®s); + if (ret) + goto out_iter; + + ret = tv_dump(regs); + + pci_device_unmap_range(dev, regs, dev->regions[0].size); +out_iter: + pci_iterator_destroy(it); +out_sys: + pci_system_cleanup(); +out: + if (ret) + fprintf(stderr, "%s: %s\n", argv[0], strerror(ret)); + + return ret; } diff --git a/tvdump2code.py b/tvdump2code.py deleted file mode 100644 index 05ec95f..0000000 --- a/tvdump2code.py +++ /dev/null @@ -1,87 +0,0 @@ -#!/usr/bin/python -# -# Copyright 2009 Francisco Jerez -# -# Permission is hereby granted, free of charge, to any person obtaining a -# copy of this software and associated documentation files (the "Software"), -# to deal in the Software without restriction, including without limitation -# the rights to use, copy, modify, merge, publish, distribute, sublicense, -# and/or sell copies of the Software, and to permit persons to whom the -# Software is furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -# THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. -# - -import sys -import re - -mode="" - -print """#define NV_PRAMDAC_84C 0x0068084c -#define NV_PRAMDAC_898 0x00680898 -#define NV_PRAMDAC_89C 0x0068089c - -#define NV_PRAMDAC_TV_SETUP 0x00680700 -#define NV_PRAMDAC_TV_VBLANK_START 0x00680704 -#define NV_PRAMDAC_TV_VBLANK_END 0x00680708 -#define NV_PRAMDAC_TV_HBLANK_START 0x0068070c -#define NV_PRAMDAC_TV_HBLANK_END 0x00680710 -#define NV_PRAMDAC_TV_BLANK_COLOR 0x00680714 -#define NV_PRAMDAC_TV_VTOTAL 0x00680720 -#define NV_PRAMDAC_TV_VSYNC_START 0x00680724 -#define NV_PRAMDAC_TV_VSYNC_END 0x00680728 -#define NV_PRAMDAC_TV_HTOTAL 0x0068072c -#define NV_PRAMDAC_TV_HSYNC_START 0x00680730 -#define NV_PRAMDAC_TV_HSYNC_STOP 0x00680734 -#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738""" - - -for l in sys.stdin.readlines(): - if re.match(".*TV encoder register dump.*",l): - mode="tvenc" - continue - elif re.match(".*PTV register dump.*",l): - mode="ptv" - continue - elif re.match(".*CRTC . timings.*",l): - mode="" - continue - elif re.match(".*VGA CRTC. registers.*",l): - mode="vgacrtc" - continue - elif re.match(".*PRAMDAC. registers.*",l): - mode="pramdac" - i=int(re.match(".*PRAMDAC(.) registers.*",l).group(1)) - continue - elif re.match(".*PCRTC. registers.*",l): - mode="pcrtc" - i=int(re.match(".*PCRTC(.) registers.*",l).group(1)) - continue - elif re.match(".*(OUTPUT|MISC) registers.*",l): - mode="output" - continue - - if mode == "": - pass - elif mode == "tvenc": - print re.sub("(.*) *: *(.*)","nv_write_tv_enc(pNv, 0x\\1, 0x\\2);",l)[0:-1] - elif mode == "ptv": - print re.sub("(.*) *: *(.*)","nv_write_ptv(pNv, 0x\\1, 0x\\2);",l)[0:-1] - elif mode == "vgacrtc": - if re.match("^CRTC[01]",l): - print re.sub("CRTC(.) (.*) *: *(.*)"," NVWriteVgaCrtc(pNv, \\1, 0x\\2, 0x\\3);",l)[0:-1] - elif mode == "pramdac": - print re.sub("(.*) *: *(.*)"," NVWriteRAMDAC(pNv, %d, \\1, \\2);" % (i),l)[0:-1] - elif mode == "pcrtc": - print re.sub("(.*) *: *(.*)"," NVWriteCRTC(pNv, %d, \\1, \\2);" % (i),l)[0:-1] - elif mode == "output": - print re.sub("(.*) *: *(.*)"," NV_WR32(pNv->REGS, \\1, \\2);",l)[0:-1] @@ -0,0 +1,43 @@ +/* + * Copyright 2010 Francisco Jerez + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial + * portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef __UTIL_H__ +#define __UTIL_H__ + +#define subm(a, b, m) (((a) % (m) + (m) - (b) % (m)) % (m)) + +#define lambda(x, y) \ + ({ \ + x __attribute__((__unused__)); \ + \ + auto typeof((y)) __f(x) { \ + return (y); \ + }; \ + \ + __f; \ + }) + +#endif |