Big cleanup.HEADmaster

1 files changed, 301 insertions, 520 deletions

diff --git a/tvdump.c b/tvdump.c
index 7fa1ab1..f1c007d 100644
--- a/tvdump.c
+++ b/tvdump.c
@@ -1,550 +1,331 @@
 /*
- * Copyright 1996-1997 David J. McKay
- * Copyright 2005-2006 Erik Waling
- * Copyright 2006 Stephane Marchesin
- * Copyright 2007-2009 Stuart Bennett
- * Copyright 2009 Francisco Jerez
+ * Copyright 2009-2010 Francisco Jerez
+ * All Rights Reserved.
  *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
  *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
  */
 
 #include <stdio.h>
 #include <pciaccess.h>
-#include "nvreg.h"
 #include <string.h>
 #include <unistd.h>
-
-#define NV_CIO_CRE_FP_HTIMING_INDEX 0x53
-#define NV_CIO_CRE_FP_VTIMING_INDEX 0x54
-#define NV_CIO_CRE_43 0x43
-#define NV_PRAMDAC_8C0 0x006808c0
-
-#define NV_PRAMDAC_84C 0x0068084c
-#define NV_PRAMDAC_898 0x00680898
-#define NV_PRAMDAC_89C 0x0068089c
-
-#define NV_PRAMDAC_TV_SETUP 0x00680700
-#define NV_PRAMDAC_TV_VBLANK_START 0x00680704
-#define NV_PRAMDAC_TV_VBLANK_END 0x00680708
-#define NV_PRAMDAC_TV_HBLANK_START 0x0068070c
-#define NV_PRAMDAC_TV_HBLANK_END 0x00680710
-#define NV_PRAMDAC_TV_BLANK_COLOR 0x00680714
-#define NV_PRAMDAC_TV_VTOTAL 0x00680720
-#define NV_PRAMDAC_TV_VSYNC_START 0x00680724
-#define NV_PRAMDAC_TV_VSYNC_END 0x00680728
-#define NV_PRAMDAC_TV_HTOTAL 0x0068072c
-#define NV_PRAMDAC_TV_HSYNC_START 0x00680730
-#define NV_PRAMDAC_TV_HSYNC_STOP 0x00680734
-#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738
-
-int arch;
-
-#define NV_RD32(p, reg) (*(volatile uint32_t*)((char*)(p)+(reg)))
-#define NV_RD08(p, reg) (*(volatile uint8_t*)((char*)(p)+(reg)))
-#define NV_WR32(p, reg, val) do{                 \
-      *(volatile uint32_t*)((char*)(p)+(reg)) = (val);  \
-   }while(0)
-#define NV_WR08(p, reg, val) do{                 \
-      *(volatile uint8_t*)((char*)(p)+(reg)) = (val);   \
-   }while(0)
-
-
-static uint8_t read_vga_crtc(void* regs, int head, uint8_t index)
-{
-   NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
-   return NV_RD08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
-}
-static void write_vga_crtc(void* regs, int head, uint8_t index, uint8_t val)
+#include "nvhw.h"
+#include "util.h"
+
+#define mmio_domain(p) \
+	lambda(uint32_t *x, nv_rd32(p, *x))
+#define vga_crtc_domain(p, i) \
+	lambda(uint32_t *x, (uint32_t)read_vga_crtc(p, i, *x))
+#define itv_domain(p) \
+	lambda(uint32_t *x, (uint32_t)read_itv(p, *x))
+#define tmds_domain(p, i, j) \
+	lambda(uint32_t *x, (uint32_t)read_tmds(p, i, j, *x))
+
+#define head_domain(p, i)			\
+	lambda(uint32_t *x, {			\
+			*x += i * 0x2000;	\
+			nv_rd32(p, *x);		\
+		})
+
+static void
+dump_block(struct reg *rs, uint32_t (*f)(uint32_t *),
+	   const char *name)
 {
-   NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
-   NV_WR08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, val);
-}
+	printf("-- %s registers\n", name);
 
-static uint8_t read_prmvio(void* regs, int head, uint32_t reg)
-{
-   if(head && (arch & 0xf0) == 0x40)
-      reg += NV_PRMVIO_SIZE;
+	for (; rs->class; rs++) {
+		if (nv_class(rs->class)) {
+			uint32_t addr = rs->offset;
+			uint32_t val = f(&addr);
 
-   return NV_RD08(regs, reg);
-}
+			printf(" %s 0x%x: 0x%-8x", name, addr, val);
+			if (rs->name)
+				printf("\t(%s)", rs->name);
+			printf("\n");
+		}
+	}
 
-static void write_prmvio(void* regs, int head, uint32_t reg, uint8_t val)
-{
-   if(head && (arch & 0xf0) == 0x40)
-      reg += NV_PRMVIO_SIZE;
-
-   NV_WR08(regs, reg, val);
+	printf("\n");
 }
 
-static uint32_t NVReadRAMDAC(void* regs, int head, uint32_t reg)
+static void
+dump_pll(void *regs, const char *name, uint32_t reg)
 {
-	if (head)
-		reg += NV_PRAMDAC0_SIZE;
-	return NV_RD32(regs, reg);
-}
+	int pll = nv_rd32(regs, reg);
+	int n1, m1, n2, m2, p, vco2;
+	uint32_t strap_mask;
+	float f0;
 
-void NVWriteRAMDAC(void* regs, int head, uint32_t reg, uint32_t val)
-{
-	if (head)
-		reg += NV_PRAMDAC0_SIZE;
-        NV_WR32(regs, reg,val);
-}
+	strap_mask = 1 << 6;
+	if (nv_class(DUALHEAD_CLASS))
+		strap_mask |= 1 << 22;
 
-static uint32_t NVReadCRTC(void* regs, int head, uint32_t reg)
-{
-	if (head)
-		reg += NV_PCRTC0_SIZE;
-	return NV_RD32(regs, reg);
+	switch (nv_rd32(regs, NV_PEXTDEV_BOOT_0) & strap_mask) {
+	case 0:
+		f0 = 13.500;
+		break;
+	case (1 << 6):
+		f0 = 14.318;
+		break;
+	case (1 << 22):
+		f0 = 27.000;
+		break;
+	case (1 << 22 | 1 << 6):
+		f0 = 25.000;
+		break;
+	}
+
+	if (nv_class(TWOREG_PLL_CLASS)) {
+		uint32_t reg2 = reg + (reg == NV_PRAMDAC_VPLL2 ? 0x5c : 0x70);
+		uint32_t vco2_ctrl = nv_rd32(regs, 0x680580);
+		int pll2 = nv_rd32(regs, reg2);
+
+		vco2 = (chipset < 0x40 ||
+			(reg == NV_PRAMDAC_VPLL1 && !(vco2_ctrl & (1 << 8))) ||
+			(reg == NV_PRAMDAC_VPLL2 && !(vco2_ctrl & (1 << 28))));
+
+		n1 = (pll & 0xff00) >> 8;
+		m1 = pll & 0xff;
+		p = (pll & 0x70000) >> 16;
+
+		n2 = (pll2 & 0xff00) >> 8;
+		m2 = pll2 & 0xff;
+
+	} else if (nv_class(TWOSTAGE_PLL_CLASS)) {
+		n1 = (pll & 0xff00) >> 8;
+		m1 = pll & 0xf;
+		n2 = (pll & 0x380000) >> 19 | (pll & 0x3000000) >> 24 << 3;
+		m2 = (pll & 0x70) >> 4;
+		p = (pll & 0x70000) >> 16;
+		vco2 = pll & 0x80;
+
+	} else {
+		n1 = (pll & 0xff00) >> 8;
+		m1 = pll & 0xff;
+		n2 = 1;
+		m2 = 1;
+		p = (pll & 0x70000) >> 16;
+		vco2 = 0;
+	}
+
+	printf(" %s: 0x%x N1=0x%x M1=0x%x N2=0x%x M2=0x%x"
+	       " P=0x%x VCO2=%d f0=%f f=%f\n",
+	       name, pll, n1, m1, n2, m2, p, vco2, f0,
+	       (f0 * (float)n1 / m1 * (vco2 ? n2 / m2 : 1) *
+		(float)(1 << (7 - p)) / (1 << 7)));
 }
 
-void NVWriteCRTC(void* regs, int head, uint32_t reg, uint32_t val)
+static void
+dump_crtc_timings(void *regs, int head)
 {
-	if (head)
-		reg += NV_PCRTC0_SIZE;
-	NV_WR32(regs, reg ,val);
-}
-
-void nv_write_ptv(void* regs, uint32_t reg, uint32_t val){
-        NV_WR32(regs, 0xd000+reg, val);
+	int hdisplay, htotal, hsync_start, hsync_end, hblank_start, hblank_end,
+		vdisplay, vtotal, vsync_start, vsync_end, vblank_start,
+		vblank_end, ilace, dblscan, clkdiv, nhsync, nvsync;
+
+	write_vga_crtc(regs, 0, NV_CIO_SR_LOCK, 0x57);
+	write_vga_crtc(regs, 0, 0x44, head);
+
+        hdisplay = read_vga_crtc(regs, head, NV_CIO_CR_HDE) |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x2) >> 1 << 8;
+
+        htotal = read_vga_crtc(regs, head, NV_CIO_CR_HDT) |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x1) << 8;
+
+        hsync_start = read_vga_crtc(regs, head, NV_CIO_CR_HRS) |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x8) >> 3 << 8;
+
+        hsync_end = read_vga_crtc(regs, head, NV_CIO_CR_HRE) & 0x1F;
+
+        hblank_start = read_vga_crtc(regs, head, NV_CIO_CR_HBS) |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x4) >> 2 << 8;
+
+        hblank_end = (read_vga_crtc(regs, head, NV_CIO_CR_HBE) & 0x1f) |
+                (read_vga_crtc(regs, head, NV_CIO_CR_HRE) & 0x80) >> 7 << 5 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x10) >> 4 << 6;
+
+        vdisplay = read_vga_crtc(regs, head, NV_CIO_CR_VDE) |
+                (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x2) >> 1 << 8 |
+		(read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x40) >> 6 << 9 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x2) >> 1 << 10 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x4) >> 2 << 11;
+
+        vtotal = read_vga_crtc(regs, head, NV_CIO_CR_VDT) |
+                (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x20) >> 5 << 9 |
+                (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x1) << 8 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x1) << 10 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x1) << 11;
+
+        vsync_start = read_vga_crtc(regs, head, NV_CIO_CR_VRS) |
+		(read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x80) >> 7 << 9 |
+                (read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x4) >> 2 << 8 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x4) >> 2 << 10 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x10) >> 4 << 11;
+
+        vsync_end = read_vga_crtc(regs, head, NV_CIO_CR_VRE) & 0xF;
+
+        vblank_start = read_vga_crtc(regs, head, NV_CIO_CR_VBS) |
+		(read_vga_crtc(regs, head, NV_CIO_CR_OVL) & 0x8) >> 3 << 8 |
+                (read_vga_crtc(regs, head, NV_CIO_CR_CELL_HT) & 0x20) >> 5 << 9 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_LSR) & 0x8) >> 3 << 10 |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_EBR) & 0x40) >> 6 << 11;
+
+        vblank_end = read_vga_crtc(regs, head, NV_CIO_CR_VBE);
+
+        ilace = read_vga_crtc(regs, head, NV_CIO_CRE_ILACE) |
+                (read_vga_crtc(regs, head, NV_CIO_CRE_HEB) & 0x10) >> 4 << 8;
+
+        dblscan = read_vga_crtc(regs, head, NV_CIO_CR_CELL_HT) & 0x80;
+	clkdiv = read_vga_seq(regs, head, NV_VIO_SR_CLOCK) & 0x8;
+	nhsync = read_prmvio(regs, head, NV_PRMVIO_MISC__READ) & 0x40;
+	nvsync = read_prmvio(regs, head, NV_PRMVIO_MISC__READ) & 0x80;
+
+	printf("-- CRTC%d timings\n", head);
+
+	printf(" hdisplay: %d\n", (hdisplay + 1) * 8);
+	printf(" htotal: %d\n", (htotal + 5) * 8);
+	printf(" hsync start: %d\n", (hsync_start - 1) * 8);
+	printf(" hsync end: %d\n",
+	       (subm(hsync_end, hsync_start, 32) + hsync_start - 1) * 8);
+	printf(" hblank start: %d\n", (hblank_start + 1) * 8);
+	printf(" hblank end: %d\n",
+	       (subm(hblank_end, hblank_start, 128) + hblank_start + 1) * 8);
+
+	printf(" vdisplay: %d\n", vdisplay + 1);
+	printf(" vtotal: %d\n", vtotal + 2);
+	printf(" vsync start: %d\n", vsync_start + 1);
+	printf(" vsync end: %d\n",
+	       subm(vsync_end, vsync_start, 16) + vsync_start + 1);
+	printf(" vblank start: %d\n", vblank_start + 1);
+	printf(" vblank end: %d\n",
+	       subm(vblank_end, vblank_start, 256) + vblank_start + 1);
+	printf(" ilace: %d%s\n", ilace,
+	       (ilace & 0xff) == 0xff ? " [off]" : "");
+
+	printf(" dblscan: %d\n", dblscan);
+	printf(" clkdiv2: %d\n", clkdiv);
+	printf(" nhsync: %d\n", nhsync);
+	printf(" nvsync: %d\n", nvsync);
+	printf("\n");
 }
 
-uint32_t nv_read_ptv(void* regs, uint32_t reg){
-        return NV_RD32(regs, 0xd000+reg);
-}
-
-void nv_write_tve(void* regs, uint32_t reg, uint32_t val){
-      NV_WR32(regs, 0xd220, reg);
-      NV_WR32(regs, 0xd224, val);
-}
+#define block_name(buf, ...)						\
+	({								\
+		snprintf(buf, sizeof(buf), __VA_ARGS__);		\
+		buf;							\
+	})
 
-uint8_t nv_read_tmds(void *regs,
-		     int ramdac, int dl, uint8_t address)
+static int
+tv_dump(void *regs)
 {
-	NVWriteRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8,
-		      NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address);
-	return NVReadRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8);
+	char buf[64];
+	int i, j;
+
+	nv_detect_chipset(regs);
+	printf("-- Chipset: NV%x\n", chipset);
+
+	dump_block(pmc_block, mmio_domain(regs), block_name(buf, "PMC"));
+	dump_block(pbus_block, mmio_domain(regs), block_name(buf, "PBUS"));
+	dump_block(pfb_block, mmio_domain(regs), block_name(buf, "PFB"));
+
+	printf("-- PLLs\n");
+	dump_pll(regs, "NVPLL", NV_PRAMDAC_NVPLL);
+	dump_pll(regs, "MPLL", NV_PRAMDAC_MPLL);
+	dump_pll(regs, "VPLL1", NV_PRAMDAC_VPLL1);
+	dump_pll(regs, "VPLL2", NV_PRAMDAC_VPLL2);
+	printf("\n");
+
+	for (i = 0; i < 2; i++) {
+		dump_block(pcrtc_block, head_domain(regs, i),
+			   block_name(buf, "PCRTC%d", i));
+		dump_block(vga_crtc_block, vga_crtc_domain(regs, i),
+			   block_name(buf, "CIO%d", i));
+		dump_crtc_timings(regs, i);
+	}
+
+	for (i = 0; i < 2; i++)
+		dump_block(pramdac_block, head_domain(regs, i),
+			   block_name(buf, "PRAMDAC%d", i));
+
+	dump_block(ptv_block, mmio_domain(regs), block_name(buf, "PTV"));
+	dump_block(itv_block, itv_domain(regs), block_name(buf, "ITV"));
+
+	for (i = 0; i < 2; i++) {
+		for (j = 0; j < 2; j++) {
+			dump_block(tmds_block, tmds_domain(regs, i, j),
+				   block_name(buf, "TMDS%dL%d", i, j));
+		}
+	}
+
+	dump_block(pvideo_block, mmio_domain(regs), block_name(buf, "PVIDEO"));
+
+	return 0;
 }
 
-int NVGetArchitecture(volatile uint32_t *regs)
+int
+main(int argc, char *argv[])
 {
-	int architecture = 0;
-
-	/* We're dealing with >=NV10 */
-	if ((regs[0] & 0x0f000000) > 0 )
-		/* Bit 27-20 contain the architecture in hex */
-		architecture = (regs[0] & 0xff00000) >> 20;
-	/* NV04 or NV05 */
-	else if ((regs[0] & 0xff00fff0) == 0x20004000)
-		architecture = 0x04;
-
-	return architecture;
-}
-
-#define DIFFM(A,B,M) ((A%M + M - B%M)%M)
-#define MASK(field) ((0xffffffff >> (31 - ((1?field) - (0?field)))) << (0?field))
-#define XLATE(src, srclowbit, outfield) ((((src) >> (srclowbit)) << (0?outfield)) & MASK(outfield))
-#define LEN(xs) (sizeof(xs) / sizeof(*(xs)))
-
-void tv_dump(void* regs){
-   int i,j;
-   arch = NVGetArchitecture(regs);
-
-   printf("-- Architecture: NV%x\n", arch);
-
-   printf("-- TV encoder register dump --\n");
-   for(i=0; i<0x40; i++){
-      NV_WR32(regs, 0xd220, i);
-      printf("%x: %x\n",i,NV_RD32(regs, 0xd224));
-   }
-
-   printf("-- PTV register dump --\n");
-   for(i=0; i<0x10; i+=4)
-      printf("%x: %x\n",0x200+i,NV_RD32(regs, 0xd200+i));
-   for(i=0; i<0x100; i+=4)
-      printf("%x: %x\n",0x300+i,NV_RD32(regs, 0xd300+i));
-   for(i=0; i<0x10; i+=4)
-      printf("%x: %x\n",0x400+i,NV_RD32(regs, 0xd400+i));
-   for(i=0; i<0x90; i+=4)
-      printf("%x: %x\n",0x500+i,NV_RD32(regs, 0xd500+i));
-   for(i=0; i<0x20; i+=4)
-      printf("%x: %x\n",0x600+i,NV_RD32(regs, 0xd600+i));
-
-   write_vga_crtc(regs, 0, NV_CIO_SR_LOCK_INDEX, NV_CIO_SR_UNLOCK_RW_VALUE);
-
-   for(i=0; i<2; i++){
-      write_vga_crtc(regs, 0, NV_CIO_CRE_44, i);
-
-      int horizDisplay = read_vga_crtc(regs, i, NV_CIO_CR_HDE_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),1,8:8);
-      int horizTotal = read_vga_crtc(regs, i, NV_CIO_CR_HDT_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),0,8:8);
-      int horizStart = read_vga_crtc(regs, i, NV_CIO_CR_HRS_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),3,8:8);
-      int horizEnd = read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX) & 0x1F;
-      int horizBlankStart = read_vga_crtc(regs, i, NV_CIO_CR_HBS_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),2,8:8);
-      int horizBlankEnd = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HBE_INDEX),0,4:0) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX),7, 5:5) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),4,6:6);
-
-      int vertDisplay = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),6,9:9)|
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),1,8:8) |
-         read_vga_crtc(regs, i, NV_CIO_CR_VDE_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),1,10:10) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),2,11:11);
-      int vertTotal = read_vga_crtc(regs, i, NV_CIO_CR_VDT_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),5,9:9) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),0,8:8) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),0,10:10) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),0,11:11);
-      int vertStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),7,9:9) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),2,8:8) |
-         read_vga_crtc(regs, i, NV_CIO_CR_VRS_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),2,10:10) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),4,11:11);
-      int vertEnd = read_vga_crtc(regs, i, NV_CIO_CR_VRE_INDEX) & 0xF;
-      int vertBlankStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),3,8:8) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX),5,9:9) |
-         read_vga_crtc(regs, i, NV_CIO_CR_VBS_INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),3,10:10) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),6,11:11);
-      int vertBlankEnd = read_vga_crtc(regs, i, NV_CIO_CR_VBE_INDEX);
-
-      int ilace_idx = read_vga_crtc(regs, i, NV_CIO_CRE_ILACE__INDEX) |
-         XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),4,8:8);
-      int dblscan = read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX) & 0x80;
-
-      write_prmvio(regs, i, NV_PRMVIO_SRX, NV_VIO_SR_CLOCK_INDEX);
-      int clkdiv2 = read_prmvio(regs, i, NV_PRMVIO_SR)& 0x8;
-
-      int nhsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x40;
-      int nvsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x80;
-
-      printf("-- CRTC %d timings --\n",i);
-      printf("horizDisplay: %d\n",(horizDisplay+1)*8);
-      printf("horizTotal: %d\n",(horizTotal+5)*8);
-      printf("horizSyncStart: %d\n",(horizStart-1)*8);
-      printf("horizSyncEnd: %d\n",(DIFFM(horizEnd,horizStart,0x20)+horizStart-1)*8);
-      printf("horizBlankStart: %d\n",(horizBlankStart+1)*8);
-      printf("horizBlankEnd: %d\n",(DIFFM(horizBlankEnd,horizBlankStart,128)+horizBlankStart+1)*8);
-      printf("vertDisplay: %d\n",vertDisplay+1);
-      printf("vertTotal: %d\n",vertTotal+2);
-      printf("vertSyncStart: %d\n",vertStart+1);
-      printf("vertSyncEnd: %d\n",DIFFM(vertEnd,vertStart,16)+vertStart+1);
-      printf("vertBlankStart: %d\n",vertBlankStart+1);
-      printf("vertBlankEnd: %d\n",DIFFM(vertBlankEnd,vertBlankStart,256)+vertBlankStart+1);
-      printf("ilace_idx: %d%s\n",ilace_idx,(ilace_idx&0xff) == 0xff ? " [off]":"");
-      printf("dblscan: %d\n",dblscan);
-      printf("clkdiv2: %d\n",clkdiv2);
-      printf("nhsync: %d\n",nhsync);
-      printf("nvsync: %d\n",nvsync);
-
-   }
-
-   for(i=0; i<2; i++){
-      int pll = NV_RD32(regs, i? NV_RAMDAC_VPLL2: NV_PRAMDAC_VPLL_COEFF);
-      int n1,m1,n2,m2,p,vco2;
-      float f0;
-
-      {
-         uint32_t crystal_strap_mask = 1 << 6;
-         /* open coded pNv->twoHeads test */
-         if (arch > 0x10 && arch != 0x15 && arch != 0x1a && arch != 0x20)
-            crystal_strap_mask |= 1 << 22;
-
-         switch (NV_RD32(regs, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) {
-            case 0:
-		f0 = 13.500;
-                break;
-            case (1 << 6):
-               f0 = 14.318;
-               break;
-            case (1 << 22):
-               f0 = 27.000;
-               break;
-            case (1 << 22 | 1 << 6):
-               f0 = 25.000;
-               break;
-         }
-      }
-
-
-      if(arch == 0x35 || arch == 0x30){
-              n1=XLATE(pll,8,7:0);
-              m1=XLATE(pll, 0, 3:0);
-              n2=XLATE(pll, 19, 2:0) | XLATE(pll, 24, 4:3);
-              m2=XLATE(pll, 4, 2:0);
-              p=XLATE(pll, 16, 2:0);
-              vco2=pll&0x80;
-
-      } else if(arch == 0x31 || arch == 0x36 || arch >= 0x40) {
-              int pll2 = NV_RD32(regs, i? NV_RAMDAC_VPLL2 + 0x5c: NV_PRAMDAC_VPLL_COEFF + 0x70);
-
-              if(arch >= 0x40)
-                      vco2 = (i==0 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL1_ACTIVE)) ||
-                              (i==1 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL2_ACTIVE));
-              else
-                      vco2 = 1;
-
-              n1=XLATE(pll,8,7:0);
-              m1=XLATE(pll, 0, 7:0);
-              p=XLATE(pll, 16, 2:0);
-
-              n2=XLATE(pll2,8,7:0);
-              m2=XLATE(pll2, 0, 7:0);
-
-      } else {
-              n1=XLATE(pll,8,7:0);
-              m1=XLATE(pll, 0, 7:0);
-              n2=1;
-              m2=1;
-              p=XLATE(pll, 16, 2:0);
-              vco2=0;
-      }
-
-      printf("-- VPLL%d: 0x%x N1=0x%x M1=0x%x N2=0x%x M2=0x%x P=0x%x VCO2=%d f0=%f f=%f\n",
-             i ,pll, n1, m1, n2, m2, p, vco2, f0, f0*(float)n1/m1*(vco2?n2/m2:1)*(float)(1<<(7-p))/(1<<7));
-   }
-
-   for(i=0; i<2; i++){
-      printf("-- VGA CRTC%d registers --\n",i);
-      printf("NV_CIO_CRE_PIXEL_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_PIXEL_INDEX));
-      printf("NV_CIO_CRE_LCD__INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_LCD__INDEX));
-      printf("NV_CIO_CRE_FP_HTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_HTIMING_INDEX));
-      printf("NV_CIO_CRE_FP_VTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_VTIMING_INDEX));
-      printf("NV_CIO_CRE_43: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_43));
-      printf("NV_CIO_CRE_RPC1_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_RPC1_INDEX));
-      printf("NV_CIO_CRE_ENH_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_ENH_INDEX));
-   }
-
-
-   for(j=0; j<2; j++){
-           printf("-- VGA CRTC%d registers --\n", j);
-           for(i=0; i<0xa0; i++)
-                   printf("CRTC%x %x: %x\n", j, i, read_vga_crtc(regs, j, i));
-   }
-
-   for(i=0; i<2; i++){
-      printf("-- PRAMDAC%d registers --\n",i);
-      printf("NV_PRAMDAC_630: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_630));
-      printf("NV_PRAMDAC0_OFFSET+0x674: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0x674));
-      printf("NV_PRAMDAC_TV_SETUP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SETUP));
-      printf("NV_PRAMDAC_TV_VBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_START));
-      printf("NV_PRAMDAC_TV_VBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_END));
-      printf("NV_PRAMDAC_TV_HBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_START));
-      printf("NV_PRAMDAC_TV_HBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_END));
-      printf("NV_PRAMDAC_TV_BLANK_COLOR: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_BLANK_COLOR));
-      printf("NV_PRAMDAC_TV_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VTOTAL));
-      printf("NV_PRAMDAC_TV_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_START));
-      printf("NV_PRAMDAC_TV_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_END));
-      printf("NV_PRAMDAC_TV_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HTOTAL));
-      printf("NV_PRAMDAC_TV_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_START));
-      printf("NV_PRAMDAC_TV_HSYNC_STOP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_STOP));
-      printf("NV_PRAMDAC_TV_SYNC_DELAY: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SYNC_DELAY));
-      printf("NV_PRAMDAC_FP_DEBUG_0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_0));
-      printf("NV_PRAMDAC_FP_DEBUG_1: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_1));
-      printf("NV_PRAMDAC_FP_DEBUG_2: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_2));
-      printf("NV_PRAMDAC_FP_TG_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_TG_CONTROL));
-      printf("NV_PRAMDAC_FP_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HTOTAL));
-      printf("NV_PRAMDAC_FP_HVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_START));
-      printf("NV_PRAMDAC_FP_HVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_END));
-      printf("NV_PRAMDAC_FP_HDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HDISPLAY_END));
-      printf("NV_PRAMDAC_FP_HCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HCRTC));
-      printf("NV_PRAMDAC_FP_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_START));
-      printf("NV_PRAMDAC_FP_HSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_END));
-      printf("NV_PRAMDAC_FP_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VTOTAL));
-      printf("NV_PRAMDAC_FP_VVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_START));
-      printf("NV_PRAMDAC_FP_VVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_END));
-      printf("NV_PRAMDAC_FP_VDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VDISPLAY_END));
-      printf("NV_PRAMDAC_FP_VCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VCRTC));
-      printf("NV_PRAMDAC_FP_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_START));
-      printf("NV_PRAMDAC_FP_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_END));
-      printf("NV_PRAMDAC_84C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_84C));
-      printf("NV_PRAMDAC_898: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_898));
-      printf("NV_PRAMDAC_89C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_89C));
-      printf("NV_PRAMDAC_8C0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_8C0));
-      printf("NV_PRAMDAC_900: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_900));
-      printf("NV_PRAMDAC_PLL_SETUP_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_SETUP_CONTROL));
-      printf("NV_PRAMDAC_SEL_CLK: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_SEL_CLK));
-      printf("NV_PRAMDAC_PLL_COEFF_SELECT: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_COEFF_SELECT));
-
-      for(j=0; j<64; j++)
-              printf("NV_PRAMDAC0_OFFSET+0xc%02x: 0x%x\n", 4*j, NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0xc00+4*j));
-   }
-
-   for(i=0; i<2; i++){
-      printf("-- TMDS%d registers --\n",i);
-      for (j=0; j<0x40; j++)
-	      printf("TMDS%d_%x: 0x%x\n", i, j, nv_read_tmds(regs, i, 0, j));
-
-   }
-
-   for(i=0; i<2; i++){
-      printf("-- PCRTC%d registers --\n",i);
-      printf("NV_PCRTC_CONFIG: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_CONFIG));
-      printf("NV_PCRTC_START: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_START));
-      printf("NV_PCRTC_GPIO_EXT: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_GPIO_EXT));
-      printf("NV_PCRTC_830: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_830));
-      printf("NV_PCRTC_834: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_834));
-   }
-
-   printf("-- OUTPUT registers--\n");
-   int offsets[] = {0, 0x68, 0x2000, 0x2068};
-
-   for(i=0; i< LEN(offsets); i++)
-           printf("NV_PRAMDAC_DACCLK+0x%x: 0x%x\n",offsets[i], NVReadRAMDAC(regs, 0, NV_PRAMDAC_DACCLK+offsets[i]));
-
-   printf("-- PVIDEO registers --\n");
-   printf("NV_PVIDEO_DEBUG_0: 0x%x\n", NV_RD32(regs,0x00008080));
-   printf("NV_PVIDEO_DEBUG_1: 0x%x\n", NV_RD32(regs,0x00008084));
-   printf("NV_PVIDEO_DEBUG_2: 0x%x\n", NV_RD32(regs,0x00008088));
-   printf("NV_PVIDEO_DEBUG_3: 0x%x\n", NV_RD32(regs,0x0000808C));
-   printf("NV_PVIDEO_DEBUG_4: 0x%x\n", NV_RD32(regs,0x00008090));
-   printf("NV_PVIDEO_DEBUG_5: 0x%x\n", NV_RD32(regs,0x00008094));
-   printf("NV_PVIDEO_DEBUG_6: 0x%x\n", NV_RD32(regs,0x00008098));
-   printf("NV_PVIDEO_DEBUG_7: 0x%x\n", NV_RD32(regs,0x0000809C));
-   printf("NV_PVIDEO_DEBUG_8: 0x%x\n", NV_RD32(regs,0x000080A0));
-   printf("NV_PVIDEO_DEBUG_9: 0x%x\n", NV_RD32(regs,0x000080A4));
-   printf("NV_PVIDEO_DEBUG_10: 0x%x\n", NV_RD32(regs,0x000080A8));
-   printf("NV_PVIDEO_INTR: 0x%x\n", NV_RD32(regs,0x00008100));
-   printf("NV_PVIDEO_INTR_REASON: 0x%x\n", NV_RD32(regs,0x00008104));
-   printf("NV_PVIDEO_INTR_EN: 0x%x\n", NV_RD32(regs,0x00008140));
-   printf("NV_PVIDEO_BUFFER: 0x%x\n", NV_RD32(regs,0x00008700));
-   printf("NV_PVIDEO_STOP: 0x%x\n", NV_RD32(regs,0x00008704));
-   printf("NV_PVIDEO_BASE: 0x%x\n", NV_RD32(regs,0x00008900));
-   printf("NV_PVIDEO_LIMIT: 0x%x\n", NV_RD32(regs,0x00008908));
-   printf("NV_PVIDEO_LUMINANCE: 0x%x\n", NV_RD32(regs,0x00008910));
-   printf("NV_PVIDEO_CHROMINANCE: 0x%x\n", NV_RD32(regs,0x00008918));
-   printf("NV_PVIDEO_OFFSET: 0x%x\n", NV_RD32(regs,0x00008920));
-   printf("NV_PVIDEO_SIZE_IN: 0x%x\n", NV_RD32(regs,0x00008928));
-   printf("NV_PVIDEO_POINT_IN: 0x%x\n", NV_RD32(regs,0x00008930));
-   printf("NV_PVIDEO_DS_DX: 0x%x\n", NV_RD32(regs,0x00008938));
-   printf("NV_PVIDEO_DT_DY: 0x%x\n", NV_RD32(regs,0x00008940));
-   printf("NV_PVIDEO_POINT_OUT: 0x%x\n", NV_RD32(regs,0x00008948));
-   printf("NV_PVIDEO_SIZE_OUT: 0x%x\n", NV_RD32(regs,0x00008950));
-   printf("NV_PVIDEO_FORMAT: 0x%x\n", NV_RD32(regs,0x00008958));
-   printf("NV_PVIDEO_COLOR_KEY: 0x%x\n", NV_RD32(regs,0x00008B00));
-   printf("NV_PVIDEO_TEST: 0x%x\n", NV_RD32(regs,0x00008D00));
-   printf("NV_PVIDEO_TST_WRITE: 0x%x\n", NV_RD32(regs,0x00008D10));
-   printf("NV_PVIDEO_TST_READ: 0x%x\n", NV_RD32(regs,0x00008D40));
-
-   printf("-- PBUS registers --\n");
-   {
-	   uint32_t pbus_regs[] = {
-		   0x1084, 0x108c, 0x1098, 0x10b8, 0x10d8, 0x10e0, 0x10f0,
-		   0x1100, 0x1140, 0x1210, 0x1214, 0x1218, 0x121c, 0x1220,
-		   0x1228, 0x122c, 0x1230, 0x1234, 0x1238, 0x123c, 0x1240,
-		   0x1244, 0x1248, 0x1518, 0x1580, 0x1584, 0x1588, 0x158c,
-		   0x1590, 0x15a0, 0x1800, 0x1804, 0x1808, 0x180c, 0x1810,
-		   0x1814, 0x1818, 0x182c, 0x1830, 0x1844, 0x1848, 0x184c,
-		   0x1850, 0x1854, 0x1860
-	   };
-
-	   for (i = 0; i < LEN(pbus_regs); i++)
-		   printf("PBUS: 0x%x: 0x%x\n", pbus_regs[i],
-			  NV_RD32(regs, pbus_regs[i]));
-   }
-
-   printf("-- PFB registers --\n");
-   {
-	   uint32_t pfb_regs[] = {
-		   0x100000, 0x100080, 0x100200, 0x100204,
-		   0x10020c, 0x100210, 0x100300, 0x100304,
-		   0x100308, 0x100328, 0x10032c, 0x100330,
-		   0x100334, 0x100338, 0x100350, 0x100360,
-		   0x10037c, 0x100380, 0x100384, 0x100388,
-		   0x10038c, 0x100390, 0x100394, 0x100398,
-		   0x10039c, 0x1003a0, 0x1003a4, 0x1003a8,
-		   0x1003ac, 0x1003b0, 0x1003b4, 0x1003b8,
-		   0x1003bc, 0x1003c0, 0x1003c4, 0x1003c8,
-		   0x1003d0
-	   };
-
-	   for (i = 0; i < LEN(pfb_regs); i++)
-		   printf("PFB: 0x%x: 0x%x\n", pfb_regs[i],
-			  NV_RD32(regs, pfb_regs[i]));
-
-   }
-
-}
-
-int main(){
-   void* regs;
-   int ret;
-
-   ret = pci_system_init();
-
-   if(ret){
-      fprintf(stderr,"Error calling pci_system_init().\n");
-
-      return 1;
-   }
-
-   struct pci_id_match nv_match = {0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x30000, 0xffff0000};
-   struct pci_device_iterator* it = pci_id_match_iterator_create(&nv_match);
-
-   if(!it){
-      fprintf(stderr,"Error calling pci_id_match_iterator_create().\n");
-
-      pci_iterator_destroy(it);
-
-      return 1;
-   }
-
-   struct pci_device* dev = pci_device_next(it);
-
-   if(!dev){
-      fprintf(stderr,"No devices found.\n");
-
-      pci_iterator_destroy(it);
-      pci_system_cleanup();
-
-      return 1;
-   }
-
-   ret = pci_device_probe(dev);
-
-   if(ret){
-      fprintf(stderr, "Error calling pci_device_probe().\n");
-
-      pci_iterator_destroy(it);
-      pci_system_cleanup();
-
-      return 1;
-   }
-
-   ret = pci_device_map_range(dev, dev->regions[0].base_addr, dev->regions[0].size, PCI_DEV_MAP_FLAG_WRITABLE,&regs);
-
-   if(ret){
-      fprintf(stderr, "Error calling pci_device_map_range().\n");
-
-      pci_iterator_destroy(it);
-      pci_system_cleanup();
-
-      return 1;
-   }
-
-   tv_dump(regs);
-
-   pci_device_unmap_range(dev, regs, dev->regions[0].size);
-   pci_iterator_destroy(it);
-   pci_system_cleanup();
-
-   return 0;
+	struct pci_id_match match = { 0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY,
+				      PCI_MATCH_ANY, 0x30000, 0xffff0000 };
+	struct pci_device_iterator *it;
+	struct pci_device *dev;
+	void *regs;
+	int ret;
+
+	ret = pci_system_init();
+	if (ret)
+		goto out;
+
+	it = pci_id_match_iterator_create(&match);
+	if (!it) {
+		ret = ENOMEM;
+		goto out_sys;
+	}
+
+	dev = pci_device_next(it);
+	if (!dev) {
+		ret = ENODEV;
+		goto out_iter;
+	}
+
+	ret = pci_device_probe(dev);
+	if (ret)
+		goto out_iter;
+
+	ret = pci_device_map_range(dev, dev->regions[0].base_addr,
+				   dev->regions[0].size,
+				   PCI_DEV_MAP_FLAG_WRITABLE, &regs);
+	if (ret)
+		goto out_iter;
+
+	ret = tv_dump(regs);
+
+	pci_device_unmap_range(dev, regs, dev->regions[0].size);
+out_iter:
+	pci_iterator_destroy(it);
+out_sys:
+	pci_system_cleanup();
+out:
+	if (ret)
+		fprintf(stderr, "%s: %s\n", argv[0], strerror(ret));
+
+	return ret;
 }