diff options
author | Francisco Jerez <currojerez@riseup.net> | 2009-06-20 18:30:50 +0200 |
---|---|---|
committer | Francisco Jerez <currojerez@riseup.net> | 2009-11-30 15:23:13 +0100 |
commit | d86a3c004027428b002c296ceeb8647feabc5ae3 (patch) | |
tree | a81ae991425e41c361657171264e8ff0bc7573c5 |
Initial import.
-rw-r--r-- | Makefile | 2 | ||||
-rw-r--r-- | nvreg.h | 508 | ||||
-rw-r--r-- | tvdump.c | 493 | ||||
-rw-r--r-- | tvdump2code.py | 66 |
4 files changed, 1069 insertions, 0 deletions
diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..ccdae18 --- /dev/null +++ b/Makefile @@ -0,0 +1,2 @@ +tvdump: tvdump.c nvreg.h + gcc -Wall -O0 -g -lpciaccess -o $@ $<
\ No newline at end of file @@ -0,0 +1,508 @@ +/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ +/* + * Copyright 1996-1997 David J. McKay + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */ + +#ifndef __NVREG_H_ +#define __NVREG_H_ + +#define NV_PMC_OFFSET 0x00000000 +#define NV_PMC_SIZE 0x00001000 + +#define NV_PBUS_OFFSET 0x00001000 +#define NV_PBUS_SIZE 0x00001000 + +#define NV_PFIFO_OFFSET 0x00002000 +#define NV_PFIFO_SIZE 0x00002000 + +#define NV_HDIAG_OFFSET 0x00005000 +#define NV_HDIAG_SIZE 0x00001000 + +#define NV_PRAM_OFFSET 0x00006000 +#define NV_PRAM_SIZE 0x00001000 + +#define NV_PVIDEO_OFFSET 0x00008000 +#define NV_PVIDEO_SIZE 0x00001000 + +#define NV_PTIMER_OFFSET 0x00009000 +#define NV_PTIMER_SIZE 0x00001000 + +#define NV_PPM_OFFSET 0x0000A000 +#define NV_PPM_SIZE 0x00001000 + +#define NV_PRMVGA_OFFSET 0x000A0000 +#define NV_PRMVGA_SIZE 0x00020000 + +#define NV_PRMVIO0_OFFSET 0x000C0000 +#define NV_PRMVIO_SIZE 0x00002000 +#define NV_PRMVIO1_OFFSET 0x000C2000 + +#define NV_PFB_OFFSET 0x00100000 +#define NV_PFB_SIZE 0x00001000 + +#define NV_PEXTDEV_OFFSET 0x00101000 +#define NV_PEXTDEV_SIZE 0x00001000 + +#define NV_PME_OFFSET 0x00200000 +#define NV_PME_SIZE 0x00001000 + +#define NV_PROM_OFFSET 0x00300000 +#define NV_PROM_SIZE 0x00010000 + +#define NV_PGRAPH_OFFSET 0x00400000 +#define NV_PGRAPH_SIZE 0x00010000 + +#define NV_PCRTC0_OFFSET 0x00600000 +#define NV_PCRTC0_SIZE 0x00002000 /* empirical */ + +#define NV_PRMCIO0_OFFSET 0x00601000 +#define NV_PRMCIO_SIZE 0x00002000 +#define NV_PRMCIO1_OFFSET 0x00603000 + +#define NV50_DISPLAY_OFFSET 0x00610000 +#define NV50_DISPLAY_SIZE 0x0000FFFF + +#define NV_PRAMDAC0_OFFSET 0x00680000 +#define NV_PRAMDAC0_SIZE 0x00002000 + +#define NV_PRMDIO0_OFFSET 0x00681000 +#define NV_PRMDIO_SIZE 0x00002000 +#define NV_PRMDIO1_OFFSET 0x00683000 + +#define NV_PRAMIN_OFFSET 0x00700000 +#define NV_PRAMIN_SIZE 0x00100000 + +#define NV_FIFO_OFFSET 0x00800000 +#define NV_FIFO_SIZE 0x00800000 + +#define NV_PMC_BOOT_0 0x00000000 +#define NV_PMC_ENABLE 0x00000200 + +#define NV_VIO_VSE2 0x000003c3 +#define NV_VIO_SRX 0x000003c4 + +#define NV_CIO_CRX__COLOR 0x000003d4 +#define NV_CIO_CR__COLOR 0x000003d5 + +#define NV_PBUS_DEBUG_1 0x00001084 +#define NV_PBUS_DEBUG_4 0x00001098 +#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0 +#define NV_PBUS_POWERCTRL_1 0x00001584 +#define NV_PBUS_POWERCTRL_2 0x00001588 +#define NV_PBUS_POWERCTRL_4 0x00001590 +#define NV_PBUS_PCI_NV_19 0x0000184C +#define NV_PBUS_PCI_NV_20 0x00001850 +# define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) +# define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) + +#define NV_PFIFO_RAMHT 0x00002210 + +#define NV_PRMVIO_MISC__WRITE 0x000c03c2 +#define NV_PRMVIO_SRX 0x000c03c4 +#define NV_PRMVIO_SR 0x000c03c5 +# define NV_VIO_SR_RESET_INDEX 0x00 +# define NV_VIO_SR_CLOCK_INDEX 0x01 +# define NV_VIO_SR_PLANE_MASK_INDEX 0x02 +# define NV_VIO_SR_CHAR_MAP_INDEX 0x03 +# define NV_VIO_SR_MEM_MODE_INDEX 0x04 +#define NV_PRMVIO_MISC__READ 0x000c03cc +#define NV_PRMVIO_GRX 0x000c03ce +#define NV_PRMVIO_GX 0x000c03cf +# define NV_VIO_GX_SR_INDEX 0x00 +# define NV_VIO_GX_SREN_INDEX 0x01 +# define NV_VIO_GX_CCOMP_INDEX 0x02 +# define NV_VIO_GX_ROP_INDEX 0x03 +# define NV_VIO_GX_READ_MAP_INDEX 0x04 +# define NV_VIO_GX_MODE_INDEX 0x05 +# define NV_VIO_GX_MISC_INDEX 0x06 +# define NV_VIO_GX_DONT_CARE_INDEX 0x07 +# define NV_VIO_GX_BIT_MASK_INDEX 0x08 + +#define NV_PFB_BOOT_0 0x00100000 +#define NV_PFB_CFG0 0x00100200 +#define NV_PFB_CFG1 0x00100204 +#define NV_PFB_CSTATUS 0x0010020C +#define NV_PFB_REFCTRL 0x00100210 +# define NV_PFB_REFCTRL_VALID_1 (1 << 31) +#define NV_PFB_PAD 0x0010021C +# define NV_PFB_PAD_CKE_NORMAL (1 << 0) +#define NV_PFB_TILE_NV10 0x00100240 +#define NV_PFB_TILE_SIZE_NV10 0x00100244 +#define NV_PFB_REF 0x001002D0 +# define NV_PFB_REF_CMD_REFRESH (1 << 0) +#define NV_PFB_PRE 0x001002D4 +# define NV_PFB_PRE_CMD_PRECHARGE (1 << 0) +#define NV_PFB_CLOSE_PAGE2 0x0010033C +#define NV_PFB_TILE_NV40 0x00100600 +#define NV_PFB_TILE_SIZE_NV40 0x00100604 + +#define NV_PEXTDEV_BOOT_0 0x00101000 +# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12) +#define NV_PEXTDEV_BOOT_3 0x0010100c + +#define NV_PCRTC_INTR_0 0x00600100 +# define NV_PCRTC_INTR_0_VBLANK (1 << 0) +#define NV_PCRTC_INTR_EN_0 0x00600140 +#define NV_PCRTC_START 0x00600800 +#define NV_PCRTC_CONFIG 0x00600804 +# define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA (1 << 0) +# define NV_PCRTC_CONFIG_START_ADDRESS_HSYNC (2 << 0) +#define NV_PCRTC_CURSOR_CONFIG 0x00600810 +# define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE (1 << 0) +# define NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE (1 << 4) +# define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM (1 << 8) +# define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32 (1 << 12) +# define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 (1 << 16) +# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32 (2 << 24) +# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 (4 << 24) +# define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA (1 << 28) + +/* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */ +#define NV_PCRTC_GPIO 0x00600818 +#define NV_PCRTC_GPIO_EXT 0x0060081c +#define NV_PCRTC_830 0x00600830 +#define NV_PCRTC_834 0x00600834 +#define NV_PCRTC_850 0x00600850 +#define NV_PCRTC_ENGINE_CTRL 0x00600860 +# define NV_CRTC_FSEL_I2C (1 << 4) +# define NV_CRTC_FSEL_OVERLAY (1 << 12) + +#define NV_PRMCIO_ARX 0x006013c0 +#define NV_PRMCIO_AR__WRITE 0x006013c0 +#define NV_PRMCIO_AR__READ 0x006013c1 +# define NV_CIO_AR_MODE_INDEX 0x10 +# define NV_CIO_AR_OSCAN_INDEX 0x11 +# define NV_CIO_AR_PLANE_INDEX 0x12 +# define NV_CIO_AR_HPP_INDEX 0x13 +# define NV_CIO_AR_CSEL_INDEX 0x14 +#define NV_PRMCIO_INP0 0x006013c2 +#define NV_PRMCIO_CRX__COLOR 0x006013d4 +#define NV_PRMCIO_CR__COLOR 0x006013d5 + /* Standard VGA CRTC registers */ +# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */ +# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */ +# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */ +# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */ +# define NV_CIO_CR_HBE_4_0 4:0 +# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */ +# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */ +# define NV_CIO_CR_HRE_4_0 4:0 +# define NV_CIO_CR_HRE_HBE_5 7:7 +# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */ +# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */ +# define NV_CIO_CR_OVL_VDT_8 0:0 +# define NV_CIO_CR_OVL_VDE_8 1:1 +# define NV_CIO_CR_OVL_VRS_8 2:2 +# define NV_CIO_CR_OVL_VBS_8 3:3 +# define NV_CIO_CR_OVL_VDT_9 5:5 +# define NV_CIO_CR_OVL_VDE_9 6:6 +# define NV_CIO_CR_OVL_VRS_9 7:7 +# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */ +# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */ +# define NV_CIO_CR_CELL_HT_VBS_9 5:5 +# define NV_CIO_CR_CELL_HT_SCANDBL 7:7 +# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */ +# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */ +# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */ +# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */ +# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */ +# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */ +# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */ +# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */ +# define NV_CIO_CR_VRE_3_0 3:0 +# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */ +# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */ +# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */ +# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */ +# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */ +# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */ +# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */ + /* Extended VGA CRTC registers */ +# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */ +# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5 +# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */ +# define NV_CIO_CRE_RPC1_LARGE 2:2 +# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */ +# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */ +# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */ +# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57 +# define NV_CIO_SR_LOCK_VALUE 0x99 +# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */ +# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */ +# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */ +# define NV_CIO_CRE_LSR_VDT_10 0:0 +# define NV_CIO_CRE_LSR_VDE_10 1:1 +# define NV_CIO_CRE_LSR_VRS_10 2:2 +# define NV_CIO_CRE_LSR_VBS_10 3:3 +# define NV_CIO_CRE_LSR_HBE_6 4:4 +# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */ +# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */ +# define NV_CIO_CRE_PIXEL_INDEX 0x28 +# define NV_CIO_CRE_PIXEL_FORMAT 1:0 +# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */ +# define NV_CIO_CRE_HEB_HDT_8 0:0 +# define NV_CIO_CRE_HEB_HDE_8 1:1 +# define NV_CIO_CRE_HEB_HBS_8 2:2 +# define NV_CIO_CRE_HEB_HRS_8 3:3 +# define NV_CIO_CRE_HEB_ILC_8 4:4 +# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */ +# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */ +# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */ +# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0 +# define NV_CIO_CRE_HCUR_ASI 7:7 +# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */ +# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0 +# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1 +# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2 +# define NV_CIO_CRE_LCD__INDEX 0x33 +# define NV_CIO_CRE_LCD_LCD_SELECT 0:0 +# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36 +# define NV_CIO_CRE_DDC0_WR__INDEX 0x37 +# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */ +# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b +# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c +# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e +# define NV_CIO_CRE_DDC_WR__INDEX 0x3f +# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */ +# define NV_CIO_CRE_EBR_VDT_11 0:0 +# define NV_CIO_CRE_EBR_VDE_11 2:2 +# define NV_CIO_CRE_EBR_VRS_11 4:4 +# define NV_CIO_CRE_EBR_VBS_11 6:6 +# define NV_CIO_CRE_43 0x43 +# define NV_CIO_CRE_44 0x44 /* head control */ +# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */ +# define NV_CIO_CRE_RCR 0x46 +# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7 +# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */ +# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */ +# define NV_CIO_CRE_TVOUT_LATENCY 0x52 +# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */ +# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */ +# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */ +# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */ +# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */ +# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */ +# define NV_CIO_CRE_85 0x85 +# define NV_CIO_CRE_86 0x86 +#define NV_PRMCIO_INP0__COLOR 0x006013da + +#define NV_PRAMDAC_CU_START_POS 0x00680300 +# define NV_PRAMDAC_CU_START_POS_X 15:0 +# define NV_PRAMDAC_CU_START_POS_Y 31:16 +#define NV_RAMDAC_NV10_CURSYNC 0x00680404 + +#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 +#define NV_PRAMDAC_MPLL_COEFF 0x00680504 +#define NV_PRAMDAC_VPLL_COEFF 0x00680508 +# define NV30_RAMDAC_ENABLE_VCO2 (8 << 4) + +#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c +# define NV_RAMDAC_PLL_SELECT_USE_VPLL2_TRUE (4 << 0) +# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL (1 << 8) +# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL (2 << 8) +# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL (4 << 8) +# define NV_RAMDAC_PLL_SELECT_PLL_SOURCE_VPLL2 (8 << 8) +# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 (1 << 28) +# define NV_RAMDAC_PLL_SELECT_VCLK2_RATIO_DB2 (2 << 28) + +#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510 +#define NV_RAMDAC_VPLL2 0x00680520 +#define NV_PRAMDAC_SEL_CLK 0x00680524 +#define NV_RAMDAC_DITHER_NV11 0x00680528 +#define NV_PRAMDAC_DACCLK 0x0068052c +# define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0) + +#define NV_RAMDAC_NVPLL_B 0x00680570 +#define NV_RAMDAC_MPLL_B 0x00680574 +#define NV_RAMDAC_VPLL_B 0x00680578 +#define NV_RAMDAC_VPLL2_B 0x0068057c +# define NV31_RAMDAC_ENABLE_VCO2 (8 << 28) +#define NV_PRAMDAC_580 0x00680580 +# define NV_RAMDAC_580_VPLL1_ACTIVE (1 << 8) +# define NV_RAMDAC_580_VPLL2_ACTIVE (1 << 28) + +#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 +# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4) +# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8) +# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12) +# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16) +# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20) +# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28) +#define NV_PRAMDAC_TEST_CONTROL 0x00680608 +# define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12) +# define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16) +# define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28) +#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610 +# define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (8 << 28) +#define NV_PRAMDAC_630 0x00680630 +#define NV_PRAMDAC_634 0x00680634 + +#define NV_PRAMDAC_TV_SETUP 0x00680700 + +#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800 +#define NV_PRAMDAC_FP_VTOTAL 0x00680804 +#define NV_PRAMDAC_FP_VCRTC 0x00680808 +#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c +#define NV_PRAMDAC_FP_VSYNC_END 0x00680810 +#define NV_PRAMDAC_FP_VVALID_START 0x00680814 +#define NV_PRAMDAC_FP_VVALID_END 0x00680818 +#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820 +#define NV_PRAMDAC_FP_HTOTAL 0x00680824 +#define NV_PRAMDAC_FP_HCRTC 0x00680828 +#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c +#define NV_PRAMDAC_FP_HSYNC_END 0x00680830 +#define NV_PRAMDAC_FP_HVALID_START 0x00680834 +#define NV_PRAMDAC_FP_HVALID_END 0x00680838 + +#define NV_RAMDAC_FP_DITHER 0x0068083c +#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848 +# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0) +# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0) +# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS (1 << 4) +# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE (2 << 4) +# define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8) +# define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER (1 << 8) +# define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE (2 << 8) +# define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG (1 << 20) +# define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24) +# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28) +# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28) +#define NV_PRAMDAC_850 0x00680850 +#define NV_PRAMDAC_85C 0x0068085c +#define NV_PRAMDAC_FP_DEBUG_0 0x00680880 +# define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0) +# define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE (1 << 4) +/* This doesn't seem to be essential for tmds, but still often set */ +# define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (8 << 4) +# define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR (1 << 8) +# define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR (1 << 12) +# define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND (1 << 20) +# define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND (1 << 24) +# define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28) +#define NV_PRAMDAC_FP_DEBUG_1 0x00680884 +# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0 +# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE (1 << 12) +# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16 +# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE (1 << 28) +#define NV_PRAMDAC_FP_DEBUG_2 0x00680888 +#define NV_PRAMDAC_FP_DEBUG_3 0x0068088C + +/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */ +#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0 +# define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1 << 16) +#define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4 + +#define NV_PRAMDAC_8C0 0x006808c0 + +/* Some kind of switch */ +#define NV_PRAMDAC_900 0x00680900 +#define NV_PRAMDAC_A20 0x00680A20 +#define NV_PRAMDAC_A24 0x00680A24 +#define NV_PRAMDAC_A34 0x00680A34 + +/* names fabricated from NV_USER_DAC info */ +#define NV_PRMDIO_PIXEL_MASK 0x006813c6 +# define NV_PRMDIO_PIXEL_MASK_MASK 0xff +#define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7 +#define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8 +#define NV_PRMDIO_PALETTE_DATA 0x006813c9 + +#define NV_PGRAPH_DEBUG_0 0x00400080 +#define NV_PGRAPH_DEBUG_1 0x00400084 +#define NV_PGRAPH_DEBUG_2_NV04 0x00400088 +#define NV_PGRAPH_DEBUG_2 0x00400620 +#define NV_PGRAPH_DEBUG_3 0x0040008c +#define NV_PGRAPH_DEBUG_4 0x00400090 +#define NV_PGRAPH_INTR 0x00400100 +#define NV_PGRAPH_INTR_EN 0x00400140 +#define NV_PGRAPH_CTX_CONTROL 0x00400144 +#define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170 +#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +#define NV_PGRAPH_BETA_AND 0x00400608 +#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 +#define NV_PGRAPH_BOFFSET0 0x00400640 +#define NV_PGRAPH_BOFFSET1 0x00400644 +#define NV_PGRAPH_BOFFSET2 0x00400648 +#define NV_PGRAPH_BLIMIT0 0x00400684 +#define NV_PGRAPH_BLIMIT1 0x00400688 +#define NV_PGRAPH_BLIMIT2 0x0040068c +#define NV_PGRAPH_STATUS 0x00400700 +#define NV_PGRAPH_SURFACE 0x00400710 +#define NV_PGRAPH_STATE 0x00400714 +#define NV_PGRAPH_FIFO 0x00400720 +#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 +#define NV_PGRAPH_TILE 0x00400b00 + +#define NV_PVIDEO_INTR_EN 0x00008140 +#define NV_PVIDEO_BUFFER 0x00008700 +#define NV_PVIDEO_STOP 0x00008704 +#define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4) +#define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4) +#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4) +#define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4) +#define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4) +#define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4) +#define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4) +#define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4) +#define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4) +#define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4) +#define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4) +#define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4) +#define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4) +#define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4) +#define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4) +# define NV_PVIDEO_FORMAT_PLANAR (1 << 0) +# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16) +# define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20) +# define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24) +#define NV_PVIDEO_COLOR_KEY 0x00008B00 + +/* NV04 overlay defines from VIDIX & Haiku */ +#define NV_PVIDEO_INTR_EN_0 0x00680140 +#define NV_PVIDEO_STEP_SIZE 0x00680200 +#define NV_PVIDEO_CONTROL_Y 0x00680204 +#define NV_PVIDEO_CONTROL_X 0x00680208 +#define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c +#define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214 +#define NV_PVIDEO_BUFF0_OFFSET 0x0068021c +#define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210 +#define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218 +#define NV_PVIDEO_BUFF1_OFFSET 0x00680220 +#define NV_PVIDEO_OE_STATE 0x00680224 +#define NV_PVIDEO_SU_STATE 0x00680228 +#define NV_PVIDEO_RM_STATE 0x0068022c +#define NV_PVIDEO_WINDOW_START 0x00680230 +#define NV_PVIDEO_WINDOW_SIZE 0x00680234 +#define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238 +#define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c +#define NV_PVIDEO_KEY 0x00680240 +#define NV_PVIDEO_OVERLAY 0x00680244 +#define NV_PVIDEO_RED_CSC_OFFSET 0x00680280 +#define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284 +#define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288 +#define NV_PVIDEO_CSC_ADJUST 0x0068028c + +#endif diff --git a/tvdump.c b/tvdump.c new file mode 100644 index 0000000..9a487df --- /dev/null +++ b/tvdump.c @@ -0,0 +1,493 @@ +#include <stdio.h> +#include <pciaccess.h> +#include "nvreg.h" +#include <string.h> +#include <unistd.h> + +#define NV_CIO_CRE_FP_HTIMING_INDEX 0x53 +#define NV_CIO_CRE_FP_VTIMING_INDEX 0x54 +#define NV_CIO_CRE_43 0x43 +#define NV_PRAMDAC_8C0 0x006808c0 + +#define NV_PRAMDAC_84C 0x0068084c +#define NV_PRAMDAC_898 0x00680898 +#define NV_PRAMDAC_89C 0x0068089c + +#define NV_PRAMDAC_TV_SETUP 0x00680700 +#define NV_PRAMDAC_TV_VBLANK_START 0x00680704 +#define NV_PRAMDAC_TV_VBLANK_END 0x00680708 +#define NV_PRAMDAC_TV_HBLANK_START 0x0068070c +#define NV_PRAMDAC_TV_HBLANK_END 0x00680710 +#define NV_PRAMDAC_TV_BLANK_COLOR 0x00680714 +#define NV_PRAMDAC_TV_VTOTAL 0x00680720 +#define NV_PRAMDAC_TV_VSYNC_START 0x00680724 +#define NV_PRAMDAC_TV_VSYNC_END 0x00680728 +#define NV_PRAMDAC_TV_HTOTAL 0x0068072c +#define NV_PRAMDAC_TV_HSYNC_START 0x00680730 +#define NV_PRAMDAC_TV_HSYNC_STOP 0x00680734 +#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738 + +int arch; + +#define NV_RD32(p, reg) (*(volatile uint32_t*)((char*)(p)+(reg))) +#define NV_RD08(p, reg) (*(volatile uint8_t*)((char*)(p)+(reg))) +#define NV_WR32(p, reg, val) do{ \ + *(volatile uint32_t*)((char*)(p)+(reg)) = (val); \ + }while(0) +#define NV_WR08(p, reg, val) do{ \ + *(volatile uint8_t*)((char*)(p)+(reg)) = (val); \ + }while(0) + + +static uint8_t read_vga_crtc(void* regs, int head, uint8_t index) +{ + NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); + return NV_RD08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); +} +static void write_vga_crtc(void* regs, int head, uint8_t index, uint8_t val) +{ + NV_WR08(regs, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); + NV_WR08(regs, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, val); +} + +static uint8_t read_prmvio(void* regs, int head, uint32_t reg) +{ + if(head && (arch & 0xf0) == 0x40) + reg += NV_PRMVIO_SIZE; + + return NV_RD08(regs, reg); +} + +static void write_prmvio(void* regs, int head, uint32_t reg, uint8_t val) +{ + if(head && (arch & 0xf0) == 0x40) + reg += NV_PRMVIO_SIZE; + + NV_WR08(regs, reg, val); +} + +static uint32_t NVReadRAMDAC(void* regs, int head, uint32_t reg) +{ + if (head) + reg += NV_PRAMDAC0_SIZE; + return NV_RD32(regs, reg); +} + +void NVWriteRAMDAC(void* regs, int head, uint32_t reg, uint32_t val) +{ + if (head) + reg += NV_PRAMDAC0_SIZE; + NV_WR32(regs, reg,val); +} + +static uint32_t NVReadCRTC(void* regs, int head, uint32_t reg) +{ + if (head) + reg += NV_PCRTC0_SIZE; + return NV_RD32(regs, reg); +} + +void NVWriteCRTC(void* regs, int head, uint32_t reg, uint32_t val) +{ + if (head) + reg += NV_PCRTC0_SIZE; + NV_WR32(regs, reg ,val); +} + +void nv_write_ptv(void* regs, uint32_t reg, uint32_t val){ + NV_WR32(regs, 0xd000+reg, val); +} + +uint32_t nv_read_ptv(void* regs, uint32_t reg){ + return NV_RD32(regs, 0xd000+reg); +} + +void nv_write_tve(void* regs, uint32_t reg, uint32_t val){ + NV_WR32(regs, 0xd220, reg); + NV_WR32(regs, 0xd224, val); +} + +uint8_t nv_read_tmds(void *regs, + int ramdac, int dl, uint8_t address) +{ + NVWriteRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, + NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address); + return NVReadRAMDAC(regs, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8); +} + +int NVGetArchitecture(volatile uint32_t *regs) +{ + int architecture = 0; + + /* We're dealing with >=NV10 */ + if ((regs[0] & 0x0f000000) > 0 ) + /* Bit 27-20 contain the architecture in hex */ + architecture = (regs[0] & 0xff00000) >> 20; + /* NV04 or NV05 */ + else if ((regs[0] & 0xff00fff0) == 0x20004000) + architecture = 0x04; + + return architecture; +} + +#define DIFFM(A,B,M) ((A%M + M - B%M)%M) +#define MASK(field) ((0xffffffff >> (31 - ((1?field) - (0?field)))) << (0?field)) +#define XLATE(src, srclowbit, outfield) ((((src) >> (srclowbit)) << (0?outfield)) & MASK(outfield)) + +void tv_dump(void* regs){ + int i,j; + arch = NVGetArchitecture(regs); + + printf("-- Architecture: NV%x\n", arch); + + printf("-- TV encoder register dump --\n"); + for(i=0; i<0x40; i++){ + NV_WR32(regs, 0xd220, i); + printf("%x: %x\n",i,NV_RD32(regs, 0xd224)); + } + + printf("-- PTV register dump --\n"); + for(i=0; i<0x10; i+=4) + printf("%x: %x\n",0x200+i,NV_RD32(regs, 0xd200+i)); + for(i=0; i<0x100; i+=4) + printf("%x: %x\n",0x300+i,NV_RD32(regs, 0xd300+i)); + for(i=0; i<0x10; i+=4) + printf("%x: %x\n",0x400+i,NV_RD32(regs, 0xd400+i)); + for(i=0; i<0x90; i+=4) + printf("%x: %x\n",0x500+i,NV_RD32(regs, 0xd500+i)); + for(i=0; i<0x20; i+=4) + printf("%x: %x\n",0x600+i,NV_RD32(regs, 0xd600+i)); + + write_vga_crtc(regs, 0, NV_CIO_SR_LOCK_INDEX, NV_CIO_SR_UNLOCK_RW_VALUE); + + for(i=0; i<2; i++){ + write_vga_crtc(regs, 0, NV_CIO_CRE_44, i); + + int horizDisplay = read_vga_crtc(regs, i, NV_CIO_CR_HDE_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),1,8:8); + int horizTotal = read_vga_crtc(regs, i, NV_CIO_CR_HDT_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),0,8:8); + int horizStart = read_vga_crtc(regs, i, NV_CIO_CR_HRS_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),3,8:8); + int horizEnd = read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX) & 0x1F; + int horizBlankStart = read_vga_crtc(regs, i, NV_CIO_CR_HBS_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),2,8:8); + int horizBlankEnd = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HBE_INDEX),0,4:0) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_HRE_INDEX),7, 5:5) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),4,6:6); + + int vertDisplay = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),6,9:9)| + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),1,8:8) | + read_vga_crtc(regs, i, NV_CIO_CR_VDE_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),1,10:10) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),2,11:11); + int vertTotal = read_vga_crtc(regs, i, NV_CIO_CR_VDT_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),5,9:9) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),0,8:8) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),0,10:10) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),0,11:11); + int vertStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),7,9:9) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),2,8:8) | + read_vga_crtc(regs, i, NV_CIO_CR_VRS_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),2,10:10) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),4,11:11); + int vertEnd = read_vga_crtc(regs, i, NV_CIO_CR_VRE_INDEX) & 0xF; + int vertBlankStart = XLATE(read_vga_crtc(regs, i, NV_CIO_CR_OVL_INDEX),3,8:8) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX),5,9:9) | + read_vga_crtc(regs, i, NV_CIO_CR_VBS_INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_LSR_INDEX),3,10:10) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_EBR_INDEX),6,11:11); + int vertBlankEnd = read_vga_crtc(regs, i, NV_CIO_CR_VBE_INDEX); + + int ilace_idx = read_vga_crtc(regs, i, NV_CIO_CRE_ILACE__INDEX) | + XLATE(read_vga_crtc(regs, i, NV_CIO_CRE_HEB__INDEX),4,8:8); + int dblscan = read_vga_crtc(regs, i, NV_CIO_CR_CELL_HT_INDEX) & 0x80; + + write_prmvio(regs, i, NV_PRMVIO_SRX, NV_VIO_SR_CLOCK_INDEX); + int clkdiv2 = read_prmvio(regs, i, NV_PRMVIO_SR)& 0x8; + + int nhsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x40; + int nvsync = read_prmvio(regs, i, NV_PRMVIO_MISC__READ) & 0x80; + + printf("-- CRTC %d timings --\n",i); + printf("horizDisplay: %d\n",(horizDisplay+1)*8); + printf("horizTotal: %d\n",(horizTotal+5)*8); + printf("horizSyncStart: %d\n",(horizStart+1)*8); + printf("horizSyncEnd: %d\n",(DIFFM(horizEnd,horizStart,0x20)+horizStart+1)*8); + printf("horizBlankStart: %d\n",(horizBlankStart+1)*8); + printf("horizBlankEnd: %d\n",(DIFFM(horizBlankEnd,horizBlankStart,128)+horizBlankStart+1)*8); + printf("vertDisplay: %d\n",vertDisplay+1); + printf("vertTotal: %d\n",vertTotal+2); + printf("vertSyncStart: %d\n",vertStart+1); + printf("vertSyncEnd: %d\n",DIFFM(vertEnd,vertStart,16)+vertStart+1); + printf("vertBlankStart: %d\n",vertBlankStart+1); + printf("vertBlankEnd: %d\n",DIFFM(vertBlankEnd,vertBlankStart,256)+vertBlankStart+1); + printf("ilace_idx: %d%s\n",ilace_idx,(ilace_idx&0xff) == 0xff ? " [off]":""); + printf("dblscan: %d\n",dblscan); + printf("clkdiv2: %d\n",clkdiv2); + printf("nhsync: %d\n",nhsync); + printf("nvsync: %d\n",nvsync); + + } + + for(i=0; i<2; i++){ + int pll = NV_RD32(regs, i? NV_RAMDAC_VPLL2: NV_PRAMDAC_VPLL_COEFF); + int n1,m1,n2,m2,p,vco2; + float f0; + + { + uint32_t crystal_strap_mask = 1 << 6; + /* open coded pNv->twoHeads test */ + if (arch > 0x10 && arch != 0x15 && arch != 0x1a && arch != 0x20) + crystal_strap_mask |= 1 << 22; + + switch (NV_RD32(regs, NV_PEXTDEV_BOOT_0) & crystal_strap_mask) { + case 0: + f0 = 13.500; + break; + case (1 << 6): + f0 = 14.318; + break; + case (1 << 22): + f0 = 27.000; + break; + case (1 << 22 | 1 << 6): + f0 = 25.000; + break; + } + } + + + if(arch == 0x35 || arch == 0x30){ + n1=XLATE(pll,8,7:0); + m1=XLATE(pll, 0, 3:0); + n2=XLATE(pll, 19, 2:0) | XLATE(pll, 24, 4:3); + m2=XLATE(pll, 4, 2:0); + p=XLATE(pll, 16, 2:0); + vco2=pll&0x80; + + } else if(arch == 0x31 || arch == 0x36 || arch >= 0x40) { + int pll2 = NV_RD32(regs, i? NV_RAMDAC_VPLL2 + 0x5c: NV_PRAMDAC_VPLL_COEFF + 0x70); + + if(arch >= 0x40) + vco2 = (i==0 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL1_ACTIVE)) || + (i==1 && !(NVReadRAMDAC(regs, 0, NV_PRAMDAC_580) & NV_RAMDAC_580_VPLL2_ACTIVE)); + else + vco2 = 1; + + n1=XLATE(pll,8,7:0); + m1=XLATE(pll, 0, 7:0); + p=XLATE(pll, 16, 2:0); + + n2=XLATE(pll2,8,7:0); + m2=XLATE(pll2, 0, 7:0); + + } else { + n1=XLATE(pll,8,7:0); + m1=XLATE(pll, 0, 7:0); + n2=1; + m2=1; + p=XLATE(pll, 16, 2:0); + vco2=0; + } + + printf("-- VPLL%d: 0x%x N1=0x%x M1=0x%x N2=0x%x M2=0x%x P=0x%x VCO2=%d f0=%f f=%f\n", + i ,pll, n1, m1, n2, m2, p, vco2, f0, f0*(float)n1/m1*(vco2?n2/m2:1)*(float)(1<<(7-p))/(1<<7)); + } + + for(i=0; i<2; i++){ + printf("-- VGA CRTC%d registers --\n",i); + printf("NV_CIO_CRE_PIXEL_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_PIXEL_INDEX)); + printf("NV_CIO_CRE_LCD__INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_LCD__INDEX)); + printf("NV_CIO_CRE_FP_HTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_HTIMING_INDEX)); + printf("NV_CIO_CRE_FP_VTIMING_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_FP_VTIMING_INDEX)); + printf("NV_CIO_CRE_43: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_43)); + printf("NV_CIO_CRE_RPC1_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_RPC1_INDEX)); + printf("NV_CIO_CRE_ENH_INDEX: 0x%x\n", read_vga_crtc(regs, i, NV_CIO_CRE_ENH_INDEX)); + } + + + for(j=0; j<2; j++){ + printf("-- VGA CRTC%d registers --\n", j); + for(i=0; i<0x9f; i++) + printf("CRTC%x %x: %x\n", j, i, read_vga_crtc(regs, j, i)); + } + + for(i=0; i<2; i++){ + printf("-- PRAMDAC%d registers --\n",i); + printf("NV_PRAMDAC_630: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_630)); + printf("NV_PRAMDAC0_OFFSET+0x674: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0x674)); + printf("NV_PRAMDAC_TV_SETUP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SETUP)); + printf("NV_PRAMDAC_TV_VBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_START)); + printf("NV_PRAMDAC_TV_VBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VBLANK_END)); + printf("NV_PRAMDAC_TV_HBLANK_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_START)); + printf("NV_PRAMDAC_TV_HBLANK_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HBLANK_END)); + printf("NV_PRAMDAC_TV_BLANK_COLOR: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_BLANK_COLOR)); + printf("NV_PRAMDAC_TV_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VTOTAL)); + printf("NV_PRAMDAC_TV_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_START)); + printf("NV_PRAMDAC_TV_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_VSYNC_END)); + printf("NV_PRAMDAC_TV_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HTOTAL)); + printf("NV_PRAMDAC_TV_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_START)); + printf("NV_PRAMDAC_TV_HSYNC_STOP: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_HSYNC_STOP)); + printf("NV_PRAMDAC_TV_SYNC_DELAY: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_TV_SYNC_DELAY)); + printf("NV_PRAMDAC_FP_DEBUG_0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_0)); + printf("NV_PRAMDAC_FP_DEBUG_1: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_1)); + printf("NV_PRAMDAC_FP_DEBUG_2: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_DEBUG_2)); + printf("NV_PRAMDAC_FP_TG_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_TG_CONTROL)); + printf("NV_PRAMDAC_FP_HTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HTOTAL)); + printf("NV_PRAMDAC_FP_HVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_START)); + printf("NV_PRAMDAC_FP_HVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HVALID_END)); + printf("NV_PRAMDAC_FP_HDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HDISPLAY_END)); + printf("NV_PRAMDAC_FP_HCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HCRTC)); + printf("NV_PRAMDAC_FP_HSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_START)); + printf("NV_PRAMDAC_FP_HSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_HSYNC_END)); + printf("NV_PRAMDAC_FP_VTOTAL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VTOTAL)); + printf("NV_PRAMDAC_FP_VVALID_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_START)); + printf("NV_PRAMDAC_FP_VVALID_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VVALID_END)); + printf("NV_PRAMDAC_FP_VDISPLAY_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VDISPLAY_END)); + printf("NV_PRAMDAC_FP_VCRTC: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VCRTC)); + printf("NV_PRAMDAC_FP_VSYNC_START: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_START)); + printf("NV_PRAMDAC_FP_VSYNC_END: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_FP_VSYNC_END)); + printf("NV_PRAMDAC_84C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_84C)); + printf("NV_PRAMDAC_898: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_898)); + printf("NV_PRAMDAC_89C: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_89C)); + printf("NV_PRAMDAC_8C0: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_8C0)); + printf("NV_PRAMDAC_900: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_900)); + printf("NV_PRAMDAC_PLL_SETUP_CONTROL: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_SETUP_CONTROL)); + printf("NV_PRAMDAC_SEL_CLK: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_SEL_CLK)); + printf("NV_PRAMDAC_PLL_COEFF_SELECT: 0x%x\n", NVReadRAMDAC(regs, i, NV_PRAMDAC_PLL_COEFF_SELECT)); + + for(j=0; j<64; j++) + printf("NV_PRAMDAC0_OFFSET+0xc%02x: 0x%x\n", 4*j, NVReadRAMDAC(regs, i, NV_PRAMDAC0_OFFSET+0xc00+4*j)); + } + + for(i=0; i<2; i++){ + printf("-- TMDS%d registers --\n",i); + for (j=0; j<0x40; j++) + printf("TMDS%d_%x: 0x%x\n", i, j, nv_read_tmds(regs, i, 0, j)); + + } + + for(i=0; i<2; i++){ + printf("-- PCRTC%d registers --\n",i); + printf("NV_PCRTC_CONFIG: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_CONFIG)); + printf("NV_PCRTC_START: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_START)); + printf("NV_PCRTC_GPIO_EXT: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_GPIO_EXT)); + printf("NV_PCRTC_830: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_830)); + printf("NV_PCRTC_834: 0x%x\n", NVReadCRTC(regs, i, NV_PCRTC_834)); + } + + printf("-- OUTPUT registers--\n"); + int offsets[] = {0, 0x68, 0x2000, 0x2068}; + + for(i=0; i< sizeof(offsets)/sizeof(int); i++) + printf("NV_PRAMDAC_DACCLK+0x%x: 0x%x\n",offsets[i], NVReadRAMDAC(regs, 0, NV_PRAMDAC_DACCLK+offsets[i])); + + printf("-- PVIDEO registers --\n"); + printf("NV_PVIDEO_DEBUG_0: 0x%x\n", NV_RD32(regs,0x00008080)); + printf("NV_PVIDEO_DEBUG_1: 0x%x\n", NV_RD32(regs,0x00008084)); + printf("NV_PVIDEO_DEBUG_2: 0x%x\n", NV_RD32(regs,0x00008088)); + printf("NV_PVIDEO_DEBUG_3: 0x%x\n", NV_RD32(regs,0x0000808C)); + printf("NV_PVIDEO_DEBUG_4: 0x%x\n", NV_RD32(regs,0x00008090)); + printf("NV_PVIDEO_DEBUG_5: 0x%x\n", NV_RD32(regs,0x00008094)); + printf("NV_PVIDEO_DEBUG_6: 0x%x\n", NV_RD32(regs,0x00008098)); + printf("NV_PVIDEO_DEBUG_7: 0x%x\n", NV_RD32(regs,0x0000809C)); + printf("NV_PVIDEO_DEBUG_8: 0x%x\n", NV_RD32(regs,0x000080A0)); + printf("NV_PVIDEO_DEBUG_9: 0x%x\n", NV_RD32(regs,0x000080A4)); + printf("NV_PVIDEO_DEBUG_10: 0x%x\n", NV_RD32(regs,0x000080A8)); + printf("NV_PVIDEO_INTR: 0x%x\n", NV_RD32(regs,0x00008100)); + printf("NV_PVIDEO_INTR_REASON: 0x%x\n", NV_RD32(regs,0x00008104)); + printf("NV_PVIDEO_INTR_EN: 0x%x\n", NV_RD32(regs,0x00008140)); + printf("NV_PVIDEO_BUFFER: 0x%x\n", NV_RD32(regs,0x00008700)); + printf("NV_PVIDEO_STOP: 0x%x\n", NV_RD32(regs,0x00008704)); + printf("NV_PVIDEO_BASE: 0x%x\n", NV_RD32(regs,0x00008900)); + printf("NV_PVIDEO_LIMIT: 0x%x\n", NV_RD32(regs,0x00008908)); + printf("NV_PVIDEO_LUMINANCE: 0x%x\n", NV_RD32(regs,0x00008910)); + printf("NV_PVIDEO_CHROMINANCE: 0x%x\n", NV_RD32(regs,0x00008918)); + printf("NV_PVIDEO_OFFSET: 0x%x\n", NV_RD32(regs,0x00008920)); + printf("NV_PVIDEO_SIZE_IN: 0x%x\n", NV_RD32(regs,0x00008928)); + printf("NV_PVIDEO_POINT_IN: 0x%x\n", NV_RD32(regs,0x00008930)); + printf("NV_PVIDEO_DS_DX: 0x%x\n", NV_RD32(regs,0x00008938)); + printf("NV_PVIDEO_DT_DY: 0x%x\n", NV_RD32(regs,0x00008940)); + printf("NV_PVIDEO_POINT_OUT: 0x%x\n", NV_RD32(regs,0x00008948)); + printf("NV_PVIDEO_SIZE_OUT: 0x%x\n", NV_RD32(regs,0x00008950)); + printf("NV_PVIDEO_FORMAT: 0x%x\n", NV_RD32(regs,0x00008958)); + printf("NV_PVIDEO_COLOR_KEY: 0x%x\n", NV_RD32(regs,0x00008B00)); + printf("NV_PVIDEO_TEST: 0x%x\n", NV_RD32(regs,0x00008D00)); + printf("NV_PVIDEO_TST_WRITE: 0x%x\n", NV_RD32(regs,0x00008D10)); + printf("NV_PVIDEO_TST_READ: 0x%x\n", NV_RD32(regs,0x00008D40)); + + printf("-- MISC registers --\n"); + printf("0x00c1e040: 0x%x\n", NV_RD32(regs, 0x00c1e040)); + printf("NV_PBUS_POWERCTRL_2: 0x%x\n", NV_RD32(regs, NV_PBUS_POWERCTRL_2)); + printf("NV_PBUS_PCI_NV_20: 0x%x\n", NV_RD32(regs, NV_PBUS_PCI_NV_20)); + printf("NV_PBUS_OFFSET+0x524: 0x%x\n", NV_RD32(regs, NV_PBUS_OFFSET+0x524)); + printf("NV_PBUS_OFFSET+0x588: 0x%x\n", NV_RD32(regs, NV_PBUS_OFFSET+0x588)); + + +} + +int main(){ + void* regs; + int ret; + + ret = pci_system_init(); + + if(ret){ + fprintf(stderr,"Error calling pci_system_init().\n"); + + return 1; + } + + struct pci_id_match nv_match = {0x10de, PCI_MATCH_ANY, PCI_MATCH_ANY, PCI_MATCH_ANY, 0x30000, 0xffff0000}; + struct pci_device_iterator* it = pci_id_match_iterator_create(&nv_match); + + if(!it){ + fprintf(stderr,"Error calling pci_id_match_iterator_create().\n"); + + pci_iterator_destroy(it); + + return 1; + } + + struct pci_device* dev = pci_device_next(it); + + if(!dev){ + fprintf(stderr,"No devices found.\n"); + + pci_iterator_destroy(it); + pci_system_cleanup(); + + return 1; + } + + ret = pci_device_probe(dev); + + if(ret){ + fprintf(stderr, "Error calling pci_device_probe().\n"); + + pci_iterator_destroy(it); + pci_system_cleanup(); + + return 1; + } + + ret = pci_device_map_range(dev, dev->regions[0].base_addr, dev->regions[0].size, PCI_DEV_MAP_FLAG_WRITABLE,®s); + + if(ret){ + fprintf(stderr, "Error calling pci_device_map_range().\n"); + + pci_iterator_destroy(it); + pci_system_cleanup(); + + return 1; + } + + tv_dump(regs); + + pci_device_unmap_range(dev, regs, dev->regions[0].size); + pci_iterator_destroy(it); + pci_system_cleanup(); + + return 0; +} diff --git a/tvdump2code.py b/tvdump2code.py new file mode 100644 index 0000000..9b73cc0 --- /dev/null +++ b/tvdump2code.py @@ -0,0 +1,66 @@ +#!/usr/bin/python + +import sys +import re + +mode="" + +print """#define NV_PRAMDAC_84C 0x0068084c +#define NV_PRAMDAC_898 0x00680898 +#define NV_PRAMDAC_89C 0x0068089c + +#define NV_PRAMDAC_TV_SETUP 0x00680700 +#define NV_PRAMDAC_TV_VBLANK_START 0x00680704 +#define NV_PRAMDAC_TV_VBLANK_END 0x00680708 +#define NV_PRAMDAC_TV_HBLANK_START 0x0068070c +#define NV_PRAMDAC_TV_HBLANK_END 0x00680710 +#define NV_PRAMDAC_TV_BLANK_COLOR 0x00680714 +#define NV_PRAMDAC_TV_VTOTAL 0x00680720 +#define NV_PRAMDAC_TV_VSYNC_START 0x00680724 +#define NV_PRAMDAC_TV_VSYNC_END 0x00680728 +#define NV_PRAMDAC_TV_HTOTAL 0x0068072c +#define NV_PRAMDAC_TV_HSYNC_START 0x00680730 +#define NV_PRAMDAC_TV_HSYNC_STOP 0x00680734 +#define NV_PRAMDAC_TV_SYNC_DELAY 0x00680738""" + + +for l in sys.stdin.readlines(): + if re.match(".*TV encoder register dump.*",l): + mode="tvenc" + continue + elif re.match(".*PTV register dump.*",l): + mode="ptv" + continue + elif re.match(".*CRTC . timings.*",l): + mode="" + continue + elif re.match(".*VGA CRTC. registers.*",l): + mode="vgacrtc" + continue + elif re.match(".*PRAMDAC. registers.*",l): + mode="pramdac" + i=int(re.match(".*PRAMDAC(.) registers.*",l).group(1)) + continue + elif re.match(".*PCRTC. registers.*",l): + mode="pcrtc" + i=int(re.match(".*PCRTC(.) registers.*",l).group(1)) + continue + elif re.match(".*(OUTPUT|MISC) registers.*",l): + mode="output" + continue + + if mode == "": + pass + elif mode == "tvenc": + print re.sub("(.*) *: *(.*)","nv_write_tv_enc(pNv, 0x\\1, 0x\\2);",l)[0:-1] + elif mode == "ptv": + print re.sub("(.*) *: *(.*)","nv_write_ptv(pNv, 0x\\1, 0x\\2);",l)[0:-1] + elif mode == "vgacrtc": + if re.match("^CRTC[01]",l): + print re.sub("CRTC(.) (.*) *: *(.*)"," NVWriteVgaCrtc(pNv, \\1, 0x\\2, 0x\\3);",l)[0:-1] + elif mode == "pramdac": + print re.sub("(.*) *: *(.*)"," NVWriteRAMDAC(pNv, %d, \\1, \\2);" % (i),l)[0:-1] + elif mode == "pcrtc": + print re.sub("(.*) *: *(.*)"," NVWriteCRTC(pNv, %d, \\1, \\2);" % (i),l)[0:-1] + elif mode == "output": + print re.sub("(.*) *: *(.*)"," NV_WR32(pNv->REGS, \\1, \\2);",l)[0:-1] |